root / hw / misc / exynos4210_pmu.c @ f487b677
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1 | df91b48f | Maksim Kozlov | /*
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2 | df91b48f | Maksim Kozlov | * Exynos4210 Power Management Unit (PMU) Emulation
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3 | df91b48f | Maksim Kozlov | *
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4 | df91b48f | Maksim Kozlov | * Copyright (C) 2011 Samsung Electronics Co Ltd.
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5 | df91b48f | Maksim Kozlov | * Maksim Kozlov <m.kozlov@samsung.com>
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6 | df91b48f | Maksim Kozlov | *
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7 | df91b48f | Maksim Kozlov | * This program is free software; you can redistribute it and/or modify it
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8 | df91b48f | Maksim Kozlov | * under the terms of the GNU General Public License as published by the
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9 | df91b48f | Maksim Kozlov | * Free Software Foundation; either version 2 of the License, or
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10 | df91b48f | Maksim Kozlov | * (at your option) any later version.
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11 | df91b48f | Maksim Kozlov | *
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12 | df91b48f | Maksim Kozlov | * This program is distributed in the hope that it will be useful, but WITHOUT
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13 | df91b48f | Maksim Kozlov | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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14 | df91b48f | Maksim Kozlov | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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15 | df91b48f | Maksim Kozlov | * for more details.
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16 | df91b48f | Maksim Kozlov | *
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17 | df91b48f | Maksim Kozlov | * You should have received a copy of the GNU General Public License along
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18 | df91b48f | Maksim Kozlov | * with this program; if not, see <http://www.gnu.org/licenses/>.
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19 | df91b48f | Maksim Kozlov | */
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20 | df91b48f | Maksim Kozlov | |
21 | df91b48f | Maksim Kozlov | /*
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22 | df91b48f | Maksim Kozlov | * This model implements PMU registers just as a bulk of memory. Currently,
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23 | df91b48f | Maksim Kozlov | * the only reason this device exists is that secondary CPU boot loader
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24 | df91b48f | Maksim Kozlov | * uses PMU INFORM5 register as a holding pen.
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25 | df91b48f | Maksim Kozlov | */
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26 | df91b48f | Maksim Kozlov | |
27 | 83c9f4ca | Paolo Bonzini | #include "hw/sysbus.h" |
28 | df91b48f | Maksim Kozlov | |
29 | df91b48f | Maksim Kozlov | #ifndef DEBUG_PMU
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30 | df91b48f | Maksim Kozlov | #define DEBUG_PMU 0 |
31 | df91b48f | Maksim Kozlov | #endif
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32 | df91b48f | Maksim Kozlov | |
33 | df91b48f | Maksim Kozlov | #ifndef DEBUG_PMU_EXTEND
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34 | df91b48f | Maksim Kozlov | #define DEBUG_PMU_EXTEND 0 |
35 | df91b48f | Maksim Kozlov | #endif
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36 | df91b48f | Maksim Kozlov | |
37 | df91b48f | Maksim Kozlov | #if DEBUG_PMU
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38 | df91b48f | Maksim Kozlov | #define PRINT_DEBUG(fmt, args...) \
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39 | df91b48f | Maksim Kozlov | do { \
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40 | df91b48f | Maksim Kozlov | fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ |
41 | df91b48f | Maksim Kozlov | } while (0) |
42 | df91b48f | Maksim Kozlov | |
43 | df91b48f | Maksim Kozlov | #if DEBUG_PMU_EXTEND
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44 | df91b48f | Maksim Kozlov | #define PRINT_DEBUG_EXTEND(fmt, args...) \
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45 | df91b48f | Maksim Kozlov | do { \
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46 | df91b48f | Maksim Kozlov | fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ |
47 | df91b48f | Maksim Kozlov | } while (0) |
48 | df91b48f | Maksim Kozlov | #else
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49 | df91b48f | Maksim Kozlov | #define PRINT_DEBUG_EXTEND(fmt, args...) do {} while (0) |
50 | df91b48f | Maksim Kozlov | #endif /* EXTEND */ |
51 | df91b48f | Maksim Kozlov | |
52 | df91b48f | Maksim Kozlov | #else
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53 | df91b48f | Maksim Kozlov | #define PRINT_DEBUG(fmt, args...) do {} while (0) |
54 | df91b48f | Maksim Kozlov | #define PRINT_DEBUG_EXTEND(fmt, args...) do {} while (0) |
55 | df91b48f | Maksim Kozlov | #endif
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56 | df91b48f | Maksim Kozlov | |
57 | df91b48f | Maksim Kozlov | /*
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58 | df91b48f | Maksim Kozlov | * Offsets for PMU registers
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59 | df91b48f | Maksim Kozlov | */
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60 | df91b48f | Maksim Kozlov | #define OM_STAT 0x0000 /* OM status register */ |
61 | df91b48f | Maksim Kozlov | #define RTC_CLKO_SEL 0x000C /* Controls RTCCLKOUT */ |
62 | df91b48f | Maksim Kozlov | #define GNSS_RTC_OUT_CTRL 0x0010 /* Controls GNSS_RTC_OUT */ |
63 | df91b48f | Maksim Kozlov | /* Decides whether system-level low-power mode is used. */
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64 | df91b48f | Maksim Kozlov | #define SYSTEM_POWER_DOWN_CTRL 0x0200 |
65 | df91b48f | Maksim Kozlov | /* Sets control options for CENTRAL_SEQ */
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66 | df91b48f | Maksim Kozlov | #define SYSTEM_POWER_DOWN_OPTION 0x0208 |
67 | df91b48f | Maksim Kozlov | #define SWRESET 0x0400 /* Generate software reset */ |
68 | df91b48f | Maksim Kozlov | #define RST_STAT 0x0404 /* Reset status register */ |
69 | df91b48f | Maksim Kozlov | #define WAKEUP_STAT 0x0600 /* Wakeup status register */ |
70 | df91b48f | Maksim Kozlov | #define EINT_WAKEUP_MASK 0x0604 /* Configure External INTerrupt mask */ |
71 | df91b48f | Maksim Kozlov | #define WAKEUP_MASK 0x0608 /* Configure wakeup source mask */ |
72 | df91b48f | Maksim Kozlov | #define HDMI_PHY_CONTROL 0x0700 /* HDMI PHY control register */ |
73 | df91b48f | Maksim Kozlov | #define USBDEVICE_PHY_CONTROL 0x0704 /* USB Device PHY control register */ |
74 | df91b48f | Maksim Kozlov | #define USBHOST_PHY_CONTROL 0x0708 /* USB HOST PHY control register */ |
75 | df91b48f | Maksim Kozlov | #define DAC_PHY_CONTROL 0x070C /* DAC control register */ |
76 | df91b48f | Maksim Kozlov | #define MIPI_PHY0_CONTROL 0x0710 /* MIPI PHY control register */ |
77 | df91b48f | Maksim Kozlov | #define MIPI_PHY1_CONTROL 0x0714 /* MIPI PHY control register */ |
78 | df91b48f | Maksim Kozlov | #define ADC_PHY_CONTROL 0x0718 /* TS-ADC control register */ |
79 | df91b48f | Maksim Kozlov | #define PCIe_PHY_CONTROL 0x071C /* TS-PCIe control register */ |
80 | df91b48f | Maksim Kozlov | #define SATA_PHY_CONTROL 0x0720 /* TS-SATA control register */ |
81 | df91b48f | Maksim Kozlov | #define INFORM0 0x0800 /* Information register 0 */ |
82 | df91b48f | Maksim Kozlov | #define INFORM1 0x0804 /* Information register 1 */ |
83 | df91b48f | Maksim Kozlov | #define INFORM2 0x0808 /* Information register 2 */ |
84 | df91b48f | Maksim Kozlov | #define INFORM3 0x080C /* Information register 3 */ |
85 | df91b48f | Maksim Kozlov | #define INFORM4 0x0810 /* Information register 4 */ |
86 | df91b48f | Maksim Kozlov | #define INFORM5 0x0814 /* Information register 5 */ |
87 | df91b48f | Maksim Kozlov | #define INFORM6 0x0818 /* Information register 6 */ |
88 | df91b48f | Maksim Kozlov | #define INFORM7 0x081C /* Information register 7 */ |
89 | df91b48f | Maksim Kozlov | #define PMU_DEBUG 0x0A00 /* PMU debug register */ |
90 | df91b48f | Maksim Kozlov | /* Registers to set system-level low-power option */
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91 | df91b48f | Maksim Kozlov | #define ARM_CORE0_SYS_PWR_REG 0x1000 |
92 | df91b48f | Maksim Kozlov | #define ARM_CORE1_SYS_PWR_REG 0x1010 |
93 | df91b48f | Maksim Kozlov | #define ARM_COMMON_SYS_PWR_REG 0x1080 |
94 | df91b48f | Maksim Kozlov | #define ARM_CPU_L2_0_SYS_PWR_REG 0x10C0 |
95 | df91b48f | Maksim Kozlov | #define ARM_CPU_L2_1_SYS_PWR_REG 0x10C4 |
96 | df91b48f | Maksim Kozlov | #define CMU_ACLKSTOP_SYS_PWR_REG 0x1100 |
97 | df91b48f | Maksim Kozlov | #define CMU_SCLKSTOP_SYS_PWR_REG 0x1104 |
98 | df91b48f | Maksim Kozlov | #define CMU_RESET_SYS_PWR_REG 0x110C |
99 | df91b48f | Maksim Kozlov | #define APLL_SYSCLK_SYS_PWR_REG 0x1120 |
100 | df91b48f | Maksim Kozlov | #define MPLL_SYSCLK_SYS_PWR_REG 0x1124 |
101 | df91b48f | Maksim Kozlov | #define VPLL_SYSCLK_SYS_PWR_REG 0x1128 |
102 | df91b48f | Maksim Kozlov | #define EPLL_SYSCLK_SYS_PWR_REG 0x112C |
103 | df91b48f | Maksim Kozlov | #define CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG 0x1138 |
104 | df91b48f | Maksim Kozlov | #define CMU_RESET_GPS_ALIVE_SYS_PWR_REG 0x113C |
105 | df91b48f | Maksim Kozlov | #define CMU_CLKSTOP_CAM_SYS_PWR_REG 0x1140 |
106 | df91b48f | Maksim Kozlov | #define CMU_CLKSTOP_TV_SYS_PWR_REG 0x1144 |
107 | df91b48f | Maksim Kozlov | #define CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1148 |
108 | df91b48f | Maksim Kozlov | #define CMU_CLKSTOP_G3D_SYS_PWR_REG 0x114C |
109 | df91b48f | Maksim Kozlov | #define CMU_CLKSTOP_LCD0_SYS_PWR_REG 0x1150 |
110 | df91b48f | Maksim Kozlov | #define CMU_CLKSTOP_LCD1_SYS_PWR_REG 0x1154 |
111 | df91b48f | Maksim Kozlov | #define CMU_CLKSTOP_MAUDIO_SYS_PWR_REG 0x1158 |
112 | df91b48f | Maksim Kozlov | #define CMU_CLKSTOP_GPS_SYS_PWR_REG 0x115C |
113 | df91b48f | Maksim Kozlov | #define CMU_RESET_CAM_SYS_PWR_REG 0x1160 |
114 | df91b48f | Maksim Kozlov | #define CMU_RESET_TV_SYS_PWR_REG 0x1164 |
115 | df91b48f | Maksim Kozlov | #define CMU_RESET_MFC_SYS_PWR_REG 0x1168 |
116 | df91b48f | Maksim Kozlov | #define CMU_RESET_G3D_SYS_PWR_REG 0x116C |
117 | df91b48f | Maksim Kozlov | #define CMU_RESET_LCD0_SYS_PWR_REG 0x1170 |
118 | df91b48f | Maksim Kozlov | #define CMU_RESET_LCD1_SYS_PWR_REG 0x1174 |
119 | df91b48f | Maksim Kozlov | #define CMU_RESET_MAUDIO_SYS_PWR_REG 0x1178 |
120 | df91b48f | Maksim Kozlov | #define CMU_RESET_GPS_SYS_PWR_REG 0x117C |
121 | df91b48f | Maksim Kozlov | #define TOP_BUS_SYS_PWR_REG 0x1180 |
122 | df91b48f | Maksim Kozlov | #define TOP_RETENTION_SYS_PWR_REG 0x1184 |
123 | df91b48f | Maksim Kozlov | #define TOP_PWR_SYS_PWR_REG 0x1188 |
124 | df91b48f | Maksim Kozlov | #define LOGIC_RESET_SYS_PWR_REG 0x11A0 |
125 | df91b48f | Maksim Kozlov | #define OneNANDXL_MEM_SYS_PWR_REG 0x11C0 |
126 | df91b48f | Maksim Kozlov | #define MODEMIF_MEM_SYS_PWR_REG 0x11C4 |
127 | df91b48f | Maksim Kozlov | #define USBDEVICE_MEM_SYS_PWR_REG 0x11CC |
128 | df91b48f | Maksim Kozlov | #define SDMMC_MEM_SYS_PWR_REG 0x11D0 |
129 | df91b48f | Maksim Kozlov | #define CSSYS_MEM_SYS_PWR_REG 0x11D4 |
130 | df91b48f | Maksim Kozlov | #define SECSS_MEM_SYS_PWR_REG 0x11D8 |
131 | df91b48f | Maksim Kozlov | #define PCIe_MEM_SYS_PWR_REG 0x11E0 |
132 | df91b48f | Maksim Kozlov | #define SATA_MEM_SYS_PWR_REG 0x11E4 |
133 | df91b48f | Maksim Kozlov | #define PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200 |
134 | df91b48f | Maksim Kozlov | #define PAD_RETENTION_MAUDIO_SYS_PWR_REG 0x1204 |
135 | df91b48f | Maksim Kozlov | #define PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220 |
136 | df91b48f | Maksim Kozlov | #define PAD_RETENTION_UART_SYS_PWR_REG 0x1224 |
137 | df91b48f | Maksim Kozlov | #define PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228 |
138 | df91b48f | Maksim Kozlov | #define PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C |
139 | df91b48f | Maksim Kozlov | #define PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230 |
140 | df91b48f | Maksim Kozlov | #define PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234 |
141 | df91b48f | Maksim Kozlov | #define PAD_ISOLATION_SYS_PWR_REG 0x1240 |
142 | df91b48f | Maksim Kozlov | #define PAD_ALV_SEL_SYS_PWR_REG 0x1260 |
143 | df91b48f | Maksim Kozlov | #define XUSBXTI_SYS_PWR_REG 0x1280 |
144 | df91b48f | Maksim Kozlov | #define XXTI_SYS_PWR_REG 0x1284 |
145 | df91b48f | Maksim Kozlov | #define EXT_REGULATOR_SYS_PWR_REG 0x12C0 |
146 | df91b48f | Maksim Kozlov | #define GPIO_MODE_SYS_PWR_REG 0x1300 |
147 | df91b48f | Maksim Kozlov | #define GPIO_MODE_MAUDIO_SYS_PWR_REG 0x1340 |
148 | df91b48f | Maksim Kozlov | #define CAM_SYS_PWR_REG 0x1380 |
149 | df91b48f | Maksim Kozlov | #define TV_SYS_PWR_REG 0x1384 |
150 | df91b48f | Maksim Kozlov | #define MFC_SYS_PWR_REG 0x1388 |
151 | df91b48f | Maksim Kozlov | #define G3D_SYS_PWR_REG 0x138C |
152 | df91b48f | Maksim Kozlov | #define LCD0_SYS_PWR_REG 0x1390 |
153 | df91b48f | Maksim Kozlov | #define LCD1_SYS_PWR_REG 0x1394 |
154 | df91b48f | Maksim Kozlov | #define MAUDIO_SYS_PWR_REG 0x1398 |
155 | df91b48f | Maksim Kozlov | #define GPS_SYS_PWR_REG 0x139C |
156 | df91b48f | Maksim Kozlov | #define GPS_ALIVE_SYS_PWR_REG 0x13A0 |
157 | df91b48f | Maksim Kozlov | #define ARM_CORE0_CONFIGURATION 0x2000 /* Configure power mode of ARM_CORE0 */ |
158 | df91b48f | Maksim Kozlov | #define ARM_CORE0_STATUS 0x2004 /* Check power mode of ARM_CORE0 */ |
159 | df91b48f | Maksim Kozlov | #define ARM_CORE0_OPTION 0x2008 /* Sets control options for ARM_CORE0 */ |
160 | df91b48f | Maksim Kozlov | #define ARM_CORE1_CONFIGURATION 0x2080 /* Configure power mode of ARM_CORE1 */ |
161 | df91b48f | Maksim Kozlov | #define ARM_CORE1_STATUS 0x2084 /* Check power mode of ARM_CORE1 */ |
162 | df91b48f | Maksim Kozlov | #define ARM_CORE1_OPTION 0x2088 /* Sets control options for ARM_CORE0 */ |
163 | df91b48f | Maksim Kozlov | #define ARM_COMMON_OPTION 0x2408 /* Sets control options for ARM_COMMON */ |
164 | df91b48f | Maksim Kozlov | /* Configure power mode of ARM_CPU_L2_0 */
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165 | df91b48f | Maksim Kozlov | #define ARM_CPU_L2_0_CONFIGURATION 0x2600 |
166 | df91b48f | Maksim Kozlov | #define ARM_CPU_L2_0_STATUS 0x2604 /* Check power mode of ARM_CPU_L2_0 */ |
167 | df91b48f | Maksim Kozlov | /* Configure power mode of ARM_CPU_L2_1 */
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168 | df91b48f | Maksim Kozlov | #define ARM_CPU_L2_1_CONFIGURATION 0x2620 |
169 | df91b48f | Maksim Kozlov | #define ARM_CPU_L2_1_STATUS 0x2624 /* Check power mode of ARM_CPU_L2_1 */ |
170 | df91b48f | Maksim Kozlov | /* Sets control options for PAD_RETENTION_MAUDIO */
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171 | df91b48f | Maksim Kozlov | #define PAD_RETENTION_MAUDIO_OPTION 0x3028 |
172 | df91b48f | Maksim Kozlov | /* Sets control options for PAD_RETENTION_GPIO */
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173 | df91b48f | Maksim Kozlov | #define PAD_RETENTION_GPIO_OPTION 0x3108 |
174 | df91b48f | Maksim Kozlov | /* Sets control options for PAD_RETENTION_UART */
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175 | df91b48f | Maksim Kozlov | #define PAD_RETENTION_UART_OPTION 0x3128 |
176 | df91b48f | Maksim Kozlov | /* Sets control options for PAD_RETENTION_MMCA */
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177 | df91b48f | Maksim Kozlov | #define PAD_RETENTION_MMCA_OPTION 0x3148 |
178 | df91b48f | Maksim Kozlov | /* Sets control options for PAD_RETENTION_MMCB */
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179 | df91b48f | Maksim Kozlov | #define PAD_RETENTION_MMCB_OPTION 0x3168 |
180 | df91b48f | Maksim Kozlov | /* Sets control options for PAD_RETENTION_EBIA */
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181 | df91b48f | Maksim Kozlov | #define PAD_RETENTION_EBIA_OPTION 0x3188 |
182 | df91b48f | Maksim Kozlov | /* Sets control options for PAD_RETENTION_EBIB */
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183 | df91b48f | Maksim Kozlov | #define PAD_RETENTION_EBIB_OPTION 0x31A8 |
184 | df91b48f | Maksim Kozlov | #define PS_HOLD_CONTROL 0x330C /* PS_HOLD control register */ |
185 | df91b48f | Maksim Kozlov | #define XUSBXTI_CONFIGURATION 0x3400 /* Configure the pad of XUSBXTI */ |
186 | df91b48f | Maksim Kozlov | #define XUSBXTI_STATUS 0x3404 /* Check the pad of XUSBXTI */ |
187 | df91b48f | Maksim Kozlov | /* Sets time required for XUSBXTI to be stabilized */
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188 | df91b48f | Maksim Kozlov | #define XUSBXTI_DURATION 0x341C |
189 | df91b48f | Maksim Kozlov | #define XXTI_CONFIGURATION 0x3420 /* Configure the pad of XXTI */ |
190 | df91b48f | Maksim Kozlov | #define XXTI_STATUS 0x3424 /* Check the pad of XXTI */ |
191 | df91b48f | Maksim Kozlov | /* Sets time required for XXTI to be stabilized */
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192 | df91b48f | Maksim Kozlov | #define XXTI_DURATION 0x343C |
193 | df91b48f | Maksim Kozlov | /* Sets time required for EXT_REGULATOR to be stabilized */
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194 | df91b48f | Maksim Kozlov | #define EXT_REGULATOR_DURATION 0x361C |
195 | df91b48f | Maksim Kozlov | #define CAM_CONFIGURATION 0x3C00 /* Configure power mode of CAM */ |
196 | df91b48f | Maksim Kozlov | #define CAM_STATUS 0x3C04 /* Check power mode of CAM */ |
197 | df91b48f | Maksim Kozlov | #define CAM_OPTION 0x3C08 /* Sets control options for CAM */ |
198 | df91b48f | Maksim Kozlov | #define TV_CONFIGURATION 0x3C20 /* Configure power mode of TV */ |
199 | df91b48f | Maksim Kozlov | #define TV_STATUS 0x3C24 /* Check power mode of TV */ |
200 | df91b48f | Maksim Kozlov | #define TV_OPTION 0x3C28 /* Sets control options for TV */ |
201 | df91b48f | Maksim Kozlov | #define MFC_CONFIGURATION 0x3C40 /* Configure power mode of MFC */ |
202 | df91b48f | Maksim Kozlov | #define MFC_STATUS 0x3C44 /* Check power mode of MFC */ |
203 | df91b48f | Maksim Kozlov | #define MFC_OPTION 0x3C48 /* Sets control options for MFC */ |
204 | df91b48f | Maksim Kozlov | #define G3D_CONFIGURATION 0x3C60 /* Configure power mode of G3D */ |
205 | df91b48f | Maksim Kozlov | #define G3D_STATUS 0x3C64 /* Check power mode of G3D */ |
206 | df91b48f | Maksim Kozlov | #define G3D_OPTION 0x3C68 /* Sets control options for G3D */ |
207 | df91b48f | Maksim Kozlov | #define LCD0_CONFIGURATION 0x3C80 /* Configure power mode of LCD0 */ |
208 | df91b48f | Maksim Kozlov | #define LCD0_STATUS 0x3C84 /* Check power mode of LCD0 */ |
209 | df91b48f | Maksim Kozlov | #define LCD0_OPTION 0x3C88 /* Sets control options for LCD0 */ |
210 | df91b48f | Maksim Kozlov | #define LCD1_CONFIGURATION 0x3CA0 /* Configure power mode of LCD1 */ |
211 | df91b48f | Maksim Kozlov | #define LCD1_STATUS 0x3CA4 /* Check power mode of LCD1 */ |
212 | df91b48f | Maksim Kozlov | #define LCD1_OPTION 0x3CA8 /* Sets control options for LCD1 */ |
213 | df91b48f | Maksim Kozlov | #define GPS_CONFIGURATION 0x3CE0 /* Configure power mode of GPS */ |
214 | df91b48f | Maksim Kozlov | #define GPS_STATUS 0x3CE4 /* Check power mode of GPS */ |
215 | df91b48f | Maksim Kozlov | #define GPS_OPTION 0x3CE8 /* Sets control options for GPS */ |
216 | df91b48f | Maksim Kozlov | #define GPS_ALIVE_CONFIGURATION 0x3D00 /* Configure power mode of GPS */ |
217 | df91b48f | Maksim Kozlov | #define GPS_ALIVE_STATUS 0x3D04 /* Check power mode of GPS */ |
218 | df91b48f | Maksim Kozlov | #define GPS_ALIVE_OPTION 0x3D08 /* Sets control options for GPS */ |
219 | df91b48f | Maksim Kozlov | |
220 | df91b48f | Maksim Kozlov | #define EXYNOS4210_PMU_REGS_MEM_SIZE 0x3d0c |
221 | df91b48f | Maksim Kozlov | |
222 | df91b48f | Maksim Kozlov | typedef struct Exynos4210PmuReg { |
223 | df91b48f | Maksim Kozlov | const char *name; /* for debug only */ |
224 | df91b48f | Maksim Kozlov | uint32_t offset; |
225 | df91b48f | Maksim Kozlov | uint32_t reset_value; |
226 | df91b48f | Maksim Kozlov | } Exynos4210PmuReg; |
227 | df91b48f | Maksim Kozlov | |
228 | df91b48f | Maksim Kozlov | static const Exynos4210PmuReg exynos4210_pmu_regs[] = { |
229 | df91b48f | Maksim Kozlov | {"OM_STAT", OM_STAT, 0x00000000}, |
230 | df91b48f | Maksim Kozlov | {"RTC_CLKO_SEL", RTC_CLKO_SEL, 0x00000000}, |
231 | df91b48f | Maksim Kozlov | {"GNSS_RTC_OUT_CTRL", GNSS_RTC_OUT_CTRL, 0x00000001}, |
232 | df91b48f | Maksim Kozlov | {"SYSTEM_POWER_DOWN_CTRL", SYSTEM_POWER_DOWN_CTRL, 0x00010000}, |
233 | df91b48f | Maksim Kozlov | {"SYSTEM_POWER_DOWN_OPTION", SYSTEM_POWER_DOWN_OPTION, 0x03030000}, |
234 | df91b48f | Maksim Kozlov | {"SWRESET", SWRESET, 0x00000000}, |
235 | df91b48f | Maksim Kozlov | {"RST_STAT", RST_STAT, 0x00000000}, |
236 | df91b48f | Maksim Kozlov | {"WAKEUP_STAT", WAKEUP_STAT, 0x00000000}, |
237 | df91b48f | Maksim Kozlov | {"EINT_WAKEUP_MASK", EINT_WAKEUP_MASK, 0x00000000}, |
238 | df91b48f | Maksim Kozlov | {"WAKEUP_MASK", WAKEUP_MASK, 0x00000000}, |
239 | df91b48f | Maksim Kozlov | {"HDMI_PHY_CONTROL", HDMI_PHY_CONTROL, 0x00960000}, |
240 | df91b48f | Maksim Kozlov | {"USBDEVICE_PHY_CONTROL", USBDEVICE_PHY_CONTROL, 0x00000000}, |
241 | df91b48f | Maksim Kozlov | {"USBHOST_PHY_CONTROL", USBHOST_PHY_CONTROL, 0x00000000}, |
242 | df91b48f | Maksim Kozlov | {"DAC_PHY_CONTROL", DAC_PHY_CONTROL, 0x00000000}, |
243 | df91b48f | Maksim Kozlov | {"MIPI_PHY0_CONTROL", MIPI_PHY0_CONTROL, 0x00000000}, |
244 | df91b48f | Maksim Kozlov | {"MIPI_PHY1_CONTROL", MIPI_PHY1_CONTROL, 0x00000000}, |
245 | df91b48f | Maksim Kozlov | {"ADC_PHY_CONTROL", ADC_PHY_CONTROL, 0x00000001}, |
246 | df91b48f | Maksim Kozlov | {"PCIe_PHY_CONTROL", PCIe_PHY_CONTROL, 0x00000000}, |
247 | df91b48f | Maksim Kozlov | {"SATA_PHY_CONTROL", SATA_PHY_CONTROL, 0x00000000}, |
248 | df91b48f | Maksim Kozlov | {"INFORM0", INFORM0, 0x00000000}, |
249 | df91b48f | Maksim Kozlov | {"INFORM1", INFORM1, 0x00000000}, |
250 | df91b48f | Maksim Kozlov | {"INFORM2", INFORM2, 0x00000000}, |
251 | df91b48f | Maksim Kozlov | {"INFORM3", INFORM3, 0x00000000}, |
252 | df91b48f | Maksim Kozlov | {"INFORM4", INFORM4, 0x00000000}, |
253 | df91b48f | Maksim Kozlov | {"INFORM5", INFORM5, 0x00000000}, |
254 | df91b48f | Maksim Kozlov | {"INFORM6", INFORM6, 0x00000000}, |
255 | df91b48f | Maksim Kozlov | {"INFORM7", INFORM7, 0x00000000}, |
256 | df91b48f | Maksim Kozlov | {"PMU_DEBUG", PMU_DEBUG, 0x00000000}, |
257 | df91b48f | Maksim Kozlov | {"ARM_CORE0_SYS_PWR_REG", ARM_CORE0_SYS_PWR_REG, 0xFFFFFFFF}, |
258 | df91b48f | Maksim Kozlov | {"ARM_CORE1_SYS_PWR_REG", ARM_CORE1_SYS_PWR_REG, 0xFFFFFFFF}, |
259 | df91b48f | Maksim Kozlov | {"ARM_COMMON_SYS_PWR_REG", ARM_COMMON_SYS_PWR_REG, 0xFFFFFFFF}, |
260 | df91b48f | Maksim Kozlov | {"ARM_CPU_L2_0_SYS_PWR_REG", ARM_CPU_L2_0_SYS_PWR_REG, 0xFFFFFFFF}, |
261 | df91b48f | Maksim Kozlov | {"ARM_CPU_L2_1_SYS_PWR_REG", ARM_CPU_L2_1_SYS_PWR_REG, 0xFFFFFFFF}, |
262 | df91b48f | Maksim Kozlov | {"CMU_ACLKSTOP_SYS_PWR_REG", CMU_ACLKSTOP_SYS_PWR_REG, 0xFFFFFFFF}, |
263 | df91b48f | Maksim Kozlov | {"CMU_SCLKSTOP_SYS_PWR_REG", CMU_SCLKSTOP_SYS_PWR_REG, 0xFFFFFFFF}, |
264 | df91b48f | Maksim Kozlov | {"CMU_RESET_SYS_PWR_REG", CMU_RESET_SYS_PWR_REG, 0xFFFFFFFF}, |
265 | df91b48f | Maksim Kozlov | {"APLL_SYSCLK_SYS_PWR_REG", APLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF}, |
266 | df91b48f | Maksim Kozlov | {"MPLL_SYSCLK_SYS_PWR_REG", MPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF}, |
267 | df91b48f | Maksim Kozlov | {"VPLL_SYSCLK_SYS_PWR_REG", VPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF}, |
268 | df91b48f | Maksim Kozlov | {"EPLL_SYSCLK_SYS_PWR_REG", EPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF}, |
269 | df91b48f | Maksim Kozlov | {"CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG", CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG,
|
270 | df91b48f | Maksim Kozlov | 0xFFFFFFFF},
|
271 | df91b48f | Maksim Kozlov | {"CMU_RESET_GPS_ALIVE_SYS_PWR_REG", CMU_RESET_GPS_ALIVE_SYS_PWR_REG,
|
272 | df91b48f | Maksim Kozlov | 0xFFFFFFFF},
|
273 | df91b48f | Maksim Kozlov | {"CMU_CLKSTOP_CAM_SYS_PWR_REG", CMU_CLKSTOP_CAM_SYS_PWR_REG, 0xFFFFFFFF}, |
274 | df91b48f | Maksim Kozlov | {"CMU_CLKSTOP_TV_SYS_PWR_REG", CMU_CLKSTOP_TV_SYS_PWR_REG, 0xFFFFFFFF}, |
275 | df91b48f | Maksim Kozlov | {"CMU_CLKSTOP_MFC_SYS_PWR_REG", CMU_CLKSTOP_MFC_SYS_PWR_REG, 0xFFFFFFFF}, |
276 | df91b48f | Maksim Kozlov | {"CMU_CLKSTOP_G3D_SYS_PWR_REG", CMU_CLKSTOP_G3D_SYS_PWR_REG, 0xFFFFFFFF}, |
277 | df91b48f | Maksim Kozlov | {"CMU_CLKSTOP_LCD0_SYS_PWR_REG", CMU_CLKSTOP_LCD0_SYS_PWR_REG, 0xFFFFFFFF}, |
278 | df91b48f | Maksim Kozlov | {"CMU_CLKSTOP_LCD1_SYS_PWR_REG", CMU_CLKSTOP_LCD1_SYS_PWR_REG, 0xFFFFFFFF}, |
279 | df91b48f | Maksim Kozlov | {"CMU_CLKSTOP_MAUDIO_SYS_PWR_REG", CMU_CLKSTOP_MAUDIO_SYS_PWR_REG,
|
280 | df91b48f | Maksim Kozlov | 0xFFFFFFFF},
|
281 | df91b48f | Maksim Kozlov | {"CMU_CLKSTOP_GPS_SYS_PWR_REG", CMU_CLKSTOP_GPS_SYS_PWR_REG, 0xFFFFFFFF}, |
282 | df91b48f | Maksim Kozlov | {"CMU_RESET_CAM_SYS_PWR_REG", CMU_RESET_CAM_SYS_PWR_REG, 0xFFFFFFFF}, |
283 | df91b48f | Maksim Kozlov | {"CMU_RESET_TV_SYS_PWR_REG", CMU_RESET_TV_SYS_PWR_REG, 0xFFFFFFFF}, |
284 | df91b48f | Maksim Kozlov | {"CMU_RESET_MFC_SYS_PWR_REG", CMU_RESET_MFC_SYS_PWR_REG, 0xFFFFFFFF}, |
285 | df91b48f | Maksim Kozlov | {"CMU_RESET_G3D_SYS_PWR_REG", CMU_RESET_G3D_SYS_PWR_REG, 0xFFFFFFFF}, |
286 | df91b48f | Maksim Kozlov | {"CMU_RESET_LCD0_SYS_PWR_REG", CMU_RESET_LCD0_SYS_PWR_REG, 0xFFFFFFFF}, |
287 | df91b48f | Maksim Kozlov | {"CMU_RESET_LCD1_SYS_PWR_REG", CMU_RESET_LCD1_SYS_PWR_REG, 0xFFFFFFFF}, |
288 | df91b48f | Maksim Kozlov | {"CMU_RESET_MAUDIO_SYS_PWR_REG", CMU_RESET_MAUDIO_SYS_PWR_REG, 0xFFFFFFFF}, |
289 | df91b48f | Maksim Kozlov | {"CMU_RESET_GPS_SYS_PWR_REG", CMU_RESET_GPS_SYS_PWR_REG, 0xFFFFFFFF}, |
290 | df91b48f | Maksim Kozlov | {"TOP_BUS_SYS_PWR_REG", TOP_BUS_SYS_PWR_REG, 0xFFFFFFFF}, |
291 | df91b48f | Maksim Kozlov | {"TOP_RETENTION_SYS_PWR_REG", TOP_RETENTION_SYS_PWR_REG, 0xFFFFFFFF}, |
292 | df91b48f | Maksim Kozlov | {"TOP_PWR_SYS_PWR_REG", TOP_PWR_SYS_PWR_REG, 0xFFFFFFFF}, |
293 | df91b48f | Maksim Kozlov | {"LOGIC_RESET_SYS_PWR_REG", LOGIC_RESET_SYS_PWR_REG, 0xFFFFFFFF}, |
294 | df91b48f | Maksim Kozlov | {"OneNANDXL_MEM_SYS_PWR_REG", OneNANDXL_MEM_SYS_PWR_REG, 0xFFFFFFFF}, |
295 | df91b48f | Maksim Kozlov | {"MODEMIF_MEM_SYS_PWR_REG", MODEMIF_MEM_SYS_PWR_REG, 0xFFFFFFFF}, |
296 | df91b48f | Maksim Kozlov | {"USBDEVICE_MEM_SYS_PWR_REG", USBDEVICE_MEM_SYS_PWR_REG, 0xFFFFFFFF}, |
297 | df91b48f | Maksim Kozlov | {"SDMMC_MEM_SYS_PWR_REG", SDMMC_MEM_SYS_PWR_REG, 0xFFFFFFFF}, |
298 | df91b48f | Maksim Kozlov | {"CSSYS_MEM_SYS_PWR_REG", CSSYS_MEM_SYS_PWR_REG, 0xFFFFFFFF}, |
299 | df91b48f | Maksim Kozlov | {"SECSS_MEM_SYS_PWR_REG", SECSS_MEM_SYS_PWR_REG, 0xFFFFFFFF}, |
300 | df91b48f | Maksim Kozlov | {"PCIe_MEM_SYS_PWR_REG", PCIe_MEM_SYS_PWR_REG, 0xFFFFFFFF}, |
301 | df91b48f | Maksim Kozlov | {"SATA_MEM_SYS_PWR_REG", SATA_MEM_SYS_PWR_REG, 0xFFFFFFFF}, |
302 | df91b48f | Maksim Kozlov | {"PAD_RETENTION_DRAM_SYS_PWR_REG", PAD_RETENTION_DRAM_SYS_PWR_REG,
|
303 | df91b48f | Maksim Kozlov | 0xFFFFFFFF},
|
304 | df91b48f | Maksim Kozlov | {"PAD_RETENTION_MAUDIO_SYS_PWR_REG", PAD_RETENTION_MAUDIO_SYS_PWR_REG,
|
305 | df91b48f | Maksim Kozlov | 0xFFFFFFFF},
|
306 | df91b48f | Maksim Kozlov | {"PAD_RETENTION_GPIO_SYS_PWR_REG", PAD_RETENTION_GPIO_SYS_PWR_REG,
|
307 | df91b48f | Maksim Kozlov | 0xFFFFFFFF},
|
308 | df91b48f | Maksim Kozlov | {"PAD_RETENTION_UART_SYS_PWR_REG", PAD_RETENTION_UART_SYS_PWR_REG,
|
309 | df91b48f | Maksim Kozlov | 0xFFFFFFFF},
|
310 | df91b48f | Maksim Kozlov | {"PAD_RETENTION_MMCA_SYS_PWR_REG", PAD_RETENTION_MMCA_SYS_PWR_REG,
|
311 | df91b48f | Maksim Kozlov | 0xFFFFFFFF},
|
312 | df91b48f | Maksim Kozlov | {"PAD_RETENTION_MMCB_SYS_PWR_REG", PAD_RETENTION_MMCB_SYS_PWR_REG,
|
313 | df91b48f | Maksim Kozlov | 0xFFFFFFFF},
|
314 | df91b48f | Maksim Kozlov | {"PAD_RETENTION_EBIA_SYS_PWR_REG", PAD_RETENTION_EBIA_SYS_PWR_REG,
|
315 | df91b48f | Maksim Kozlov | 0xFFFFFFFF},
|
316 | df91b48f | Maksim Kozlov | {"PAD_RETENTION_EBIB_SYS_PWR_REG", PAD_RETENTION_EBIB_SYS_PWR_REG,
|
317 | df91b48f | Maksim Kozlov | 0xFFFFFFFF},
|
318 | df91b48f | Maksim Kozlov | {"PAD_ISOLATION_SYS_PWR_REG", PAD_ISOLATION_SYS_PWR_REG, 0xFFFFFFFF}, |
319 | df91b48f | Maksim Kozlov | {"PAD_ALV_SEL_SYS_PWR_REG", PAD_ALV_SEL_SYS_PWR_REG, 0xFFFFFFFF}, |
320 | df91b48f | Maksim Kozlov | {"XUSBXTI_SYS_PWR_REG", XUSBXTI_SYS_PWR_REG, 0xFFFFFFFF}, |
321 | df91b48f | Maksim Kozlov | {"XXTI_SYS_PWR_REG", XXTI_SYS_PWR_REG, 0xFFFFFFFF}, |
322 | df91b48f | Maksim Kozlov | {"EXT_REGULATOR_SYS_PWR_REG", EXT_REGULATOR_SYS_PWR_REG, 0xFFFFFFFF}, |
323 | df91b48f | Maksim Kozlov | {"GPIO_MODE_SYS_PWR_REG", GPIO_MODE_SYS_PWR_REG, 0xFFFFFFFF}, |
324 | df91b48f | Maksim Kozlov | {"GPIO_MODE_MAUDIO_SYS_PWR_REG", GPIO_MODE_MAUDIO_SYS_PWR_REG, 0xFFFFFFFF}, |
325 | df91b48f | Maksim Kozlov | {"CAM_SYS_PWR_REG", CAM_SYS_PWR_REG, 0xFFFFFFFF}, |
326 | df91b48f | Maksim Kozlov | {"TV_SYS_PWR_REG", TV_SYS_PWR_REG, 0xFFFFFFFF}, |
327 | df91b48f | Maksim Kozlov | {"MFC_SYS_PWR_REG", MFC_SYS_PWR_REG, 0xFFFFFFFF}, |
328 | df91b48f | Maksim Kozlov | {"G3D_SYS_PWR_REG", G3D_SYS_PWR_REG, 0xFFFFFFFF}, |
329 | df91b48f | Maksim Kozlov | {"LCD0_SYS_PWR_REG", LCD0_SYS_PWR_REG, 0xFFFFFFFF}, |
330 | df91b48f | Maksim Kozlov | {"LCD1_SYS_PWR_REG", LCD1_SYS_PWR_REG, 0xFFFFFFFF}, |
331 | df91b48f | Maksim Kozlov | {"MAUDIO_SYS_PWR_REG", MAUDIO_SYS_PWR_REG, 0xFFFFFFFF}, |
332 | df91b48f | Maksim Kozlov | {"GPS_SYS_PWR_REG", GPS_SYS_PWR_REG, 0xFFFFFFFF}, |
333 | df91b48f | Maksim Kozlov | {"GPS_ALIVE_SYS_PWR_REG", GPS_ALIVE_SYS_PWR_REG, 0xFFFFFFFF}, |
334 | df91b48f | Maksim Kozlov | {"ARM_CORE0_CONFIGURATION", ARM_CORE0_CONFIGURATION, 0x00000003}, |
335 | df91b48f | Maksim Kozlov | {"ARM_CORE0_STATUS", ARM_CORE0_STATUS, 0x00030003}, |
336 | df91b48f | Maksim Kozlov | {"ARM_CORE0_OPTION", ARM_CORE0_OPTION, 0x01010001}, |
337 | df91b48f | Maksim Kozlov | {"ARM_CORE1_CONFIGURATION", ARM_CORE1_CONFIGURATION, 0x00000003}, |
338 | df91b48f | Maksim Kozlov | {"ARM_CORE1_STATUS", ARM_CORE1_STATUS, 0x00030003}, |
339 | df91b48f | Maksim Kozlov | {"ARM_CORE1_OPTION", ARM_CORE1_OPTION, 0x01010001}, |
340 | df91b48f | Maksim Kozlov | {"ARM_COMMON_OPTION", ARM_COMMON_OPTION, 0x00000001}, |
341 | df91b48f | Maksim Kozlov | {"ARM_CPU_L2_0_CONFIGURATION", ARM_CPU_L2_0_CONFIGURATION, 0x00000003}, |
342 | df91b48f | Maksim Kozlov | {"ARM_CPU_L2_0_STATUS", ARM_CPU_L2_0_STATUS, 0x00000003}, |
343 | df91b48f | Maksim Kozlov | {"ARM_CPU_L2_1_CONFIGURATION", ARM_CPU_L2_1_CONFIGURATION, 0x00000003}, |
344 | df91b48f | Maksim Kozlov | {"ARM_CPU_L2_1_STATUS", ARM_CPU_L2_1_STATUS, 0x00000003}, |
345 | df91b48f | Maksim Kozlov | {"PAD_RETENTION_MAUDIO_OPTION", PAD_RETENTION_MAUDIO_OPTION, 0x00000000}, |
346 | df91b48f | Maksim Kozlov | {"PAD_RETENTION_GPIO_OPTION", PAD_RETENTION_GPIO_OPTION, 0x00000000}, |
347 | df91b48f | Maksim Kozlov | {"PAD_RETENTION_UART_OPTION", PAD_RETENTION_UART_OPTION, 0x00000000}, |
348 | df91b48f | Maksim Kozlov | {"PAD_RETENTION_MMCA_OPTION", PAD_RETENTION_MMCA_OPTION, 0x00000000}, |
349 | df91b48f | Maksim Kozlov | {"PAD_RETENTION_MMCB_OPTION", PAD_RETENTION_MMCB_OPTION, 0x00000000}, |
350 | df91b48f | Maksim Kozlov | {"PAD_RETENTION_EBIA_OPTION", PAD_RETENTION_EBIA_OPTION, 0x00000000}, |
351 | df91b48f | Maksim Kozlov | {"PAD_RETENTION_EBIB_OPTION", PAD_RETENTION_EBIB_OPTION, 0x00000000}, |
352 | df91b48f | Maksim Kozlov | {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200}, |
353 | df91b48f | Maksim Kozlov | {"XUSBXTI_CONFIGURATION", XUSBXTI_CONFIGURATION, 0x00000001}, |
354 | df91b48f | Maksim Kozlov | {"XUSBXTI_STATUS", XUSBXTI_STATUS, 0x00000001}, |
355 | df91b48f | Maksim Kozlov | {"XUSBXTI_DURATION", XUSBXTI_DURATION, 0xFFF00000}, |
356 | df91b48f | Maksim Kozlov | {"XXTI_CONFIGURATION", XXTI_CONFIGURATION, 0x00000001}, |
357 | df91b48f | Maksim Kozlov | {"XXTI_STATUS", XXTI_STATUS, 0x00000001}, |
358 | df91b48f | Maksim Kozlov | {"XXTI_DURATION", XXTI_DURATION, 0xFFF00000}, |
359 | df91b48f | Maksim Kozlov | {"EXT_REGULATOR_DURATION", EXT_REGULATOR_DURATION, 0xFFF03FFF}, |
360 | df91b48f | Maksim Kozlov | {"CAM_CONFIGURATION", CAM_CONFIGURATION, 0x00000007}, |
361 | df91b48f | Maksim Kozlov | {"CAM_STATUS", CAM_STATUS, 0x00060007}, |
362 | df91b48f | Maksim Kozlov | {"CAM_OPTION", CAM_OPTION, 0x00000001}, |
363 | df91b48f | Maksim Kozlov | {"TV_CONFIGURATION", TV_CONFIGURATION, 0x00000007}, |
364 | df91b48f | Maksim Kozlov | {"TV_STATUS", TV_STATUS, 0x00060007}, |
365 | df91b48f | Maksim Kozlov | {"TV_OPTION", TV_OPTION, 0x00000001}, |
366 | df91b48f | Maksim Kozlov | {"MFC_CONFIGURATION", MFC_CONFIGURATION, 0x00000007}, |
367 | df91b48f | Maksim Kozlov | {"MFC_STATUS", MFC_STATUS, 0x00060007}, |
368 | df91b48f | Maksim Kozlov | {"MFC_OPTION", MFC_OPTION, 0x00000001}, |
369 | df91b48f | Maksim Kozlov | {"G3D_CONFIGURATION", G3D_CONFIGURATION, 0x00000007}, |
370 | df91b48f | Maksim Kozlov | {"G3D_STATUS", G3D_STATUS, 0x00060007}, |
371 | df91b48f | Maksim Kozlov | {"G3D_OPTION", G3D_OPTION, 0x00000001}, |
372 | df91b48f | Maksim Kozlov | {"LCD0_CONFIGURATION", LCD0_CONFIGURATION, 0x00000007}, |
373 | df91b48f | Maksim Kozlov | {"LCD0_STATUS", LCD0_STATUS, 0x00060007}, |
374 | df91b48f | Maksim Kozlov | {"LCD0_OPTION", LCD0_OPTION, 0x00000001}, |
375 | df91b48f | Maksim Kozlov | {"LCD1_CONFIGURATION", LCD1_CONFIGURATION, 0x00000007}, |
376 | df91b48f | Maksim Kozlov | {"LCD1_STATUS", LCD1_STATUS, 0x00060007}, |
377 | df91b48f | Maksim Kozlov | {"LCD1_OPTION", LCD1_OPTION, 0x00000001}, |
378 | df91b48f | Maksim Kozlov | {"GPS_CONFIGURATION", GPS_CONFIGURATION, 0x00000007}, |
379 | df91b48f | Maksim Kozlov | {"GPS_STATUS", GPS_STATUS, 0x00060007}, |
380 | df91b48f | Maksim Kozlov | {"GPS_OPTION", GPS_OPTION, 0x00000001}, |
381 | df91b48f | Maksim Kozlov | {"GPS_ALIVE_CONFIGURATION", GPS_ALIVE_CONFIGURATION, 0x00000007}, |
382 | df91b48f | Maksim Kozlov | {"GPS_ALIVE_STATUS", GPS_ALIVE_STATUS, 0x00060007}, |
383 | df91b48f | Maksim Kozlov | {"GPS_ALIVE_OPTION", GPS_ALIVE_OPTION, 0x00000001}, |
384 | df91b48f | Maksim Kozlov | }; |
385 | df91b48f | Maksim Kozlov | |
386 | df91b48f | Maksim Kozlov | #define PMU_NUM_OF_REGISTERS \
|
387 | df91b48f | Maksim Kozlov | (sizeof(exynos4210_pmu_regs) / sizeof(Exynos4210PmuReg)) |
388 | df91b48f | Maksim Kozlov | |
389 | df91b48f | Maksim Kozlov | typedef struct Exynos4210PmuState { |
390 | df91b48f | Maksim Kozlov | SysBusDevice busdev; |
391 | df91b48f | Maksim Kozlov | MemoryRegion iomem; |
392 | df91b48f | Maksim Kozlov | uint32_t reg[PMU_NUM_OF_REGISTERS]; |
393 | df91b48f | Maksim Kozlov | } Exynos4210PmuState; |
394 | df91b48f | Maksim Kozlov | |
395 | a8170e5e | Avi Kivity | static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset, |
396 | df91b48f | Maksim Kozlov | unsigned size)
|
397 | df91b48f | Maksim Kozlov | { |
398 | df91b48f | Maksim Kozlov | Exynos4210PmuState *s = (Exynos4210PmuState *)opaque; |
399 | df91b48f | Maksim Kozlov | unsigned i;
|
400 | df91b48f | Maksim Kozlov | const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
|
401 | df91b48f | Maksim Kozlov | |
402 | df91b48f | Maksim Kozlov | for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) { |
403 | df91b48f | Maksim Kozlov | if (reg_p->offset == offset) {
|
404 | df91b48f | Maksim Kozlov | PRINT_DEBUG_EXTEND("%s [0x%04x] -> 0x%04x\n", reg_p->name,
|
405 | df91b48f | Maksim Kozlov | (uint32_t)offset, s->reg[i]); |
406 | df91b48f | Maksim Kozlov | return s->reg[i];
|
407 | df91b48f | Maksim Kozlov | } |
408 | df91b48f | Maksim Kozlov | reg_p++; |
409 | df91b48f | Maksim Kozlov | } |
410 | df91b48f | Maksim Kozlov | PRINT_DEBUG("QEMU PMU ERROR: bad read offset 0x%04x\n", (uint32_t)offset);
|
411 | df91b48f | Maksim Kozlov | return 0; |
412 | df91b48f | Maksim Kozlov | } |
413 | df91b48f | Maksim Kozlov | |
414 | a8170e5e | Avi Kivity | static void exynos4210_pmu_write(void *opaque, hwaddr offset, |
415 | df91b48f | Maksim Kozlov | uint64_t val, unsigned size)
|
416 | df91b48f | Maksim Kozlov | { |
417 | df91b48f | Maksim Kozlov | Exynos4210PmuState *s = (Exynos4210PmuState *)opaque; |
418 | df91b48f | Maksim Kozlov | unsigned i;
|
419 | df91b48f | Maksim Kozlov | const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
|
420 | df91b48f | Maksim Kozlov | |
421 | df91b48f | Maksim Kozlov | for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) { |
422 | df91b48f | Maksim Kozlov | if (reg_p->offset == offset) {
|
423 | df91b48f | Maksim Kozlov | PRINT_DEBUG_EXTEND("%s <0x%04x> <- 0x%04x\n", reg_p->name,
|
424 | df91b48f | Maksim Kozlov | (uint32_t)offset, (uint32_t)val); |
425 | df91b48f | Maksim Kozlov | s->reg[i] = val; |
426 | df91b48f | Maksim Kozlov | return;
|
427 | df91b48f | Maksim Kozlov | } |
428 | df91b48f | Maksim Kozlov | reg_p++; |
429 | df91b48f | Maksim Kozlov | } |
430 | df91b48f | Maksim Kozlov | PRINT_DEBUG("QEMU PMU ERROR: bad write offset 0x%04x\n", (uint32_t)offset);
|
431 | df91b48f | Maksim Kozlov | } |
432 | df91b48f | Maksim Kozlov | |
433 | df91b48f | Maksim Kozlov | static const MemoryRegionOps exynos4210_pmu_ops = { |
434 | df91b48f | Maksim Kozlov | .read = exynos4210_pmu_read, |
435 | df91b48f | Maksim Kozlov | .write = exynos4210_pmu_write, |
436 | df91b48f | Maksim Kozlov | .endianness = DEVICE_NATIVE_ENDIAN, |
437 | df91b48f | Maksim Kozlov | .valid = { |
438 | df91b48f | Maksim Kozlov | .min_access_size = 4,
|
439 | df91b48f | Maksim Kozlov | .max_access_size = 4,
|
440 | df91b48f | Maksim Kozlov | .unaligned = false
|
441 | df91b48f | Maksim Kozlov | } |
442 | df91b48f | Maksim Kozlov | }; |
443 | df91b48f | Maksim Kozlov | |
444 | df91b48f | Maksim Kozlov | static void exynos4210_pmu_reset(DeviceState *dev) |
445 | df91b48f | Maksim Kozlov | { |
446 | df91b48f | Maksim Kozlov | Exynos4210PmuState *s = |
447 | df91b48f | Maksim Kozlov | container_of(dev, Exynos4210PmuState, busdev.qdev); |
448 | df91b48f | Maksim Kozlov | unsigned i;
|
449 | df91b48f | Maksim Kozlov | |
450 | df91b48f | Maksim Kozlov | /* Set default values for registers */
|
451 | df91b48f | Maksim Kozlov | for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) { |
452 | df91b48f | Maksim Kozlov | s->reg[i] = exynos4210_pmu_regs[i].reset_value; |
453 | df91b48f | Maksim Kozlov | } |
454 | df91b48f | Maksim Kozlov | } |
455 | df91b48f | Maksim Kozlov | |
456 | df91b48f | Maksim Kozlov | static int exynos4210_pmu_init(SysBusDevice *dev) |
457 | df91b48f | Maksim Kozlov | { |
458 | df91b48f | Maksim Kozlov | Exynos4210PmuState *s = FROM_SYSBUS(Exynos4210PmuState, dev); |
459 | df91b48f | Maksim Kozlov | |
460 | df91b48f | Maksim Kozlov | /* memory mapping */
|
461 | df91b48f | Maksim Kozlov | memory_region_init_io(&s->iomem, &exynos4210_pmu_ops, s, "exynos4210.pmu",
|
462 | df91b48f | Maksim Kozlov | EXYNOS4210_PMU_REGS_MEM_SIZE); |
463 | df91b48f | Maksim Kozlov | sysbus_init_mmio(dev, &s->iomem); |
464 | df91b48f | Maksim Kozlov | return 0; |
465 | df91b48f | Maksim Kozlov | } |
466 | df91b48f | Maksim Kozlov | |
467 | df91b48f | Maksim Kozlov | static const VMStateDescription exynos4210_pmu_vmstate = { |
468 | df91b48f | Maksim Kozlov | .name = "exynos4210.pmu",
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469 | df91b48f | Maksim Kozlov | .version_id = 1,
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470 | df91b48f | Maksim Kozlov | .minimum_version_id = 1,
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471 | df91b48f | Maksim Kozlov | .fields = (VMStateField[]) { |
472 | df91b48f | Maksim Kozlov | VMSTATE_UINT32_ARRAY(reg, Exynos4210PmuState, PMU_NUM_OF_REGISTERS), |
473 | df91b48f | Maksim Kozlov | VMSTATE_END_OF_LIST() |
474 | df91b48f | Maksim Kozlov | } |
475 | df91b48f | Maksim Kozlov | }; |
476 | df91b48f | Maksim Kozlov | |
477 | df91b48f | Maksim Kozlov | static void exynos4210_pmu_class_init(ObjectClass *klass, void *data) |
478 | df91b48f | Maksim Kozlov | { |
479 | df91b48f | Maksim Kozlov | DeviceClass *dc = DEVICE_CLASS(klass); |
480 | df91b48f | Maksim Kozlov | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
481 | df91b48f | Maksim Kozlov | |
482 | df91b48f | Maksim Kozlov | k->init = exynos4210_pmu_init; |
483 | df91b48f | Maksim Kozlov | dc->reset = exynos4210_pmu_reset; |
484 | df91b48f | Maksim Kozlov | dc->vmsd = &exynos4210_pmu_vmstate; |
485 | df91b48f | Maksim Kozlov | } |
486 | df91b48f | Maksim Kozlov | |
487 | 8c43a6f0 | Andreas Färber | static const TypeInfo exynos4210_pmu_info = { |
488 | df91b48f | Maksim Kozlov | .name = "exynos4210.pmu",
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489 | df91b48f | Maksim Kozlov | .parent = TYPE_SYS_BUS_DEVICE, |
490 | df91b48f | Maksim Kozlov | .instance_size = sizeof(Exynos4210PmuState),
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491 | df91b48f | Maksim Kozlov | .class_init = exynos4210_pmu_class_init, |
492 | df91b48f | Maksim Kozlov | }; |
493 | df91b48f | Maksim Kozlov | |
494 | df91b48f | Maksim Kozlov | static void exynos4210_pmu_register(void) |
495 | df91b48f | Maksim Kozlov | { |
496 | df91b48f | Maksim Kozlov | type_register_static(&exynos4210_pmu_info); |
497 | df91b48f | Maksim Kozlov | } |
498 | df91b48f | Maksim Kozlov | |
499 | df91b48f | Maksim Kozlov | type_init(exynos4210_pmu_register) |