root / hw / dma / xilinx_axidma.c @ f487b677
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/*
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* QEMU model of Xilinx AXI-DMA block.
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*
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* Copyright (c) 2011 Edgar E. Iglesias.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/sysbus.h" |
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#include "qemu/timer.h" |
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#include "hw/ptimer.h" |
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#include "qemu/log.h" |
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#include "qapi/qmp/qerror.h" |
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#include "hw/stream.h" |
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#define D(x)
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#define TYPE_XILINX_AXI_DMA "xlnx.axi-dma" |
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#define TYPE_XILINX_AXI_DMA_DATA_STREAM "xilinx-axi-dma-data-stream" |
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#define TYPE_XILINX_AXI_DMA_CONTROL_STREAM "xilinx-axi-dma-control-stream" |
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#define XILINX_AXI_DMA(obj) \
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OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA) |
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#define XILINX_AXI_DMA_DATA_STREAM(obj) \
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OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\ |
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TYPE_XILINX_AXI_DMA_DATA_STREAM) |
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#define XILINX_AXI_DMA_CONTROL_STREAM(obj) \
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OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\ |
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TYPE_XILINX_AXI_DMA_CONTROL_STREAM) |
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#define R_DMACR (0x00 / 4) |
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#define R_DMASR (0x04 / 4) |
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#define R_CURDESC (0x08 / 4) |
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#define R_TAILDESC (0x10 / 4) |
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#define R_MAX (0x30 / 4) |
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#define CONTROL_PAYLOAD_WORDS 5 |
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#define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t))) |
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typedef struct XilinxAXIDMA XilinxAXIDMA; |
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typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave; |
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enum {
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DMACR_RUNSTOP = 1,
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DMACR_TAILPTR_MODE = 2,
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DMACR_RESET = 4
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}; |
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enum {
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DMASR_HALTED = 1,
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DMASR_IDLE = 2,
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DMASR_IOC_IRQ = 1 << 12, |
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DMASR_DLY_IRQ = 1 << 13, |
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DMASR_IRQ_MASK = 7 << 12 |
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}; |
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struct SDesc {
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uint64_t nxtdesc; |
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uint64_t buffer_address; |
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uint64_t reserved; |
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uint32_t control; |
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uint32_t status; |
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uint8_t app[CONTROL_PAYLOAD_SIZE]; |
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}; |
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enum {
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SDESC_CTRL_EOF = (1 << 26), |
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SDESC_CTRL_SOF = (1 << 27), |
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SDESC_CTRL_LEN_MASK = (1 << 23) - 1 |
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}; |
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enum {
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SDESC_STATUS_EOF = (1 << 26), |
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SDESC_STATUS_SOF_BIT = 27,
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SDESC_STATUS_SOF = (1 << SDESC_STATUS_SOF_BIT),
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SDESC_STATUS_COMPLETE = (1 << 31) |
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}; |
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struct Stream {
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QEMUBH *bh; |
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ptimer_state *ptimer; |
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qemu_irq irq; |
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int nr;
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struct SDesc desc;
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int pos;
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unsigned int complete_cnt; |
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uint32_t regs[R_MAX]; |
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uint8_t app[20];
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}; |
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struct XilinxAXIDMAStreamSlave {
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Object parent; |
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struct XilinxAXIDMA *dma;
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}; |
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struct XilinxAXIDMA {
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SysBusDevice busdev; |
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MemoryRegion iomem; |
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uint32_t freqhz; |
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StreamSlave *tx_data_dev; |
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StreamSlave *tx_control_dev; |
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XilinxAXIDMAStreamSlave rx_data_dev; |
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XilinxAXIDMAStreamSlave rx_control_dev; |
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struct Stream streams[2]; |
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StreamCanPushNotifyFn notify; |
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void *notify_opaque;
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}; |
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/*
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* Helper calls to extract info from desriptors and other trivial
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* state from regs.
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*/
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static inline int stream_desc_sof(struct SDesc *d) |
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{ |
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return d->control & SDESC_CTRL_SOF;
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} |
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static inline int stream_desc_eof(struct SDesc *d) |
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{ |
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return d->control & SDESC_CTRL_EOF;
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} |
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static inline int stream_resetting(struct Stream *s) |
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{ |
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return !!(s->regs[R_DMACR] & DMACR_RESET);
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} |
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static inline int stream_running(struct Stream *s) |
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{ |
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return s->regs[R_DMACR] & DMACR_RUNSTOP;
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} |
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static inline int stream_halted(struct Stream *s) |
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{ |
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return s->regs[R_DMASR] & DMASR_HALTED;
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} |
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static inline int stream_idle(struct Stream *s) |
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{ |
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return !!(s->regs[R_DMASR] & DMASR_IDLE);
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} |
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static void stream_reset(struct Stream *s) |
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{ |
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s->regs[R_DMASR] = DMASR_HALTED; /* starts up halted. */
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s->regs[R_DMACR] = 1 << 16; /* Starts with one in compl threshold. */ |
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} |
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/* Map an offset addr into a channel index. */
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static inline int streamid_from_addr(hwaddr addr) |
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{ |
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int sid;
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sid = addr / (0x30);
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sid &= 1;
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return sid;
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} |
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#ifdef DEBUG_ENET
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static void stream_desc_show(struct SDesc *d) |
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{ |
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qemu_log("buffer_addr = " PRIx64 "\n", d->buffer_address); |
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qemu_log("nxtdesc = " PRIx64 "\n", d->nxtdesc); |
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qemu_log("control = %x\n", d->control);
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qemu_log("status = %x\n", d->status);
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} |
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#endif
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static void stream_desc_load(struct Stream *s, hwaddr addr) |
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{ |
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struct SDesc *d = &s->desc;
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cpu_physical_memory_read(addr, d, sizeof *d);
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/* Convert from LE into host endianness. */
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d->buffer_address = le64_to_cpu(d->buffer_address); |
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d->nxtdesc = le64_to_cpu(d->nxtdesc); |
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d->control = le32_to_cpu(d->control); |
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d->status = le32_to_cpu(d->status); |
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} |
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static void stream_desc_store(struct Stream *s, hwaddr addr) |
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{ |
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struct SDesc *d = &s->desc;
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/* Convert from host endianness into LE. */
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d->buffer_address = cpu_to_le64(d->buffer_address); |
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d->nxtdesc = cpu_to_le64(d->nxtdesc); |
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d->control = cpu_to_le32(d->control); |
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d->status = cpu_to_le32(d->status); |
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cpu_physical_memory_write(addr, d, sizeof *d);
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} |
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static void stream_update_irq(struct Stream *s) |
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{ |
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unsigned int pending, mask, irq; |
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pending = s->regs[R_DMASR] & DMASR_IRQ_MASK; |
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mask = s->regs[R_DMACR] & DMASR_IRQ_MASK; |
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irq = pending & mask; |
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qemu_set_irq(s->irq, !!irq); |
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} |
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static void stream_reload_complete_cnt(struct Stream *s) |
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{ |
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unsigned int comp_th; |
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comp_th = (s->regs[R_DMACR] >> 16) & 0xff; |
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s->complete_cnt = comp_th; |
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} |
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static void timer_hit(void *opaque) |
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{ |
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struct Stream *s = opaque;
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stream_reload_complete_cnt(s); |
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s->regs[R_DMASR] |= DMASR_DLY_IRQ; |
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stream_update_irq(s); |
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} |
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static void stream_complete(struct Stream *s) |
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{ |
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unsigned int comp_delay; |
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/* Start the delayed timer. */
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comp_delay = s->regs[R_DMACR] >> 24;
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if (comp_delay) {
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ptimer_stop(s->ptimer); |
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ptimer_set_count(s->ptimer, comp_delay); |
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ptimer_run(s->ptimer, 1);
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} |
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s->complete_cnt--; |
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if (s->complete_cnt == 0) { |
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/* Raise the IOC irq. */
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s->regs[R_DMASR] |= DMASR_IOC_IRQ; |
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stream_reload_complete_cnt(s); |
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} |
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} |
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static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev, |
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StreamSlave *tx_control_dev) |
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{ |
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uint32_t prev_d; |
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unsigned char txbuf[16 * 1024]; |
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unsigned int txlen; |
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if (!stream_running(s) || stream_idle(s)) {
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return;
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} |
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while (1) { |
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stream_desc_load(s, s->regs[R_CURDESC]); |
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if (s->desc.status & SDESC_STATUS_COMPLETE) {
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s->regs[R_DMASR] |= DMASR_HALTED; |
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break;
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} |
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if (stream_desc_sof(&s->desc)) {
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s->pos = 0;
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stream_push(tx_control_dev, s->desc.app, sizeof(s->desc.app));
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} |
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txlen = s->desc.control & SDESC_CTRL_LEN_MASK; |
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if ((txlen + s->pos) > sizeof txbuf) { |
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hw_error("%s: too small internal txbuf! %d\n", __func__,
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txlen + s->pos); |
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} |
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cpu_physical_memory_read(s->desc.buffer_address, |
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txbuf + s->pos, txlen); |
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s->pos += txlen; |
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if (stream_desc_eof(&s->desc)) {
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stream_push(tx_data_dev, txbuf, s->pos); |
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s->pos = 0;
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stream_complete(s); |
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} |
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/* Update the descriptor. */
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s->desc.status = txlen | SDESC_STATUS_COMPLETE; |
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stream_desc_store(s, s->regs[R_CURDESC]); |
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/* Advance. */
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prev_d = s->regs[R_CURDESC]; |
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s->regs[R_CURDESC] = s->desc.nxtdesc; |
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if (prev_d == s->regs[R_TAILDESC]) {
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s->regs[R_DMASR] |= DMASR_IDLE; |
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break;
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} |
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} |
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} |
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static size_t stream_process_s2mem(struct Stream *s, unsigned char *buf, |
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size_t len) |
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{ |
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uint32_t prev_d; |
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unsigned int rxlen; |
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size_t pos = 0;
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int sof = 1; |
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if (!stream_running(s) || stream_idle(s)) {
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return 0; |
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} |
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while (len) {
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stream_desc_load(s, s->regs[R_CURDESC]); |
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if (s->desc.status & SDESC_STATUS_COMPLETE) {
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s->regs[R_DMASR] |= DMASR_HALTED; |
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break;
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} |
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rxlen = s->desc.control & SDESC_CTRL_LEN_MASK; |
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if (rxlen > len) {
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/* It fits. */
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rxlen = len; |
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} |
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cpu_physical_memory_write(s->desc.buffer_address, buf + pos, rxlen); |
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len -= rxlen; |
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pos += rxlen; |
351 |
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/* Update the descriptor. */
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if (!len) {
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stream_complete(s); |
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memcpy(s->desc.app, s->app, sizeof(s->desc.app));
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s->desc.status |= SDESC_STATUS_EOF; |
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} |
358 |
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s->desc.status |= sof << SDESC_STATUS_SOF_BIT; |
360 |
s->desc.status |= SDESC_STATUS_COMPLETE; |
361 |
stream_desc_store(s, s->regs[R_CURDESC]); |
362 |
sof = 0;
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/* Advance. */
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prev_d = s->regs[R_CURDESC]; |
366 |
s->regs[R_CURDESC] = s->desc.nxtdesc; |
367 |
if (prev_d == s->regs[R_TAILDESC]) {
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s->regs[R_DMASR] |= DMASR_IDLE; |
369 |
break;
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} |
371 |
} |
372 |
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return pos;
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} |
375 |
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376 |
static void xilinx_axidma_reset(DeviceState *dev) |
377 |
{ |
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int i;
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379 |
XilinxAXIDMA *s = XILINX_AXI_DMA(dev); |
380 |
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381 |
for (i = 0; i < 2; i++) { |
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stream_reset(&s->streams[i]); |
383 |
} |
384 |
} |
385 |
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386 |
static size_t
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xilinx_axidma_control_stream_push(StreamSlave *obj, unsigned char *buf, |
388 |
size_t len) |
389 |
{ |
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XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj); |
391 |
struct Stream *s = &cs->dma->streams[1]; |
392 |
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if (len != CONTROL_PAYLOAD_SIZE) {
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394 |
hw_error("AXI DMA requires %d byte control stream payload\n",
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(int)CONTROL_PAYLOAD_SIZE);
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} |
397 |
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memcpy(s->app, buf, len); |
399 |
return len;
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} |
401 |
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402 |
static bool |
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xilinx_axidma_data_stream_can_push(StreamSlave *obj, |
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StreamCanPushNotifyFn notify, |
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void *notify_opaque)
|
406 |
{ |
407 |
XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj); |
408 |
struct Stream *s = &ds->dma->streams[1]; |
409 |
|
410 |
if (!stream_running(s) || stream_idle(s)) {
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411 |
ds->dma->notify = notify; |
412 |
ds->dma->notify_opaque = notify_opaque; |
413 |
return false; |
414 |
} |
415 |
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416 |
return true; |
417 |
} |
418 |
|
419 |
static size_t
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420 |
xilinx_axidma_data_stream_push(StreamSlave *obj, unsigned char *buf, size_t len) |
421 |
{ |
422 |
XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj); |
423 |
struct Stream *s = &ds->dma->streams[1]; |
424 |
size_t ret; |
425 |
|
426 |
ret = stream_process_s2mem(s, buf, len); |
427 |
stream_update_irq(s); |
428 |
return ret;
|
429 |
} |
430 |
|
431 |
static uint64_t axidma_read(void *opaque, hwaddr addr, |
432 |
unsigned size)
|
433 |
{ |
434 |
XilinxAXIDMA *d = opaque; |
435 |
struct Stream *s;
|
436 |
uint32_t r = 0;
|
437 |
int sid;
|
438 |
|
439 |
sid = streamid_from_addr(addr); |
440 |
s = &d->streams[sid]; |
441 |
|
442 |
addr = addr % 0x30;
|
443 |
addr >>= 2;
|
444 |
switch (addr) {
|
445 |
case R_DMACR:
|
446 |
/* Simulate one cycles reset delay. */
|
447 |
s->regs[addr] &= ~DMACR_RESET; |
448 |
r = s->regs[addr]; |
449 |
break;
|
450 |
case R_DMASR:
|
451 |
s->regs[addr] &= 0xffff;
|
452 |
s->regs[addr] |= (s->complete_cnt & 0xff) << 16; |
453 |
s->regs[addr] |= (ptimer_get_count(s->ptimer) & 0xff) << 24; |
454 |
r = s->regs[addr]; |
455 |
break;
|
456 |
default:
|
457 |
r = s->regs[addr]; |
458 |
D(qemu_log("%s ch=%d addr=" TARGET_FMT_plx " v=%x\n", |
459 |
__func__, sid, addr * 4, r));
|
460 |
break;
|
461 |
} |
462 |
return r;
|
463 |
|
464 |
} |
465 |
|
466 |
static void axidma_write(void *opaque, hwaddr addr, |
467 |
uint64_t value, unsigned size)
|
468 |
{ |
469 |
XilinxAXIDMA *d = opaque; |
470 |
struct Stream *s;
|
471 |
int sid;
|
472 |
|
473 |
sid = streamid_from_addr(addr); |
474 |
s = &d->streams[sid]; |
475 |
|
476 |
addr = addr % 0x30;
|
477 |
addr >>= 2;
|
478 |
switch (addr) {
|
479 |
case R_DMACR:
|
480 |
/* Tailptr mode is always on. */
|
481 |
value |= DMACR_TAILPTR_MODE; |
482 |
/* Remember our previous reset state. */
|
483 |
value |= (s->regs[addr] & DMACR_RESET); |
484 |
s->regs[addr] = value; |
485 |
|
486 |
if (value & DMACR_RESET) {
|
487 |
stream_reset(s); |
488 |
} |
489 |
|
490 |
if ((value & 1) && !stream_resetting(s)) { |
491 |
/* Start processing. */
|
492 |
s->regs[R_DMASR] &= ~(DMASR_HALTED | DMASR_IDLE); |
493 |
} |
494 |
stream_reload_complete_cnt(s); |
495 |
break;
|
496 |
|
497 |
case R_DMASR:
|
498 |
/* Mask away write to clear irq lines. */
|
499 |
value &= ~(value & DMASR_IRQ_MASK); |
500 |
s->regs[addr] = value; |
501 |
break;
|
502 |
|
503 |
case R_TAILDESC:
|
504 |
s->regs[addr] = value; |
505 |
s->regs[R_DMASR] &= ~DMASR_IDLE; /* Not idle. */
|
506 |
if (!sid) {
|
507 |
stream_process_mem2s(s, d->tx_data_dev, d->tx_control_dev); |
508 |
} |
509 |
break;
|
510 |
default:
|
511 |
D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx " v=%x\n", |
512 |
__func__, sid, addr * 4, (unsigned)value)); |
513 |
s->regs[addr] = value; |
514 |
break;
|
515 |
} |
516 |
if (sid == 1 && d->notify) { |
517 |
StreamCanPushNotifyFn notifytmp = d->notify; |
518 |
d->notify = NULL;
|
519 |
notifytmp(d->notify_opaque); |
520 |
} |
521 |
stream_update_irq(s); |
522 |
} |
523 |
|
524 |
static const MemoryRegionOps axidma_ops = { |
525 |
.read = axidma_read, |
526 |
.write = axidma_write, |
527 |
.endianness = DEVICE_NATIVE_ENDIAN, |
528 |
}; |
529 |
|
530 |
static void xilinx_axidma_realize(DeviceState *dev, Error **errp) |
531 |
{ |
532 |
XilinxAXIDMA *s = XILINX_AXI_DMA(dev); |
533 |
XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev); |
534 |
XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM( |
535 |
&s->rx_control_dev); |
536 |
Error *local_errp = NULL;
|
537 |
|
538 |
object_property_add_link(OBJECT(ds), "dma", TYPE_XILINX_AXI_DMA,
|
539 |
(Object **)&ds->dma, &local_errp); |
540 |
object_property_add_link(OBJECT(cs), "dma", TYPE_XILINX_AXI_DMA,
|
541 |
(Object **)&cs->dma, &local_errp); |
542 |
if (local_errp) {
|
543 |
goto xilinx_axidma_realize_fail;
|
544 |
} |
545 |
object_property_set_link(OBJECT(ds), OBJECT(s), "dma", &local_errp);
|
546 |
object_property_set_link(OBJECT(cs), OBJECT(s), "dma", &local_errp);
|
547 |
if (local_errp) {
|
548 |
goto xilinx_axidma_realize_fail;
|
549 |
} |
550 |
|
551 |
int i;
|
552 |
|
553 |
for (i = 0; i < 2; i++) { |
554 |
s->streams[i].nr = i; |
555 |
s->streams[i].bh = qemu_bh_new(timer_hit, &s->streams[i]); |
556 |
s->streams[i].ptimer = ptimer_init(s->streams[i].bh); |
557 |
ptimer_set_freq(s->streams[i].ptimer, s->freqhz); |
558 |
} |
559 |
return;
|
560 |
|
561 |
xilinx_axidma_realize_fail:
|
562 |
if (!*errp) {
|
563 |
*errp = local_errp; |
564 |
} |
565 |
} |
566 |
|
567 |
static void xilinx_axidma_init(Object *obj) |
568 |
{ |
569 |
XilinxAXIDMA *s = XILINX_AXI_DMA(obj); |
570 |
SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
571 |
Error *errp = NULL;
|
572 |
|
573 |
object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
|
574 |
(Object **) &s->tx_data_dev, &errp); |
575 |
assert_no_error(errp); |
576 |
object_property_add_link(obj, "axistream-control-connected",
|
577 |
TYPE_STREAM_SLAVE, |
578 |
(Object **) &s->tx_control_dev, &errp); |
579 |
assert_no_error(errp); |
580 |
|
581 |
object_initialize(&s->rx_data_dev, TYPE_XILINX_AXI_DMA_DATA_STREAM); |
582 |
object_initialize(&s->rx_control_dev, TYPE_XILINX_AXI_DMA_CONTROL_STREAM); |
583 |
object_property_add_child(OBJECT(s), "axistream-connected-target",
|
584 |
(Object *)&s->rx_data_dev, &errp); |
585 |
assert_no_error(errp); |
586 |
object_property_add_child(OBJECT(s), "axistream-control-connected-target",
|
587 |
(Object *)&s->rx_control_dev, &errp); |
588 |
assert_no_error(errp); |
589 |
|
590 |
sysbus_init_irq(sbd, &s->streams[0].irq);
|
591 |
sysbus_init_irq(sbd, &s->streams[1].irq);
|
592 |
|
593 |
memory_region_init_io(&s->iomem, &axidma_ops, s, |
594 |
"xlnx.axi-dma", R_MAX * 4 * 2); |
595 |
sysbus_init_mmio(sbd, &s->iomem); |
596 |
} |
597 |
|
598 |
static Property axidma_properties[] = {
|
599 |
DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000), |
600 |
DEFINE_PROP_END_OF_LIST(), |
601 |
}; |
602 |
|
603 |
static void axidma_class_init(ObjectClass *klass, void *data) |
604 |
{ |
605 |
DeviceClass *dc = DEVICE_CLASS(klass); |
606 |
|
607 |
dc->realize = xilinx_axidma_realize, |
608 |
dc->reset = xilinx_axidma_reset; |
609 |
dc->props = axidma_properties; |
610 |
} |
611 |
|
612 |
static StreamSlaveClass xilinx_axidma_data_stream_class = {
|
613 |
.push = xilinx_axidma_data_stream_push, |
614 |
.can_push = xilinx_axidma_data_stream_can_push, |
615 |
}; |
616 |
|
617 |
static StreamSlaveClass xilinx_axidma_control_stream_class = {
|
618 |
.push = xilinx_axidma_control_stream_push, |
619 |
}; |
620 |
|
621 |
static void xilinx_axidma_stream_class_init(ObjectClass *klass, void *data) |
622 |
{ |
623 |
StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); |
624 |
|
625 |
ssc->push = ((StreamSlaveClass *)data)->push; |
626 |
ssc->can_push = ((StreamSlaveClass *)data)->can_push; |
627 |
} |
628 |
|
629 |
static const TypeInfo axidma_info = { |
630 |
.name = TYPE_XILINX_AXI_DMA, |
631 |
.parent = TYPE_SYS_BUS_DEVICE, |
632 |
.instance_size = sizeof(XilinxAXIDMA),
|
633 |
.class_init = axidma_class_init, |
634 |
.instance_init = xilinx_axidma_init, |
635 |
}; |
636 |
|
637 |
static const TypeInfo xilinx_axidma_data_stream_info = { |
638 |
.name = TYPE_XILINX_AXI_DMA_DATA_STREAM, |
639 |
.parent = TYPE_OBJECT, |
640 |
.instance_size = sizeof(struct XilinxAXIDMAStreamSlave), |
641 |
.class_init = xilinx_axidma_stream_class_init, |
642 |
.class_data = &xilinx_axidma_data_stream_class, |
643 |
.interfaces = (InterfaceInfo[]) { |
644 |
{ TYPE_STREAM_SLAVE }, |
645 |
{ } |
646 |
} |
647 |
}; |
648 |
|
649 |
static const TypeInfo xilinx_axidma_control_stream_info = { |
650 |
.name = TYPE_XILINX_AXI_DMA_CONTROL_STREAM, |
651 |
.parent = TYPE_OBJECT, |
652 |
.instance_size = sizeof(struct XilinxAXIDMAStreamSlave), |
653 |
.class_init = xilinx_axidma_stream_class_init, |
654 |
.class_data = &xilinx_axidma_control_stream_class, |
655 |
.interfaces = (InterfaceInfo[]) { |
656 |
{ TYPE_STREAM_SLAVE }, |
657 |
{ } |
658 |
} |
659 |
}; |
660 |
|
661 |
static void xilinx_axidma_register_types(void) |
662 |
{ |
663 |
type_register_static(&axidma_info); |
664 |
type_register_static(&xilinx_axidma_data_stream_info); |
665 |
type_register_static(&xilinx_axidma_control_stream_info); |
666 |
} |
667 |
|
668 |
type_init(xilinx_axidma_register_types) |