gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functions
This avoids polluting the global namespace with a non-prefixed macro andmakes it obvious in the call sites that we return.
Semi-automatic conversion using, e.g., sed i 's/GET_REGL(/return gdb_get_regl(mem_buf, /g' target*/gdbstub.c...
cpu: Introduce CPUClass::gdb_{read,write}_register()
Completes migration of target-specific code to new target-*/gdbstub.c.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Introduce CPUClass::gdb_core_xml_file for GDB_CORE_XML
Replace the GDB_CORE_XML define in gdbstub.c with a CPUClass field.Use first_cpu for qSupported and qXfer:features:read: for now.Add a stub for xml_builtin.
Signed-off-by: Andreas Färber <afaerber@suse.de>
target-ppc: Move cpu_gdb_{read,write}_register()
cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs
CPUState::gdb_num_regs replaces num_g_regs.CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS.
Allows building gdb_register_coprocessor() for xtensa, too.
As a side effect this should fix coprocessor register numbering for SMP....
cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook
Change breakpoint_invalidate() argument to CPUState alongside.
Since all targets now assign a softmmu-only field, we can drop helperscpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd()....
gdbstub: Change gdb_register_coprocessor() argument to CPUState
cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()
Where no extra implementation is needed, fall back to CPUClass::set_pc().
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
Prepares for changing cpu_single_step() argument to CPUState.
cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()
This moves setting the Program Counter from gdbstub into target code.Use vaddr type as upper-bound replacement for target_ulong.
e600 core for MPC86xx processors
MPC86xx processors are based on the e600 core, which is not the casein qemu where it is based on the 7400 processor.
This patch creates the e600 core and instantiates the MPC86xxprocessors based on it. Therefore, adding the high BATs, the SPRG...
target-ppc: Add POWER8 v1.0 CPU model
This patch adds CPU PVR definition for POWER8,and enables QEMU to launch guests on POWER8 hardware.
Signed-off-by: Prerna Saxena
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Paul Mackerras <paulus@samba.org>...
log: Change log_cpu_state[_mask]() argument to CPUState
Since commit 878096eeb278a8ac1ccd6667af73e026f29b4cf5 (cpu: Turncpu_dump_{state,statistics}() into CPUState hooks) CPUArchState is nolonger needed.
Add documentation and make the functions available through qemu/log.h...
target-ppc: Change LOG_MMU_STATE() argument to CPUState
Choose CPUState rather than PowerPCCPU since doing a CPU cast on themacro argument would hide type mismatches.
cpu: Move reset logging to CPUState
x86 was using additional CPU_DUMP_* flags, so make that configurable inCPUClass::reset_dump_flags.
This adds reset logging for alpha, unicore32 and xtensa.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Reviewed-by: Richard Henderson <rth@twiddle.net>...
target-ppc: Change gen_intermediate_code_internal() argument to PowerPCCPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-ppc: Don't overuse ENV_GET_CPU()
Commit b632a148b677b773ff155f9de840b37a653567b9 (target-ppc: QOM methoddispatch for MMU fault handling) introduced a use of ENV_GET_CPU()inside target-ppc/ code. Use ppc_env_get_cpu() instead.
Purely cosmetic, non-functional change to aid in locating and removing...
cpu: Make first_cpu and next_cpu CPUState
Move next_cpu from CPU_COMMON to CPUState.Move first_cpu variable to qom/cpu.h.
gdbstub needs to use CPUState::env_ptr for now.cpu_copy() no longer needs to save and restore cpu_next.
Acked-by: Paolo Bonzini <pbonzini@redhat.com>...
linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-user
The functions cpu_clone_regs() and cpu_set_tls() are not purely CPUrelated -- they are specific to the TLS ABI for a a particular OS.Move them into the linux-user/ tree where they belong....
cpu: Drop unnecessary dynamic casts in *_env_get_cpu()
A transition from CPUFooState to FooCPU can be considered safe,just like FooCPU::env access in the opposite direction.The only benefit of the FOO_CPU() casts would be protection againstbogus CPUFooState pointers, but then surrounding code would likely...
memory: add owner argument to initialization functions
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
PPC: Add dump_mmu() for 6xx
"(qemu) info tlb" is a very useful tool for debugging, so I implementedthe missing 6xx version.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>[agraf: fix printfs on hwaddr to PRI]Signed-off-by: Alexander Graf <agraf@suse.de>
PPC: Fix GDB read on code area for PPC6xx
On PPC 6xx, data and code have separated TLBs. Until now QEMU was onlylooking at data TLBs, which is not good when GDB wants to read code.
This patch adds a second call to get_physical_address() with anACCESS_CODE type of access when the first call with ACCESS_INT fails....
PPC: Introduce an alias cache for faster lookups
When running QEMU with "-cpu ?" we walk through every alias for everytarget CPU we know about. This takes several seconds on my very fasthost system.
Let's introduce a class object cache in the alias table. Using that we...
PPC: Ignore writes to L2CR
The L2CR register contains a number of bits that either impose configurationwhich we can't deal with or mean "something is in progress until the bit is0 again".
Since we don't model the former and we do want to accomodate guests using the...
target-ppc kvm: save cr register
This adds a missing code to save CR (condition register) viakvm_arch_put_registers(). kvm_arch_get_registers() already has it.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>Signed-off-by: David Gibson <david@gibson.dropbear.id.au>...
target-ppc: Introduce unrealizefn for PowerPCCPU
Use it to clean up the opcode table, resolving a former TODO from Jocelyn.Also switch from malloc() to g_malloc().
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Drop redundant flags assignments from CPU families
Previous code has #define POWERPC_INSNS2_<family> PPC_NONE in someplaces for macrofied assignment to insns_flags2 field.
PPC_NONE is defined as zero though and QOM classes are zero-initialized,...
ppc: do not register IABR SPR twice for 603e
IABR SPR is already registered in gen_spr_603(), called from init_proc_603E().
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
PPC: Add non-kvm stub file
There are cases where a kvm provided function is called from generichw code that doesn't know whether kvm is available or not. Providea stub file which can provide simple replacement functions for thosecases.
Signed-off-by: Alexander Graf <agraf@suse.de>...
kvm/openpic: in-kernel mpic support
Enables support for the in-kernel MPIC that thas been merged into theKVM next branch. This includes irqfd/KVM_IRQ_LINE support from AlexGraf (along with some other improvements).
Note from Alex regarding kvm_irqchip_create():...
cpu: Change qemu_init_vcpu() argument to CPUState
This allows to move the call into CPUState's realizefn.Therefore move the stub into libqemustub.a.
kvm: Change cpu_synchronize_state() argument to CPUState
Change Monitor::mon_cpu to CPUState as well.
Reviewed-by: liguang <lig.fnst@cn.fujitsu.com>Acked-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Make cpustats monitor command available unconditionally.
Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec()arguments to CPUState.
KVM: PPC: Add dummy kvm_arch_init_irq_routing()
The common KVM code insists on calling kvm_arch_init_irq_routing()as soon as it sees kernel header support for it (regardless of whetherQEMU supports it). Provide a dummy function to satisfy this.
Unlike x86, PPC does not have one default irqchip, so there's no common...
remove some double-includes
Some source files #include the same header more thanonce for no good reason. Remove second #includes insuch cases.
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
PPC: Depend behavior of cmp instructions only on instruction encoding
When running an L=1 cmp instruction on a 64bit PPC CPU with SF off, itstill behaves identical to what it does when SF is on. Remove the implicitdifference in the code.
Also, on most 32bit CPUs we should always treat the compare as 32bit...
PPC: Fix rldcl
The implementation for rldcl tried to always fetch itsparameters from the opcode, even though the opcode wasalready passed in in decoded and different forms.
Use the parameters instead, fixing rldcl.
Reported-by: Torbjorn Granlund <tg@gmplib.org>...
PPC: Add MMU type for 2.06 with AMR but no TB pages
When running -cpu on a POWER7 system with PR KVM, we mask out the 1TBMMU capability from the MMU type mask, but not the AMR bit.
This leads to us having a new MMU type that we don't check for in ourMMU management functions....
target-ppc: Fix invalid SPR read/write warnings
Invalid and privileged SPR warnings currently print the wrongaddress. While fixing that, also make it clear that we areprinting both the decimal and hexadecimal SPR number.
Before:
Trying to read invalid spr 896 380 at 0000000000000714...
target-ppc: Add read and write of PPR SPR
Recent Linux kernels save and restore the PPR across exceptionsso we need to handle it.
Signed-off-by: Anton Blanchard <anton@au1.ibm.com>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: slightly optimize lfiwax
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-ppc: emulate lfiwax instruction
Needed for Power ISA version 2.05 compliance.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>[agraf: fix tcg debug error]Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: emulate load doubleword pair instructions
Needed for Power ISA version 2.05 compliance. The check for odd registerpairs is done using the invalid bits.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: emulate store doubleword pair instructions
target-ppc: add support for extended mtfsf/mtfsfi forms
Power ISA 2.05 adds support for extended mtfsf/mtfsfi form, with a newW field to select the upper part of the FPCSR register.
For that the helper is changed to handle 64-bit input values and mask with...
powerpc: correctly handle fpu exceptions.
Raise the exception on the first occurence, do not wait for the nextfloating point operation.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>Signed-off-by: Alexander Graf <agraf@suse.de>
PPC: Fix dcbz for linux-user on 970
The default with linux-user for dcbz on 970 is to emulate 32 byte clears.However, redoing the dcbzl support we added a check to not honor the bitin HID5 that sets this.
Remove the #ifdef check on linux user, so that we get 32 byte clears again....
target-ppc: optimize fabs, fnabs, fneg
fabs, fnabs and fneg are just flipping the bit sign of an FP register,this can be implemented in TCG instead of using softfloat.
target-ppc: add instruction flags for Book I 2.05
.. and enable it on POWER7 CPU.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: emulate cmpb instruction
target-ppc: emulate prtyw and prtyd instructions
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>[agraf: fix 32-bit host compile, simplify code]Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: emulate fcpsgn instruction
pseries: Fix incorrect calculation of RMA size in certain configurations
For the pseries machine, we need to advertise to the guest the size of itsRMA - that is the amount of memory it can access with the MMU off. For HVKVM, this is constrained by the hardware limitations on the virtual RMA of...
pseries: Fixes and enhancements to L1 cache properties
PAPR requires that the device tree's CPU nodes have several propertieswith information about the L1 cache. We already create two of theseproperties, but with incorrect names - "[id]cache-block-size" instead...
target-ppc: Add more stubs for POWER7 PMU registers
In addition to the performance monitor registers found on nearly all6xx chips, the POWER7 has two additional counters (PMC5 & PMC6) and anextra control register (MMCRA). This patch adds stub support for them to...
target-ppc: Synchronize VPA state with KVM
For PAPR guests, KVM tracks the various areas registered with theH_REGISTER_VPA hypercall. For full emulation, of course, these are trackedwithin qemu. At present these values are not synchronized. This is a...
PPC: e500: advertise 4.2 MPIC only if KVM supports EPR
Older KVM versions don't support EPR which breaks guests when we announceMPIC variants that support EPR.
Catch that case and expose only MPIC version 2.0 which tells the guest thatwe don't support the EPR capability yet....
PPC: Remove env->hreset_excp_prefix
This value is not needed if we use correctly the MSR[IP] bit.
excp_prefix is always 0x00000000, except when the MSR[IP] bit isimplemented and set to 1, in that case excp_prefix is 0xfff00000.
The handling of MSR[IP] was already implemented but not used at reset...
target-ppc: fix nego and subf*o instructions
The overflow computation of nego and subf*o instructions has been brokenin commit ffe30937. Contrary to other targets, the instruction is subtractfrom an not subtract on PowerPC.
This patch fixes the issue by using the correct argument in the xor...
PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
According to the different user's manuals, the vector offset for systemreset (both /HRESET and /SRESET) is 0x00100.
This patch may break support of some executables, as the power-on start...
PPC: Add breakpoint registers for 603 and e300
target-ppc: Fix narrow-mode add/sub carry output
Broken in b5a73f8d8a57e940f9bbeb399a9e47897522ee9a, the carry itself wasfixed in 79482e5ab38a05ca8869040b0d8b8f451f16ff62. But we still need toproduce the full 64-bit addition.
Simplify the conditions at the top of the functions for when we need a...
Enable kvm emulated watchdog
Enable the KVM emulated watchdog if KVM supports (use thecapability enablement in watchdog handler). Also watchdog exit(KVM_EXIT_WATCHDOG) handling is added.Watchdog state machine is cleared whenever VM state changes to running....
target-ppc: Enable ISEL on POWER7
ISEL is a Power ISA 2.06 instruction and thus is available on POWER7.Given this is trapped and emulated by the Linux kernel, I guess it wentunnoticed.
memory: move core typedefs to qemu/typedefs.h
hw: move headers to include/
Many of these should be cleaned up with proper qdev-/QOM-ification.Right now there are many catch-all headers in include/hw/ARCH dependingon cpu.h, and this makes it necessary to compile these files per-target.However, fixing this does not belong in these patches....
target-ppc: Fix add and subf carry generation in narrow mode
The set of computations used in b5a73f8d8a57e940f9bbeb399a9e47897522ee9aare only valid if the current word size == target_long size. This failedto take ppc64 in 32-bit (narrow) mode into account....
target-ppc: Use NARROW_MODE macro for branches
Removing conditional compilation in the process.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Use NARROW_MODE macro for comparisons
target-ppc: Use NARROW_MODE macro for addresses
target-ppc: Use NARROW_MODE macro for tlbie
mmu-hash*: Correctly mask RPN from hash PTE
BEHAVIOUR CHANGE
At present we take the whole of word 1 of the hash PTE as the real pagenumber used to calculate the translated address. This is incorrect,because it leaves the flags from the low bits of PTE word 1 in place in the...
mmu-hash*: Don't use full ppc_hash{32, 64}_translate() path for get_phys_page_debug()
Currently the hash mmu versionsof get_phys_page_debug() use the sameppc64_hash64_translate() function to do the translation logic as the normalmm fault handler code....
mmu-hash*: Merge translate and fault handling functions
ppc_hash{32,64}_handle_mmu_fault() is now the only caller ofppc_hash{32,64{_translate(), so this patch combines them together. Thismeans that instead of one returning a variety of non-obvious error codes...
mmu-hash64: Implement Virtual Page Class Key Protection
Version 2.06 of the Power architecture describes an additional pageprotection mechanism. Each virtual page has a "class" (0-31) recorded inthe PTE. The AMR register contains bits which can prohibit reads and/or...
target-ppc: Split user only code out of mmu_helper.c
mmu_helper.c is, for obvious reasons, almost entirely concerned withsoftmmu builds of qemu. However, it does contain one stub function whichis used when CONFIG_USER_ONLY=y - the user only versoin of...
target-ppc: Move ppc tlb_fill implementation into mmu_helper.c
For softmmu builds the interface from the generic code to the targetspecific MMU implementation is through the tlb_fill() function. For ppcthis is currently in mem_helper.c, whereas it would make more sense in...
target-ppc: Use QOM method dispatch for MMU fault handling
After previous cleanups, the many scattered checks of env->mmu_model inthe ppc MMU implementation have, at least for "classic" hash MMUs beenreduced (almost) to a single switch at the top ofcpu_ppc_handle_mmu_fault()....
mmu-hash*: Don't update PTE flags when permission is denied
Currently if ppc_hash{32,64}_translate() finds a PTE matching the givenvirtual address, it will always update the PTE's R & C (Referenced andChanged) bits. This happens even if the PTE's permissions mean we are...
mmu-hash32: Remove nx from context structure
Previous cleanups have meant the nx field of the mmu_ctx_hash32 structureis now only used within ppc_hash32_translate(), and so it can be replacedby a local variable.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>...
mmu-hash*: Clean up permission checking
Currently checking of PTE permission bits is split messily amongstppc_hash{32,64}_pp_check(), ppc_hash{32,64}_check_prot() and their callers.This patch cleans this up to have the new functionppc_hash{32,64}_pte_prot() compute the page permissions from the SLBE (for...
mmu-hash64: Factor SLB N bit into permissions bits
Currently, for 64-bit hash mmu, the execute protection bit placed into theqemu tlb is based only on the N (No execute) bit from the PTE. However,No Execute can also be set at the segment level. We do check this on...
mmu-hash*: Clean up PTE flags update
Currently the ppc_hash{32,64}_pte_update_flags() helper functions update aPTE's referenced and changed bits as necessary to reflect the access. Itis somewhat long winded, though. This patch open codes them in their...
mmu-hash*: Clean up real address calculation
More recent 64-bit hash MMUs support multiple page sizes, and PTEs forlarge pages only include the offset of the whole large page. But the qemutlb only handles pages of the base size (4k) so we need to break up the...
mmu-hash*: Fold pte_check*() logic into caller
With previous cleanups made, the 32-bit and 64-bit pte_check*() functionsare pretty trivial and only have one call site. This patch thereforeclarifies the overall code flow by folding those functions into their...
mmu-hash32: Remove odd pointer usage from BAT code
In the code for handling BATs, the hash32_bat_size_prot() andhash32_bat_601_size_prot() functions are passed the BAT contents byreference (pointer) for no clear reason, since they only need the valueswithin....
mmu-hash32: Split BAT size logic from permissions logic
hash32_bat_size_prot() and its 601 variant, as the name suggests, returnsboth a BAT's size - needed to search for a matching BAT - and itspermissions, only relevant once a matching BAT has been located....
mmu-hash32: Clean up BAT matching logic
The code to search for a matching BAT for a virtual address is somewhatlongwinded and awkward. In particular, it relies on seperate size andvalidity information being returned from the hash32_bat_size() function...
mmu-hash32: Cleanup BAT lookup
This patch makes a general cleanup of the ppc_hash32_get_bat() function,renaming it to ppc_hash32_bat_lookup(). In particular, the new functiononly looks for a matching BAT, with the permissions check from the oldfunction moved to the caller....
mmu-hash32: Don't look up page tables on BAT permission error
Currently, on any failure translating an address with BATs, we proceed tonormal segment and page table translation. That's incorrect if theBAT error was due to permissions, rather than not finding a matching BAT....
mmu-hash*: Don't keep looking for PTEs after we find a match
The ppc hash mmu hashes each virtual address to a primary and secondarypossible hash bucket (aka PTE group or PTEG) each with 8 PTEs. Then weneed a linear search through the PTEs to find the correct one for the...
mmu-hash*: Separate PTEG searching from permissions checking
find_pte{32,64{() do several things. First they search through a PTEGooking for a PTE matching our virtual address. Then they do permissionschecking and other processing on that PTE.
This patch separates the search by VA out from the rest. The search is...
mmu-hash*: Make find_pte{32, 64} do more of the job of finding ptes
find_pte{32,64}() are not particularly well named. They only "find" a PTEwithin a given PTE group, and they also do permissions checking and otherthings.
This patch makes it somewhat close to matching the name, by folding the...
mmu-hash*: Remove permission checking from find_pte{32, 64}()
find_pte{32,64}() are poorly named, since they both find a PTE and dopermissions checking of it. This patch makes them only locate a matchingPTE, moving the permission checking and other logic to the caller. We...
mmu-hash64: Clean up ppc_hash64_htab_lookup()
This patch makes a general cleanup of the address mangling logic inppc_hash64_htab_lookup(). In particular it now avoids repeatedly switchingon the segment size. The lack of SLB and multiple segment sizes on 32-bit...
mmu-hash*: Combine ppc_hash{32, 64}_get_physical_address and get_segment{32, 64}()
After previous work, ppc_hash{32,64}_get_physical_address() are almosttrivial wrappers around get_segment{32,64}() which does nearly all the work oftranslating an address according to the hash mmu model. Therefore combine the...
mmu-hash32: Split out handling of direct store segments
At present a large chunk of ppc_hash32_translate() is taken up with anugly if selecting between direct store segments (hardly ever used) andnormal paged segments. This patch clarifies the flow of code by...
mmu-hash32: Split direct store segment handling into a helper
This further separates the unusual case handling of direct store segmentsfrom the main translation path by moving its logic into a helper function,with some tiny cleanups along the way.
mmu-hash*: Cleanup segment-level NX check
On the ppc hash mmus, no-execute can be set at the segment level (on morerecent 64-bit hash mmus it can also be set at the page level). This patchseparates out this check to make it clearer what is going on, and avoiding...