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# Date Author Comment
f290e498 07/15/2013 11:21 pm Richard Henderson

Merge git://github.com/hw-claudio/qemu-aarch64-queue into tcg-next
c6d8ed24 07/15/2013 02:13 pm Jani Kokkonen

tcg/aarch64: Implement tlb lookup fast path

Supports CONFIG_QEMU_LDST_OPTIMIZATION

Signed-off-by: Jani Kokkonen <>
Reviewed-by: Richard Henderson <>
Reviewed-by: Claudio Fontana <>
b5cc476d 07/09/2013 05:15 pm Richard Henderson

tcg-i386: Use QEMU_BUILD_BUG_ON instead of assert for frame size

We can check the condition at compile time, rather than run time.

Reviewed-by: Andreas Färber <>
Signed-off-by: Richard Henderson <>
0caa91fe 07/09/2013 05:15 pm Richard Henderson

tcg-arm: Implement tcg_register_jit

Allows unwinding past the code_gen_buffer.

Reviewed-by: Peter Maydell <>
Signed-off-by: Richard Henderson <>
45aba097 07/09/2013 05:15 pm Richard Henderson

tcg: Fix high_pc fields in .debug_info

I don't think the debugger actually looks at this for anything,
using the correct .debug_frame contents, but might as well get
it all correct.

Reviewed-by: Peter Maydell <>
Signed-off-by: Richard Henderson <>
497a22eb 07/09/2013 05:15 pm Richard Henderson

tcg: Move the CIE and FDE header definitions to common code

These will necessarily be the same layout for all hosts. This limits
the amount of boilerplate required to implement jit debug for a host.

Reviewed-by: Peter Maydell <>...
1e709f38 07/09/2013 05:15 pm Richard Henderson

tcg-arm: Use AT_PLATFORM to detect the host ISA

With this we can generate armv7 insns even when the OS compiles for a
lower common denominator. The macros are arranged so that when we do
compile for a given ISA, all of the runtime checks for that ISA are...
cb91021a 07/09/2013 05:15 pm Richard Henderson

tcg-arm: Simplify logic in detecting the ARM ISA in use

GCC 4.8 defines a handy __ARM_ARCH symbol that we can use, which
will make us nicely forward compatible with ARMv8 AArch32.

Reviewed-by: Peter Maydell <>
Signed-off-by: Richard Henderson <>
fb822738 07/09/2013 05:14 pm Richard Henderson

tcg-arm: Rename use_armv5_instructions to use_armvt5_instructions

As it really controls the availability of a thumb interworking
instruction on armv5t.

Reviewed-by: Peter Maydell <>
Signed-off-by: Richard Henderson <>
4ef76952 07/09/2013 05:14 pm Richard Henderson

tcg: Allow non-constant control macros

This allows TCG_TARGET_HAS_* to be a variable rather than a constant,
which allows easier support for differing ISA levels for the host.

Reviewed-by: Peter Maydell <>
Signed-off-by: Richard Henderson <>
c1a61f6c 07/09/2013 05:14 pm Richard Henderson

tcg: Simplify logic using TCG_OPF_NOT_PRESENT

Expand the definition of "not present" to include "should not be present".
This means we can simplify the logic surrounding the generic tcg opcodes
for which the host backend ought not be providing definitions....
72e1ccfc 07/09/2013 05:14 pm Richard Henderson

tcg-arm: Make use of conditional availability of opcodes for divide

We can now detect and use divide instructions at runtime, rather than
having to restrict their availability to compile-time.

Reviewed-by: Peter Maydell <>
Signed-off-by: Richard Henderson <>
5e1108b3 07/09/2013 05:14 pm Richard Henderson

tcg-arm: Don't implement rem

Reviewed-by: Peter Maydell <>
Signed-off-by: Richard Henderson <>
865a4671 07/09/2013 05:14 pm Richard Henderson

tcg-ppc: Don't implement rem

Reviewed-by: Andreas Färber <>
Signed-off-by: Richard Henderson <>
5b9f72ab 07/09/2013 05:14 pm Richard Henderson

tcg-ppc64: Don't implement rem

Reviewed-by: Andreas Färber <>
Signed-off-by: Richard Henderson <>
ca675f46 07/09/2013 05:14 pm Richard Henderson

tcg: Split rem requirement from div requirement

There are several hosts with only a "div" insn. Remainder is computed
manually from the quotient and inputs. We can do this generically.

Reviewed-by: Peter Maydell <>
Signed-off-by: Richard Henderson <>
b1f6dc0d 07/03/2013 03:43 pm Claudio Fontana

tcg/aarch64: implement ldst 12bit scaled uimm offset

implement the 12bit scaled unsigned immediate offset
variant of LDR/STR. This improves code size by avoiding
the movi + ldst_r for naturally aligned offsets in range.

Signed-off-by: Claudio Fontana <>...
82e0f917 06/17/2013 08:42 pm Anton Blanchard

tcg-ppc64: bswap64 rotates output 32 bits

If our input and output is in the same register, bswap64 tries to
undo a rotate of the input. This just ends up rotating the output.

Cc:
Signed-off-by: Anton Blanchard <>
Signed-off-by: Richard Henderson <>
84247357 06/17/2013 08:42 pm Anton Blanchard

tcg-ppc64: Fix add2_i64

add2_i64 was adding the lower double word to the upper double word
of each input. Fix this so we add the lower double words, then the
upper double words with carry propagation.

Cc:
Signed-off-by: Anton Blanchard <>...
d1bdd3af 06/17/2013 08:42 pm Anton Blanchard

tcg-ppc64: rotr_i32 rotates wrong amount

rotr_i32 calculates the amount to left shift and puts it into a
temporary, but then doesn't use it when doing the shift.

Cc:
Signed-off-by: Anton Blanchard <>
Signed-off-by: Richard Henderson <>
8a94cfb0 06/17/2013 08:41 pm Anton Blanchard

tcg-ppc64: Fix RLDCL opcode

The rldcl instruction doesn't have an sh field, so the minor opcode
is shifted 1 bit. We were using the XO30 macro which shifted the
minor opcode 2 bits.

Remove XO30 and add MD30 and MDS30 macros which match the
Power ISA categories....
86a6a077 06/14/2013 03:51 pm Anthony Liguori

Merge remote-tracking branch 'pmaydell/tcg-aarch64.next' into staging

  1. By Claudio Fontana (9) and others
  2. Via Peter Maydell
    • pmaydell/tcg-aarch64.next:
      MAINTAINERS: add tcg/aarch64 maintainer
      configure: permit compilation on arm aarch64
      tcg/aarch64: implement user mode qemu ld/st...
9c4a059d 06/12/2013 06:20 pm Claudio Fontana

tcg/aarch64: implement byte swap operations

implement the optional byte swap operations with the dedicated
aarch64 instructions.

Signed-off-by: Claudio Fontana <>
Reviewed-by: Richard Henderson <>
Message-id: ...
31f1275b 06/12/2013 06:20 pm Claudio Fontana

tcg/aarch64: implement sign/zero extend operations

implement the optional sign/zero extend operations with the dedicated
aarch64 instructions.

Signed-off-by: Claudio Fontana <>
Reviewed-by: Richard Henderson <>
Message-id: ...
6a91c7c9 06/12/2013 06:20 pm Jani Kokkonen

tcg/aarch64: implement user mode qemu ld/st

also put aarch64 in the list of archs that do not need an ldscript.

Signed-off-by: Jani Kokkoken <>
Signed-off-by: Claudio Fontana <>
Reviewed-by: Richard Henderson <>...
4a136e0a 06/12/2013 06:20 pm Claudio Fontana

tcg/aarch64: implement new TCG target for aarch64

add preliminary support for TCG target aarch64.

Signed-off-by: Claudio Fontana <>
Reviewed-by: Richard Henderson <>
Reviewed-by: Peter Maydell <>...
36fac14a 06/12/2013 06:20 pm Claudio Fontana

tcg/aarch64: improve arith shifted regs operations

for arith operations, add SUBS, ANDS, ADDS and add a shift parameter
so that all arith instructions can make use of shifted registers.

Signed-off-by: Claudio Fontana <>
Reviewed-by: Richard Henderson <>...
7deea126 06/12/2013 06:20 pm Claudio Fontana

tcg/aarch64: implement AND/TEST immediate pattern

add functions to AND/TEST registers with immediate patterns.

Signed-off-by: Claudio Fontana <>
Reviewed-by: Richard Henderson <>
Message-id: ...
56bbc2f9 06/05/2013 03:54 pm Richard Henderson

tcg: Remove redundant tcg_target_init checks

We've got a compile-time check for the condition in exec/cpu-defs.h.

Reviewed-by: Andreas Färber <>
Reviewed-by: liguang <>
Signed-off-by: Richard Henderson <>
66e61b55 05/09/2013 05:14 pm Aurelien Jarno

tcg/optimize: fix setcond2 optimization

When setcond2 is rewritten into setcond, the state of the destination
temp should be reset, so that a copy of the previous value is not
used instead of the result.

Reported-by: Michael Tokarev <>
Reviewed-by: Richard Henderson <>...
c9e53a4c 05/03/2013 12:53 pm Richard Henderson

tcg-arm: Use movi32 in exit_tb

Avoid the mini constant pool for armv7, and avoid replicating
the test for pre-v7.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
8ddaeb1b 05/03/2013 12:53 pm Richard Henderson

tcg-arm: Fix 64-bit tlb load for pre-v6

Found by inspection, since the effect of the bug was simply to
send all memory ops through the slow path.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
cee87be8 04/27/2013 03:16 am Richard Henderson

tcg-arm: Split out tcg_out_tlb_read

Share code between qemu_ld and qemu_st to process the tlb.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
702b33b1 04/27/2013 03:16 am Richard Henderson

tcg-arm: Improve scheduling of tcg_out_tlb_read

The schedule was fully serial, with no possibility for dual issue.
The old schedule had a minimal issue of 7 cycles; the new schedule
has a minimal issue of 5 cycles.

Signed-off-by: Richard Henderson <>
595b5397 04/27/2013 03:16 am Richard Henderson

tcg-arm: Delete the 'S' constraint

After the previous patch, 's' and 'S' are the same.

Signed-off-by: Richard Henderson <>
302fdde7 04/27/2013 03:16 am Richard Henderson

tcg-arm: Use movi32 + blx for calls on v7

Work better with branch predition when we have movw+movt,
as the size of the code is the same. Perhaps re-evaluate
when we have a proper constant pool.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
df5e0ef7 04/27/2013 03:16 am Richard Henderson

tcg-arm: Convert to CONFIG_QEMU_LDST_OPTIMIZATION

Move the slow path out of line, as the TODO's mention.
This allows the fast path to be unconditional, which can
speed up the fast path as well, depending on the core.

Signed-off-by: Richard Henderson <>
96fbd7de 04/27/2013 03:16 am Richard Henderson

tcg-arm: Remove long jump from tcg_out_goto_label

Branches within a TB will always be within 16MB.

Signed-off-by: Richard Henderson <>
b6b24cb0 04/27/2013 03:16 am Richard Henderson

tcg-arm: Implement deposit for armv7

We have BFI and BFC available for implementing it.

Signed-off-by: Richard Henderson <>
0637c56c 04/27/2013 03:16 am Richard Henderson

tcg-arm: Implement division instructions

An armv7 extension implements division, present on Cortex A15.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
4346457a 04/27/2013 03:16 am Richard Henderson

tcg-arm: Use TCG_REG_TMP name for the tcg temporary

Don't hard-code R8.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
13dd6fb9 04/27/2013 03:16 am Richard Henderson

tcg-arm: Use R12 for the tcg temporary

R12 is call clobbered, while R8 is call saved. This change
gives tcg one more call saved register for real data.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
34358a12 04/27/2013 03:16 am Richard Henderson

tcg-arm: Cleanup multiply subroutines

Make the code more readable by only having one copy of the magic
numbers, swapping registers as needed prior to that. Speed the
compiler by not applying the rd == rn avoidance for v6 or later.

Reviewed-by: Aurelien Jarno <>...
9feac1d7 04/27/2013 03:16 am Richard Henderson

tcg-arm: Cleanup most primitive load store subroutines

Use even more primitive helper functions to avoid lots of duplicated code.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
a9a86ae9 04/27/2013 03:16 am Richard Henderson

tcg-arm: Handle negated constant arguments to and/sub

This greatly improves code generation for addition of small
negative constants.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
d9fda575 04/27/2013 03:16 am Richard Henderson

tcg-arm: Allow constant first argument to sub

This allows the generation of RSB instructions.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
5d53b4c9 04/27/2013 03:16 am Richard Henderson

tcg-arm: Use tcg_out_dat_rIN for compares

This allows us to emit CMN instructions.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
2df3f1ee 04/27/2013 03:16 am Richard Henderson

tcg-arm: Handle constant arguments to add2/sub2

We get to re-use the _rIN and _rIK subroutines to handle the various
combinations of add vs sub. Fold the << 21 into the opcode enum values
so that we can explicitly add TO_CPSR as desired.

Reviewed-by: Aurelien Jarno <>...
e86e0f28 04/27/2013 03:16 am Richard Henderson

tcg-arm: Improve constant generation

Try fully rotated arguments to mov and mvn before trying movt
or full decomposition. Begin decomposition with mvn when it
looks like it'll help. Examples include

: mov r9, #0x00000fa0
: orr r9, r9, #0x000ee000...
19b62bf4 04/27/2013 03:16 am Richard Henderson

tcg-arm: Use bic to implement and with constant

This greatly improves the code we can produce for deposit
without armv7 support.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
d6b64b2b 04/27/2013 03:15 am Richard Henderson

tcg: Log the contents of the prologue with -d out_asm

This makes it easier to verify changes to the code
generating the prologue.

[Aurelien: change the format from %i to %zu]

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
fc4d60ee 04/27/2013 02:19 am Richard Henderson

tcg-arm: Fix local stack frame

We were not allocating TCG_STATIC_CALL_ARGS_SIZE, so this meant that
any helper with more than 4 arguments would clobber the saved regs.
Realizing that we're supposed to have this memory pre-allocated means
we can clean up the tcg_out_arg functions, which were trying to do...
ed605126 04/27/2013 02:10 am Aurelien Jarno

tcg: fix deposit_i64 op on 32-bit targets

On 32-bit TCG targets, when emulating deposit_i64 with a mov_i32 +
deposit_i32, care should be taken to not overwrite the low part of
the second argument before the deposit when it is the same the
destination.

This fixes the shld instruction in qemu-system-x86_64, which in turns...
39dc85b9 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Handle deposit of zero

The TCG optimizer does great work when inserting constants, being able
to fold the open-coded deposit expansion to just an AND or an OR. Avoid
a bit the regression caused by having the deposit opcode by expanding
deposit of zero as an AND....
027ffea9 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Implement movcond

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
1e6e9aca 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Use getauxval for ISA detection

Glibc 2.16 includes an easy way to get feature bits previously
buried in /proc or the program startup auxiliary vector. Use it.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
6c858762 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Implement add2/sub2_i64

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
6645c147 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Implement mulu2/muls2_i64

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
991041a4 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Cleanup i32 constants to tcg_out_cmp

Nothing else in the call chain ensures that these
constants don't have garbage in the high bits.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
6995a4a0 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Use MFOCRF instead of MFCR

It takes half the cycles to read one CR register instead of all 8.
This is a backward compatible addition to the ISA, so chips prior
to Power 2.00 spec will simply continue to read the entire CR register.

Reviewed-by: Aurelien Jarno <>...
70fac59a 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Use ISEL for setcond

There are a few simple special cases that should be handled first.
Break these out to subroutines to avoid code duplication.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
33de9ed2 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Implement deposit

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
ef809300 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Use I constraint for mul

The mul_i32 pattern was loading non-16-bit constants into a register,
when we can get the middle-end to do that for us. The mul_i64 pattern
was not considering that MULLI takes 64-bit inputs.

Reviewed-by: Aurelien Jarno <>...
4c314da6 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Use TCGType throughout compares

The optimization/bug being fixed is that tcg_out_cmp was not applying the
right type to loading a constant, in the case it can't be implemented
directly. Rather than recomputing the TCGType enum from the arch64 bool,...
68aebd45 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Implement bswap64

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
ce1010d6 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Implement compound logicals

Mostly copied from the ppc32 port.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
37251b98 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Handle constant inputs for some compound logicals

Since we have special code to handle and/or/xor with a constant,
apply the same to andc/orc/eqv with a constant.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
5d221582 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Implement bswap16 and bswap32

Signed-off-by: Richard Henderson <>
313d91c7 04/15/2013 08:55 pm Richard Henderson

tcg-ppc64: Implement rotates

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
49d9870a 04/15/2013 08:55 pm Richard Henderson

tcg-ppc64: Streamline qemu_ld/st insn selection

Using a table to look up insns of the right width and sign.
Include support for the Power 2.06 LDBRX and STDBRX insns.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
28f2dba6 04/15/2013 08:55 pm Richard Henderson

tcg-ppc64: Use automatic implementation of ext32u_i64

The enhancements to and immediate obviate this.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
a9249dff 04/15/2013 08:55 pm Richard Henderson

tcg-ppc64: Improve and_i32 with constant

Use RLWINM

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
637af30c 04/15/2013 08:55 pm Richard Henderson

tcg-ppc64: Improve and_i64 with constant

Use RLDICL and RLDICR.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
dce74c57 04/15/2013 08:55 pm Richard Henderson

tcg-ppc64: Tidy or and xor patterns.

Handle constants in common code; we'll want to reuse that later.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
148bdd23 04/15/2013 08:55 pm Richard Henderson

tcg-ppc64: Allow constant first argument to sub

Using SUBFIC for 16-bit signed constants.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
ee924fa6 04/15/2013 08:55 pm Richard Henderson

tcg-ppc64: Improve constant add and sub ops.

Improve constant addition -- previously we'd emit useless addi with 0.
Use new constraints to force the driver to pull full 64-bit constants
into a register.

Reviewed-by: Aurelien Jarno <>...
3d582c61 04/15/2013 08:52 pm Richard Henderson

tcg-ppc64: Rearrange integer constant constraints

We'll need a zero, and Z makes more sense for that. Make sure we
have a full compliment of signed and unsigned 16 and 32-bit tests.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
421233a1 04/15/2013 08:52 pm Richard Henderson

tcg-ppc64: Cleanup tcg_out_movi

The test for using movi32 was sub-optimal for TCG_TYPE_I32, comparing
a signed 32-bit quantity against an unsigned 32-bit quantity.

When possible, use addi+oris for 32-bit unsigned constants. Otherwise,
standardize on addi+oris+ori instead of addis+ori+rldicl....
752c1fdb 04/15/2013 08:51 pm Richard Henderson

tcg-ppc64: Fix setcond_i32

We weren't ignoring the high 32 bits during a NE comparison.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
2fd8eddc 04/15/2013 08:44 pm Richard Henderson

tcg-ppc64: Introduce and use TAI and SAI

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
5e916c28 04/15/2013 08:44 pm Richard Henderson

tcg-ppc64: Introduce and use tcg_out_shri64

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
0a9564b9 04/15/2013 08:44 pm Richard Henderson

tcg-ppc64: Introduce and use tcg_out_shli64

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
6e5e0602 04/15/2013 08:44 pm Richard Henderson

tcg-ppc64: Introduce and use tcg_out_ext32u

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
9e555b73 04/15/2013 08:44 pm Richard Henderson

tcg-ppc64: Introduce and use tcg_out_rlw

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
aceac8d6 04/15/2013 08:44 pm Richard Henderson

tcg-ppc64: Use TCGReg everywhere

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
0a9c2341 04/13/2013 02:50 pm Aurelien Jarno

Merge branch 'tci' of git://qemu.weilnetz.de/qemu

  • 'tci' of git://qemu.weilnetz.de/qemu:
    tci: Make tcg temporaries local to tcg_qemu_tb_exec
    tci: Delete unused tb_ret_addr
    tci: Avoid code before declarations
    tci: Use a local variable for env
    tci: Use 32-bit signed offsets to loads/stores
03fc0548 04/11/2013 08:58 pm Richard Henderson

tci: Use 32-bit signed offsets to loads/stores

Since the change to tcg_exit_req, the first insn of every TB is
a load with a negative offset from env.

Signed-off-by: Richard Henderson <>
Signed-off by: Stefan Weil <>
4699ca6d 04/11/2013 08:58 pm Richard Henderson

tci: Delete unused tb_ret_addr

Signed-off-by: Richard Henderson <>
Signed-off by: Stefan Weil <>
ee79c356 04/11/2013 08:58 pm Richard Henderson

tci: Make tcg temporaries local to tcg_qemu_tb_exec

We're moving away from the temporaries stored in env. Make sure we can
differentiate between temp stores and possibly bogus stores for extra
call arguments. Move TCG_AREG0 and TCG_REG_CALL_STACK out of the way...
b879f308 04/05/2013 09:35 pm Richard Henderson

tcg-s390: Fix merge error in tgen_brcond

When the TCG condition codes were re-organized last year,
we failed to update all of the "old-style" tests for unsigned.

Signed-off-by: Richard Henderson <>
07ff7983 04/05/2013 09:35 pm Richard Henderson

tcg-s390: Remove constraint letters for and

Since we have a free temporary and can always just load the constant, we
ought to do so, rather than spending the same effort constraining the const.

Signed-off-by: Richard Henderson <>
f0bffc27 04/05/2013 09:35 pm Richard Henderson

tcg-s390: Use risbgz for andi

This is immediately usable by the tlb lookup code.

Signed-off-by: Richard Henderson <>
65a62a75 04/05/2013 09:35 pm Richard Henderson

tcg-s390: Cleanup argument shuffling fixme in softmmu code

Signed-off-by: Richard Henderson <>
0db921e6 04/05/2013 09:35 pm Richard Henderson

tcg-s390: Use load-address for addition

Since we're always in 64-bit mode, load address performs a full
64-bit add. Use that for 3-address addition, as well as for
larger constant addends when we lack extended-immediates facility.

Signed-off-by: Richard Henderson <>
78c9f7c5 04/05/2013 09:35 pm Richard Henderson

tcg-s390: Use all 20 bits of the offset in tcg_out_mem

This can save one insn, if the constant has any bits in 32-63 set,
but no bits in 21-31 set. It never results in more insns.

Signed-off-by: Richard Henderson <>
a01fc30d 04/05/2013 09:35 pm Richard Henderson

tcg-s390: Remove useless preprocessor conditions

We only support 64-bit code generation for s390x.
Don't clutter the code with ifdefs that suggest otherwise.

Signed-off-by: Richard Henderson <>
3790b918 04/05/2013 09:35 pm Richard Henderson

tcg-s390: Implement add2/sub2 opcodes

Signed-off-by: Richard Henderson <>
36017dc6 04/05/2013 09:35 pm Richard Henderson

tcg-s390: Implement mulu2_i64 opcode

Signed-off-by: Richard Henderson <>
96a9f093 04/05/2013 09:35 pm Richard Henderson

tcg-s390: Implement movcond opcodes

Signed-off-by: Richard Henderson <>
d5690ea4 04/05/2013 09:35 pm Richard Henderson

tcg-s390: Implement deposit opcodes

Signed-off-by: Richard Henderson <>