root / tests / i440fx-test.c @ f53ec699
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/*
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* qtest I440FX test case
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*
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* Copyright IBM, Corp. 2012-2013
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*
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* Authors:
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* Anthony Liguori <aliguori@us.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "libqos/pci.h" |
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#include "libqos/pci-pc.h" |
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#include "libqtest.h" |
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#include "hw/pci/pci_regs.h" |
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#include <glib.h> |
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#include <string.h> |
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#define BROKEN 1 |
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#define ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0])) |
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typedef struct TestData |
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{
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int num_cpus;
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QPCIBus *bus; |
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} TestData; |
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static void test_i440fx_defaults(gconstpointer opaque) |
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{
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const TestData *s = opaque;
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QPCIDevice *dev; |
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uint32_t value; |
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dev = qpci_device_find(s->bus, QPCI_DEVFN(0, 0)); |
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g_assert(dev != NULL);
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/* 3.2.2 */
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g_assert_cmpint(qpci_config_readw(dev, PCI_VENDOR_ID), ==, 0x8086);
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/* 3.2.3 */
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g_assert_cmpint(qpci_config_readw(dev, PCI_DEVICE_ID), ==, 0x1237);
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#ifndef BROKEN
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/* 3.2.4 */
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g_assert_cmpint(qpci_config_readw(dev, PCI_COMMAND), ==, 0x0006);
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/* 3.2.5 */
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g_assert_cmpint(qpci_config_readw(dev, PCI_STATUS), ==, 0x0280);
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#endif
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/* 3.2.7 */
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g_assert_cmpint(qpci_config_readb(dev, PCI_CLASS_PROG), ==, 0x00);
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g_assert_cmpint(qpci_config_readw(dev, PCI_CLASS_DEVICE), ==, 0x0600);
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/* 3.2.8 */
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g_assert_cmpint(qpci_config_readb(dev, PCI_LATENCY_TIMER), ==, 0x00);
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/* 3.2.9 */
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g_assert_cmpint(qpci_config_readb(dev, PCI_HEADER_TYPE), ==, 0x00);
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/* 3.2.10 */
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g_assert_cmpint(qpci_config_readb(dev, PCI_BIST), ==, 0x00);
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/* 3.2.11 */
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value = qpci_config_readw(dev, 0x50); /* PMCCFG */ |
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if (s->num_cpus == 1) { /* WPE */ |
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g_assert(!(value & (1 << 15))); |
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} else {
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g_assert((value & (1 << 15))); |
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} |
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g_assert(!(value & (1 << 6))); /* EPTE */ |
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/* 3.2.12 */
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g_assert_cmpint(qpci_config_readb(dev, 0x52), ==, 0x00); /* DETURBO */ |
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/* 3.2.13 */
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#ifndef BROKEN
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g_assert_cmpint(qpci_config_readb(dev, 0x53), ==, 0x80); /* DBC */ |
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#endif
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/* 3.2.14 */
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g_assert_cmpint(qpci_config_readb(dev, 0x54), ==, 0x00); /* AXC */ |
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/* 3.2.15 */
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g_assert_cmpint(qpci_config_readw(dev, 0x55), ==, 0x0000); /* DRT */ |
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#ifndef BROKEN
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/* 3.2.16 */
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g_assert_cmpint(qpci_config_readb(dev, 0x57), ==, 0x01); /* DRAMC */ |
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/* 3.2.17 */
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g_assert_cmpint(qpci_config_readb(dev, 0x58), ==, 0x10); /* DRAMT */ |
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#endif
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/* 3.2.18 */
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g_assert_cmpint(qpci_config_readb(dev, 0x59), ==, 0x00); /* PAM0 */ |
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g_assert_cmpint(qpci_config_readb(dev, 0x5A), ==, 0x00); /* PAM1 */ |
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g_assert_cmpint(qpci_config_readb(dev, 0x5B), ==, 0x00); /* PAM2 */ |
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g_assert_cmpint(qpci_config_readb(dev, 0x5C), ==, 0x00); /* PAM3 */ |
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g_assert_cmpint(qpci_config_readb(dev, 0x5D), ==, 0x00); /* PAM4 */ |
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g_assert_cmpint(qpci_config_readb(dev, 0x5E), ==, 0x00); /* PAM5 */ |
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g_assert_cmpint(qpci_config_readb(dev, 0x5F), ==, 0x00); /* PAM6 */ |
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#ifndef BROKEN
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/* 3.2.19 */
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g_assert_cmpint(qpci_config_readb(dev, 0x60), ==, 0x01); /* DRB0 */ |
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g_assert_cmpint(qpci_config_readb(dev, 0x61), ==, 0x01); /* DRB1 */ |
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g_assert_cmpint(qpci_config_readb(dev, 0x62), ==, 0x01); /* DRB2 */ |
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g_assert_cmpint(qpci_config_readb(dev, 0x63), ==, 0x01); /* DRB3 */ |
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g_assert_cmpint(qpci_config_readb(dev, 0x64), ==, 0x01); /* DRB4 */ |
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g_assert_cmpint(qpci_config_readb(dev, 0x65), ==, 0x01); /* DRB5 */ |
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g_assert_cmpint(qpci_config_readb(dev, 0x66), ==, 0x01); /* DRB6 */ |
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g_assert_cmpint(qpci_config_readb(dev, 0x67), ==, 0x01); /* DRB7 */ |
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#endif
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/* 3.2.20 */
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g_assert_cmpint(qpci_config_readb(dev, 0x68), ==, 0x00); /* FDHC */ |
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/* 3.2.21 */
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g_assert_cmpint(qpci_config_readb(dev, 0x70), ==, 0x00); /* MTT */ |
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#ifndef BROKEN
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/* 3.2.22 */
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g_assert_cmpint(qpci_config_readb(dev, 0x71), ==, 0x10); /* CLT */ |
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#endif
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/* 3.2.23 */
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g_assert_cmpint(qpci_config_readb(dev, 0x72), ==, 0x02); /* SMRAM */ |
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/* 3.2.24 */
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g_assert_cmpint(qpci_config_readb(dev, 0x90), ==, 0x00); /* ERRCMD */ |
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/* 3.2.25 */
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g_assert_cmpint(qpci_config_readb(dev, 0x91), ==, 0x00); /* ERRSTS */ |
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/* 3.2.26 */
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g_assert_cmpint(qpci_config_readb(dev, 0x93), ==, 0x00); /* TRC */ |
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} |
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#define PAM_RE 1 |
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#define PAM_WE 2 |
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static void pam_set(QPCIDevice *dev, int index, int flags) |
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{
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int regno = 0x59 + (index / 2); |
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uint8_t reg; |
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reg = qpci_config_readb(dev, regno); |
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if (index & 1) { |
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reg = (reg & 0x0F) | (flags << 4); |
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} else {
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reg = (reg & 0xF0) | flags;
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} |
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qpci_config_writeb(dev, regno, reg); |
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} |
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static gboolean verify_area(uint32_t start, uint32_t end, uint8_t value)
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{
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uint32_t size = end - start + 1;
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gboolean ret = TRUE; |
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uint8_t *data; |
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int i;
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data = g_malloc0(size); |
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memread(start, data, size); |
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g_test_message("verify_area: data[0] = 0x%x", data[0]); |
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for (i = 0; i < size; i++) { |
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if (data[i] != value) {
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ret = FALSE; |
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break;
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} |
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} |
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g_free(data); |
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return ret;
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} |
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static void write_area(uint32_t start, uint32_t end, uint8_t value) |
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{
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uint32_t size = end - start + 1;
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uint8_t *data; |
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data = g_malloc0(size); |
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memset(data, value, size); |
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memwrite(start, data, size); |
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g_free(data); |
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} |
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static void test_i440fx_pam(gconstpointer opaque) |
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{
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const TestData *s = opaque;
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QPCIDevice *dev; |
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int i;
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static struct { |
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uint32_t start; |
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uint32_t end; |
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} pam_area[] = {
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{ 0, 0 }, /* Reserved */
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{ 0xF0000, 0xFFFFF }, /* BIOS Area */
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{ 0xC0000, 0xC3FFF }, /* Option ROM */
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{ 0xC4000, 0xC7FFF }, /* Option ROM */
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{ 0xC8000, 0xCBFFF }, /* Option ROM */
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{ 0xCC000, 0xCFFFF }, /* Option ROM */
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{ 0xD0000, 0xD3FFF }, /* Option ROM */
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{ 0xD4000, 0xD7FFF }, /* Option ROM */
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{ 0xD8000, 0xDBFFF }, /* Option ROM */
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{ 0xDC000, 0xDFFFF }, /* Option ROM */
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{ 0xE0000, 0xE3FFF }, /* BIOS Extension */
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{ 0xE4000, 0xE7FFF }, /* BIOS Extension */
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{ 0xE8000, 0xEBFFF }, /* BIOS Extension */
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{ 0xEC000, 0xEFFFF }, /* BIOS Extension */
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}; |
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dev = qpci_device_find(s->bus, QPCI_DEVFN(0, 0)); |
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g_assert(dev != NULL);
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for (i = 0; i < ARRAY_SIZE(pam_area); i++) { |
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if (pam_area[i].start == pam_area[i].end) {
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continue;
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} |
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g_test_message("Checking area 0x%05x..0x%05x",
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pam_area[i].start, pam_area[i].end); |
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/* Switch to RE for the area */
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pam_set(dev, i, PAM_RE); |
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/* Verify the RAM is all zeros */
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g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0));
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/* Switch to WE for the area */
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pam_set(dev, i, PAM_RE | PAM_WE); |
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/* Write out a non-zero mask to the full area */
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write_area(pam_area[i].start, pam_area[i].end, 0x42);
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#ifndef BROKEN
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/* QEMU only supports a limited form of PAM */
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/* Switch to !RE for the area */
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pam_set(dev, i, PAM_WE); |
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/* Verify the area is not our mask */
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g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x42));
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#endif
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/* Verify the area is our new mask */
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g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x42));
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/* Write out a new mask */
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write_area(pam_area[i].start, pam_area[i].end, 0x82);
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#ifndef BROKEN
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/* QEMU only supports a limited form of PAM */
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/* Verify the area is not our mask */
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g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
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/* Switch to RE for the area */
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pam_set(dev, i, PAM_RE | PAM_WE); |
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#endif
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/* Verify the area is our new mask */
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g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x82));
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/* Reset area */
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pam_set(dev, i, 0);
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/* Verify the area is not our new mask */
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g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
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} |
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} |
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int main(int argc, char **argv) |
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{
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QTestState *s; |
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TestData data; |
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char *cmdline;
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int ret;
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g_test_init(&argc, &argv, NULL);
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data.num_cpus = 1;
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cmdline = g_strdup_printf("-display none -smp %d", data.num_cpus);
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s = qtest_start(cmdline); |
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g_free(cmdline); |
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data.bus = qpci_init_pc(); |
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g_test_add_data_func("/i440fx/defaults", &data, test_i440fx_defaults);
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g_test_add_data_func("/i440fx/pam", &data, test_i440fx_pam);
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ret = g_test_run(); |
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if (s) {
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qtest_quit(s); |
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} |
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return ret;
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} |