root / hw / char / grlib_apbuart.c @ f53f81e0
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1 | 8b1e1320 | Fabien Chouteau | /*
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2 | 8b1e1320 | Fabien Chouteau | * QEMU GRLIB APB UART Emulator
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3 | 8b1e1320 | Fabien Chouteau | *
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4 | 8b1e1320 | Fabien Chouteau | * Copyright (c) 2010-2011 AdaCore
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5 | 8b1e1320 | Fabien Chouteau | *
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6 | 8b1e1320 | Fabien Chouteau | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 8b1e1320 | Fabien Chouteau | * of this software and associated documentation files (the "Software"), to deal
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8 | 8b1e1320 | Fabien Chouteau | * in the Software without restriction, including without limitation the rights
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9 | 8b1e1320 | Fabien Chouteau | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 8b1e1320 | Fabien Chouteau | * copies of the Software, and to permit persons to whom the Software is
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11 | 8b1e1320 | Fabien Chouteau | * furnished to do so, subject to the following conditions:
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12 | 8b1e1320 | Fabien Chouteau | *
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13 | 8b1e1320 | Fabien Chouteau | * The above copyright notice and this permission notice shall be included in
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14 | 8b1e1320 | Fabien Chouteau | * all copies or substantial portions of the Software.
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15 | 8b1e1320 | Fabien Chouteau | *
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16 | 8b1e1320 | Fabien Chouteau | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 8b1e1320 | Fabien Chouteau | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 8b1e1320 | Fabien Chouteau | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 8b1e1320 | Fabien Chouteau | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 8b1e1320 | Fabien Chouteau | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 8b1e1320 | Fabien Chouteau | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 8b1e1320 | Fabien Chouteau | * THE SOFTWARE.
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23 | 8b1e1320 | Fabien Chouteau | */
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24 | 8b1e1320 | Fabien Chouteau | |
25 | 83c9f4ca | Paolo Bonzini | #include "hw/sysbus.h" |
26 | dccfcd0e | Paolo Bonzini | #include "sysemu/char.h" |
27 | 8b1e1320 | Fabien Chouteau | |
28 | 8b1e1320 | Fabien Chouteau | #include "trace.h" |
29 | 8b1e1320 | Fabien Chouteau | |
30 | 8b1e1320 | Fabien Chouteau | #define UART_REG_SIZE 20 /* Size of memory mapped registers */ |
31 | 8b1e1320 | Fabien Chouteau | |
32 | 8b1e1320 | Fabien Chouteau | /* UART status register fields */
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33 | 8b1e1320 | Fabien Chouteau | #define UART_DATA_READY (1 << 0) |
34 | 8b1e1320 | Fabien Chouteau | #define UART_TRANSMIT_SHIFT_EMPTY (1 << 1) |
35 | 8b1e1320 | Fabien Chouteau | #define UART_TRANSMIT_FIFO_EMPTY (1 << 2) |
36 | 8b1e1320 | Fabien Chouteau | #define UART_BREAK_RECEIVED (1 << 3) |
37 | 8b1e1320 | Fabien Chouteau | #define UART_OVERRUN (1 << 4) |
38 | 8b1e1320 | Fabien Chouteau | #define UART_PARITY_ERROR (1 << 5) |
39 | 8b1e1320 | Fabien Chouteau | #define UART_FRAMING_ERROR (1 << 6) |
40 | 8b1e1320 | Fabien Chouteau | #define UART_TRANSMIT_FIFO_HALF (1 << 7) |
41 | 8b1e1320 | Fabien Chouteau | #define UART_RECEIVE_FIFO_HALF (1 << 8) |
42 | 8b1e1320 | Fabien Chouteau | #define UART_TRANSMIT_FIFO_FULL (1 << 9) |
43 | 8b1e1320 | Fabien Chouteau | #define UART_RECEIVE_FIFO_FULL (1 << 10) |
44 | 8b1e1320 | Fabien Chouteau | |
45 | 8b1e1320 | Fabien Chouteau | /* UART control register fields */
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46 | 8b1e1320 | Fabien Chouteau | #define UART_RECEIVE_ENABLE (1 << 0) |
47 | 8b1e1320 | Fabien Chouteau | #define UART_TRANSMIT_ENABLE (1 << 1) |
48 | 8b1e1320 | Fabien Chouteau | #define UART_RECEIVE_INTERRUPT (1 << 2) |
49 | 8b1e1320 | Fabien Chouteau | #define UART_TRANSMIT_INTERRUPT (1 << 3) |
50 | 8b1e1320 | Fabien Chouteau | #define UART_PARITY_SELECT (1 << 4) |
51 | 8b1e1320 | Fabien Chouteau | #define UART_PARITY_ENABLE (1 << 5) |
52 | 8b1e1320 | Fabien Chouteau | #define UART_FLOW_CONTROL (1 << 6) |
53 | 8b1e1320 | Fabien Chouteau | #define UART_LOOPBACK (1 << 7) |
54 | 8b1e1320 | Fabien Chouteau | #define UART_EXTERNAL_CLOCK (1 << 8) |
55 | 8b1e1320 | Fabien Chouteau | #define UART_RECEIVE_FIFO_INTERRUPT (1 << 9) |
56 | 8b1e1320 | Fabien Chouteau | #define UART_TRANSMIT_FIFO_INTERRUPT (1 << 10) |
57 | 8b1e1320 | Fabien Chouteau | #define UART_FIFO_DEBUG_MODE (1 << 11) |
58 | 8b1e1320 | Fabien Chouteau | #define UART_OUTPUT_ENABLE (1 << 12) |
59 | 8b1e1320 | Fabien Chouteau | #define UART_FIFO_AVAILABLE (1 << 31) |
60 | 8b1e1320 | Fabien Chouteau | |
61 | 8b1e1320 | Fabien Chouteau | /* Memory mapped register offsets */
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62 | 8b1e1320 | Fabien Chouteau | #define DATA_OFFSET 0x00 |
63 | 8b1e1320 | Fabien Chouteau | #define STATUS_OFFSET 0x04 |
64 | 8b1e1320 | Fabien Chouteau | #define CONTROL_OFFSET 0x08 |
65 | 8b1e1320 | Fabien Chouteau | #define SCALER_OFFSET 0x0C /* not supported */ |
66 | 8b1e1320 | Fabien Chouteau | #define FIFO_DEBUG_OFFSET 0x10 /* not supported */ |
67 | 8b1e1320 | Fabien Chouteau | |
68 | 0c685d28 | Fabien Chouteau | #define FIFO_LENGTH 1024 |
69 | 0c685d28 | Fabien Chouteau | |
70 | ae8e0490 | Andreas Färber | #define TYPE_GRLIB_APB_UART "grlib,apbuart" |
71 | ae8e0490 | Andreas Färber | #define GRLIB_APB_UART(obj) \
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72 | ae8e0490 | Andreas Färber | OBJECT_CHECK(UART, (obj), TYPE_GRLIB_APB_UART) |
73 | ae8e0490 | Andreas Färber | |
74 | 8b1e1320 | Fabien Chouteau | typedef struct UART { |
75 | ae8e0490 | Andreas Färber | SysBusDevice parent_obj; |
76 | ae8e0490 | Andreas Färber | |
77 | 6281f7d1 | Avi Kivity | MemoryRegion iomem; |
78 | 8b1e1320 | Fabien Chouteau | qemu_irq irq; |
79 | 8b1e1320 | Fabien Chouteau | |
80 | 8b1e1320 | Fabien Chouteau | CharDriverState *chr; |
81 | 8b1e1320 | Fabien Chouteau | |
82 | 8b1e1320 | Fabien Chouteau | /* registers */
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83 | 8b1e1320 | Fabien Chouteau | uint32_t status; |
84 | 8b1e1320 | Fabien Chouteau | uint32_t control; |
85 | 0c685d28 | Fabien Chouteau | |
86 | 0c685d28 | Fabien Chouteau | /* FIFO */
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87 | 0c685d28 | Fabien Chouteau | char buffer[FIFO_LENGTH];
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88 | 0c685d28 | Fabien Chouteau | int len;
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89 | 0c685d28 | Fabien Chouteau | int current;
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90 | 8b1e1320 | Fabien Chouteau | } UART; |
91 | 8b1e1320 | Fabien Chouteau | |
92 | 0c685d28 | Fabien Chouteau | static int uart_data_to_read(UART *uart) |
93 | 0c685d28 | Fabien Chouteau | { |
94 | 0c685d28 | Fabien Chouteau | return uart->current < uart->len;
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95 | 0c685d28 | Fabien Chouteau | } |
96 | 0c685d28 | Fabien Chouteau | |
97 | 0c685d28 | Fabien Chouteau | static char uart_pop(UART *uart) |
98 | 0c685d28 | Fabien Chouteau | { |
99 | 0c685d28 | Fabien Chouteau | char ret;
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100 | 0c685d28 | Fabien Chouteau | |
101 | 0c685d28 | Fabien Chouteau | if (uart->len == 0) { |
102 | 0c685d28 | Fabien Chouteau | uart->status &= ~UART_DATA_READY; |
103 | 0c685d28 | Fabien Chouteau | return 0; |
104 | 0c685d28 | Fabien Chouteau | } |
105 | 0c685d28 | Fabien Chouteau | |
106 | 0c685d28 | Fabien Chouteau | ret = uart->buffer[uart->current++]; |
107 | 0c685d28 | Fabien Chouteau | |
108 | 0c685d28 | Fabien Chouteau | if (uart->current >= uart->len) {
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109 | 0c685d28 | Fabien Chouteau | /* Flush */
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110 | 0c685d28 | Fabien Chouteau | uart->len = 0;
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111 | 0c685d28 | Fabien Chouteau | uart->current = 0;
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112 | 0c685d28 | Fabien Chouteau | } |
113 | 0c685d28 | Fabien Chouteau | |
114 | 0c685d28 | Fabien Chouteau | if (!uart_data_to_read(uart)) {
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115 | 0c685d28 | Fabien Chouteau | uart->status &= ~UART_DATA_READY; |
116 | 0c685d28 | Fabien Chouteau | } |
117 | 0c685d28 | Fabien Chouteau | |
118 | 0c685d28 | Fabien Chouteau | return ret;
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119 | 0c685d28 | Fabien Chouteau | } |
120 | 0c685d28 | Fabien Chouteau | |
121 | 0c685d28 | Fabien Chouteau | static void uart_add_to_fifo(UART *uart, |
122 | 0c685d28 | Fabien Chouteau | const uint8_t *buffer,
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123 | 0c685d28 | Fabien Chouteau | int length)
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124 | 0c685d28 | Fabien Chouteau | { |
125 | 0c685d28 | Fabien Chouteau | if (uart->len + length > FIFO_LENGTH) {
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126 | 0c685d28 | Fabien Chouteau | abort(); |
127 | 0c685d28 | Fabien Chouteau | } |
128 | 0c685d28 | Fabien Chouteau | memcpy(uart->buffer + uart->len, buffer, length); |
129 | 0c685d28 | Fabien Chouteau | uart->len += length; |
130 | 0c685d28 | Fabien Chouteau | } |
131 | 0c685d28 | Fabien Chouteau | |
132 | 8b1e1320 | Fabien Chouteau | static int grlib_apbuart_can_receive(void *opaque) |
133 | 8b1e1320 | Fabien Chouteau | { |
134 | 8b1e1320 | Fabien Chouteau | UART *uart = opaque; |
135 | 8b1e1320 | Fabien Chouteau | |
136 | 0c685d28 | Fabien Chouteau | return FIFO_LENGTH - uart->len;
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137 | 8b1e1320 | Fabien Chouteau | } |
138 | 8b1e1320 | Fabien Chouteau | |
139 | 8b1e1320 | Fabien Chouteau | static void grlib_apbuart_receive(void *opaque, const uint8_t *buf, int size) |
140 | 8b1e1320 | Fabien Chouteau | { |
141 | 8b1e1320 | Fabien Chouteau | UART *uart = opaque; |
142 | 8b1e1320 | Fabien Chouteau | |
143 | 99e44800 | Ronald Hecht | if (uart->control & UART_RECEIVE_ENABLE) {
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144 | 99e44800 | Ronald Hecht | uart_add_to_fifo(uart, buf, size); |
145 | 0c685d28 | Fabien Chouteau | |
146 | 99e44800 | Ronald Hecht | uart->status |= UART_DATA_READY; |
147 | 8b1e1320 | Fabien Chouteau | |
148 | 99e44800 | Ronald Hecht | if (uart->control & UART_RECEIVE_INTERRUPT) {
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149 | 99e44800 | Ronald Hecht | qemu_irq_pulse(uart->irq); |
150 | 99e44800 | Ronald Hecht | } |
151 | 8b1e1320 | Fabien Chouteau | } |
152 | 8b1e1320 | Fabien Chouteau | } |
153 | 8b1e1320 | Fabien Chouteau | |
154 | 8b1e1320 | Fabien Chouteau | static void grlib_apbuart_event(void *opaque, int event) |
155 | 8b1e1320 | Fabien Chouteau | { |
156 | 8b1e1320 | Fabien Chouteau | trace_grlib_apbuart_event(event); |
157 | 8b1e1320 | Fabien Chouteau | } |
158 | 8b1e1320 | Fabien Chouteau | |
159 | 0c685d28 | Fabien Chouteau | |
160 | a8170e5e | Avi Kivity | static uint64_t grlib_apbuart_read(void *opaque, hwaddr addr, |
161 | 0c685d28 | Fabien Chouteau | unsigned size)
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162 | 0c685d28 | Fabien Chouteau | { |
163 | 0c685d28 | Fabien Chouteau | UART *uart = opaque; |
164 | 0c685d28 | Fabien Chouteau | |
165 | 0c685d28 | Fabien Chouteau | addr &= 0xff;
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166 | 0c685d28 | Fabien Chouteau | |
167 | 0c685d28 | Fabien Chouteau | /* Unit registers */
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168 | 0c685d28 | Fabien Chouteau | switch (addr) {
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169 | 0c685d28 | Fabien Chouteau | case DATA_OFFSET:
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170 | 0c685d28 | Fabien Chouteau | case DATA_OFFSET + 3: /* when only one byte read */ |
171 | 0c685d28 | Fabien Chouteau | return uart_pop(uart);
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172 | 0c685d28 | Fabien Chouteau | |
173 | 0c685d28 | Fabien Chouteau | case STATUS_OFFSET:
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174 | 0c685d28 | Fabien Chouteau | /* Read Only */
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175 | 0c685d28 | Fabien Chouteau | return uart->status;
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176 | 0c685d28 | Fabien Chouteau | |
177 | 0c685d28 | Fabien Chouteau | case CONTROL_OFFSET:
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178 | 0c685d28 | Fabien Chouteau | return uart->control;
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179 | 0c685d28 | Fabien Chouteau | |
180 | 0c685d28 | Fabien Chouteau | case SCALER_OFFSET:
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181 | 0c685d28 | Fabien Chouteau | /* Not supported */
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182 | 0c685d28 | Fabien Chouteau | return 0; |
183 | 0c685d28 | Fabien Chouteau | |
184 | 0c685d28 | Fabien Chouteau | default:
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185 | 0c685d28 | Fabien Chouteau | trace_grlib_apbuart_readl_unknown(addr); |
186 | 0c685d28 | Fabien Chouteau | return 0; |
187 | 0c685d28 | Fabien Chouteau | } |
188 | 0c685d28 | Fabien Chouteau | } |
189 | 0c685d28 | Fabien Chouteau | |
190 | a8170e5e | Avi Kivity | static void grlib_apbuart_write(void *opaque, hwaddr addr, |
191 | 0c685d28 | Fabien Chouteau | uint64_t value, unsigned size)
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192 | 8b1e1320 | Fabien Chouteau | { |
193 | 8b1e1320 | Fabien Chouteau | UART *uart = opaque; |
194 | 8b1e1320 | Fabien Chouteau | unsigned char c = 0; |
195 | 8b1e1320 | Fabien Chouteau | |
196 | 8b1e1320 | Fabien Chouteau | addr &= 0xff;
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197 | 8b1e1320 | Fabien Chouteau | |
198 | 8b1e1320 | Fabien Chouteau | /* Unit registers */
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199 | 8b1e1320 | Fabien Chouteau | switch (addr) {
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200 | 8b1e1320 | Fabien Chouteau | case DATA_OFFSET:
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201 | 0c685d28 | Fabien Chouteau | case DATA_OFFSET + 3: /* When only one byte write */ |
202 | 99e44800 | Ronald Hecht | /* Transmit when character device available and transmitter enabled */
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203 | 99e44800 | Ronald Hecht | if ((uart->chr) && (uart->control & UART_TRANSMIT_ENABLE)) {
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204 | 99e44800 | Ronald Hecht | c = value & 0xFF;
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205 | 99e44800 | Ronald Hecht | qemu_chr_fe_write(uart->chr, &c, 1);
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206 | 99e44800 | Ronald Hecht | /* Generate interrupt */
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207 | 99e44800 | Ronald Hecht | if (uart->control & UART_TRANSMIT_INTERRUPT) {
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208 | 99e44800 | Ronald Hecht | qemu_irq_pulse(uart->irq); |
209 | 99e44800 | Ronald Hecht | } |
210 | 99e44800 | Ronald Hecht | } |
211 | 8b1e1320 | Fabien Chouteau | return;
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212 | 8b1e1320 | Fabien Chouteau | |
213 | 8b1e1320 | Fabien Chouteau | case STATUS_OFFSET:
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214 | 8b1e1320 | Fabien Chouteau | /* Read Only */
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215 | 8b1e1320 | Fabien Chouteau | return;
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216 | 8b1e1320 | Fabien Chouteau | |
217 | 8b1e1320 | Fabien Chouteau | case CONTROL_OFFSET:
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218 | 0c685d28 | Fabien Chouteau | uart->control = value; |
219 | 8b1e1320 | Fabien Chouteau | return;
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220 | 8b1e1320 | Fabien Chouteau | |
221 | 8b1e1320 | Fabien Chouteau | case SCALER_OFFSET:
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222 | 8b1e1320 | Fabien Chouteau | /* Not supported */
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223 | 8b1e1320 | Fabien Chouteau | return;
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224 | 8b1e1320 | Fabien Chouteau | |
225 | 8b1e1320 | Fabien Chouteau | default:
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226 | 8b1e1320 | Fabien Chouteau | break;
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227 | 8b1e1320 | Fabien Chouteau | } |
228 | 8b1e1320 | Fabien Chouteau | |
229 | b4548fcc | Stefan Hajnoczi | trace_grlib_apbuart_writel_unknown(addr, value); |
230 | 8b1e1320 | Fabien Chouteau | } |
231 | 8b1e1320 | Fabien Chouteau | |
232 | 6281f7d1 | Avi Kivity | static const MemoryRegionOps grlib_apbuart_ops = { |
233 | 0c685d28 | Fabien Chouteau | .write = grlib_apbuart_write, |
234 | 0c685d28 | Fabien Chouteau | .read = grlib_apbuart_read, |
235 | 6281f7d1 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
236 | 8b1e1320 | Fabien Chouteau | }; |
237 | 8b1e1320 | Fabien Chouteau | |
238 | 8b1e1320 | Fabien Chouteau | static int grlib_apbuart_init(SysBusDevice *dev) |
239 | 8b1e1320 | Fabien Chouteau | { |
240 | ae8e0490 | Andreas Färber | UART *uart = GRLIB_APB_UART(dev); |
241 | 8b1e1320 | Fabien Chouteau | |
242 | 8b1e1320 | Fabien Chouteau | qemu_chr_add_handlers(uart->chr, |
243 | 8b1e1320 | Fabien Chouteau | grlib_apbuart_can_receive, |
244 | 8b1e1320 | Fabien Chouteau | grlib_apbuart_receive, |
245 | 8b1e1320 | Fabien Chouteau | grlib_apbuart_event, |
246 | 8b1e1320 | Fabien Chouteau | uart); |
247 | 8b1e1320 | Fabien Chouteau | |
248 | 8b1e1320 | Fabien Chouteau | sysbus_init_irq(dev, &uart->irq); |
249 | 8b1e1320 | Fabien Chouteau | |
250 | 300b1fc6 | Paolo Bonzini | memory_region_init_io(&uart->iomem, OBJECT(uart), &grlib_apbuart_ops, uart, |
251 | 6281f7d1 | Avi Kivity | "uart", UART_REG_SIZE);
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252 | 8b1e1320 | Fabien Chouteau | |
253 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &uart->iomem); |
254 | 8b1e1320 | Fabien Chouteau | |
255 | 8b1e1320 | Fabien Chouteau | return 0; |
256 | 8b1e1320 | Fabien Chouteau | } |
257 | 8b1e1320 | Fabien Chouteau | |
258 | 99e44800 | Ronald Hecht | static void grlib_apbuart_reset(DeviceState *d) |
259 | 99e44800 | Ronald Hecht | { |
260 | ae8e0490 | Andreas Färber | UART *uart = GRLIB_APB_UART(d); |
261 | 99e44800 | Ronald Hecht | |
262 | 99e44800 | Ronald Hecht | /* Transmitter FIFO and shift registers are always empty in QEMU */
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263 | 99e44800 | Ronald Hecht | uart->status = UART_TRANSMIT_FIFO_EMPTY | UART_TRANSMIT_SHIFT_EMPTY; |
264 | 99e44800 | Ronald Hecht | /* Everything is off */
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265 | 99e44800 | Ronald Hecht | uart->control = 0;
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266 | 99e44800 | Ronald Hecht | /* Flush receive FIFO */
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267 | 99e44800 | Ronald Hecht | uart->len = 0;
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268 | 99e44800 | Ronald Hecht | uart->current = 0;
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269 | 99e44800 | Ronald Hecht | } |
270 | 99e44800 | Ronald Hecht | |
271 | 8eda2228 | Fabien Chouteau | static Property grlib_apbuart_properties[] = {
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272 | 999e12bb | Anthony Liguori | DEFINE_PROP_CHR("chrdev", UART, chr),
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273 | 999e12bb | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
274 | 999e12bb | Anthony Liguori | }; |
275 | 999e12bb | Anthony Liguori | |
276 | 8eda2228 | Fabien Chouteau | static void grlib_apbuart_class_init(ObjectClass *klass, void *data) |
277 | 999e12bb | Anthony Liguori | { |
278 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
279 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
280 | 999e12bb | Anthony Liguori | |
281 | 999e12bb | Anthony Liguori | k->init = grlib_apbuart_init; |
282 | 99e44800 | Ronald Hecht | dc->reset = grlib_apbuart_reset; |
283 | 8eda2228 | Fabien Chouteau | dc->props = grlib_apbuart_properties; |
284 | 999e12bb | Anthony Liguori | } |
285 | 999e12bb | Anthony Liguori | |
286 | 8eda2228 | Fabien Chouteau | static const TypeInfo grlib_apbuart_info = { |
287 | ae8e0490 | Andreas Färber | .name = TYPE_GRLIB_APB_UART, |
288 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
289 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(UART),
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290 | 8eda2228 | Fabien Chouteau | .class_init = grlib_apbuart_class_init, |
291 | 8b1e1320 | Fabien Chouteau | }; |
292 | 8b1e1320 | Fabien Chouteau | |
293 | 8eda2228 | Fabien Chouteau | static void grlib_apbuart_register_types(void) |
294 | 8b1e1320 | Fabien Chouteau | { |
295 | 8eda2228 | Fabien Chouteau | type_register_static(&grlib_apbuart_info); |
296 | 8b1e1320 | Fabien Chouteau | } |
297 | 8b1e1320 | Fabien Chouteau | |
298 | 8eda2228 | Fabien Chouteau | type_init(grlib_apbuart_register_types) |