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/*
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* APIC support
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*
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* Copyright (c) 2004-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "apic_internal.h" |
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#include "apic.h" |
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#include "ioapic.h" |
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#include "host-utils.h" |
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#include "trace.h" |
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#include "pc.h" |
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#define MAX_APIC_WORDS 8 |
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/* Intel APIC constants: from include/asm/msidef.h */
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#define MSI_DATA_VECTOR_SHIFT 0 |
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#define MSI_DATA_VECTOR_MASK 0x000000ff |
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#define MSI_DATA_DELIVERY_MODE_SHIFT 8 |
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#define MSI_DATA_TRIGGER_SHIFT 15 |
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#define MSI_DATA_LEVEL_SHIFT 14 |
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#define MSI_ADDR_DEST_MODE_SHIFT 2 |
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#define MSI_ADDR_DEST_ID_SHIFT 12 |
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#define MSI_ADDR_DEST_ID_MASK 0x00ffff0 |
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#define SYNC_FROM_VAPIC 0x1 |
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#define SYNC_TO_VAPIC 0x2 |
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#define SYNC_ISR_IRR_TO_VAPIC 0x4 |
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static APICCommonState *local_apics[MAX_APICS + 1]; |
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static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode); |
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static void apic_update_irq(APICCommonState *s); |
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static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
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uint8_t dest, uint8_t dest_mode); |
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/* Find first bit starting from msb */
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static int fls_bit(uint32_t value) |
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{ |
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return 31 - clz32(value); |
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} |
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/* Find first bit starting from lsb */
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static int ffs_bit(uint32_t value) |
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{ |
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return ctz32(value);
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} |
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static inline void set_bit(uint32_t *tab, int index) |
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{ |
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f); |
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tab[i] |= mask; |
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} |
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static inline void reset_bit(uint32_t *tab, int index) |
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{ |
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f); |
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tab[i] &= ~mask; |
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} |
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static inline int get_bit(uint32_t *tab, int index) |
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{ |
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f); |
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return !!(tab[i] & mask);
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} |
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/* return -1 if no bit is set */
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static int get_highest_priority_int(uint32_t *tab) |
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{ |
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int i;
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for (i = 7; i >= 0; i--) { |
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if (tab[i] != 0) { |
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return i * 32 + fls_bit(tab[i]); |
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} |
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} |
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return -1; |
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} |
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static void apic_sync_vapic(APICCommonState *s, int sync_type) |
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{ |
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VAPICState vapic_state; |
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size_t length; |
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off_t start; |
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int vector;
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if (!s->vapic_paddr) {
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return;
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} |
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if (sync_type & SYNC_FROM_VAPIC) {
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cpu_physical_memory_rw(s->vapic_paddr, (void *)&vapic_state,
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sizeof(vapic_state), 0); |
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s->tpr = vapic_state.tpr; |
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} |
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if (sync_type & (SYNC_TO_VAPIC | SYNC_ISR_IRR_TO_VAPIC)) {
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start = offsetof(VAPICState, isr); |
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length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr); |
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if (sync_type & SYNC_TO_VAPIC) {
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assert(qemu_cpu_is_self(s->cpu_env)); |
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vapic_state.tpr = s->tpr; |
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vapic_state.enabled = 1;
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start = 0;
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length = sizeof(VAPICState);
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} |
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vector = get_highest_priority_int(s->isr); |
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if (vector < 0) { |
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vector = 0;
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} |
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vapic_state.isr = vector & 0xf0;
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vapic_state.zero = 0;
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vector = get_highest_priority_int(s->irr); |
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if (vector < 0) { |
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vector = 0;
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} |
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vapic_state.irr = vector & 0xff;
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cpu_physical_memory_write_rom(s->vapic_paddr + start, |
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((void *)&vapic_state) + start, length);
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} |
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} |
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static void apic_vapic_base_update(APICCommonState *s) |
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{ |
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apic_sync_vapic(s, SYNC_TO_VAPIC); |
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} |
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static void apic_local_deliver(APICCommonState *s, int vector) |
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{ |
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uint32_t lvt = s->lvt[vector]; |
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int trigger_mode;
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trace_apic_local_deliver(vector, (lvt >> 8) & 7); |
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if (lvt & APIC_LVT_MASKED)
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return;
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switch ((lvt >> 8) & 7) { |
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case APIC_DM_SMI:
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI); |
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break;
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case APIC_DM_NMI:
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI); |
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break;
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case APIC_DM_EXTINT:
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
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break;
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case APIC_DM_FIXED:
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trigger_mode = APIC_TRIGGER_EDGE; |
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if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
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(lvt & APIC_LVT_LEVEL_TRIGGER)) |
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trigger_mode = APIC_TRIGGER_LEVEL; |
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apic_set_irq(s, lvt & 0xff, trigger_mode);
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} |
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} |
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void apic_deliver_pic_intr(DeviceState *d, int level) |
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{ |
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APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
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if (level) {
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apic_local_deliver(s, APIC_LVT_LINT0); |
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} else {
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uint32_t lvt = s->lvt[APIC_LVT_LINT0]; |
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switch ((lvt >> 8) & 7) { |
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case APIC_DM_FIXED:
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if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
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break;
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reset_bit(s->irr, lvt & 0xff);
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/* fall through */
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case APIC_DM_EXTINT:
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cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
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break;
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} |
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} |
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} |
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static void apic_external_nmi(APICCommonState *s) |
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{ |
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apic_local_deliver(s, APIC_LVT_LINT1); |
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} |
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#define foreach_apic(apic, deliver_bitmask, code) \
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{\ |
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int __i, __j, __mask;\
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for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ |
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__mask = deliver_bitmask[__i];\ |
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if (__mask) {\
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for(__j = 0; __j < 32; __j++) {\ |
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if (__mask & (1 << __j)) {\ |
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apic = local_apics[__i * 32 + __j];\
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if (apic) {\
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code;\ |
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}\ |
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}\ |
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}\ |
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}\ |
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}\ |
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} |
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static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
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uint8_t delivery_mode, uint8_t vector_num, |
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uint8_t trigger_mode) |
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{ |
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APICCommonState *apic_iter; |
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switch (delivery_mode) {
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case APIC_DM_LOWPRI:
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/* XXX: search for focus processor, arbitration */
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{ |
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int i, d;
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d = -1;
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for(i = 0; i < MAX_APIC_WORDS; i++) { |
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if (deliver_bitmask[i]) {
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d = i * 32 + ffs_bit(deliver_bitmask[i]);
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break;
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} |
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} |
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if (d >= 0) { |
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apic_iter = local_apics[d]; |
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if (apic_iter) {
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apic_set_irq(apic_iter, vector_num, trigger_mode); |
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} |
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} |
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} |
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return;
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case APIC_DM_FIXED:
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break;
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case APIC_DM_SMI:
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foreach_apic(apic_iter, deliver_bitmask, |
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cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); |
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return;
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case APIC_DM_NMI:
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foreach_apic(apic_iter, deliver_bitmask, |
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cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); |
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return;
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case APIC_DM_INIT:
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/* normal INIT IPI sent to processors */
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foreach_apic(apic_iter, deliver_bitmask, |
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cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) ); |
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return;
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case APIC_DM_EXTINT:
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/* handled in I/O APIC code */
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break;
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default:
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return;
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} |
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foreach_apic(apic_iter, deliver_bitmask, |
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apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
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} |
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void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode,
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uint8_t vector_num, uint8_t trigger_mode) |
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{ |
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uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
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trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num, |
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trigger_mode); |
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apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
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apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); |
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} |
295 |
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static void apic_set_base(APICCommonState *s, uint64_t val) |
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{ |
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s->apicbase = (val & 0xfffff000) |
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(s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
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/* if disabled, cannot be enabled again */
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if (!(val & MSR_IA32_APICBASE_ENABLE)) {
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s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; |
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cpu_clear_apic_feature(s->cpu_env); |
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s->spurious_vec &= ~APIC_SV_ENABLE; |
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} |
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} |
307 |
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static void apic_set_tpr(APICCommonState *s, uint8_t val) |
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{ |
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/* Updates from cr8 are ignored while the VAPIC is active */
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if (!s->vapic_paddr) {
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s->tpr = val << 4;
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apic_update_irq(s); |
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} |
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} |
316 |
|
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static uint8_t apic_get_tpr(APICCommonState *s)
|
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{ |
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apic_sync_vapic(s, SYNC_FROM_VAPIC); |
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return s->tpr >> 4; |
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} |
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static int apic_get_ppr(APICCommonState *s) |
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{ |
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int tpr, isrv, ppr;
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tpr = (s->tpr >> 4);
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isrv = get_highest_priority_int(s->isr); |
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if (isrv < 0) |
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isrv = 0;
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isrv >>= 4;
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if (tpr >= isrv)
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ppr = s->tpr; |
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else
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ppr = isrv << 4;
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return ppr;
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} |
338 |
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static int apic_get_arb_pri(APICCommonState *s) |
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{ |
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/* XXX: arbitration */
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return 0; |
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} |
344 |
|
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/*
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* <0 - low prio interrupt,
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* 0 - no interrupt,
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* >0 - interrupt number
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*/
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static int apic_irq_pending(APICCommonState *s) |
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{ |
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int irrv, ppr;
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irrv = get_highest_priority_int(s->irr); |
355 |
if (irrv < 0) { |
356 |
return 0; |
357 |
} |
358 |
ppr = apic_get_ppr(s); |
359 |
if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) { |
360 |
return -1; |
361 |
} |
362 |
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return irrv;
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} |
365 |
|
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/* signal the CPU if an irq is pending */
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367 |
static void apic_update_irq(APICCommonState *s) |
368 |
{ |
369 |
if (!(s->spurious_vec & APIC_SV_ENABLE)) {
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370 |
return;
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371 |
} |
372 |
if (apic_irq_pending(s) > 0) { |
373 |
cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
374 |
} else if (apic_accept_pic_intr(&s->busdev.qdev) && |
375 |
pic_get_output(isa_pic)) { |
376 |
apic_deliver_pic_intr(&s->busdev.qdev, 1);
|
377 |
} |
378 |
} |
379 |
|
380 |
void apic_poll_irq(DeviceState *d)
|
381 |
{ |
382 |
APICCommonState *s = APIC_COMMON(d); |
383 |
|
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apic_sync_vapic(s, SYNC_FROM_VAPIC); |
385 |
apic_update_irq(s); |
386 |
} |
387 |
|
388 |
static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode) |
389 |
{ |
390 |
apic_report_irq_delivered(!get_bit(s->irr, vector_num)); |
391 |
|
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set_bit(s->irr, vector_num); |
393 |
if (trigger_mode)
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set_bit(s->tmr, vector_num); |
395 |
else
|
396 |
reset_bit(s->tmr, vector_num); |
397 |
if (s->vapic_paddr) {
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apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC); |
399 |
/*
|
400 |
* The vcpu thread needs to see the new IRR before we pull its current
|
401 |
* TPR value. That way, if we miss a lowering of the TRP, the guest
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402 |
* has the chance to notice the new IRR and poll for IRQs on its own.
|
403 |
*/
|
404 |
smp_wmb(); |
405 |
apic_sync_vapic(s, SYNC_FROM_VAPIC); |
406 |
} |
407 |
apic_update_irq(s); |
408 |
} |
409 |
|
410 |
static void apic_eoi(APICCommonState *s) |
411 |
{ |
412 |
int isrv;
|
413 |
isrv = get_highest_priority_int(s->isr); |
414 |
if (isrv < 0) |
415 |
return;
|
416 |
reset_bit(s->isr, isrv); |
417 |
if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && get_bit(s->tmr, isrv)) {
|
418 |
ioapic_eoi_broadcast(isrv); |
419 |
} |
420 |
apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC); |
421 |
apic_update_irq(s); |
422 |
} |
423 |
|
424 |
static int apic_find_dest(uint8_t dest) |
425 |
{ |
426 |
APICCommonState *apic = local_apics[dest]; |
427 |
int i;
|
428 |
|
429 |
if (apic && apic->id == dest)
|
430 |
return dest; /* shortcut in case apic->id == apic->idx */ |
431 |
|
432 |
for (i = 0; i < MAX_APICS; i++) { |
433 |
apic = local_apics[i]; |
434 |
if (apic && apic->id == dest)
|
435 |
return i;
|
436 |
if (!apic)
|
437 |
break;
|
438 |
} |
439 |
|
440 |
return -1; |
441 |
} |
442 |
|
443 |
static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
444 |
uint8_t dest, uint8_t dest_mode) |
445 |
{ |
446 |
APICCommonState *apic_iter; |
447 |
int i;
|
448 |
|
449 |
if (dest_mode == 0) { |
450 |
if (dest == 0xff) { |
451 |
memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); |
452 |
} else {
|
453 |
int idx = apic_find_dest(dest);
|
454 |
memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
455 |
if (idx >= 0) |
456 |
set_bit(deliver_bitmask, idx); |
457 |
} |
458 |
} else {
|
459 |
/* XXX: cluster mode */
|
460 |
memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
461 |
for(i = 0; i < MAX_APICS; i++) { |
462 |
apic_iter = local_apics[i]; |
463 |
if (apic_iter) {
|
464 |
if (apic_iter->dest_mode == 0xf) { |
465 |
if (dest & apic_iter->log_dest)
|
466 |
set_bit(deliver_bitmask, i); |
467 |
} else if (apic_iter->dest_mode == 0x0) { |
468 |
if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && |
469 |
(dest & apic_iter->log_dest & 0x0f)) {
|
470 |
set_bit(deliver_bitmask, i); |
471 |
} |
472 |
} |
473 |
} else {
|
474 |
break;
|
475 |
} |
476 |
} |
477 |
} |
478 |
} |
479 |
|
480 |
static void apic_startup(APICCommonState *s, int vector_num) |
481 |
{ |
482 |
s->sipi_vector = vector_num; |
483 |
cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); |
484 |
} |
485 |
|
486 |
void apic_sipi(DeviceState *d)
|
487 |
{ |
488 |
APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
489 |
|
490 |
cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); |
491 |
|
492 |
if (!s->wait_for_sipi)
|
493 |
return;
|
494 |
cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector); |
495 |
s->wait_for_sipi = 0;
|
496 |
} |
497 |
|
498 |
static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode, |
499 |
uint8_t delivery_mode, uint8_t vector_num, |
500 |
uint8_t trigger_mode) |
501 |
{ |
502 |
APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
503 |
uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
504 |
int dest_shorthand = (s->icr[0] >> 18) & 3; |
505 |
APICCommonState *apic_iter; |
506 |
|
507 |
switch (dest_shorthand) {
|
508 |
case 0: |
509 |
apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
510 |
break;
|
511 |
case 1: |
512 |
memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); |
513 |
set_bit(deliver_bitmask, s->idx); |
514 |
break;
|
515 |
case 2: |
516 |
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
517 |
break;
|
518 |
case 3: |
519 |
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
520 |
reset_bit(deliver_bitmask, s->idx); |
521 |
break;
|
522 |
} |
523 |
|
524 |
switch (delivery_mode) {
|
525 |
case APIC_DM_INIT:
|
526 |
{ |
527 |
int trig_mode = (s->icr[0] >> 15) & 1; |
528 |
int level = (s->icr[0] >> 14) & 1; |
529 |
if (level == 0 && trig_mode == 1) { |
530 |
foreach_apic(apic_iter, deliver_bitmask, |
531 |
apic_iter->arb_id = apic_iter->id ); |
532 |
return;
|
533 |
} |
534 |
} |
535 |
break;
|
536 |
|
537 |
case APIC_DM_SIPI:
|
538 |
foreach_apic(apic_iter, deliver_bitmask, |
539 |
apic_startup(apic_iter, vector_num) ); |
540 |
return;
|
541 |
} |
542 |
|
543 |
apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); |
544 |
} |
545 |
|
546 |
int apic_get_interrupt(DeviceState *d)
|
547 |
{ |
548 |
APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
549 |
int intno;
|
550 |
|
551 |
/* if the APIC is installed or enabled, we let the 8259 handle the
|
552 |
IRQs */
|
553 |
if (!s)
|
554 |
return -1; |
555 |
if (!(s->spurious_vec & APIC_SV_ENABLE))
|
556 |
return -1; |
557 |
|
558 |
apic_sync_vapic(s, SYNC_FROM_VAPIC); |
559 |
intno = apic_irq_pending(s); |
560 |
|
561 |
if (intno == 0) { |
562 |
apic_sync_vapic(s, SYNC_TO_VAPIC); |
563 |
return -1; |
564 |
} else if (intno < 0) { |
565 |
apic_sync_vapic(s, SYNC_TO_VAPIC); |
566 |
return s->spurious_vec & 0xff; |
567 |
} |
568 |
reset_bit(s->irr, intno); |
569 |
set_bit(s->isr, intno); |
570 |
apic_sync_vapic(s, SYNC_TO_VAPIC); |
571 |
apic_update_irq(s); |
572 |
return intno;
|
573 |
} |
574 |
|
575 |
int apic_accept_pic_intr(DeviceState *d)
|
576 |
{ |
577 |
APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
578 |
uint32_t lvt0; |
579 |
|
580 |
if (!s)
|
581 |
return -1; |
582 |
|
583 |
lvt0 = s->lvt[APIC_LVT_LINT0]; |
584 |
|
585 |
if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || |
586 |
(lvt0 & APIC_LVT_MASKED) == 0)
|
587 |
return 1; |
588 |
|
589 |
return 0; |
590 |
} |
591 |
|
592 |
static uint32_t apic_get_current_count(APICCommonState *s)
|
593 |
{ |
594 |
int64_t d; |
595 |
uint32_t val; |
596 |
d = (qemu_get_clock_ns(vm_clock) - s->initial_count_load_time) >> |
597 |
s->count_shift; |
598 |
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
599 |
/* periodic */
|
600 |
val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
|
601 |
} else {
|
602 |
if (d >= s->initial_count)
|
603 |
val = 0;
|
604 |
else
|
605 |
val = s->initial_count - d; |
606 |
} |
607 |
return val;
|
608 |
} |
609 |
|
610 |
static void apic_timer_update(APICCommonState *s, int64_t current_time) |
611 |
{ |
612 |
if (apic_next_timer(s, current_time)) {
|
613 |
qemu_mod_timer(s->timer, s->next_time); |
614 |
} else {
|
615 |
qemu_del_timer(s->timer); |
616 |
} |
617 |
} |
618 |
|
619 |
static void apic_timer(void *opaque) |
620 |
{ |
621 |
APICCommonState *s = opaque; |
622 |
|
623 |
apic_local_deliver(s, APIC_LVT_TIMER); |
624 |
apic_timer_update(s, s->next_time); |
625 |
} |
626 |
|
627 |
static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) |
628 |
{ |
629 |
return 0; |
630 |
} |
631 |
|
632 |
static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) |
633 |
{ |
634 |
return 0; |
635 |
} |
636 |
|
637 |
static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
638 |
{ |
639 |
} |
640 |
|
641 |
static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
642 |
{ |
643 |
} |
644 |
|
645 |
static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) |
646 |
{ |
647 |
DeviceState *d; |
648 |
APICCommonState *s; |
649 |
uint32_t val; |
650 |
int index;
|
651 |
|
652 |
d = cpu_get_current_apic(); |
653 |
if (!d) {
|
654 |
return 0; |
655 |
} |
656 |
s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
657 |
|
658 |
index = (addr >> 4) & 0xff; |
659 |
switch(index) {
|
660 |
case 0x02: /* id */ |
661 |
val = s->id << 24;
|
662 |
break;
|
663 |
case 0x03: /* version */ |
664 |
val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ |
665 |
break;
|
666 |
case 0x08: |
667 |
apic_sync_vapic(s, SYNC_FROM_VAPIC); |
668 |
if (apic_report_tpr_access) {
|
669 |
cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_READ); |
670 |
} |
671 |
val = s->tpr; |
672 |
break;
|
673 |
case 0x09: |
674 |
val = apic_get_arb_pri(s); |
675 |
break;
|
676 |
case 0x0a: |
677 |
/* ppr */
|
678 |
val = apic_get_ppr(s); |
679 |
break;
|
680 |
case 0x0b: |
681 |
val = 0;
|
682 |
break;
|
683 |
case 0x0d: |
684 |
val = s->log_dest << 24;
|
685 |
break;
|
686 |
case 0x0e: |
687 |
val = s->dest_mode << 28;
|
688 |
break;
|
689 |
case 0x0f: |
690 |
val = s->spurious_vec; |
691 |
break;
|
692 |
case 0x10 ... 0x17: |
693 |
val = s->isr[index & 7];
|
694 |
break;
|
695 |
case 0x18 ... 0x1f: |
696 |
val = s->tmr[index & 7];
|
697 |
break;
|
698 |
case 0x20 ... 0x27: |
699 |
val = s->irr[index & 7];
|
700 |
break;
|
701 |
case 0x28: |
702 |
val = s->esr; |
703 |
break;
|
704 |
case 0x30: |
705 |
case 0x31: |
706 |
val = s->icr[index & 1];
|
707 |
break;
|
708 |
case 0x32 ... 0x37: |
709 |
val = s->lvt[index - 0x32];
|
710 |
break;
|
711 |
case 0x38: |
712 |
val = s->initial_count; |
713 |
break;
|
714 |
case 0x39: |
715 |
val = apic_get_current_count(s); |
716 |
break;
|
717 |
case 0x3e: |
718 |
val = s->divide_conf; |
719 |
break;
|
720 |
default:
|
721 |
s->esr |= ESR_ILLEGAL_ADDRESS; |
722 |
val = 0;
|
723 |
break;
|
724 |
} |
725 |
trace_apic_mem_readl(addr, val); |
726 |
return val;
|
727 |
} |
728 |
|
729 |
static void apic_send_msi(target_phys_addr_t addr, uint32_t data) |
730 |
{ |
731 |
uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; |
732 |
uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; |
733 |
uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
|
734 |
uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
|
735 |
uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
|
736 |
/* XXX: Ignore redirection hint. */
|
737 |
apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); |
738 |
} |
739 |
|
740 |
static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
741 |
{ |
742 |
DeviceState *d; |
743 |
APICCommonState *s; |
744 |
int index = (addr >> 4) & 0xff; |
745 |
if (addr > 0xfff || !index) { |
746 |
/* MSI and MMIO APIC are at the same memory location,
|
747 |
* but actually not on the global bus: MSI is on PCI bus
|
748 |
* APIC is connected directly to the CPU.
|
749 |
* Mapping them on the global bus happens to work because
|
750 |
* MSI registers are reserved in APIC MMIO and vice versa. */
|
751 |
apic_send_msi(addr, val); |
752 |
return;
|
753 |
} |
754 |
|
755 |
d = cpu_get_current_apic(); |
756 |
if (!d) {
|
757 |
return;
|
758 |
} |
759 |
s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
760 |
|
761 |
trace_apic_mem_writel(addr, val); |
762 |
|
763 |
switch(index) {
|
764 |
case 0x02: |
765 |
s->id = (val >> 24);
|
766 |
break;
|
767 |
case 0x03: |
768 |
break;
|
769 |
case 0x08: |
770 |
if (apic_report_tpr_access) {
|
771 |
cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_WRITE); |
772 |
} |
773 |
s->tpr = val; |
774 |
apic_sync_vapic(s, SYNC_TO_VAPIC); |
775 |
apic_update_irq(s); |
776 |
break;
|
777 |
case 0x09: |
778 |
case 0x0a: |
779 |
break;
|
780 |
case 0x0b: /* EOI */ |
781 |
apic_eoi(s); |
782 |
break;
|
783 |
case 0x0d: |
784 |
s->log_dest = val >> 24;
|
785 |
break;
|
786 |
case 0x0e: |
787 |
s->dest_mode = val >> 28;
|
788 |
break;
|
789 |
case 0x0f: |
790 |
s->spurious_vec = val & 0x1ff;
|
791 |
apic_update_irq(s); |
792 |
break;
|
793 |
case 0x10 ... 0x17: |
794 |
case 0x18 ... 0x1f: |
795 |
case 0x20 ... 0x27: |
796 |
case 0x28: |
797 |
break;
|
798 |
case 0x30: |
799 |
s->icr[0] = val;
|
800 |
apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, |
801 |
(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), |
802 |
(s->icr[0] >> 15) & 1); |
803 |
break;
|
804 |
case 0x31: |
805 |
s->icr[1] = val;
|
806 |
break;
|
807 |
case 0x32 ... 0x37: |
808 |
{ |
809 |
int n = index - 0x32; |
810 |
s->lvt[n] = val; |
811 |
if (n == APIC_LVT_TIMER)
|
812 |
apic_timer_update(s, qemu_get_clock_ns(vm_clock)); |
813 |
} |
814 |
break;
|
815 |
case 0x38: |
816 |
s->initial_count = val; |
817 |
s->initial_count_load_time = qemu_get_clock_ns(vm_clock); |
818 |
apic_timer_update(s, s->initial_count_load_time); |
819 |
break;
|
820 |
case 0x39: |
821 |
break;
|
822 |
case 0x3e: |
823 |
{ |
824 |
int v;
|
825 |
s->divide_conf = val & 0xb;
|
826 |
v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); |
827 |
s->count_shift = (v + 1) & 7; |
828 |
} |
829 |
break;
|
830 |
default:
|
831 |
s->esr |= ESR_ILLEGAL_ADDRESS; |
832 |
break;
|
833 |
} |
834 |
} |
835 |
|
836 |
static void apic_pre_save(APICCommonState *s) |
837 |
{ |
838 |
apic_sync_vapic(s, SYNC_FROM_VAPIC); |
839 |
} |
840 |
|
841 |
static void apic_post_load(APICCommonState *s) |
842 |
{ |
843 |
if (s->timer_expiry != -1) { |
844 |
qemu_mod_timer(s->timer, s->timer_expiry); |
845 |
} else {
|
846 |
qemu_del_timer(s->timer); |
847 |
} |
848 |
} |
849 |
|
850 |
static const MemoryRegionOps apic_io_ops = { |
851 |
.old_mmio = { |
852 |
.read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, }, |
853 |
.write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, }, |
854 |
}, |
855 |
.endianness = DEVICE_NATIVE_ENDIAN, |
856 |
}; |
857 |
|
858 |
static void apic_init(APICCommonState *s) |
859 |
{ |
860 |
memory_region_init_io(&s->io_memory, &apic_io_ops, s, "apic-msi",
|
861 |
MSI_SPACE_SIZE); |
862 |
|
863 |
s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s); |
864 |
local_apics[s->idx] = s; |
865 |
} |
866 |
|
867 |
static void apic_class_init(ObjectClass *klass, void *data) |
868 |
{ |
869 |
APICCommonClass *k = APIC_COMMON_CLASS(klass); |
870 |
|
871 |
k->init = apic_init; |
872 |
k->set_base = apic_set_base; |
873 |
k->set_tpr = apic_set_tpr; |
874 |
k->get_tpr = apic_get_tpr; |
875 |
k->vapic_base_update = apic_vapic_base_update; |
876 |
k->external_nmi = apic_external_nmi; |
877 |
k->pre_save = apic_pre_save; |
878 |
k->post_load = apic_post_load; |
879 |
} |
880 |
|
881 |
static TypeInfo apic_info = {
|
882 |
.name = "apic",
|
883 |
.instance_size = sizeof(APICCommonState),
|
884 |
.parent = TYPE_APIC_COMMON, |
885 |
.class_init = apic_class_init, |
886 |
}; |
887 |
|
888 |
static void apic_register_types(void) |
889 |
{ |
890 |
type_register_static(&apic_info); |
891 |
} |
892 |
|
893 |
type_init(apic_register_types) |