Revision f59df3f2 target-arm/cpu.h
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typedef struct ARMCPRegInfo ARMCPRegInfo; |
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/* Access functions for coprocessor registers. These should return |
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* 0 on success, or one of the EXCP_* constants if access should cause |
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* an exception (in which case *value is not written). |
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*/ |
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typedef enum CPAccessResult {
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/* Access is permitted */ |
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CP_ACCESS_OK = 0, |
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/* Access fails due to a configurable trap or enable which would |
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* result in a categorized exception syndrome giving information about |
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* the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, |
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* 0xc or 0x18). |
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*/ |
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CP_ACCESS_TRAP = 1, |
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/* Access fails and results in an exception syndrome 0x0 ("uncategorized").
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* Note that this is not a catch-all case -- the set of cases which may |
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* result in this failure is specifically defined by the architecture. |
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*/ |
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CP_ACCESS_TRAP_UNCATEGORIZED = 2, |
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} CPAccessResult; |
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/* Access functions for coprocessor registers. These should always succeed. */ |
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typedef int CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque, |
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uint64_t *value); |
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typedef int CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, |
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uint64_t value); |
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/* Access permission check functions for coprocessor registers. */ |
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typedef CPAccessResult CPAccessFn(CPUARMState *env, const ARMCPRegInfo *opaque); |
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/* Hook function for register reset */ |
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typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); |
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|
| ... | ... | |
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* 2. both readfn and writefn are specified |
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*/ |
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ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ |
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/* Function for making any access checks for this register in addition to |
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* those specified by the 'access' permissions bits. If NULL, no extra |
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* checks required. The access check is performed at runtime, not at |
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* translate time. |
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*/ |
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CPAccessFn *accessfn; |
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/* Function for handling reads of this register. If NULL, then reads |
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* will be done by loading from the offset into CPUARMState specified |
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* by fieldoffset. |
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