root / target-ppc / kvm.c @ f5fc40bb
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1 | d76d1650 | aurel32 | /*
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2 | d76d1650 | aurel32 | * PowerPC implementation of KVM hooks
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3 | d76d1650 | aurel32 | *
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4 | d76d1650 | aurel32 | * Copyright IBM Corp. 2007
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5 | 90dc8812 | Scott Wood | * Copyright (C) 2011 Freescale Semiconductor, Inc.
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6 | d76d1650 | aurel32 | *
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7 | d76d1650 | aurel32 | * Authors:
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8 | d76d1650 | aurel32 | * Jerone Young <jyoung5@us.ibm.com>
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9 | d76d1650 | aurel32 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
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10 | d76d1650 | aurel32 | * Hollis Blanchard <hollisb@us.ibm.com>
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11 | d76d1650 | aurel32 | *
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12 | d76d1650 | aurel32 | * This work is licensed under the terms of the GNU GPL, version 2 or later.
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13 | d76d1650 | aurel32 | * See the COPYING file in the top-level directory.
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14 | d76d1650 | aurel32 | *
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15 | d76d1650 | aurel32 | */
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16 | d76d1650 | aurel32 | |
17 | d76d1650 | aurel32 | #include <sys/types.h> |
18 | d76d1650 | aurel32 | #include <sys/ioctl.h> |
19 | d76d1650 | aurel32 | #include <sys/mman.h> |
20 | d76d1650 | aurel32 | |
21 | d76d1650 | aurel32 | #include <linux/kvm.h> |
22 | d76d1650 | aurel32 | |
23 | d76d1650 | aurel32 | #include "qemu-common.h" |
24 | d76d1650 | aurel32 | #include "qemu-timer.h" |
25 | d76d1650 | aurel32 | #include "sysemu.h" |
26 | d76d1650 | aurel32 | #include "kvm.h" |
27 | d76d1650 | aurel32 | #include "kvm_ppc.h" |
28 | d76d1650 | aurel32 | #include "cpu.h" |
29 | d76d1650 | aurel32 | #include "device_tree.h" |
30 | d76d1650 | aurel32 | |
31 | d76d1650 | aurel32 | //#define DEBUG_KVM
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32 | d76d1650 | aurel32 | |
33 | d76d1650 | aurel32 | #ifdef DEBUG_KVM
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34 | d76d1650 | aurel32 | #define dprintf(fmt, ...) \
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35 | d76d1650 | aurel32 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
36 | d76d1650 | aurel32 | #else
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37 | d76d1650 | aurel32 | #define dprintf(fmt, ...) \
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38 | d76d1650 | aurel32 | do { } while (0) |
39 | d76d1650 | aurel32 | #endif
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40 | d76d1650 | aurel32 | |
41 | 94a8d39a | Jan Kiszka | const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
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42 | 94a8d39a | Jan Kiszka | KVM_CAP_LAST_INFO |
43 | 94a8d39a | Jan Kiszka | }; |
44 | 94a8d39a | Jan Kiszka | |
45 | fc87e185 | Alexander Graf | static int cap_interrupt_unset = false; |
46 | fc87e185 | Alexander Graf | static int cap_interrupt_level = false; |
47 | 90dc8812 | Scott Wood | static int cap_segstate; |
48 | 90dc8812 | Scott Wood | static int cap_booke_sregs; |
49 | fc87e185 | Alexander Graf | |
50 | c821c2bd | Alexander Graf | /* XXX We have a race condition where we actually have a level triggered
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51 | c821c2bd | Alexander Graf | * interrupt, but the infrastructure can't expose that yet, so the guest
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52 | c821c2bd | Alexander Graf | * takes but ignores it, goes to sleep and never gets notified that there's
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53 | c821c2bd | Alexander Graf | * still an interrupt pending.
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54 | c6a94ba5 | Alexander Graf | *
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55 | c821c2bd | Alexander Graf | * As a quick workaround, let's just wake up again 20 ms after we injected
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56 | c821c2bd | Alexander Graf | * an interrupt. That way we can assure that we're always reinjecting
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57 | c821c2bd | Alexander Graf | * interrupts in case the guest swallowed them.
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58 | c6a94ba5 | Alexander Graf | */
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59 | c6a94ba5 | Alexander Graf | static QEMUTimer *idle_timer;
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60 | c6a94ba5 | Alexander Graf | |
61 | c821c2bd | Alexander Graf | static void kvm_kick_env(void *env) |
62 | c6a94ba5 | Alexander Graf | { |
63 | c821c2bd | Alexander Graf | qemu_cpu_kick(env); |
64 | c6a94ba5 | Alexander Graf | } |
65 | c6a94ba5 | Alexander Graf | |
66 | cad1e282 | Jan Kiszka | int kvm_arch_init(KVMState *s)
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67 | d76d1650 | aurel32 | { |
68 | fc87e185 | Alexander Graf | cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ); |
69 | fc87e185 | Alexander Graf | cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL); |
70 | 90dc8812 | Scott Wood | cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE); |
71 | 90dc8812 | Scott Wood | cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS); |
72 | fc87e185 | Alexander Graf | |
73 | fc87e185 | Alexander Graf | if (!cap_interrupt_level) {
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74 | fc87e185 | Alexander Graf | fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the "
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75 | fc87e185 | Alexander Graf | "VM to stall at times!\n");
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76 | fc87e185 | Alexander Graf | } |
77 | fc87e185 | Alexander Graf | |
78 | d76d1650 | aurel32 | return 0; |
79 | d76d1650 | aurel32 | } |
80 | d76d1650 | aurel32 | |
81 | 5666ca4a | Scott Wood | static int kvm_arch_sync_sregs(CPUState *cenv) |
82 | d76d1650 | aurel32 | { |
83 | 861bbc80 | Alexander Graf | struct kvm_sregs sregs;
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84 | 5666ca4a | Scott Wood | int ret;
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85 | 5666ca4a | Scott Wood | |
86 | 5666ca4a | Scott Wood | if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
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87 | 64e07be5 | Alexander Graf | /* What we're really trying to say is "if we're on BookE, we use
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88 | 64e07be5 | Alexander Graf | the native PVR for now". This is the only sane way to check
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89 | 64e07be5 | Alexander Graf | it though, so we potentially confuse users that they can run
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90 | 64e07be5 | Alexander Graf | BookE guests on BookS. Let's hope nobody dares enough :) */
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91 | 5666ca4a | Scott Wood | return 0; |
92 | 5666ca4a | Scott Wood | } else {
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93 | 90dc8812 | Scott Wood | if (!cap_segstate) {
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94 | 64e07be5 | Alexander Graf | fprintf(stderr, "kvm error: missing PVR setting capability\n");
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95 | 64e07be5 | Alexander Graf | return -ENOSYS;
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96 | 5666ca4a | Scott Wood | } |
97 | 5666ca4a | Scott Wood | } |
98 | 5666ca4a | Scott Wood | |
99 | 5666ca4a | Scott Wood | ret = kvm_vcpu_ioctl(cenv, KVM_GET_SREGS, &sregs); |
100 | 5666ca4a | Scott Wood | if (ret) {
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101 | 5666ca4a | Scott Wood | return ret;
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102 | 5666ca4a | Scott Wood | } |
103 | 861bbc80 | Alexander Graf | |
104 | 861bbc80 | Alexander Graf | sregs.pvr = cenv->spr[SPR_PVR]; |
105 | 5666ca4a | Scott Wood | return kvm_vcpu_ioctl(cenv, KVM_SET_SREGS, &sregs);
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106 | 5666ca4a | Scott Wood | } |
107 | 5666ca4a | Scott Wood | |
108 | 5666ca4a | Scott Wood | int kvm_arch_init_vcpu(CPUState *cenv)
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109 | 5666ca4a | Scott Wood | { |
110 | 5666ca4a | Scott Wood | int ret;
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111 | 5666ca4a | Scott Wood | |
112 | 5666ca4a | Scott Wood | ret = kvm_arch_sync_sregs(cenv); |
113 | 5666ca4a | Scott Wood | if (ret) {
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114 | 5666ca4a | Scott Wood | return ret;
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115 | 5666ca4a | Scott Wood | } |
116 | 861bbc80 | Alexander Graf | |
117 | 74475455 | Paolo Bonzini | idle_timer = qemu_new_timer_ns(vm_clock, kvm_kick_env, cenv); |
118 | c821c2bd | Alexander Graf | |
119 | 861bbc80 | Alexander Graf | return ret;
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120 | d76d1650 | aurel32 | } |
121 | d76d1650 | aurel32 | |
122 | caa5af0f | Jan Kiszka | void kvm_arch_reset_vcpu(CPUState *env)
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123 | caa5af0f | Jan Kiszka | { |
124 | caa5af0f | Jan Kiszka | } |
125 | caa5af0f | Jan Kiszka | |
126 | ea375f9a | Jan Kiszka | int kvm_arch_put_registers(CPUState *env, int level) |
127 | d76d1650 | aurel32 | { |
128 | d76d1650 | aurel32 | struct kvm_regs regs;
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129 | d76d1650 | aurel32 | int ret;
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130 | d76d1650 | aurel32 | int i;
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131 | d76d1650 | aurel32 | |
132 | d76d1650 | aurel32 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); |
133 | d76d1650 | aurel32 | if (ret < 0) |
134 | d76d1650 | aurel32 | return ret;
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135 | d76d1650 | aurel32 | |
136 | d76d1650 | aurel32 | regs.ctr = env->ctr; |
137 | d76d1650 | aurel32 | regs.lr = env->lr; |
138 | d76d1650 | aurel32 | regs.xer = env->xer; |
139 | d76d1650 | aurel32 | regs.msr = env->msr; |
140 | d76d1650 | aurel32 | regs.pc = env->nip; |
141 | d76d1650 | aurel32 | |
142 | d76d1650 | aurel32 | regs.srr0 = env->spr[SPR_SRR0]; |
143 | d76d1650 | aurel32 | regs.srr1 = env->spr[SPR_SRR1]; |
144 | d76d1650 | aurel32 | |
145 | d76d1650 | aurel32 | regs.sprg0 = env->spr[SPR_SPRG0]; |
146 | d76d1650 | aurel32 | regs.sprg1 = env->spr[SPR_SPRG1]; |
147 | d76d1650 | aurel32 | regs.sprg2 = env->spr[SPR_SPRG2]; |
148 | d76d1650 | aurel32 | regs.sprg3 = env->spr[SPR_SPRG3]; |
149 | d76d1650 | aurel32 | regs.sprg4 = env->spr[SPR_SPRG4]; |
150 | d76d1650 | aurel32 | regs.sprg5 = env->spr[SPR_SPRG5]; |
151 | d76d1650 | aurel32 | regs.sprg6 = env->spr[SPR_SPRG6]; |
152 | d76d1650 | aurel32 | regs.sprg7 = env->spr[SPR_SPRG7]; |
153 | d76d1650 | aurel32 | |
154 | 90dc8812 | Scott Wood | regs.pid = env->spr[SPR_BOOKE_PID]; |
155 | 90dc8812 | Scott Wood | |
156 | d76d1650 | aurel32 | for (i = 0;i < 32; i++) |
157 | d76d1650 | aurel32 | regs.gpr[i] = env->gpr[i]; |
158 | d76d1650 | aurel32 | |
159 | d76d1650 | aurel32 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); |
160 | d76d1650 | aurel32 | if (ret < 0) |
161 | d76d1650 | aurel32 | return ret;
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162 | d76d1650 | aurel32 | |
163 | d76d1650 | aurel32 | return ret;
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164 | d76d1650 | aurel32 | } |
165 | d76d1650 | aurel32 | |
166 | d76d1650 | aurel32 | int kvm_arch_get_registers(CPUState *env)
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167 | d76d1650 | aurel32 | { |
168 | d76d1650 | aurel32 | struct kvm_regs regs;
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169 | ba5e5090 | Alexander Graf | struct kvm_sregs sregs;
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170 | 90dc8812 | Scott Wood | uint32_t cr; |
171 | 138b38b6 | Alexander Graf | int i, ret;
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172 | d76d1650 | aurel32 | |
173 | d76d1650 | aurel32 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); |
174 | d76d1650 | aurel32 | if (ret < 0) |
175 | d76d1650 | aurel32 | return ret;
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176 | d76d1650 | aurel32 | |
177 | 90dc8812 | Scott Wood | cr = regs.cr; |
178 | 90dc8812 | Scott Wood | for (i = 7; i >= 0; i--) { |
179 | 90dc8812 | Scott Wood | env->crf[i] = cr & 15;
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180 | 90dc8812 | Scott Wood | cr >>= 4;
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181 | 90dc8812 | Scott Wood | } |
182 | ba5e5090 | Alexander Graf | |
183 | d76d1650 | aurel32 | env->ctr = regs.ctr; |
184 | d76d1650 | aurel32 | env->lr = regs.lr; |
185 | d76d1650 | aurel32 | env->xer = regs.xer; |
186 | d76d1650 | aurel32 | env->msr = regs.msr; |
187 | d76d1650 | aurel32 | env->nip = regs.pc; |
188 | d76d1650 | aurel32 | |
189 | d76d1650 | aurel32 | env->spr[SPR_SRR0] = regs.srr0; |
190 | d76d1650 | aurel32 | env->spr[SPR_SRR1] = regs.srr1; |
191 | d76d1650 | aurel32 | |
192 | d76d1650 | aurel32 | env->spr[SPR_SPRG0] = regs.sprg0; |
193 | d76d1650 | aurel32 | env->spr[SPR_SPRG1] = regs.sprg1; |
194 | d76d1650 | aurel32 | env->spr[SPR_SPRG2] = regs.sprg2; |
195 | d76d1650 | aurel32 | env->spr[SPR_SPRG3] = regs.sprg3; |
196 | d76d1650 | aurel32 | env->spr[SPR_SPRG4] = regs.sprg4; |
197 | d76d1650 | aurel32 | env->spr[SPR_SPRG5] = regs.sprg5; |
198 | d76d1650 | aurel32 | env->spr[SPR_SPRG6] = regs.sprg6; |
199 | d76d1650 | aurel32 | env->spr[SPR_SPRG7] = regs.sprg7; |
200 | d76d1650 | aurel32 | |
201 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_PID] = regs.pid; |
202 | 90dc8812 | Scott Wood | |
203 | d76d1650 | aurel32 | for (i = 0;i < 32; i++) |
204 | d76d1650 | aurel32 | env->gpr[i] = regs.gpr[i]; |
205 | d76d1650 | aurel32 | |
206 | 90dc8812 | Scott Wood | if (cap_booke_sregs) {
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207 | 90dc8812 | Scott Wood | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); |
208 | 90dc8812 | Scott Wood | if (ret < 0) { |
209 | 90dc8812 | Scott Wood | return ret;
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210 | 90dc8812 | Scott Wood | } |
211 | 90dc8812 | Scott Wood | |
212 | 90dc8812 | Scott Wood | if (sregs.u.e.features & KVM_SREGS_E_BASE) {
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213 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0; |
214 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1; |
215 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr; |
216 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear; |
217 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr; |
218 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr; |
219 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr; |
220 | 90dc8812 | Scott Wood | env->spr[SPR_DECR] = sregs.u.e.dec; |
221 | 90dc8812 | Scott Wood | env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
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222 | 90dc8812 | Scott Wood | env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
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223 | 90dc8812 | Scott Wood | env->spr[SPR_VRSAVE] = sregs.u.e.vrsave; |
224 | 90dc8812 | Scott Wood | } |
225 | 90dc8812 | Scott Wood | |
226 | 90dc8812 | Scott Wood | if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
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227 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir; |
228 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0; |
229 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1; |
230 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar; |
231 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr; |
232 | 90dc8812 | Scott Wood | } |
233 | 90dc8812 | Scott Wood | |
234 | 90dc8812 | Scott Wood | if (sregs.u.e.features & KVM_SREGS_E_64) {
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235 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr; |
236 | 90dc8812 | Scott Wood | } |
237 | 90dc8812 | Scott Wood | |
238 | 90dc8812 | Scott Wood | if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
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239 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8; |
240 | 90dc8812 | Scott Wood | } |
241 | 90dc8812 | Scott Wood | |
242 | 90dc8812 | Scott Wood | if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
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243 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
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244 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
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245 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
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246 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
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247 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
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248 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
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249 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
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250 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
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251 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
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252 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
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253 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
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254 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
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255 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
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256 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
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257 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
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258 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];
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259 | 90dc8812 | Scott Wood | |
260 | 90dc8812 | Scott Wood | if (sregs.u.e.features & KVM_SREGS_E_SPE) {
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261 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
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262 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
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263 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
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264 | 90dc8812 | Scott Wood | } |
265 | 90dc8812 | Scott Wood | |
266 | 90dc8812 | Scott Wood | if (sregs.u.e.features & KVM_SREGS_E_PM) {
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267 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
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268 | 90dc8812 | Scott Wood | } |
269 | 90dc8812 | Scott Wood | |
270 | 90dc8812 | Scott Wood | if (sregs.u.e.features & KVM_SREGS_E_PC) {
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271 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
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272 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
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273 | 90dc8812 | Scott Wood | } |
274 | 90dc8812 | Scott Wood | } |
275 | 90dc8812 | Scott Wood | |
276 | 90dc8812 | Scott Wood | if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
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277 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0; |
278 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1; |
279 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2; |
280 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
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281 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4; |
282 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6; |
283 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
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284 | 90dc8812 | Scott Wood | env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg; |
285 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
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286 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
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287 | 90dc8812 | Scott Wood | } |
288 | 90dc8812 | Scott Wood | |
289 | 90dc8812 | Scott Wood | if (sregs.u.e.features & KVM_SREGS_EXP) {
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290 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr; |
291 | 90dc8812 | Scott Wood | } |
292 | 90dc8812 | Scott Wood | |
293 | 90dc8812 | Scott Wood | if (sregs.u.e.features & KVM_SREGS_E_PD) {
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294 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc; |
295 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc; |
296 | 90dc8812 | Scott Wood | } |
297 | 90dc8812 | Scott Wood | |
298 | 90dc8812 | Scott Wood | if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
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299 | 90dc8812 | Scott Wood | env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr; |
300 | 90dc8812 | Scott Wood | env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar; |
301 | 90dc8812 | Scott Wood | env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0; |
302 | 90dc8812 | Scott Wood | |
303 | 90dc8812 | Scott Wood | if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
|
304 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1; |
305 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2; |
306 | 90dc8812 | Scott Wood | } |
307 | 90dc8812 | Scott Wood | } |
308 | fafc0b6a | Alexander Graf | } |
309 | 90dc8812 | Scott Wood | |
310 | 90dc8812 | Scott Wood | if (cap_segstate) {
|
311 | 90dc8812 | Scott Wood | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); |
312 | 90dc8812 | Scott Wood | if (ret < 0) { |
313 | 90dc8812 | Scott Wood | return ret;
|
314 | 90dc8812 | Scott Wood | } |
315 | 90dc8812 | Scott Wood | |
316 | bb593904 | David Gibson | ppc_store_sdr1(env, sregs.u.s.sdr1); |
317 | ba5e5090 | Alexander Graf | |
318 | ba5e5090 | Alexander Graf | /* Sync SLB */
|
319 | 82c09f2f | Alexander Graf | #ifdef TARGET_PPC64
|
320 | ba5e5090 | Alexander Graf | for (i = 0; i < 64; i++) { |
321 | ba5e5090 | Alexander Graf | ppc_store_slb(env, sregs.u.s.ppc64.slb[i].slbe, |
322 | ba5e5090 | Alexander Graf | sregs.u.s.ppc64.slb[i].slbv); |
323 | ba5e5090 | Alexander Graf | } |
324 | 82c09f2f | Alexander Graf | #endif
|
325 | ba5e5090 | Alexander Graf | |
326 | ba5e5090 | Alexander Graf | /* Sync SRs */
|
327 | ba5e5090 | Alexander Graf | for (i = 0; i < 16; i++) { |
328 | ba5e5090 | Alexander Graf | env->sr[i] = sregs.u.s.ppc32.sr[i]; |
329 | ba5e5090 | Alexander Graf | } |
330 | ba5e5090 | Alexander Graf | |
331 | ba5e5090 | Alexander Graf | /* Sync BATs */
|
332 | ba5e5090 | Alexander Graf | for (i = 0; i < 8; i++) { |
333 | ba5e5090 | Alexander Graf | env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff; |
334 | ba5e5090 | Alexander Graf | env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32; |
335 | ba5e5090 | Alexander Graf | env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; |
336 | ba5e5090 | Alexander Graf | env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; |
337 | ba5e5090 | Alexander Graf | } |
338 | fafc0b6a | Alexander Graf | } |
339 | ba5e5090 | Alexander Graf | |
340 | d76d1650 | aurel32 | return 0; |
341 | d76d1650 | aurel32 | } |
342 | d76d1650 | aurel32 | |
343 | fc87e185 | Alexander Graf | int kvmppc_set_interrupt(CPUState *env, int irq, int level) |
344 | fc87e185 | Alexander Graf | { |
345 | fc87e185 | Alexander Graf | unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
|
346 | fc87e185 | Alexander Graf | |
347 | fc87e185 | Alexander Graf | if (irq != PPC_INTERRUPT_EXT) {
|
348 | fc87e185 | Alexander Graf | return 0; |
349 | fc87e185 | Alexander Graf | } |
350 | fc87e185 | Alexander Graf | |
351 | fc87e185 | Alexander Graf | if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) {
|
352 | fc87e185 | Alexander Graf | return 0; |
353 | fc87e185 | Alexander Graf | } |
354 | fc87e185 | Alexander Graf | |
355 | fc87e185 | Alexander Graf | kvm_vcpu_ioctl(env, KVM_INTERRUPT, &virq); |
356 | fc87e185 | Alexander Graf | |
357 | fc87e185 | Alexander Graf | return 0; |
358 | fc87e185 | Alexander Graf | } |
359 | fc87e185 | Alexander Graf | |
360 | 16415335 | Alexander Graf | #if defined(TARGET_PPCEMB)
|
361 | 16415335 | Alexander Graf | #define PPC_INPUT_INT PPC40x_INPUT_INT
|
362 | 16415335 | Alexander Graf | #elif defined(TARGET_PPC64)
|
363 | 16415335 | Alexander Graf | #define PPC_INPUT_INT PPC970_INPUT_INT
|
364 | 16415335 | Alexander Graf | #else
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365 | 16415335 | Alexander Graf | #define PPC_INPUT_INT PPC6xx_INPUT_INT
|
366 | 16415335 | Alexander Graf | #endif
|
367 | 16415335 | Alexander Graf | |
368 | bdcbd3e2 | Jan Kiszka | void kvm_arch_pre_run(CPUState *env, struct kvm_run *run) |
369 | d76d1650 | aurel32 | { |
370 | d76d1650 | aurel32 | int r;
|
371 | d76d1650 | aurel32 | unsigned irq;
|
372 | d76d1650 | aurel32 | |
373 | d76d1650 | aurel32 | /* PowerPC Qemu tracks the various core input pins (interrupt, critical
|
374 | d76d1650 | aurel32 | * interrupt, reset, etc) in PPC-specific env->irq_input_state. */
|
375 | fc87e185 | Alexander Graf | if (!cap_interrupt_level &&
|
376 | fc87e185 | Alexander Graf | run->ready_for_interrupt_injection && |
377 | d76d1650 | aurel32 | (env->interrupt_request & CPU_INTERRUPT_HARD) && |
378 | 16415335 | Alexander Graf | (env->irq_input_state & (1<<PPC_INPUT_INT)))
|
379 | d76d1650 | aurel32 | { |
380 | d76d1650 | aurel32 | /* For now KVM disregards the 'irq' argument. However, in the
|
381 | d76d1650 | aurel32 | * future KVM could cache it in-kernel to avoid a heavyweight exit
|
382 | d76d1650 | aurel32 | * when reading the UIC.
|
383 | d76d1650 | aurel32 | */
|
384 | fc87e185 | Alexander Graf | irq = KVM_INTERRUPT_SET; |
385 | d76d1650 | aurel32 | |
386 | d76d1650 | aurel32 | dprintf("injected interrupt %d\n", irq);
|
387 | d76d1650 | aurel32 | r = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &irq); |
388 | d76d1650 | aurel32 | if (r < 0) |
389 | d76d1650 | aurel32 | printf("cpu %d fail inject %x\n", env->cpu_index, irq);
|
390 | c821c2bd | Alexander Graf | |
391 | c821c2bd | Alexander Graf | /* Always wake up soon in case the interrupt was level based */
|
392 | 74475455 | Paolo Bonzini | qemu_mod_timer(idle_timer, qemu_get_clock_ns(vm_clock) + |
393 | c821c2bd | Alexander Graf | (get_ticks_per_sec() / 50));
|
394 | d76d1650 | aurel32 | } |
395 | d76d1650 | aurel32 | |
396 | d76d1650 | aurel32 | /* We don't know if there are more interrupts pending after this. However,
|
397 | d76d1650 | aurel32 | * the guest will return to userspace in the course of handling this one
|
398 | d76d1650 | aurel32 | * anyways, so we will get a chance to deliver the rest. */
|
399 | d76d1650 | aurel32 | } |
400 | d76d1650 | aurel32 | |
401 | 7a39fe58 | Jan Kiszka | void kvm_arch_post_run(CPUState *env, struct kvm_run *run) |
402 | d76d1650 | aurel32 | { |
403 | d76d1650 | aurel32 | } |
404 | d76d1650 | aurel32 | |
405 | 99036865 | Jan Kiszka | int kvm_arch_process_async_events(CPUState *env)
|
406 | 0af691d7 | Marcelo Tosatti | { |
407 | bdcbd3e2 | Jan Kiszka | return 0; |
408 | 0af691d7 | Marcelo Tosatti | } |
409 | 0af691d7 | Marcelo Tosatti | |
410 | d76d1650 | aurel32 | static int kvmppc_handle_halt(CPUState *env) |
411 | d76d1650 | aurel32 | { |
412 | d76d1650 | aurel32 | if (!(env->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
|
413 | d76d1650 | aurel32 | env->halted = 1;
|
414 | d76d1650 | aurel32 | env->exception_index = EXCP_HLT; |
415 | d76d1650 | aurel32 | } |
416 | d76d1650 | aurel32 | |
417 | bb4ea393 | Jan Kiszka | return 0; |
418 | d76d1650 | aurel32 | } |
419 | d76d1650 | aurel32 | |
420 | d76d1650 | aurel32 | /* map dcr access to existing qemu dcr emulation */
|
421 | d76d1650 | aurel32 | static int kvmppc_handle_dcr_read(CPUState *env, uint32_t dcrn, uint32_t *data) |
422 | d76d1650 | aurel32 | { |
423 | d76d1650 | aurel32 | if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) |
424 | d76d1650 | aurel32 | fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
|
425 | d76d1650 | aurel32 | |
426 | bb4ea393 | Jan Kiszka | return 0; |
427 | d76d1650 | aurel32 | } |
428 | d76d1650 | aurel32 | |
429 | d76d1650 | aurel32 | static int kvmppc_handle_dcr_write(CPUState *env, uint32_t dcrn, uint32_t data) |
430 | d76d1650 | aurel32 | { |
431 | d76d1650 | aurel32 | if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) |
432 | d76d1650 | aurel32 | fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
|
433 | d76d1650 | aurel32 | |
434 | bb4ea393 | Jan Kiszka | return 0; |
435 | d76d1650 | aurel32 | } |
436 | d76d1650 | aurel32 | |
437 | d76d1650 | aurel32 | int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) |
438 | d76d1650 | aurel32 | { |
439 | bb4ea393 | Jan Kiszka | int ret;
|
440 | d76d1650 | aurel32 | |
441 | d76d1650 | aurel32 | switch (run->exit_reason) {
|
442 | d76d1650 | aurel32 | case KVM_EXIT_DCR:
|
443 | d76d1650 | aurel32 | if (run->dcr.is_write) {
|
444 | d76d1650 | aurel32 | dprintf("handle dcr write\n");
|
445 | d76d1650 | aurel32 | ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); |
446 | d76d1650 | aurel32 | } else {
|
447 | d76d1650 | aurel32 | dprintf("handle dcr read\n");
|
448 | d76d1650 | aurel32 | ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); |
449 | d76d1650 | aurel32 | } |
450 | d76d1650 | aurel32 | break;
|
451 | d76d1650 | aurel32 | case KVM_EXIT_HLT:
|
452 | d76d1650 | aurel32 | dprintf("handle halt\n");
|
453 | d76d1650 | aurel32 | ret = kvmppc_handle_halt(env); |
454 | d76d1650 | aurel32 | break;
|
455 | 73aaec4a | Jan Kiszka | default:
|
456 | 73aaec4a | Jan Kiszka | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
|
457 | 73aaec4a | Jan Kiszka | ret = -1;
|
458 | 73aaec4a | Jan Kiszka | break;
|
459 | d76d1650 | aurel32 | } |
460 | d76d1650 | aurel32 | |
461 | d76d1650 | aurel32 | return ret;
|
462 | d76d1650 | aurel32 | } |
463 | d76d1650 | aurel32 | |
464 | dc333cd6 | Alexander Graf | static int read_cpuinfo(const char *field, char *value, int len) |
465 | dc333cd6 | Alexander Graf | { |
466 | dc333cd6 | Alexander Graf | FILE *f; |
467 | dc333cd6 | Alexander Graf | int ret = -1; |
468 | dc333cd6 | Alexander Graf | int field_len = strlen(field);
|
469 | dc333cd6 | Alexander Graf | char line[512]; |
470 | dc333cd6 | Alexander Graf | |
471 | dc333cd6 | Alexander Graf | f = fopen("/proc/cpuinfo", "r"); |
472 | dc333cd6 | Alexander Graf | if (!f) {
|
473 | dc333cd6 | Alexander Graf | return -1; |
474 | dc333cd6 | Alexander Graf | } |
475 | dc333cd6 | Alexander Graf | |
476 | dc333cd6 | Alexander Graf | do {
|
477 | dc333cd6 | Alexander Graf | if(!fgets(line, sizeof(line), f)) { |
478 | dc333cd6 | Alexander Graf | break;
|
479 | dc333cd6 | Alexander Graf | } |
480 | dc333cd6 | Alexander Graf | if (!strncmp(line, field, field_len)) {
|
481 | dc333cd6 | Alexander Graf | strncpy(value, line, len); |
482 | dc333cd6 | Alexander Graf | ret = 0;
|
483 | dc333cd6 | Alexander Graf | break;
|
484 | dc333cd6 | Alexander Graf | } |
485 | dc333cd6 | Alexander Graf | } while(*line);
|
486 | dc333cd6 | Alexander Graf | |
487 | dc333cd6 | Alexander Graf | fclose(f); |
488 | dc333cd6 | Alexander Graf | |
489 | dc333cd6 | Alexander Graf | return ret;
|
490 | dc333cd6 | Alexander Graf | } |
491 | dc333cd6 | Alexander Graf | |
492 | dc333cd6 | Alexander Graf | uint32_t kvmppc_get_tbfreq(void)
|
493 | dc333cd6 | Alexander Graf | { |
494 | dc333cd6 | Alexander Graf | char line[512]; |
495 | dc333cd6 | Alexander Graf | char *ns;
|
496 | dc333cd6 | Alexander Graf | uint32_t retval = get_ticks_per_sec(); |
497 | dc333cd6 | Alexander Graf | |
498 | dc333cd6 | Alexander Graf | if (read_cpuinfo("timebase", line, sizeof(line))) { |
499 | dc333cd6 | Alexander Graf | return retval;
|
500 | dc333cd6 | Alexander Graf | } |
501 | dc333cd6 | Alexander Graf | |
502 | dc333cd6 | Alexander Graf | if (!(ns = strchr(line, ':'))) { |
503 | dc333cd6 | Alexander Graf | return retval;
|
504 | dc333cd6 | Alexander Graf | } |
505 | dc333cd6 | Alexander Graf | |
506 | dc333cd6 | Alexander Graf | ns++; |
507 | dc333cd6 | Alexander Graf | |
508 | dc333cd6 | Alexander Graf | retval = atoi(ns); |
509 | dc333cd6 | Alexander Graf | return retval;
|
510 | dc333cd6 | Alexander Graf | } |
511 | 4513d923 | Gleb Natapov | |
512 | 45024f09 | Alexander Graf | int kvmppc_get_hypercall(CPUState *env, uint8_t *buf, int buf_len) |
513 | 45024f09 | Alexander Graf | { |
514 | 45024f09 | Alexander Graf | uint32_t *hc = (uint32_t*)buf; |
515 | 45024f09 | Alexander Graf | |
516 | 45024f09 | Alexander Graf | struct kvm_ppc_pvinfo pvinfo;
|
517 | 45024f09 | Alexander Graf | |
518 | 45024f09 | Alexander Graf | if (kvm_check_extension(env->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
|
519 | 45024f09 | Alexander Graf | !kvm_vm_ioctl(env->kvm_state, KVM_PPC_GET_PVINFO, &pvinfo)) { |
520 | 45024f09 | Alexander Graf | memcpy(buf, pvinfo.hcall, buf_len); |
521 | 45024f09 | Alexander Graf | |
522 | 45024f09 | Alexander Graf | return 0; |
523 | 45024f09 | Alexander Graf | } |
524 | 45024f09 | Alexander Graf | |
525 | 45024f09 | Alexander Graf | /*
|
526 | 45024f09 | Alexander Graf | * Fallback to always fail hypercalls:
|
527 | 45024f09 | Alexander Graf | *
|
528 | 45024f09 | Alexander Graf | * li r3, -1
|
529 | 45024f09 | Alexander Graf | * nop
|
530 | 45024f09 | Alexander Graf | * nop
|
531 | 45024f09 | Alexander Graf | * nop
|
532 | 45024f09 | Alexander Graf | */
|
533 | 45024f09 | Alexander Graf | |
534 | 45024f09 | Alexander Graf | hc[0] = 0x3860ffff; |
535 | 45024f09 | Alexander Graf | hc[1] = 0x60000000; |
536 | 45024f09 | Alexander Graf | hc[2] = 0x60000000; |
537 | 45024f09 | Alexander Graf | hc[3] = 0x60000000; |
538 | 45024f09 | Alexander Graf | |
539 | 45024f09 | Alexander Graf | return 0; |
540 | 45024f09 | Alexander Graf | } |
541 | 45024f09 | Alexander Graf | |
542 | 4513d923 | Gleb Natapov | bool kvm_arch_stop_on_emulation_error(CPUState *env)
|
543 | 4513d923 | Gleb Natapov | { |
544 | 4513d923 | Gleb Natapov | return true; |
545 | 4513d923 | Gleb Natapov | } |
546 | a1b87fe0 | Jan Kiszka | |
547 | a1b87fe0 | Jan Kiszka | int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr) |
548 | a1b87fe0 | Jan Kiszka | { |
549 | a1b87fe0 | Jan Kiszka | return 1; |
550 | a1b87fe0 | Jan Kiszka | } |
551 | a1b87fe0 | Jan Kiszka | |
552 | a1b87fe0 | Jan Kiszka | int kvm_arch_on_sigbus(int code, void *addr) |
553 | a1b87fe0 | Jan Kiszka | { |
554 | a1b87fe0 | Jan Kiszka | return 1; |
555 | a1b87fe0 | Jan Kiszka | } |