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1
/*
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 * QEMU PCI bus manager
3
 *
4
 * Copyright (c) 2004 Fabrice Bellard
5
 * 
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
8
 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
23
 */
24
#include "vl.h"
25

    
26
//#define DEBUG_PCI
27

    
28
#define PCI_VENDOR_ID                0x00        /* 16 bits */
29
#define PCI_DEVICE_ID                0x02        /* 16 bits */
30
#define PCI_COMMAND                0x04        /* 16 bits */
31
#define  PCI_COMMAND_IO                0x1        /* Enable response in I/O space */
32
#define  PCI_COMMAND_MEMORY        0x2        /* Enable response in Memory space */
33
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
34
#define PCI_INTERRUPT_LINE        0x3c        /* 8 bits */
35
#define PCI_INTERRUPT_PIN        0x3d        /* 8 bits */
36
#define PCI_MIN_GNT                0x3e        /* 8 bits */
37
#define PCI_MAX_LAT                0x3f        /* 8 bits */
38

    
39
/* just used for simpler irq handling. */
40
#define PCI_DEVICES_MAX 64
41
#define PCI_IRQ_WORDS   ((PCI_DEVICES_MAX + 31) / 32)
42

    
43
typedef struct PCIBridge {
44
    uint32_t config_reg;
45
    PCIDevice **pci_bus[256];
46
} PCIBridge;
47

    
48
static PCIBridge pci_bridge;
49
target_phys_addr_t pci_mem_base;
50
static int pci_irq_index;
51
static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS];
52

    
53
/* -1 for devfn means auto assign */
54
PCIDevice *pci_register_device(const char *name, int instance_size,
55
                               int bus_num, int devfn,
56
                               PCIConfigReadFunc *config_read, 
57
                               PCIConfigWriteFunc *config_write)
58
{
59
    PCIBridge *s = &pci_bridge;
60
    PCIDevice *pci_dev, **bus;
61

    
62
    if (pci_irq_index >= PCI_DEVICES_MAX)
63
        return NULL;
64
    
65
    if (!s->pci_bus[bus_num]) {
66
        s->pci_bus[bus_num] = qemu_mallocz(256 * sizeof(PCIDevice *));
67
        if (!s->pci_bus[bus_num])
68
            return NULL;
69
    }
70
    bus = s->pci_bus[bus_num];
71
    if (devfn < 0) {
72
        for(devfn = 0 ; devfn < 256; devfn += 8) {
73
            if (!bus[devfn])
74
                goto found;
75
        }
76
        return NULL;
77
    found: ;
78
    }
79
    pci_dev = qemu_mallocz(instance_size);
80
    if (!pci_dev)
81
        return NULL;
82
    pci_dev->bus_num = bus_num;
83
    pci_dev->devfn = devfn;
84
    pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
85

    
86
    if (!config_read)
87
        config_read = pci_default_read_config;
88
    if (!config_write)
89
        config_write = pci_default_write_config;
90
    pci_dev->config_read = config_read;
91
    pci_dev->config_write = config_write;
92
    pci_dev->irq_index = pci_irq_index++;
93
    bus[devfn] = pci_dev;
94
    return pci_dev;
95
}
96

    
97
void pci_register_io_region(PCIDevice *pci_dev, int region_num, 
98
                            uint32_t size, int type, 
99
                            PCIMapIORegionFunc *map_func)
100
{
101
    PCIIORegion *r;
102

    
103
    if ((unsigned int)region_num >= 6)
104
        return;
105
    r = &pci_dev->io_regions[region_num];
106
    r->addr = -1;
107
    r->size = size;
108
    r->type = type;
109
    r->map_func = map_func;
110
}
111

    
112
static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val)
113
{
114
    PCIBridge *s = opaque;
115
    s->config_reg = val;
116
}
117

    
118
static uint32_t pci_addr_readl(void* opaque, uint32_t addr)
119
{
120
    PCIBridge *s = opaque;
121
    return s->config_reg;
122
}
123

    
124
static void pci_update_mappings(PCIDevice *d)
125
{
126
    PCIIORegion *r;
127
    int cmd, i;
128
    uint32_t last_addr, new_addr;
129
    
130
    cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
131
    for(i = 0; i < 6; i++) {
132
        r = &d->io_regions[i];
133
        if (r->size != 0) {
134
            if (r->type & PCI_ADDRESS_SPACE_IO) {
135
                if (cmd & PCI_COMMAND_IO) {
136
                    new_addr = le32_to_cpu(*(uint32_t *)(d->config + 
137
                                                         0x10 + i * 4));
138
                    new_addr = new_addr & ~(r->size - 1);
139
                    last_addr = new_addr + r->size - 1;
140
                    /* NOTE: we have only 64K ioports on PC */
141
                    if (last_addr <= new_addr || new_addr == 0 ||
142
                        last_addr >= 0x10000) {
143
                        new_addr = -1;
144
                    }
145
                } else {
146
                    new_addr = -1;
147
                }
148
            } else {
149
                if (cmd & PCI_COMMAND_MEMORY) {
150
                    new_addr = le32_to_cpu(*(uint32_t *)(d->config + 
151
                                                         0x10 + i * 4));
152
                    new_addr = new_addr & ~(r->size - 1);
153
                    last_addr = new_addr + r->size - 1;
154
                    /* NOTE: we do not support wrapping */
155
                    /* XXX: as we cannot support really dynamic
156
                       mappings, we handle specific values as invalid
157
                       mappings. */
158
                    if (last_addr <= new_addr || new_addr == 0 ||
159
                        last_addr == -1) {
160
                        new_addr = -1;
161
                    }
162
                } else {
163
                    new_addr = -1;
164
                }
165
            }
166
            /* now do the real mapping */
167
            if (new_addr != r->addr) {
168
                if (r->addr != -1) {
169
                    if (r->type & PCI_ADDRESS_SPACE_IO) {
170
                        int class;
171
                        /* NOTE: specific hack for IDE in PC case:
172
                           only one byte must be mapped. */
173
                        class = d->config[0x0a] | (d->config[0x0b] << 8);
174
                        if (class == 0x0101 && r->size == 4) {
175
                            isa_unassign_ioport(r->addr + 2, 1);
176
                        } else {
177
                            isa_unassign_ioport(r->addr, r->size);
178
                        }
179
                    } else {
180
                        cpu_register_physical_memory(r->addr + pci_mem_base, 
181
                                                     r->size, 
182
                                                     IO_MEM_UNASSIGNED);
183
                    }
184
                }
185
                r->addr = new_addr;
186
                if (r->addr != -1) {
187
                    r->map_func(d, i, r->addr, r->size, r->type);
188
                }
189
            }
190
        }
191
    }
192
}
193

    
194
uint32_t pci_default_read_config(PCIDevice *d, 
195
                                 uint32_t address, int len)
196
{
197
    uint32_t val;
198
    switch(len) {
199
    case 1:
200
        val = d->config[address];
201
        break;
202
    case 2:
203
        val = le16_to_cpu(*(uint16_t *)(d->config + address));
204
        break;
205
    default:
206
    case 4:
207
        val = le32_to_cpu(*(uint32_t *)(d->config + address));
208
        break;
209
    }
210
    return val;
211
}
212

    
213
void pci_default_write_config(PCIDevice *d, 
214
                              uint32_t address, uint32_t val, int len)
215
{
216
    int can_write, i;
217
    uint32_t end, addr;
218

    
219
    if (len == 4 && (address >= 0x10 && address < 0x10 + 4 * 6)) {
220
        PCIIORegion *r;
221
        int reg;
222

    
223
        reg = (address - 0x10) >> 2;
224
        r = &d->io_regions[reg];
225
        if (r->size == 0)
226
            goto default_config;
227
        /* compute the stored value */
228
        val &= ~(r->size - 1);
229
        val |= r->type;
230
        *(uint32_t *)(d->config + 0x10 + reg * 4) = cpu_to_le32(val);
231
        pci_update_mappings(d);
232
        return;
233
    }
234
 default_config:
235
    /* not efficient, but simple */
236
    addr = address;
237
    for(i = 0; i < len; i++) {
238
        /* default read/write accesses */
239
        switch(addr) {
240
        case 0x00:
241
        case 0x01:
242
        case 0x02:
243
        case 0x03:
244
        case 0x08:
245
        case 0x09:
246
        case 0x0a:
247
        case 0x0b:
248
        case 0x0e:
249
        case 0x3d:
250
            can_write = 0;
251
            break;
252
        default:
253
            can_write = 1;
254
            break;
255
        }
256
        if (can_write) {
257
            d->config[addr] = val;
258
        }
259
        addr++;
260
        val >>= 8;
261
    }
262

    
263
    end = address + len;
264
    if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
265
        /* if the command register is modified, we must modify the mappings */
266
        pci_update_mappings(d);
267
    }
268
}
269

    
270
static void pci_data_write(void *opaque, uint32_t addr, 
271
                           uint32_t val, int len)
272
{
273
    PCIBridge *s = opaque;
274
    PCIDevice **bus, *pci_dev;
275
    int config_addr;
276
    
277
#if defined(DEBUG_PCI) && 0
278
    printf("pci_data_write: addr=%08x val=%08x len=%d\n",
279
           s->config_reg, val, len);
280
#endif
281
    if (!(s->config_reg & (1 << 31))) {
282
        return;
283
    }
284
    if ((s->config_reg & 0x3) != 0) {
285
        return;
286
    }
287
    bus = s->pci_bus[(s->config_reg >> 16) & 0xff];
288
    if (!bus)
289
        return;
290
    pci_dev = bus[(s->config_reg >> 8) & 0xff];
291
    if (!pci_dev)
292
        return;
293
    config_addr = (s->config_reg & 0xfc) | (addr & 3);
294
#if defined(DEBUG_PCI)
295
    printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
296
           pci_dev->name, config_addr, val, len);
297
#endif
298
    pci_dev->config_write(pci_dev, config_addr, val, len);
299
}
300

    
301
static uint32_t pci_data_read(void *opaque, uint32_t addr, 
302
                              int len)
303
{
304
    PCIBridge *s = opaque;
305
    PCIDevice **bus, *pci_dev;
306
    int config_addr;
307
    uint32_t val;
308

    
309
    if (!(s->config_reg & (1 << 31)))
310
        goto fail;
311
    if ((s->config_reg & 0x3) != 0)
312
        goto fail;
313
    bus = s->pci_bus[(s->config_reg >> 16) & 0xff];
314
    if (!bus)
315
        goto fail;
316
    pci_dev = bus[(s->config_reg >> 8) & 0xff];
317
    if (!pci_dev) {
318
    fail:
319
        switch(len) {
320
        case 1:
321
            val = 0xff;
322
            break;
323
        case 2:
324
            val = 0xffff;
325
            break;
326
        default:
327
        case 4:
328
            val = 0xffffffff;
329
            break;
330
        }
331
        goto the_end;
332
    }
333
    config_addr = (s->config_reg & 0xfc) | (addr & 3);
334
    val = pci_dev->config_read(pci_dev, config_addr, len);
335
#if defined(DEBUG_PCI)
336
    printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
337
           pci_dev->name, config_addr, val, len);
338
#endif
339
 the_end:
340
#if defined(DEBUG_PCI) && 0
341
    printf("pci_data_read: addr=%08x val=%08x len=%d\n",
342
           s->config_reg, val, len);
343
#endif
344
    return val;
345
}
346

    
347
static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val)
348
{
349
    pci_data_write(opaque, addr, val, 1);
350
}
351

    
352
static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val)
353
{
354
    pci_data_write(opaque, addr, val, 2);
355
}
356

    
357
static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val)
358
{
359
    pci_data_write(opaque, addr, val, 4);
360
}
361

    
362
static uint32_t pci_data_readb(void* opaque, uint32_t addr)
363
{
364
    return pci_data_read(opaque, addr, 1);
365
}
366

    
367
static uint32_t pci_data_readw(void* opaque, uint32_t addr)
368
{
369
    return pci_data_read(opaque, addr, 2);
370
}
371

    
372
static uint32_t pci_data_readl(void* opaque, uint32_t addr)
373
{
374
    return pci_data_read(opaque, addr, 4);
375
}
376

    
377
/* i440FX PCI bridge */
378

    
379
void i440fx_init(void)
380
{
381
    PCIBridge *s = &pci_bridge;
382
    PCIDevice *d;
383

    
384
    register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s);
385
    register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s);
386

    
387
    register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);
388
    register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);
389
    register_ioport_write(0xcfc, 4, 4, pci_data_writel, s);
390
    register_ioport_read(0xcfc, 4, 1, pci_data_readb, s);
391
    register_ioport_read(0xcfc, 4, 2, pci_data_readw, s);
392
    register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);
393

    
394
    d = pci_register_device("i440FX", sizeof(PCIDevice), 0, 0, 
395
                            NULL, NULL);
396

    
397
    d->config[0x00] = 0x86; // vendor_id
398
    d->config[0x01] = 0x80;
399
    d->config[0x02] = 0x37; // device_id
400
    d->config[0x03] = 0x12;
401
    d->config[0x08] = 0x02; // revision
402
    d->config[0x0a] = 0x04; // class_sub = pci2pci
403
    d->config[0x0b] = 0x06; // class_base = PCI_bridge
404
    d->config[0x0c] = 0x01; // line_size in 32 bit words
405
    d->config[0x0e] = 0x01; // header_type
406
}
407

    
408
/* PIIX3 PCI to ISA bridge */
409

    
410
typedef struct PIIX3State {
411
    PCIDevice dev;
412
} PIIX3State;
413

    
414
PIIX3State *piix3_state;
415

    
416
static void piix3_reset(PIIX3State *d)
417
{
418
    uint8_t *pci_conf = d->dev.config;
419

    
420
    pci_conf[0x04] = 0x07; // master, memory and I/O
421
    pci_conf[0x05] = 0x00;
422
    pci_conf[0x06] = 0x00;
423
    pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
424
    pci_conf[0x4c] = 0x4d;
425
    pci_conf[0x4e] = 0x03;
426
    pci_conf[0x4f] = 0x00;
427
    pci_conf[0x60] = 0x80;
428
    pci_conf[0x69] = 0x02;
429
    pci_conf[0x70] = 0x80;
430
    pci_conf[0x76] = 0x0c;
431
    pci_conf[0x77] = 0x0c;
432
    pci_conf[0x78] = 0x02;
433
    pci_conf[0x79] = 0x00;
434
    pci_conf[0x80] = 0x00;
435
    pci_conf[0x82] = 0x00;
436
    pci_conf[0xa0] = 0x08;
437
    pci_conf[0xa0] = 0x08;
438
    pci_conf[0xa2] = 0x00;
439
    pci_conf[0xa3] = 0x00;
440
    pci_conf[0xa4] = 0x00;
441
    pci_conf[0xa5] = 0x00;
442
    pci_conf[0xa6] = 0x00;
443
    pci_conf[0xa7] = 0x00;
444
    pci_conf[0xa8] = 0x0f;
445
    pci_conf[0xaa] = 0x00;
446
    pci_conf[0xab] = 0x00;
447
    pci_conf[0xac] = 0x00;
448
    pci_conf[0xae] = 0x00;
449
}
450

    
451
void piix3_init(void)
452
{
453
    PIIX3State *d;
454
    uint8_t *pci_conf;
455

    
456
    d = (PIIX3State *)pci_register_device("PIIX3", sizeof(PIIX3State),
457
                                          0, -1, 
458
                                          NULL, NULL);
459
    piix3_state = d;
460
    pci_conf = d->dev.config;
461

    
462
    pci_conf[0x00] = 0x86; // Intel
463
    pci_conf[0x01] = 0x80;
464
    pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
465
    pci_conf[0x03] = 0x70;
466
    pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
467
    pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
468
    pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
469

    
470
    piix3_reset(d);
471
}
472

    
473
/* PREP pci init */
474

    
475
static inline void set_config(PCIBridge *s, target_phys_addr_t addr)
476
{
477
    int devfn, i;
478

    
479
    for(i = 0; i < 11; i++) {
480
        if ((addr & (1 << (11 + i))) != 0)
481
            break;
482
    }
483
    devfn = ((addr >> 8) & 7) | (i << 3);
484
    s->config_reg = 0x80000000 | (addr & 0xfc) | (devfn << 8);
485
}
486

    
487
static void PPC_PCIIO_writeb (target_phys_addr_t addr, uint32_t val)
488
{
489
    PCIBridge *s = &pci_bridge;
490
    set_config(s, addr);
491
    pci_data_write(s, addr, val, 1);
492
}
493

    
494
static void PPC_PCIIO_writew (target_phys_addr_t addr, uint32_t val)
495
{
496
    PCIBridge *s = &pci_bridge;
497
    set_config(s, addr);
498
#ifdef TARGET_WORDS_BIGENDIAN
499
    val = bswap16(val);
500
#endif
501
    pci_data_write(s, addr, val, 2);
502
}
503

    
504
static void PPC_PCIIO_writel (target_phys_addr_t addr, uint32_t val)
505
{
506
    PCIBridge *s = &pci_bridge;
507
    set_config(s, addr);
508
#ifdef TARGET_WORDS_BIGENDIAN
509
    val = bswap32(val);
510
#endif
511
    pci_data_write(s, addr, val, 4);
512
}
513

    
514
static uint32_t PPC_PCIIO_readb (target_phys_addr_t addr)
515
{
516
    PCIBridge *s = &pci_bridge;
517
    uint32_t val;
518
    set_config(s, addr);
519
    val = pci_data_read(s, addr, 1);
520
    return val;
521
}
522

    
523
static uint32_t PPC_PCIIO_readw (target_phys_addr_t addr)
524
{
525
    PCIBridge *s = &pci_bridge;
526
    uint32_t val;
527
    set_config(s, addr);
528
    val = pci_data_read(s, addr, 2);
529
#ifdef TARGET_WORDS_BIGENDIAN
530
    val = bswap16(val);
531
#endif
532
    return val;
533
}
534

    
535
static uint32_t PPC_PCIIO_readl (target_phys_addr_t addr)
536
{
537
    PCIBridge *s = &pci_bridge;
538
    uint32_t val;
539
    set_config(s, addr);
540
    val = pci_data_read(s, addr, 4);
541
#ifdef TARGET_WORDS_BIGENDIAN
542
    val = bswap32(val);
543
#endif
544
    return val;
545
}
546

    
547
static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
548
    &PPC_PCIIO_writeb,
549
    &PPC_PCIIO_writew,
550
    &PPC_PCIIO_writel,
551
};
552

    
553
static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
554
    &PPC_PCIIO_readb,
555
    &PPC_PCIIO_readw,
556
    &PPC_PCIIO_readl,
557
};
558

    
559
void pci_prep_init(void)
560
{
561
    PCIDevice *d;
562
    int PPC_io_memory;
563

    
564
    PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read, PPC_PCIIO_write);
565
    cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
566

    
567
    d = pci_register_device("PREP PCI Bridge", sizeof(PCIDevice), 0, 0, 
568
                            NULL, NULL);
569

    
570
    /* XXX: put correct IDs */
571
    d->config[0x00] = 0x11; // vendor_id
572
    d->config[0x01] = 0x10;
573
    d->config[0x02] = 0x26; // device_id
574
    d->config[0x03] = 0x00;
575
    d->config[0x08] = 0x02; // revision
576
    d->config[0x0a] = 0x04; // class_sub = pci2pci
577
    d->config[0x0b] = 0x06; // class_base = PCI_bridge
578
    d->config[0x0e] = 0x01; // header_type
579
}
580

    
581

    
582
/* pmac pci init */
583

    
584
static void pci_pmac_config_writel (target_phys_addr_t addr, uint32_t val)
585
{
586
    PCIBridge *s = &pci_bridge;
587
#ifdef TARGET_WORDS_BIGENDIAN
588
    val = bswap32(val);
589
#endif
590
    s->config_reg = val;
591
}
592

    
593
static uint32_t pci_pmac_config_readl (target_phys_addr_t addr)
594
{
595
    PCIBridge *s = &pci_bridge;
596
    uint32_t val;
597

    
598
    val = s->config_reg;
599
#ifdef TARGET_WORDS_BIGENDIAN
600
    val = bswap32(val);
601
#endif
602
    return val;
603
}
604

    
605
static CPUWriteMemoryFunc *pci_pmac_config_write[] = {
606
    &pci_pmac_config_writel,
607
    &pci_pmac_config_writel,
608
    &pci_pmac_config_writel,
609
};
610

    
611
static CPUReadMemoryFunc *pci_pmac_config_read[] = {
612
    &pci_pmac_config_readl,
613
    &pci_pmac_config_readl,
614
    &pci_pmac_config_readl,
615
};
616

    
617
static void pci_pmac_writeb (target_phys_addr_t addr, uint32_t val)
618
{
619
    PCIBridge *s = &pci_bridge;
620
    pci_data_write(s, addr, val, 1);
621
}
622

    
623
static void pci_pmac_writew (target_phys_addr_t addr, uint32_t val)
624
{
625
    PCIBridge *s = &pci_bridge;
626
#ifdef TARGET_WORDS_BIGENDIAN
627
    val = bswap16(val);
628
#endif
629
    pci_data_write(s, addr, val, 2);
630
}
631

    
632
static void pci_pmac_writel (target_phys_addr_t addr, uint32_t val)
633
{
634
    PCIBridge *s = &pci_bridge;
635
#ifdef TARGET_WORDS_BIGENDIAN
636
    val = bswap32(val);
637
#endif
638
    pci_data_write(s, addr, val, 4);
639
}
640

    
641
static uint32_t pci_pmac_readb (target_phys_addr_t addr)
642
{
643
    PCIBridge *s = &pci_bridge;
644
    uint32_t val;
645
    val = pci_data_read(s, addr, 1);
646
    return val;
647
}
648

    
649
static uint32_t pci_pmac_readw (target_phys_addr_t addr)
650
{
651
    PCIBridge *s = &pci_bridge;
652
    uint32_t val;
653
    val = pci_data_read(s, addr, 2);
654
#ifdef TARGET_WORDS_BIGENDIAN
655
    val = bswap16(val);
656
#endif
657
    return val;
658
}
659

    
660
static uint32_t pci_pmac_readl (target_phys_addr_t addr)
661
{
662
    PCIBridge *s = &pci_bridge;
663
    uint32_t val;
664

    
665
    val = pci_data_read(s, addr, 4);
666
#ifdef TARGET_WORDS_BIGENDIAN
667
    val = bswap32(val);
668
#endif
669
    return val;
670
}
671

    
672
static CPUWriteMemoryFunc *pci_pmac_write[] = {
673
    &pci_pmac_writeb,
674
    &pci_pmac_writew,
675
    &pci_pmac_writel,
676
};
677

    
678
static CPUReadMemoryFunc *pci_pmac_read[] = {
679
    &pci_pmac_readb,
680
    &pci_pmac_readw,
681
    &pci_pmac_readl,
682
};
683

    
684
void pci_pmac_init(void)
685
{
686
    PCIDevice *d;
687
    int pci_mem_config, pci_mem_data;
688

    
689
    pci_mem_config = cpu_register_io_memory(0, pci_pmac_config_read, 
690
                                            pci_pmac_config_write);
691
    pci_mem_data = cpu_register_io_memory(0, pci_pmac_read, pci_pmac_write);
692

    
693
    cpu_register_physical_memory(0xfec00000, 0x1000, pci_mem_config);
694
    cpu_register_physical_memory(0xfee00000, 0x1000, pci_mem_data);
695

    
696
    d = pci_register_device("MPC106", sizeof(PCIDevice), 0, 0, 
697
                            NULL, NULL);
698

    
699
    /* same values as PearPC - check this */
700
    d->config[0x00] = 0x11; // vendor_id
701
    d->config[0x01] = 0x10;
702
    d->config[0x02] = 0x26; // device_id
703
    d->config[0x03] = 0x00;
704
    d->config[0x08] = 0x02; // revision
705
    d->config[0x0a] = 0x04; // class_sub = pci2pci
706
    d->config[0x0b] = 0x06; // class_base = PCI_bridge
707
    d->config[0x0e] = 0x01; // header_type
708

    
709
    d->config[0x18] = 0x0;  // primary_bus
710
    d->config[0x19] = 0x1;  // secondary_bus
711
    d->config[0x1a] = 0x1;  // subordinate_bus
712
    d->config[0x1c] = 0x10; // io_base
713
    d->config[0x1d] = 0x20; // io_limit
714
    
715
    d->config[0x20] = 0x80; // memory_base
716
    d->config[0x21] = 0x80;
717
    d->config[0x22] = 0x90; // memory_limit
718
    d->config[0x23] = 0x80;
719
    
720
    d->config[0x24] = 0x00; // prefetchable_memory_base
721
    d->config[0x25] = 0x84;
722
    d->config[0x26] = 0x00; // prefetchable_memory_limit
723
    d->config[0x27] = 0x85;
724
}
725

    
726
/***********************************************************/
727
/* generic PCI irq support */
728

    
729
/* return the global irq number corresponding to a given device irq
730
   pin. We could also use the bus number to have a more precise
731
   mapping. */
732
static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
733
{
734
    int slot_addend;
735
    slot_addend = (pci_dev->devfn >> 3);
736
    return (irq_num + slot_addend) & 3;
737
}
738

    
739
/* 0 <= irq_num <= 3. level must be 0 or 1 */
740
#ifdef TARGET_PPC
741
void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
742
{
743
}
744
#else
745
void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
746
{
747
    int irq_index, shift, pic_irq, pic_level;
748
    uint32_t *p;
749

    
750
    irq_num = pci_slot_get_pirq(pci_dev, irq_num);
751
    irq_index = pci_dev->irq_index;
752
    p = &pci_irq_levels[irq_num][irq_index >> 5];
753
    shift = (irq_index & 0x1f);
754
    *p = (*p & ~(1 << shift)) | (level << shift);
755

    
756
    /* now we change the pic irq level according to the piix irq mappings */
757
    pic_irq = piix3_state->dev.config[0x60 + irq_num];
758
    if (pic_irq < 16) {
759
        /* the pic level is the logical OR of all the PCI irqs mapped
760
           to it */
761
        pic_level = 0;
762
#if (PCI_IRQ_WORDS == 2)
763
        pic_level = ((pci_irq_levels[irq_num][0] | 
764
                      pci_irq_levels[irq_num][1]) != 0);
765
#else
766
        {
767
            int i;
768
            pic_level = 0;
769
            for(i = 0; i < PCI_IRQ_WORDS; i++) {
770
                if (pci_irq_levels[irq_num][i]) {
771
                    pic_level = 1;
772
                    break;
773
                }
774
            }
775
        }
776
#endif
777
        pic_set_irq(pic_irq, pic_level);
778
    }
779
}
780
#endif
781

    
782
/***********************************************************/
783
/* monitor info on PCI */
784

    
785
static void pci_info_device(PCIDevice *d)
786
{
787
    int i, class;
788
    PCIIORegion *r;
789

    
790
    printf("  Bus %2d, device %3d, function %d:\n",
791
           d->bus_num, d->devfn >> 3, d->devfn & 7);
792
    class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
793
    printf("    ");
794
    switch(class) {
795
    case 0x0101:
796
        printf("IDE controller");
797
        break;
798
    case 0x0200:
799
        printf("Ethernet controller");
800
        break;
801
    case 0x0300:
802
        printf("VGA controller");
803
        break;
804
    default:
805
        printf("Class %04x", class);
806
        break;
807
    }
808
    printf(": PCI device %04x:%04x\n",
809
           le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
810
           le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
811

    
812
    if (d->config[PCI_INTERRUPT_PIN] != 0) {
813
        printf("      IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
814
    }
815
    for(i = 0;i < 6; i++) {
816
        r = &d->io_regions[i];
817
        if (r->size != 0) {
818
            printf("      BAR%d: ", i);
819
            if (r->type & PCI_ADDRESS_SPACE_IO) {
820
                printf("I/O at 0x%04x [0x%04x].\n", 
821
                       r->addr, r->addr + r->size - 1);
822
            } else {
823
                printf("32 bit memory at 0x%08x [0x%08x].\n", 
824
                       r->addr, r->addr + r->size - 1);
825
            }
826
        }
827
    }
828
}
829

    
830
void pci_info(void)
831
{
832
    PCIBridge *s = &pci_bridge;
833
    PCIDevice **bus;
834
    int bus_num, devfn;
835
    
836
    for(bus_num = 0; bus_num < 256; bus_num++) {
837
        bus = s->pci_bus[bus_num];
838
        if (bus) {
839
            for(devfn = 0; devfn < 256; devfn++) {
840
                if (bus[devfn])
841
                    pci_info_device(bus[devfn]);
842
            }
843
        }
844
    }
845
}
846

    
847
/***********************************************************/
848
/* XXX: the following should be moved to the PC BIOS */
849

    
850
static uint32_t isa_inb(uint32_t addr)
851
{
852
    return cpu_inb(cpu_single_env, addr);
853
}
854

    
855
static void isa_outb(uint32_t val, uint32_t addr)
856
{
857
    cpu_outb(cpu_single_env, addr, val);
858
}
859

    
860
static uint32_t isa_inw(uint32_t addr)
861
{
862
    return cpu_inw(cpu_single_env, addr);
863
}
864

    
865
static void isa_outw(uint32_t val, uint32_t addr)
866
{
867
    cpu_outw(cpu_single_env, addr, val);
868
}
869

    
870
static uint32_t isa_inl(uint32_t addr)
871
{
872
    return cpu_inl(cpu_single_env, addr);
873
}
874

    
875
static void isa_outl(uint32_t val, uint32_t addr)
876
{
877
    cpu_outl(cpu_single_env, addr, val);
878
}
879

    
880
static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
881
{
882
    PCIBridge *s = &pci_bridge;
883
    s->config_reg = 0x80000000 | (d->bus_num << 16) | 
884
        (d->devfn << 8) | addr;
885
    pci_data_write(s, 0, val, 4);
886
}
887

    
888
static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
889
{
890
    PCIBridge *s = &pci_bridge;
891
    s->config_reg = 0x80000000 | (d->bus_num << 16) | 
892
        (d->devfn << 8) | (addr & ~3);
893
    pci_data_write(s, addr & 3, val, 2);
894
}
895

    
896
static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
897
{
898
    PCIBridge *s = &pci_bridge;
899
    s->config_reg = 0x80000000 | (d->bus_num << 16) | 
900
        (d->devfn << 8) | (addr & ~3);
901
    pci_data_write(s, addr & 3, val, 1);
902
}
903

    
904
static uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
905
{
906
    PCIBridge *s = &pci_bridge;
907
    s->config_reg = 0x80000000 | (d->bus_num << 16) | 
908
        (d->devfn << 8) | addr;
909
    return pci_data_read(s, 0, 4);
910
}
911

    
912
static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
913
{
914
    PCIBridge *s = &pci_bridge;
915
    s->config_reg = 0x80000000 | (d->bus_num << 16) | 
916
        (d->devfn << 8) | (addr & ~3);
917
    return pci_data_read(s, addr & 3, 2);
918
}
919

    
920
static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
921
{
922
    PCIBridge *s = &pci_bridge;
923
    s->config_reg = 0x80000000 | (d->bus_num << 16) | 
924
        (d->devfn << 8) | (addr & ~3);
925
    return pci_data_read(s, addr & 3, 1);
926
}
927

    
928
static uint32_t pci_bios_io_addr;
929
static uint32_t pci_bios_mem_addr;
930
/* host irqs corresponding to PCI irqs A-D */
931
static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
932

    
933
static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
934
{
935
    PCIIORegion *r;
936
    uint16_t cmd;
937

    
938
    pci_config_writel(d, 0x10 + region_num * 4, addr);
939
    r = &d->io_regions[region_num];
940

    
941
    /* enable memory mappings */
942
    cmd = pci_config_readw(d, PCI_COMMAND);
943
    if (r->type & PCI_ADDRESS_SPACE_IO)
944
        cmd |= 1;
945
    else
946
        cmd |= 2;
947
    pci_config_writew(d, PCI_COMMAND, cmd);
948
}
949

    
950
static void pci_bios_init_device(PCIDevice *d)
951
{
952
    int class;
953
    PCIIORegion *r;
954
    uint32_t *paddr;
955
    int i, pin, pic_irq, vendor_id, device_id;
956

    
957
    class = pci_config_readw(d, PCI_CLASS_DEVICE);
958
    switch(class) {
959
    case 0x0101:
960
        vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
961
        device_id = pci_config_readw(d, PCI_DEVICE_ID);
962
        if (vendor_id == 0x8086 && device_id == 0x7010) {
963
            /* PIIX3 IDE */
964
            pci_config_writew(d, PCI_COMMAND, PCI_COMMAND_IO);
965
            pci_config_writew(d, 0x40, 0x8000); // enable IDE0
966
        } else {
967
            /* IDE: we map it as in ISA mode */
968
            pci_set_io_region_addr(d, 0, 0x1f0);
969
            pci_set_io_region_addr(d, 1, 0x3f4);
970
            pci_set_io_region_addr(d, 2, 0x170);
971
            pci_set_io_region_addr(d, 3, 0x374);
972
        }
973
        break;
974
    case 0x0300:
975
        /* VGA: map frame buffer to default Bochs VBE address */
976
        pci_set_io_region_addr(d, 0, 0xE0000000);
977
        break;
978
    default:
979
        /* default memory mappings */
980
        for(i = 0; i < 6; i++) {
981
            r = &d->io_regions[i];
982
            if (r->size) {
983
                if (r->type & PCI_ADDRESS_SPACE_IO)
984
                    paddr = &pci_bios_io_addr;
985
                else
986
                    paddr = &pci_bios_mem_addr;
987
                *paddr = (*paddr + r->size - 1) & ~(r->size - 1);
988
                pci_set_io_region_addr(d, i, *paddr);
989
                *paddr += r->size;
990
            }
991
        }
992
        break;
993
    }
994

    
995
    /* map the interrupt */
996
    pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
997
    if (pin != 0) {
998
        pin = pci_slot_get_pirq(d, pin - 1);
999
        pic_irq = pci_irqs[pin];
1000
        pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
1001
    }
1002
}
1003

    
1004
/*
1005
 * This function initializes the PCI devices as a normal PCI BIOS
1006
 * would do. It is provided just in case the BIOS has no support for
1007
 * PCI.
1008
 */
1009
void pci_bios_init(void)
1010
{
1011
    PCIBridge *s = &pci_bridge;
1012
    PCIDevice **bus;
1013
    int bus_num, devfn, i, irq;
1014
    uint8_t elcr[2];
1015

    
1016
    pci_bios_io_addr = 0xc000;
1017
    pci_bios_mem_addr = 0xf0000000;
1018

    
1019
    /* activate IRQ mappings */
1020
    elcr[0] = 0x00;
1021
    elcr[1] = 0x00;
1022
    for(i = 0; i < 4; i++) {
1023
        irq = pci_irqs[i];
1024
        /* set to trigger level */
1025
        elcr[irq >> 3] |= (1 << (irq & 7));
1026
        /* activate irq remapping in PIIX */
1027
        pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
1028
    }
1029
    isa_outb(elcr[0], 0x4d0);
1030
    isa_outb(elcr[1], 0x4d1);
1031

    
1032
    for(bus_num = 0; bus_num < 256; bus_num++) {
1033
        bus = s->pci_bus[bus_num];
1034
        if (bus) {
1035
            for(devfn = 0; devfn < 256; devfn++) {
1036
                if (bus[devfn])
1037
                    pci_bios_init_device(bus[devfn]);
1038
            }
1039
        }
1040
    }
1041
}
1042

    
1043
/*
1044
 * This function initializes the PCI devices as a normal PCI BIOS
1045
 * would do. It is provided just in case the BIOS has no support for
1046
 * PCI.
1047
 */
1048
void pci_ppc_bios_init(void)
1049
{
1050
    PCIBridge *s = &pci_bridge;
1051
    PCIDevice **bus;
1052
    int bus_num, devfn, i, irq;
1053
    uint8_t elcr[2];
1054

    
1055
    pci_bios_io_addr = 0xc000;
1056
    pci_bios_mem_addr = 0xc0000000;
1057

    
1058
#if 0
1059
    /* activate IRQ mappings */
1060
    elcr[0] = 0x00;
1061
    elcr[1] = 0x00;
1062
    for(i = 0; i < 4; i++) {
1063
        irq = pci_irqs[i];
1064
        /* set to trigger level */
1065
        elcr[irq >> 3] |= (1 << (irq & 7));
1066
        /* activate irq remapping in PIIX */
1067
        pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
1068
    }
1069
    isa_outb(elcr[0], 0x4d0);
1070
    isa_outb(elcr[1], 0x4d1);
1071
#endif
1072

    
1073
    for(bus_num = 0; bus_num < 256; bus_num++) {
1074
        bus = s->pci_bus[bus_num];
1075
        if (bus) {
1076
            for(devfn = 0; devfn < 256; devfn++) {
1077
                if (bus[devfn])
1078
                    pci_bios_init_device(bus[devfn]);
1079
            }
1080
        }
1081
    }
1082
}