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1 | ff1f20a3 | bellard | /*
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2 | ff1f20a3 | bellard | * dyngen helpers
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3 | ff1f20a3 | bellard | *
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4 | ff1f20a3 | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | ff1f20a3 | bellard | *
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6 | ff1f20a3 | bellard | * This library is free software; you can redistribute it and/or
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7 | ff1f20a3 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | ff1f20a3 | bellard | * License as published by the Free Software Foundation; either
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9 | ff1f20a3 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | ff1f20a3 | bellard | *
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11 | ff1f20a3 | bellard | * This library is distributed in the hope that it will be useful,
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12 | ff1f20a3 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | ff1f20a3 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | ff1f20a3 | bellard | * Lesser General Public License for more details.
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15 | ff1f20a3 | bellard | *
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16 | ff1f20a3 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | ff1f20a3 | bellard | * License along with this library; if not, write to the Free Software
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18 | ff1f20a3 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | ff1f20a3 | bellard | */
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20 | ff1f20a3 | bellard | |
21 | 03daf0e3 | bellard | int __op_param1, __op_param2, __op_param3;
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22 | c4687878 | bellard | int __op_gen_label1, __op_gen_label2, __op_gen_label3;
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23 | c106152d | bellard | int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3;
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24 | 03daf0e3 | bellard | |
25 | 03daf0e3 | bellard | #ifdef __i386__
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26 | 03daf0e3 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
27 | 03daf0e3 | bellard | { |
28 | 03daf0e3 | bellard | } |
29 | 03daf0e3 | bellard | #endif
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30 | 03daf0e3 | bellard | |
31 | bc51c5c9 | bellard | #ifdef __x86_64__
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32 | bc51c5c9 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
33 | bc51c5c9 | bellard | { |
34 | bc51c5c9 | bellard | } |
35 | bc51c5c9 | bellard | #endif
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36 | bc51c5c9 | bellard | |
37 | 03daf0e3 | bellard | #ifdef __s390__
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38 | 03daf0e3 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
39 | 03daf0e3 | bellard | { |
40 | 03daf0e3 | bellard | } |
41 | 03daf0e3 | bellard | #endif
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42 | 03daf0e3 | bellard | |
43 | 03daf0e3 | bellard | #ifdef __ia64__
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44 | 03daf0e3 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
45 | 03daf0e3 | bellard | { |
46 | b8076a74 | bellard | while (start < stop) {
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47 | b8076a74 | bellard | asm volatile ("fc %0" :: "r"(start)); |
48 | b8076a74 | bellard | start += 32;
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49 | b8076a74 | bellard | } |
50 | b8076a74 | bellard | asm volatile (";;sync.i;;srlz.i;;"); |
51 | 03daf0e3 | bellard | } |
52 | 03daf0e3 | bellard | #endif
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53 | 03daf0e3 | bellard | |
54 | 03daf0e3 | bellard | #ifdef __powerpc__
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55 | 03daf0e3 | bellard | |
56 | 03daf0e3 | bellard | #define MIN_CACHE_LINE_SIZE 8 /* conservative value */ |
57 | 03daf0e3 | bellard | |
58 | 03daf0e3 | bellard | static void inline flush_icache_range(unsigned long start, unsigned long stop) |
59 | 03daf0e3 | bellard | { |
60 | 03daf0e3 | bellard | unsigned long p; |
61 | 03daf0e3 | bellard | |
62 | 03daf0e3 | bellard | p = start & ~(MIN_CACHE_LINE_SIZE - 1);
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63 | 03daf0e3 | bellard | stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1); |
64 | 03daf0e3 | bellard | |
65 | 03daf0e3 | bellard | for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
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66 | 03daf0e3 | bellard | asm volatile ("dcbst 0,%0" : : "r"(p) : "memory"); |
67 | 03daf0e3 | bellard | } |
68 | 03daf0e3 | bellard | asm volatile ("sync" : : : "memory"); |
69 | 03daf0e3 | bellard | for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
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70 | 03daf0e3 | bellard | asm volatile ("icbi 0,%0" : : "r"(p) : "memory"); |
71 | 03daf0e3 | bellard | } |
72 | 03daf0e3 | bellard | asm volatile ("sync" : : : "memory"); |
73 | 03daf0e3 | bellard | asm volatile ("isync" : : : "memory"); |
74 | 03daf0e3 | bellard | } |
75 | 03daf0e3 | bellard | #endif
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76 | 03daf0e3 | bellard | |
77 | 03daf0e3 | bellard | #ifdef __alpha__
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78 | 03daf0e3 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
79 | 03daf0e3 | bellard | { |
80 | 03daf0e3 | bellard | asm ("imb"); |
81 | 03daf0e3 | bellard | } |
82 | 03daf0e3 | bellard | #endif
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83 | 03daf0e3 | bellard | |
84 | 03daf0e3 | bellard | #ifdef __sparc__
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85 | 03daf0e3 | bellard | |
86 | 03daf0e3 | bellard | static void inline flush_icache_range(unsigned long start, unsigned long stop) |
87 | 03daf0e3 | bellard | { |
88 | 03daf0e3 | bellard | unsigned long p; |
89 | 03daf0e3 | bellard | |
90 | 03daf0e3 | bellard | p = start & ~(8UL - 1UL); |
91 | 03daf0e3 | bellard | stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL); |
92 | 03daf0e3 | bellard | |
93 | 03daf0e3 | bellard | for (; p < stop; p += 8) |
94 | 03daf0e3 | bellard | __asm__ __volatile__("flush\t%0" : : "r" (p)); |
95 | 03daf0e3 | bellard | } |
96 | 03daf0e3 | bellard | |
97 | 03daf0e3 | bellard | #endif
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98 | 03daf0e3 | bellard | |
99 | 03daf0e3 | bellard | #ifdef __arm__
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100 | 03daf0e3 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
101 | 03daf0e3 | bellard | { |
102 | 03daf0e3 | bellard | register unsigned long _beg __asm ("a1") = start; |
103 | 03daf0e3 | bellard | register unsigned long _end __asm ("a2") = stop; |
104 | 03daf0e3 | bellard | register unsigned long _flg __asm ("a3") = 0; |
105 | 03daf0e3 | bellard | __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); |
106 | 03daf0e3 | bellard | } |
107 | 03daf0e3 | bellard | #endif
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108 | 03daf0e3 | bellard | |
109 | 38e584a0 | bellard | #ifdef __mc68000
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110 | 38e584a0 | bellard | #include <asm/cachectl.h> |
111 | 38e584a0 | bellard | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
112 | 38e584a0 | bellard | { |
113 | 38e584a0 | bellard | cacheflush(start,FLUSH_SCOPE_LINE,FLUSH_CACHE_BOTH,stop-start+16);
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114 | 38e584a0 | bellard | } |
115 | 38e584a0 | bellard | #endif
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116 | 38e584a0 | bellard | |
117 | ff1f20a3 | bellard | #ifdef __alpha__
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118 | ff1f20a3 | bellard | |
119 | ff1f20a3 | bellard | register int gp asm("$29"); |
120 | ff1f20a3 | bellard | |
121 | ff1f20a3 | bellard | static inline void immediate_ldah(void *p, int val) { |
122 | ff1f20a3 | bellard | uint32_t *dest = p; |
123 | ff1f20a3 | bellard | long high = ((val >> 16) + ((val >> 15) & 1)) & 0xffff; |
124 | ff1f20a3 | bellard | |
125 | ff1f20a3 | bellard | *dest &= ~0xffff;
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126 | ff1f20a3 | bellard | *dest |= high; |
127 | ff1f20a3 | bellard | *dest |= 31 << 16; |
128 | ff1f20a3 | bellard | } |
129 | ff1f20a3 | bellard | static inline void immediate_lda(void *dest, int val) { |
130 | ff1f20a3 | bellard | *(uint16_t *) dest = val; |
131 | ff1f20a3 | bellard | } |
132 | ff1f20a3 | bellard | void fix_bsr(void *p, int offset) { |
133 | ff1f20a3 | bellard | uint32_t *dest = p; |
134 | ff1f20a3 | bellard | *dest &= ~((1 << 21) - 1); |
135 | ff1f20a3 | bellard | *dest |= (offset >> 2) & ((1 << 21) - 1); |
136 | ff1f20a3 | bellard | } |
137 | ff1f20a3 | bellard | |
138 | ff1f20a3 | bellard | #endif /* __alpha__ */ |
139 | ff1f20a3 | bellard | |
140 | ff1f20a3 | bellard | #ifdef __arm__
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141 | ff1f20a3 | bellard | |
142 | ff1f20a3 | bellard | #define MAX_OP_SIZE (128 * 4) /* in bytes */ |
143 | ff1f20a3 | bellard | /* max size of the code that can be generated without calling arm_flush_ldr */
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144 | ff1f20a3 | bellard | #define MAX_FRAG_SIZE (1024 * 4) |
145 | ff1f20a3 | bellard | //#define MAX_FRAG_SIZE (135 * 4) /* for testing */
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146 | ff1f20a3 | bellard | |
147 | ff1f20a3 | bellard | typedef struct LDREntry { |
148 | ff1f20a3 | bellard | uint8_t *ptr; |
149 | ff1f20a3 | bellard | uint32_t *data_ptr; |
150 | ff1f20a3 | bellard | } LDREntry; |
151 | ff1f20a3 | bellard | |
152 | ff1f20a3 | bellard | static LDREntry arm_ldr_table[1024]; |
153 | ff1f20a3 | bellard | static uint32_t arm_data_table[1024]; |
154 | ff1f20a3 | bellard | |
155 | ff1f20a3 | bellard | extern char exec_loop; |
156 | ff1f20a3 | bellard | |
157 | ff1f20a3 | bellard | static inline void arm_reloc_pc24(uint32_t *ptr, uint32_t insn, int val) |
158 | ff1f20a3 | bellard | { |
159 | ff1f20a3 | bellard | *ptr = (insn & ~0xffffff) | ((insn + ((val - (int)ptr) >> 2)) & 0xffffff); |
160 | ff1f20a3 | bellard | } |
161 | ff1f20a3 | bellard | |
162 | ff1f20a3 | bellard | static uint8_t *arm_flush_ldr(uint8_t *gen_code_ptr,
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163 | ff1f20a3 | bellard | LDREntry *ldr_start, LDREntry *ldr_end, |
164 | ff1f20a3 | bellard | uint32_t *data_start, uint32_t *data_end, |
165 | ff1f20a3 | bellard | int gen_jmp)
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166 | ff1f20a3 | bellard | { |
167 | ff1f20a3 | bellard | LDREntry *le; |
168 | ff1f20a3 | bellard | uint32_t *ptr; |
169 | ff1f20a3 | bellard | int offset, data_size, target;
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170 | ff1f20a3 | bellard | uint8_t *data_ptr; |
171 | ff1f20a3 | bellard | uint32_t insn; |
172 | ff1f20a3 | bellard | |
173 | ff1f20a3 | bellard | data_size = (uint8_t *)data_end - (uint8_t *)data_start; |
174 | ff1f20a3 | bellard | |
175 | 9621339d | bellard | if (gen_jmp) {
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176 | ff1f20a3 | bellard | /* generate branch to skip the data */
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177 | ff1f20a3 | bellard | if (data_size == 0) |
178 | ff1f20a3 | bellard | return gen_code_ptr;
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179 | ff1f20a3 | bellard | target = (long)gen_code_ptr + data_size + 4; |
180 | ff1f20a3 | bellard | arm_reloc_pc24((uint32_t *)gen_code_ptr, 0xeafffffe, target);
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181 | ff1f20a3 | bellard | gen_code_ptr += 4;
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182 | ff1f20a3 | bellard | } |
183 | ff1f20a3 | bellard | |
184 | ff1f20a3 | bellard | /* copy the data */
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185 | ff1f20a3 | bellard | data_ptr = gen_code_ptr; |
186 | ff1f20a3 | bellard | memcpy(gen_code_ptr, data_start, data_size); |
187 | ff1f20a3 | bellard | gen_code_ptr += data_size; |
188 | ff1f20a3 | bellard | |
189 | ff1f20a3 | bellard | /* patch the ldr to point to the data */
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190 | ff1f20a3 | bellard | for(le = ldr_start; le < ldr_end; le++) {
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191 | ff1f20a3 | bellard | ptr = (uint32_t *)le->ptr; |
192 | ff1f20a3 | bellard | offset = ((unsigned long)(le->data_ptr) - (unsigned long)data_start) + |
193 | ff1f20a3 | bellard | (unsigned long)data_ptr - |
194 | ff1f20a3 | bellard | (unsigned long)ptr - 8; |
195 | ff1f20a3 | bellard | insn = *ptr & ~(0xfff | 0x00800000); |
196 | ff1f20a3 | bellard | if (offset < 0) { |
197 | ff1f20a3 | bellard | offset = - offset; |
198 | ff1f20a3 | bellard | } else {
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199 | ff1f20a3 | bellard | insn |= 0x00800000;
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200 | ff1f20a3 | bellard | } |
201 | ff1f20a3 | bellard | if (offset > 0xfff) { |
202 | ff1f20a3 | bellard | fprintf(stderr, "Error ldr offset\n");
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203 | ff1f20a3 | bellard | abort(); |
204 | ff1f20a3 | bellard | } |
205 | ff1f20a3 | bellard | insn |= offset; |
206 | ff1f20a3 | bellard | *ptr = insn; |
207 | ff1f20a3 | bellard | } |
208 | ff1f20a3 | bellard | return gen_code_ptr;
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209 | ff1f20a3 | bellard | } |
210 | ff1f20a3 | bellard | |
211 | ff1f20a3 | bellard | #endif /* __arm__ */ |
212 | b8076a74 | bellard | |
213 | b8076a74 | bellard | #ifdef __ia64
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214 | b8076a74 | bellard | |
215 | b8076a74 | bellard | |
216 | b8076a74 | bellard | /* Patch instruction with "val" where "mask" has 1 bits. */
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217 | b8076a74 | bellard | static inline void ia64_patch (uint64_t insn_addr, uint64_t mask, uint64_t val) |
218 | b8076a74 | bellard | { |
219 | b8076a74 | bellard | uint64_t m0, m1, v0, v1, b0, b1, *b = (uint64_t *) (insn_addr & -16);
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220 | b8076a74 | bellard | # define insn_mask ((1UL << 41) - 1) |
221 | b8076a74 | bellard | unsigned long shift; |
222 | b8076a74 | bellard | |
223 | b8076a74 | bellard | b0 = b[0]; b1 = b[1]; |
224 | b8076a74 | bellard | shift = 5 + 41 * (insn_addr % 16); /* 5 template, 3 x 41-bit insns */ |
225 | b8076a74 | bellard | if (shift >= 64) { |
226 | b8076a74 | bellard | m1 = mask << (shift - 64);
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227 | b8076a74 | bellard | v1 = val << (shift - 64);
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228 | b8076a74 | bellard | } else {
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229 | b8076a74 | bellard | m0 = mask << shift; m1 = mask >> (64 - shift);
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230 | b8076a74 | bellard | v0 = val << shift; v1 = val >> (64 - shift);
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231 | b8076a74 | bellard | b[0] = (b0 & ~m0) | (v0 & m0);
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232 | b8076a74 | bellard | } |
233 | b8076a74 | bellard | b[1] = (b1 & ~m1) | (v1 & m1);
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234 | b8076a74 | bellard | } |
235 | b8076a74 | bellard | |
236 | b8076a74 | bellard | static inline void ia64_patch_imm60 (uint64_t insn_addr, uint64_t val) |
237 | b8076a74 | bellard | { |
238 | b8076a74 | bellard | ia64_patch(insn_addr, |
239 | b8076a74 | bellard | 0x011ffffe000UL,
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240 | b8076a74 | bellard | ( ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */ |
241 | b8076a74 | bellard | | ((val & 0x00000000000fffffUL) << 13) /* bit 0 -> 13 */)); |
242 | b8076a74 | bellard | ia64_patch(insn_addr - 1, 0x1fffffffffcUL, val >> 18); |
243 | b8076a74 | bellard | } |
244 | b8076a74 | bellard | |
245 | b8076a74 | bellard | static inline void ia64_imm64 (void *insn, uint64_t val) |
246 | b8076a74 | bellard | { |
247 | b8076a74 | bellard | /* Ignore the slot number of the relocation; GCC and Intel
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248 | b8076a74 | bellard | toolchains differed for some time on whether IMM64 relocs are
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249 | b8076a74 | bellard | against slot 1 (Intel) or slot 2 (GCC). */
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250 | b8076a74 | bellard | uint64_t insn_addr = (uint64_t) insn & ~3UL;
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251 | b8076a74 | bellard | |
252 | b8076a74 | bellard | ia64_patch(insn_addr + 2,
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253 | b8076a74 | bellard | 0x01fffefe000UL,
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254 | b8076a74 | bellard | ( ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */ |
255 | b8076a74 | bellard | | ((val & 0x0000000000200000UL) << 0) /* bit 21 -> 21 */ |
256 | b8076a74 | bellard | | ((val & 0x00000000001f0000UL) << 6) /* bit 16 -> 22 */ |
257 | b8076a74 | bellard | | ((val & 0x000000000000ff80UL) << 20) /* bit 7 -> 27 */ |
258 | b8076a74 | bellard | | ((val & 0x000000000000007fUL) << 13) /* bit 0 -> 13 */) |
259 | b8076a74 | bellard | ); |
260 | b8076a74 | bellard | ia64_patch(insn_addr + 1, 0x1ffffffffffUL, val >> 22); |
261 | b8076a74 | bellard | } |
262 | b8076a74 | bellard | |
263 | b8076a74 | bellard | static inline void ia64_imm60b (void *insn, uint64_t val) |
264 | b8076a74 | bellard | { |
265 | b8076a74 | bellard | /* Ignore the slot number of the relocation; GCC and Intel
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266 | b8076a74 | bellard | toolchains differed for some time on whether IMM64 relocs are
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267 | b8076a74 | bellard | against slot 1 (Intel) or slot 2 (GCC). */
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268 | b8076a74 | bellard | uint64_t insn_addr = (uint64_t) insn & ~3UL;
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269 | b8076a74 | bellard | |
270 | b8076a74 | bellard | if (val + ((uint64_t) 1 << 59) >= (1UL << 60)) |
271 | b8076a74 | bellard | fprintf(stderr, "%s: value %ld out of IMM60 range\n",
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272 | b8076a74 | bellard | __FUNCTION__, (int64_t) val); |
273 | b8076a74 | bellard | ia64_patch_imm60(insn_addr + 2, val);
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274 | b8076a74 | bellard | } |
275 | b8076a74 | bellard | |
276 | b8076a74 | bellard | static inline void ia64_imm22 (void *insn, uint64_t val) |
277 | b8076a74 | bellard | { |
278 | b8076a74 | bellard | if (val + (1 << 21) >= (1 << 22)) |
279 | b8076a74 | bellard | fprintf(stderr, "%s: value %li out of IMM22 range\n",
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280 | b8076a74 | bellard | __FUNCTION__, (int64_t)val); |
281 | b8076a74 | bellard | ia64_patch((uint64_t) insn, 0x01fffcfe000UL,
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282 | b8076a74 | bellard | ( ((val & 0x200000UL) << 15) /* bit 21 -> 36 */ |
283 | b8076a74 | bellard | | ((val & 0x1f0000UL) << 6) /* bit 16 -> 22 */ |
284 | b8076a74 | bellard | | ((val & 0x00ff80UL) << 20) /* bit 7 -> 27 */ |
285 | b8076a74 | bellard | | ((val & 0x00007fUL) << 13) /* bit 0 -> 13 */)); |
286 | b8076a74 | bellard | } |
287 | b8076a74 | bellard | |
288 | b8076a74 | bellard | /* Like ia64_imm22(), but also clear bits 20-21. For addl, this has
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289 | b8076a74 | bellard | the effect of turning "addl rX=imm22,rY" into "addl
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290 | b8076a74 | bellard | rX=imm22,r0". */
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291 | b8076a74 | bellard | static inline void ia64_imm22_r0 (void *insn, uint64_t val) |
292 | b8076a74 | bellard | { |
293 | b8076a74 | bellard | if (val + (1 << 21) >= (1 << 22)) |
294 | b8076a74 | bellard | fprintf(stderr, "%s: value %li out of IMM22 range\n",
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295 | b8076a74 | bellard | __FUNCTION__, (int64_t)val); |
296 | b8076a74 | bellard | ia64_patch((uint64_t) insn, 0x01fffcfe000UL | (0x3UL << 20), |
297 | b8076a74 | bellard | ( ((val & 0x200000UL) << 15) /* bit 21 -> 36 */ |
298 | b8076a74 | bellard | | ((val & 0x1f0000UL) << 6) /* bit 16 -> 22 */ |
299 | b8076a74 | bellard | | ((val & 0x00ff80UL) << 20) /* bit 7 -> 27 */ |
300 | b8076a74 | bellard | | ((val & 0x00007fUL) << 13) /* bit 0 -> 13 */)); |
301 | b8076a74 | bellard | } |
302 | b8076a74 | bellard | |
303 | b8076a74 | bellard | static inline void ia64_imm21b (void *insn, uint64_t val) |
304 | b8076a74 | bellard | { |
305 | b8076a74 | bellard | if (val + (1 << 20) >= (1 << 21)) |
306 | b8076a74 | bellard | fprintf(stderr, "%s: value %li out of IMM21b range\n",
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307 | b8076a74 | bellard | __FUNCTION__, (int64_t)val); |
308 | b8076a74 | bellard | ia64_patch((uint64_t) insn, 0x11ffffe000UL,
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309 | b8076a74 | bellard | ( ((val & 0x100000UL) << 16) /* bit 20 -> 36 */ |
310 | b8076a74 | bellard | | ((val & 0x0fffffUL) << 13) /* bit 0 -> 13 */)); |
311 | b8076a74 | bellard | } |
312 | b8076a74 | bellard | |
313 | b8076a74 | bellard | static inline void ia64_nop_b (void *insn) |
314 | b8076a74 | bellard | { |
315 | b8076a74 | bellard | ia64_patch((uint64_t) insn, (1UL << 41) - 1, 2UL << 37); |
316 | b8076a74 | bellard | } |
317 | b8076a74 | bellard | |
318 | b8076a74 | bellard | static inline void ia64_ldxmov(void *insn, uint64_t val) |
319 | b8076a74 | bellard | { |
320 | b8076a74 | bellard | if (val + (1 << 21) < (1 << 22)) |
321 | b8076a74 | bellard | ia64_patch((uint64_t) insn, 0x1fff80fe000UL, 8UL << 37); |
322 | b8076a74 | bellard | } |
323 | b8076a74 | bellard | |
324 | b8076a74 | bellard | static inline int ia64_patch_ltoff(void *insn, uint64_t val, |
325 | b8076a74 | bellard | int relaxable)
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326 | b8076a74 | bellard | { |
327 | b8076a74 | bellard | if (relaxable && (val + (1 << 21) < (1 << 22))) { |
328 | b8076a74 | bellard | ia64_imm22_r0(insn, val); |
329 | b8076a74 | bellard | return 0; |
330 | b8076a74 | bellard | } |
331 | b8076a74 | bellard | return 1; |
332 | b8076a74 | bellard | } |
333 | b8076a74 | bellard | |
334 | b8076a74 | bellard | struct ia64_fixup {
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335 | b8076a74 | bellard | struct ia64_fixup *next;
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336 | b8076a74 | bellard | void *addr; /* address that needs to be patched */ |
337 | b8076a74 | bellard | long value;
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338 | b8076a74 | bellard | }; |
339 | b8076a74 | bellard | |
340 | b8076a74 | bellard | #define IA64_PLT(insn, plt_index) \
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341 | b8076a74 | bellard | do { \
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342 | b8076a74 | bellard | struct ia64_fixup *fixup = alloca(sizeof(*fixup)); \ |
343 | b8076a74 | bellard | fixup->next = plt_fixes; \ |
344 | b8076a74 | bellard | plt_fixes = fixup; \ |
345 | b8076a74 | bellard | fixup->addr = (insn); \ |
346 | b8076a74 | bellard | fixup->value = (plt_index); \ |
347 | b8076a74 | bellard | plt_offset[(plt_index)] = 1; \
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348 | b8076a74 | bellard | } while (0) |
349 | b8076a74 | bellard | |
350 | b8076a74 | bellard | #define IA64_LTOFF(insn, val, relaxable) \
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351 | b8076a74 | bellard | do { \
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352 | b8076a74 | bellard | if (ia64_patch_ltoff(insn, val, relaxable)) { \
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353 | b8076a74 | bellard | struct ia64_fixup *fixup = alloca(sizeof(*fixup)); \ |
354 | b8076a74 | bellard | fixup->next = ltoff_fixes; \ |
355 | b8076a74 | bellard | ltoff_fixes = fixup; \ |
356 | b8076a74 | bellard | fixup->addr = (insn); \ |
357 | b8076a74 | bellard | fixup->value = (val); \ |
358 | b8076a74 | bellard | } \ |
359 | b8076a74 | bellard | } while (0) |
360 | b8076a74 | bellard | |
361 | b8076a74 | bellard | static inline void ia64_apply_fixes (uint8_t **gen_code_pp, |
362 | b8076a74 | bellard | struct ia64_fixup *ltoff_fixes,
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363 | b8076a74 | bellard | uint64_t gp, |
364 | b8076a74 | bellard | struct ia64_fixup *plt_fixes,
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365 | b8076a74 | bellard | int num_plts,
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366 | b8076a74 | bellard | unsigned long *plt_target, |
367 | b8076a74 | bellard | unsigned int *plt_offset) |
368 | b8076a74 | bellard | { |
369 | b8076a74 | bellard | static const uint8_t plt_bundle[] = { |
370 | b8076a74 | bellard | 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; movl r1=GP */ |
371 | b8076a74 | bellard | 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x60, |
372 | b8076a74 | bellard | |
373 | b8076a74 | bellard | 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; brl IP */ |
374 | b8076a74 | bellard | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0 |
375 | b8076a74 | bellard | }; |
376 | b8076a74 | bellard | uint8_t *gen_code_ptr = *gen_code_pp, *plt_start, *got_start, *vp; |
377 | b8076a74 | bellard | struct ia64_fixup *fixup;
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378 | b8076a74 | bellard | unsigned int offset = 0; |
379 | b8076a74 | bellard | struct fdesc {
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380 | b8076a74 | bellard | long ip;
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381 | b8076a74 | bellard | long gp;
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382 | b8076a74 | bellard | } *fdesc; |
383 | b8076a74 | bellard | int i;
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384 | b8076a74 | bellard | |
385 | b8076a74 | bellard | if (plt_fixes) {
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386 | b8076a74 | bellard | plt_start = gen_code_ptr; |
387 | b8076a74 | bellard | |
388 | b8076a74 | bellard | for (i = 0; i < num_plts; ++i) { |
389 | b8076a74 | bellard | if (plt_offset[i]) {
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390 | b8076a74 | bellard | plt_offset[i] = offset; |
391 | b8076a74 | bellard | offset += sizeof(plt_bundle);
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392 | b8076a74 | bellard | |
393 | b8076a74 | bellard | fdesc = (struct fdesc *) plt_target[i];
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394 | b8076a74 | bellard | memcpy(gen_code_ptr, plt_bundle, sizeof(plt_bundle));
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395 | b8076a74 | bellard | ia64_imm64 (gen_code_ptr + 0x02, fdesc->gp);
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396 | b8076a74 | bellard | ia64_imm60b(gen_code_ptr + 0x12,
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397 | b8076a74 | bellard | (fdesc->ip - (long) (gen_code_ptr + 0x10)) >> 4); |
398 | b8076a74 | bellard | gen_code_ptr += sizeof(plt_bundle);
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399 | b8076a74 | bellard | } |
400 | b8076a74 | bellard | } |
401 | b8076a74 | bellard | |
402 | b8076a74 | bellard | for (fixup = plt_fixes; fixup; fixup = fixup->next)
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403 | b8076a74 | bellard | ia64_imm21b(fixup->addr, |
404 | b8076a74 | bellard | ((long) plt_start + plt_offset[fixup->value]
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405 | b8076a74 | bellard | - ((long) fixup->addr & ~0xf)) >> 4); |
406 | b8076a74 | bellard | } |
407 | b8076a74 | bellard | |
408 | b8076a74 | bellard | got_start = gen_code_ptr; |
409 | b8076a74 | bellard | |
410 | b8076a74 | bellard | /* First, create the GOT: */
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411 | b8076a74 | bellard | for (fixup = ltoff_fixes; fixup; fixup = fixup->next) {
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412 | b8076a74 | bellard | /* first check if we already have this value in the GOT: */
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413 | b8076a74 | bellard | for (vp = got_start; vp < gen_code_ptr; ++vp)
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414 | b8076a74 | bellard | if (*(uint64_t *) vp == fixup->value)
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415 | b8076a74 | bellard | break;
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416 | b8076a74 | bellard | if (vp == gen_code_ptr) {
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417 | b8076a74 | bellard | /* Nope, we need to put the value in the GOT: */
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418 | b8076a74 | bellard | *(uint64_t *) vp = fixup->value; |
419 | b8076a74 | bellard | gen_code_ptr += 8;
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420 | b8076a74 | bellard | } |
421 | b8076a74 | bellard | ia64_imm22(fixup->addr, (long) vp - gp);
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422 | b8076a74 | bellard | } |
423 | b8076a74 | bellard | *gen_code_pp = gen_code_ptr; |
424 | b8076a74 | bellard | } |
425 | b8076a74 | bellard | |
426 | b8076a74 | bellard | #endif |