root / hw / m48t59.c @ f68c781c
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1 | a541f297 | bellard | /*
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2 | a541f297 | bellard | * QEMU M48T59 NVRAM emulation for PPC PREP platform
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3 | a541f297 | bellard | *
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4 | a541f297 | bellard | * Copyright (c) 2003-2004 Jocelyn Mayer
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5 | a541f297 | bellard | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | a541f297 | bellard | */
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24 | a541f297 | bellard | #include "vl.h" |
25 | c5df018e | bellard | #include "m48t59.h" |
26 | a541f297 | bellard | |
27 | 13ab5daa | bellard | //#define DEBUG_NVRAM
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28 | a541f297 | bellard | |
29 | 13ab5daa | bellard | #if defined(DEBUG_NVRAM)
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30 | a541f297 | bellard | #define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0) |
31 | a541f297 | bellard | #else
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32 | a541f297 | bellard | #define NVRAM_PRINTF(fmt, args...) do { } while (0) |
33 | a541f297 | bellard | #endif
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34 | a541f297 | bellard | |
35 | c5df018e | bellard | struct m48t59_t {
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36 | a541f297 | bellard | /* Hardware parameters */
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37 | a541f297 | bellard | int IRQ;
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38 | e1bb04f7 | bellard | int mem_index;
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39 | e1bb04f7 | bellard | uint32_t mem_base; |
40 | a541f297 | bellard | uint32_t io_base; |
41 | a541f297 | bellard | uint16_t size; |
42 | a541f297 | bellard | /* RTC management */
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43 | a541f297 | bellard | time_t time_offset; |
44 | a541f297 | bellard | time_t stop_time; |
45 | a541f297 | bellard | /* Alarm & watchdog */
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46 | a541f297 | bellard | time_t alarm; |
47 | a541f297 | bellard | struct QEMUTimer *alrm_timer;
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48 | a541f297 | bellard | struct QEMUTimer *wd_timer;
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49 | a541f297 | bellard | /* NVRAM storage */
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50 | 13ab5daa | bellard | uint8_t lock; |
51 | a541f297 | bellard | uint16_t addr; |
52 | a541f297 | bellard | uint8_t *buffer; |
53 | c5df018e | bellard | }; |
54 | a541f297 | bellard | |
55 | a541f297 | bellard | /* Fake timer functions */
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56 | a541f297 | bellard | /* Generic helpers for BCD */
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57 | a541f297 | bellard | static inline uint8_t toBCD (uint8_t value) |
58 | a541f297 | bellard | { |
59 | a541f297 | bellard | return (((value / 10) % 10) << 4) | (value % 10); |
60 | a541f297 | bellard | } |
61 | a541f297 | bellard | |
62 | a541f297 | bellard | static inline uint8_t fromBCD (uint8_t BCD) |
63 | a541f297 | bellard | { |
64 | a541f297 | bellard | return ((BCD >> 4) * 10) + (BCD & 0x0F); |
65 | a541f297 | bellard | } |
66 | a541f297 | bellard | |
67 | a541f297 | bellard | /* RTC management helpers */
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68 | a541f297 | bellard | static void get_time (m48t59_t *NVRAM, struct tm *tm) |
69 | a541f297 | bellard | { |
70 | a541f297 | bellard | time_t t; |
71 | a541f297 | bellard | |
72 | a541f297 | bellard | t = time(NULL) + NVRAM->time_offset;
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73 | d157e205 | bellard | #ifdef _WIN32
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74 | d157e205 | bellard | memcpy(tm,localtime(&t),sizeof(*tm));
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75 | d157e205 | bellard | #else
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76 | d157e205 | bellard | localtime_r (&t, tm) ; |
77 | d157e205 | bellard | #endif
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78 | a541f297 | bellard | } |
79 | a541f297 | bellard | |
80 | a541f297 | bellard | static void set_time (m48t59_t *NVRAM, struct tm *tm) |
81 | a541f297 | bellard | { |
82 | a541f297 | bellard | time_t now, new_time; |
83 | a541f297 | bellard | |
84 | a541f297 | bellard | new_time = mktime(tm); |
85 | a541f297 | bellard | now = time(NULL);
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86 | a541f297 | bellard | NVRAM->time_offset = new_time - now; |
87 | a541f297 | bellard | } |
88 | a541f297 | bellard | |
89 | a541f297 | bellard | /* Alarm management */
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90 | a541f297 | bellard | static void alarm_cb (void *opaque) |
91 | a541f297 | bellard | { |
92 | a541f297 | bellard | struct tm tm, tm_now;
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93 | a541f297 | bellard | uint64_t next_time; |
94 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
95 | a541f297 | bellard | |
96 | a541f297 | bellard | pic_set_irq(NVRAM->IRQ, 1);
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97 | a541f297 | bellard | if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
98 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
99 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
100 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
101 | a541f297 | bellard | /* Repeat once a month */
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102 | a541f297 | bellard | get_time(NVRAM, &tm_now); |
103 | a541f297 | bellard | memcpy(&tm, &tm_now, sizeof(struct tm)); |
104 | a541f297 | bellard | tm.tm_mon++; |
105 | a541f297 | bellard | if (tm.tm_mon == 13) { |
106 | a541f297 | bellard | tm.tm_mon = 1;
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107 | a541f297 | bellard | tm.tm_year++; |
108 | a541f297 | bellard | } |
109 | a541f297 | bellard | next_time = mktime(&tm); |
110 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
111 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
112 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
113 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
114 | a541f297 | bellard | /* Repeat once a day */
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115 | a541f297 | bellard | next_time = 24 * 60 * 60 + mktime(&tm_now); |
116 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
117 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
118 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
119 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
120 | a541f297 | bellard | /* Repeat once an hour */
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121 | a541f297 | bellard | next_time = 60 * 60 + mktime(&tm_now); |
122 | a541f297 | bellard | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
123 | a541f297 | bellard | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
124 | a541f297 | bellard | (NVRAM->buffer[0x1FF3] & 0x80) != 0 && |
125 | a541f297 | bellard | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
126 | a541f297 | bellard | /* Repeat once a minute */
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127 | a541f297 | bellard | next_time = 60 + mktime(&tm_now);
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128 | a541f297 | bellard | } else {
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129 | a541f297 | bellard | /* Repeat once a second */
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130 | a541f297 | bellard | next_time = 1 + mktime(&tm_now);
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131 | a541f297 | bellard | } |
132 | a541f297 | bellard | qemu_mod_timer(NVRAM->alrm_timer, next_time * 1000);
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133 | a541f297 | bellard | pic_set_irq(NVRAM->IRQ, 0);
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134 | a541f297 | bellard | } |
135 | a541f297 | bellard | |
136 | a541f297 | bellard | |
137 | a541f297 | bellard | static void get_alarm (m48t59_t *NVRAM, struct tm *tm) |
138 | a541f297 | bellard | { |
139 | d157e205 | bellard | #ifdef _WIN32
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140 | d157e205 | bellard | memcpy(tm,localtime(&NVRAM->alarm),sizeof(*tm));
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141 | d157e205 | bellard | #else
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142 | d157e205 | bellard | localtime_r (&NVRAM->alarm, tm); |
143 | d157e205 | bellard | #endif
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144 | a541f297 | bellard | } |
145 | a541f297 | bellard | |
146 | a541f297 | bellard | static void set_alarm (m48t59_t *NVRAM, struct tm *tm) |
147 | a541f297 | bellard | { |
148 | a541f297 | bellard | NVRAM->alarm = mktime(tm); |
149 | a541f297 | bellard | if (NVRAM->alrm_timer != NULL) { |
150 | a541f297 | bellard | qemu_del_timer(NVRAM->alrm_timer); |
151 | a541f297 | bellard | NVRAM->alrm_timer = NULL;
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152 | a541f297 | bellard | } |
153 | a541f297 | bellard | if (NVRAM->alarm - time(NULL) > 0) |
154 | a541f297 | bellard | qemu_mod_timer(NVRAM->alrm_timer, NVRAM->alarm * 1000);
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155 | a541f297 | bellard | } |
156 | a541f297 | bellard | |
157 | a541f297 | bellard | /* Watchdog management */
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158 | a541f297 | bellard | static void watchdog_cb (void *opaque) |
159 | a541f297 | bellard | { |
160 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
161 | a541f297 | bellard | |
162 | a541f297 | bellard | NVRAM->buffer[0x1FF0] |= 0x80; |
163 | a541f297 | bellard | if (NVRAM->buffer[0x1FF7] & 0x80) { |
164 | a541f297 | bellard | NVRAM->buffer[0x1FF7] = 0x00; |
165 | a541f297 | bellard | NVRAM->buffer[0x1FFC] &= ~0x40; |
166 | 13ab5daa | bellard | /* May it be a hw CPU Reset instead ? */
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167 | d7d02e3c | bellard | qemu_system_reset_request(); |
168 | a541f297 | bellard | } else {
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169 | a541f297 | bellard | pic_set_irq(NVRAM->IRQ, 1);
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170 | a541f297 | bellard | pic_set_irq(NVRAM->IRQ, 0);
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171 | a541f297 | bellard | } |
172 | a541f297 | bellard | } |
173 | a541f297 | bellard | |
174 | a541f297 | bellard | static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value) |
175 | a541f297 | bellard | { |
176 | a541f297 | bellard | uint64_t interval; /* in 1/16 seconds */
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177 | a541f297 | bellard | |
178 | a541f297 | bellard | if (NVRAM->wd_timer != NULL) { |
179 | a541f297 | bellard | qemu_del_timer(NVRAM->wd_timer); |
180 | a541f297 | bellard | NVRAM->wd_timer = NULL;
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181 | a541f297 | bellard | } |
182 | a541f297 | bellard | NVRAM->buffer[0x1FF0] &= ~0x80; |
183 | a541f297 | bellard | if (value != 0) { |
184 | a541f297 | bellard | interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); |
185 | a541f297 | bellard | qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + |
186 | a541f297 | bellard | ((interval * 1000) >> 4)); |
187 | a541f297 | bellard | } |
188 | a541f297 | bellard | } |
189 | a541f297 | bellard | |
190 | a541f297 | bellard | /* Direct access to NVRAM */
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191 | c5df018e | bellard | void m48t59_write (m48t59_t *NVRAM, uint32_t val)
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192 | a541f297 | bellard | { |
193 | a541f297 | bellard | struct tm tm;
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194 | a541f297 | bellard | int tmp;
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195 | a541f297 | bellard | |
196 | a541f297 | bellard | if (NVRAM->addr > 0x1FF8 && NVRAM->addr < 0x2000) |
197 | a541f297 | bellard | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, NVRAM->addr, val);
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198 | a541f297 | bellard | switch (NVRAM->addr) {
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199 | a541f297 | bellard | case 0x1FF0: |
200 | a541f297 | bellard | /* flags register : read-only */
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201 | a541f297 | bellard | break;
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202 | a541f297 | bellard | case 0x1FF1: |
203 | a541f297 | bellard | /* unused */
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204 | a541f297 | bellard | break;
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205 | a541f297 | bellard | case 0x1FF2: |
206 | a541f297 | bellard | /* alarm seconds */
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207 | a541f297 | bellard | tmp = fromBCD(val & 0x7F);
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208 | a541f297 | bellard | if (tmp >= 0 && tmp <= 59) { |
209 | a541f297 | bellard | get_alarm(NVRAM, &tm); |
210 | a541f297 | bellard | tm.tm_sec = tmp; |
211 | a541f297 | bellard | NVRAM->buffer[0x1FF2] = val;
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212 | a541f297 | bellard | set_alarm(NVRAM, &tm); |
213 | a541f297 | bellard | } |
214 | a541f297 | bellard | break;
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215 | a541f297 | bellard | case 0x1FF3: |
216 | a541f297 | bellard | /* alarm minutes */
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217 | a541f297 | bellard | tmp = fromBCD(val & 0x7F);
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218 | a541f297 | bellard | if (tmp >= 0 && tmp <= 59) { |
219 | a541f297 | bellard | get_alarm(NVRAM, &tm); |
220 | a541f297 | bellard | tm.tm_min = tmp; |
221 | a541f297 | bellard | NVRAM->buffer[0x1FF3] = val;
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222 | a541f297 | bellard | set_alarm(NVRAM, &tm); |
223 | a541f297 | bellard | } |
224 | a541f297 | bellard | break;
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225 | a541f297 | bellard | case 0x1FF4: |
226 | a541f297 | bellard | /* alarm hours */
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227 | a541f297 | bellard | tmp = fromBCD(val & 0x3F);
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228 | a541f297 | bellard | if (tmp >= 0 && tmp <= 23) { |
229 | a541f297 | bellard | get_alarm(NVRAM, &tm); |
230 | a541f297 | bellard | tm.tm_hour = tmp; |
231 | a541f297 | bellard | NVRAM->buffer[0x1FF4] = val;
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232 | a541f297 | bellard | set_alarm(NVRAM, &tm); |
233 | a541f297 | bellard | } |
234 | a541f297 | bellard | break;
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235 | a541f297 | bellard | case 0x1FF5: |
236 | a541f297 | bellard | /* alarm date */
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237 | a541f297 | bellard | tmp = fromBCD(val & 0x1F);
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238 | a541f297 | bellard | if (tmp != 0) { |
239 | a541f297 | bellard | get_alarm(NVRAM, &tm); |
240 | a541f297 | bellard | tm.tm_mday = tmp; |
241 | a541f297 | bellard | NVRAM->buffer[0x1FF5] = val;
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242 | a541f297 | bellard | set_alarm(NVRAM, &tm); |
243 | a541f297 | bellard | } |
244 | a541f297 | bellard | break;
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245 | a541f297 | bellard | case 0x1FF6: |
246 | a541f297 | bellard | /* interrupts */
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247 | a541f297 | bellard | NVRAM->buffer[0x1FF6] = val;
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248 | a541f297 | bellard | break;
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249 | a541f297 | bellard | case 0x1FF7: |
250 | a541f297 | bellard | /* watchdog */
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251 | a541f297 | bellard | NVRAM->buffer[0x1FF7] = val;
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252 | a541f297 | bellard | set_up_watchdog(NVRAM, val); |
253 | a541f297 | bellard | break;
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254 | a541f297 | bellard | case 0x1FF8: |
255 | a541f297 | bellard | /* control */
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256 | a541f297 | bellard | NVRAM->buffer[0x1FF8] = (val & ~0xA0) | 0x90; |
257 | a541f297 | bellard | break;
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258 | a541f297 | bellard | case 0x1FF9: |
259 | a541f297 | bellard | /* seconds (BCD) */
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260 | a541f297 | bellard | tmp = fromBCD(val & 0x7F);
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261 | a541f297 | bellard | if (tmp >= 0 && tmp <= 59) { |
262 | a541f297 | bellard | get_time(NVRAM, &tm); |
263 | a541f297 | bellard | tm.tm_sec = tmp; |
264 | a541f297 | bellard | set_time(NVRAM, &tm); |
265 | a541f297 | bellard | } |
266 | a541f297 | bellard | if ((val & 0x80) ^ (NVRAM->buffer[0x1FF9] & 0x80)) { |
267 | a541f297 | bellard | if (val & 0x80) { |
268 | a541f297 | bellard | NVRAM->stop_time = time(NULL);
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269 | a541f297 | bellard | } else {
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270 | a541f297 | bellard | NVRAM->time_offset += NVRAM->stop_time - time(NULL);
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271 | a541f297 | bellard | NVRAM->stop_time = 0;
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272 | a541f297 | bellard | } |
273 | a541f297 | bellard | } |
274 | a541f297 | bellard | NVRAM->buffer[0x1FF9] = val & 0x80; |
275 | a541f297 | bellard | break;
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276 | a541f297 | bellard | case 0x1FFA: |
277 | a541f297 | bellard | /* minutes (BCD) */
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278 | a541f297 | bellard | tmp = fromBCD(val & 0x7F);
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279 | a541f297 | bellard | if (tmp >= 0 && tmp <= 59) { |
280 | a541f297 | bellard | get_time(NVRAM, &tm); |
281 | a541f297 | bellard | tm.tm_min = tmp; |
282 | a541f297 | bellard | set_time(NVRAM, &tm); |
283 | a541f297 | bellard | } |
284 | a541f297 | bellard | break;
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285 | a541f297 | bellard | case 0x1FFB: |
286 | a541f297 | bellard | /* hours (BCD) */
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287 | a541f297 | bellard | tmp = fromBCD(val & 0x3F);
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288 | a541f297 | bellard | if (tmp >= 0 && tmp <= 23) { |
289 | a541f297 | bellard | get_time(NVRAM, &tm); |
290 | a541f297 | bellard | tm.tm_hour = tmp; |
291 | a541f297 | bellard | set_time(NVRAM, &tm); |
292 | a541f297 | bellard | } |
293 | a541f297 | bellard | break;
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294 | a541f297 | bellard | case 0x1FFC: |
295 | a541f297 | bellard | /* day of the week / century */
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296 | a541f297 | bellard | tmp = fromBCD(val & 0x07);
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297 | a541f297 | bellard | get_time(NVRAM, &tm); |
298 | a541f297 | bellard | tm.tm_wday = tmp; |
299 | a541f297 | bellard | set_time(NVRAM, &tm); |
300 | a541f297 | bellard | NVRAM->buffer[0x1FFC] = val & 0x40; |
301 | a541f297 | bellard | break;
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302 | a541f297 | bellard | case 0x1FFD: |
303 | a541f297 | bellard | /* date */
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304 | a541f297 | bellard | tmp = fromBCD(val & 0x1F);
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305 | a541f297 | bellard | if (tmp != 0) { |
306 | a541f297 | bellard | get_time(NVRAM, &tm); |
307 | a541f297 | bellard | tm.tm_mday = tmp; |
308 | a541f297 | bellard | set_time(NVRAM, &tm); |
309 | a541f297 | bellard | } |
310 | a541f297 | bellard | break;
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311 | a541f297 | bellard | case 0x1FFE: |
312 | a541f297 | bellard | /* month */
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313 | a541f297 | bellard | tmp = fromBCD(val & 0x1F);
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314 | a541f297 | bellard | if (tmp >= 1 && tmp <= 12) { |
315 | a541f297 | bellard | get_time(NVRAM, &tm); |
316 | a541f297 | bellard | tm.tm_mon = tmp - 1;
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317 | a541f297 | bellard | set_time(NVRAM, &tm); |
318 | a541f297 | bellard | } |
319 | a541f297 | bellard | break;
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320 | a541f297 | bellard | case 0x1FFF: |
321 | a541f297 | bellard | /* year */
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322 | a541f297 | bellard | tmp = fromBCD(val); |
323 | a541f297 | bellard | if (tmp >= 0 && tmp <= 99) { |
324 | a541f297 | bellard | get_time(NVRAM, &tm); |
325 | a541f297 | bellard | tm.tm_year = fromBCD(val); |
326 | a541f297 | bellard | set_time(NVRAM, &tm); |
327 | a541f297 | bellard | } |
328 | a541f297 | bellard | break;
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329 | a541f297 | bellard | default:
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330 | 13ab5daa | bellard | /* Check lock registers state */
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331 | 13ab5daa | bellard | if (NVRAM->addr >= 0x20 && NVRAM->addr <= 0x2F && (NVRAM->lock & 1)) |
332 | 13ab5daa | bellard | break;
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333 | 13ab5daa | bellard | if (NVRAM->addr >= 0x30 && NVRAM->addr <= 0x3F && (NVRAM->lock & 2)) |
334 | 13ab5daa | bellard | break;
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335 | a541f297 | bellard | if (NVRAM->addr < 0x1FF0 || |
336 | a541f297 | bellard | (NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
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337 | a541f297 | bellard | NVRAM->buffer[NVRAM->addr] = val & 0xFF;
|
338 | a541f297 | bellard | } |
339 | a541f297 | bellard | break;
|
340 | a541f297 | bellard | } |
341 | a541f297 | bellard | } |
342 | a541f297 | bellard | |
343 | c5df018e | bellard | uint32_t m48t59_read (m48t59_t *NVRAM) |
344 | a541f297 | bellard | { |
345 | a541f297 | bellard | struct tm tm;
|
346 | a541f297 | bellard | uint32_t retval = 0xFF;
|
347 | a541f297 | bellard | |
348 | a541f297 | bellard | switch (NVRAM->addr) {
|
349 | a541f297 | bellard | case 0x1FF0: |
350 | a541f297 | bellard | /* flags register */
|
351 | a541f297 | bellard | goto do_read;
|
352 | a541f297 | bellard | case 0x1FF1: |
353 | a541f297 | bellard | /* unused */
|
354 | a541f297 | bellard | retval = 0;
|
355 | a541f297 | bellard | break;
|
356 | a541f297 | bellard | case 0x1FF2: |
357 | a541f297 | bellard | /* alarm seconds */
|
358 | a541f297 | bellard | goto do_read;
|
359 | a541f297 | bellard | case 0x1FF3: |
360 | a541f297 | bellard | /* alarm minutes */
|
361 | a541f297 | bellard | goto do_read;
|
362 | a541f297 | bellard | case 0x1FF4: |
363 | a541f297 | bellard | /* alarm hours */
|
364 | a541f297 | bellard | goto do_read;
|
365 | a541f297 | bellard | case 0x1FF5: |
366 | a541f297 | bellard | /* alarm date */
|
367 | a541f297 | bellard | goto do_read;
|
368 | a541f297 | bellard | case 0x1FF6: |
369 | a541f297 | bellard | /* interrupts */
|
370 | a541f297 | bellard | goto do_read;
|
371 | a541f297 | bellard | case 0x1FF7: |
372 | a541f297 | bellard | /* A read resets the watchdog */
|
373 | a541f297 | bellard | set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
|
374 | a541f297 | bellard | goto do_read;
|
375 | a541f297 | bellard | case 0x1FF8: |
376 | a541f297 | bellard | /* control */
|
377 | a541f297 | bellard | goto do_read;
|
378 | a541f297 | bellard | case 0x1FF9: |
379 | a541f297 | bellard | /* seconds (BCD) */
|
380 | a541f297 | bellard | get_time(NVRAM, &tm); |
381 | a541f297 | bellard | retval = (NVRAM->buffer[0x1FF9] & 0x80) | toBCD(tm.tm_sec); |
382 | a541f297 | bellard | break;
|
383 | a541f297 | bellard | case 0x1FFA: |
384 | a541f297 | bellard | /* minutes (BCD) */
|
385 | a541f297 | bellard | get_time(NVRAM, &tm); |
386 | a541f297 | bellard | retval = toBCD(tm.tm_min); |
387 | a541f297 | bellard | break;
|
388 | a541f297 | bellard | case 0x1FFB: |
389 | a541f297 | bellard | /* hours (BCD) */
|
390 | a541f297 | bellard | get_time(NVRAM, &tm); |
391 | a541f297 | bellard | retval = toBCD(tm.tm_hour); |
392 | a541f297 | bellard | break;
|
393 | a541f297 | bellard | case 0x1FFC: |
394 | a541f297 | bellard | /* day of the week / century */
|
395 | a541f297 | bellard | get_time(NVRAM, &tm); |
396 | a541f297 | bellard | retval = NVRAM->buffer[0x1FFC] | tm.tm_wday;
|
397 | a541f297 | bellard | break;
|
398 | a541f297 | bellard | case 0x1FFD: |
399 | a541f297 | bellard | /* date */
|
400 | a541f297 | bellard | get_time(NVRAM, &tm); |
401 | a541f297 | bellard | retval = toBCD(tm.tm_mday); |
402 | a541f297 | bellard | break;
|
403 | a541f297 | bellard | case 0x1FFE: |
404 | a541f297 | bellard | /* month */
|
405 | a541f297 | bellard | get_time(NVRAM, &tm); |
406 | a541f297 | bellard | retval = toBCD(tm.tm_mon + 1);
|
407 | a541f297 | bellard | break;
|
408 | a541f297 | bellard | case 0x1FFF: |
409 | a541f297 | bellard | /* year */
|
410 | a541f297 | bellard | get_time(NVRAM, &tm); |
411 | a541f297 | bellard | retval = toBCD(tm.tm_year); |
412 | a541f297 | bellard | break;
|
413 | a541f297 | bellard | default:
|
414 | 13ab5daa | bellard | /* Check lock registers state */
|
415 | 13ab5daa | bellard | if (NVRAM->addr >= 0x20 && NVRAM->addr <= 0x2F && (NVRAM->lock & 1)) |
416 | 13ab5daa | bellard | break;
|
417 | 13ab5daa | bellard | if (NVRAM->addr >= 0x30 && NVRAM->addr <= 0x3F && (NVRAM->lock & 2)) |
418 | 13ab5daa | bellard | break;
|
419 | a541f297 | bellard | if (NVRAM->addr < 0x1FF0 || |
420 | a541f297 | bellard | (NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
|
421 | a541f297 | bellard | do_read:
|
422 | a541f297 | bellard | retval = NVRAM->buffer[NVRAM->addr]; |
423 | a541f297 | bellard | } |
424 | a541f297 | bellard | break;
|
425 | a541f297 | bellard | } |
426 | a541f297 | bellard | if (NVRAM->addr > 0x1FF9 && NVRAM->addr < 0x2000) |
427 | a541f297 | bellard | NVRAM_PRINTF("0x%08x <= 0x%08x\n", NVRAM->addr, retval);
|
428 | a541f297 | bellard | |
429 | a541f297 | bellard | return retval;
|
430 | a541f297 | bellard | } |
431 | a541f297 | bellard | |
432 | c5df018e | bellard | void m48t59_set_addr (m48t59_t *NVRAM, uint32_t addr)
|
433 | a541f297 | bellard | { |
434 | a541f297 | bellard | NVRAM->addr = addr; |
435 | a541f297 | bellard | } |
436 | a541f297 | bellard | |
437 | 13ab5daa | bellard | void m48t59_toggle_lock (m48t59_t *NVRAM, int lock) |
438 | 13ab5daa | bellard | { |
439 | 13ab5daa | bellard | NVRAM->lock ^= 1 << lock;
|
440 | 13ab5daa | bellard | } |
441 | 13ab5daa | bellard | |
442 | a541f297 | bellard | /* IO access to NVRAM */
|
443 | a541f297 | bellard | static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val) |
444 | a541f297 | bellard | { |
445 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
446 | a541f297 | bellard | |
447 | a541f297 | bellard | addr -= NVRAM->io_base; |
448 | 13ab5daa | bellard | NVRAM_PRINTF("0x%08x => 0x%08x\n", addr, val);
|
449 | a541f297 | bellard | switch (addr) {
|
450 | a541f297 | bellard | case 0: |
451 | a541f297 | bellard | NVRAM->addr &= ~0x00FF;
|
452 | a541f297 | bellard | NVRAM->addr |= val; |
453 | a541f297 | bellard | break;
|
454 | a541f297 | bellard | case 1: |
455 | a541f297 | bellard | NVRAM->addr &= ~0xFF00;
|
456 | a541f297 | bellard | NVRAM->addr |= val << 8;
|
457 | a541f297 | bellard | break;
|
458 | a541f297 | bellard | case 3: |
459 | a541f297 | bellard | m48t59_write(NVRAM, val); |
460 | a541f297 | bellard | NVRAM->addr = 0x0000;
|
461 | a541f297 | bellard | break;
|
462 | a541f297 | bellard | default:
|
463 | a541f297 | bellard | break;
|
464 | a541f297 | bellard | } |
465 | a541f297 | bellard | } |
466 | a541f297 | bellard | |
467 | a541f297 | bellard | static uint32_t NVRAM_readb (void *opaque, uint32_t addr) |
468 | a541f297 | bellard | { |
469 | a541f297 | bellard | m48t59_t *NVRAM = opaque; |
470 | 13ab5daa | bellard | uint32_t retval; |
471 | a541f297 | bellard | |
472 | 13ab5daa | bellard | addr -= NVRAM->io_base; |
473 | 13ab5daa | bellard | switch (addr) {
|
474 | 13ab5daa | bellard | case 3: |
475 | 13ab5daa | bellard | retval = m48t59_read(NVRAM); |
476 | 13ab5daa | bellard | break;
|
477 | 13ab5daa | bellard | default:
|
478 | 13ab5daa | bellard | retval = -1;
|
479 | 13ab5daa | bellard | break;
|
480 | 13ab5daa | bellard | } |
481 | 13ab5daa | bellard | NVRAM_PRINTF("0x%08x <= 0x%08x\n", addr, retval);
|
482 | a541f297 | bellard | |
483 | 13ab5daa | bellard | return retval;
|
484 | a541f297 | bellard | } |
485 | a541f297 | bellard | |
486 | e1bb04f7 | bellard | static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
487 | e1bb04f7 | bellard | { |
488 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
489 | e1bb04f7 | bellard | |
490 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
491 | e1bb04f7 | bellard | if (addr < 0x1FF0) |
492 | e1bb04f7 | bellard | NVRAM->buffer[addr] = value; |
493 | e1bb04f7 | bellard | } |
494 | e1bb04f7 | bellard | |
495 | e1bb04f7 | bellard | static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
496 | e1bb04f7 | bellard | { |
497 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
498 | e1bb04f7 | bellard | |
499 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
500 | e1bb04f7 | bellard | if (addr < 0x1FF0) { |
501 | e1bb04f7 | bellard | NVRAM->buffer[addr] = value >> 8;
|
502 | e1bb04f7 | bellard | NVRAM->buffer[addr + 1] = value;
|
503 | e1bb04f7 | bellard | } |
504 | e1bb04f7 | bellard | } |
505 | e1bb04f7 | bellard | |
506 | e1bb04f7 | bellard | static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
507 | e1bb04f7 | bellard | { |
508 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
509 | e1bb04f7 | bellard | |
510 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
511 | e1bb04f7 | bellard | if (addr < 0x1FF0) { |
512 | e1bb04f7 | bellard | NVRAM->buffer[addr] = value >> 24;
|
513 | e1bb04f7 | bellard | NVRAM->buffer[addr + 1] = value >> 16; |
514 | e1bb04f7 | bellard | NVRAM->buffer[addr + 2] = value >> 8; |
515 | e1bb04f7 | bellard | NVRAM->buffer[addr + 3] = value;
|
516 | e1bb04f7 | bellard | } |
517 | e1bb04f7 | bellard | } |
518 | e1bb04f7 | bellard | |
519 | e1bb04f7 | bellard | static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) |
520 | e1bb04f7 | bellard | { |
521 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
522 | e1bb04f7 | bellard | uint32_t retval = 0;
|
523 | e1bb04f7 | bellard | |
524 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
525 | e1bb04f7 | bellard | if (addr < 0x1FF0) |
526 | e1bb04f7 | bellard | retval = NVRAM->buffer[addr]; |
527 | e1bb04f7 | bellard | |
528 | e1bb04f7 | bellard | return retval;
|
529 | e1bb04f7 | bellard | } |
530 | e1bb04f7 | bellard | |
531 | e1bb04f7 | bellard | static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) |
532 | e1bb04f7 | bellard | { |
533 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
534 | e1bb04f7 | bellard | uint32_t retval = 0;
|
535 | e1bb04f7 | bellard | |
536 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
537 | e1bb04f7 | bellard | if (addr < 0x1FF0) { |
538 | e1bb04f7 | bellard | retval = NVRAM->buffer[addr] << 8;
|
539 | e1bb04f7 | bellard | retval |= NVRAM->buffer[addr + 1];
|
540 | e1bb04f7 | bellard | } |
541 | e1bb04f7 | bellard | |
542 | e1bb04f7 | bellard | return retval;
|
543 | e1bb04f7 | bellard | } |
544 | e1bb04f7 | bellard | |
545 | e1bb04f7 | bellard | static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) |
546 | e1bb04f7 | bellard | { |
547 | e1bb04f7 | bellard | m48t59_t *NVRAM = opaque; |
548 | e1bb04f7 | bellard | uint32_t retval = 0;
|
549 | e1bb04f7 | bellard | |
550 | e1bb04f7 | bellard | addr -= NVRAM->mem_base; |
551 | e1bb04f7 | bellard | if (addr < 0x1FF0) { |
552 | e1bb04f7 | bellard | retval = NVRAM->buffer[addr] << 24;
|
553 | e1bb04f7 | bellard | retval |= NVRAM->buffer[addr + 1] << 16; |
554 | e1bb04f7 | bellard | retval |= NVRAM->buffer[addr + 2] << 8; |
555 | e1bb04f7 | bellard | retval |= NVRAM->buffer[addr + 3];
|
556 | e1bb04f7 | bellard | } |
557 | e1bb04f7 | bellard | |
558 | e1bb04f7 | bellard | return retval;
|
559 | e1bb04f7 | bellard | } |
560 | e1bb04f7 | bellard | |
561 | e1bb04f7 | bellard | static CPUWriteMemoryFunc *nvram_write[] = {
|
562 | e1bb04f7 | bellard | &nvram_writeb, |
563 | e1bb04f7 | bellard | &nvram_writew, |
564 | e1bb04f7 | bellard | &nvram_writel, |
565 | e1bb04f7 | bellard | }; |
566 | e1bb04f7 | bellard | |
567 | e1bb04f7 | bellard | static CPUReadMemoryFunc *nvram_read[] = {
|
568 | e1bb04f7 | bellard | &nvram_readb, |
569 | e1bb04f7 | bellard | &nvram_readw, |
570 | e1bb04f7 | bellard | &nvram_readl, |
571 | e1bb04f7 | bellard | }; |
572 | a541f297 | bellard | /* Initialisation routine */
|
573 | e1bb04f7 | bellard | m48t59_t *m48t59_init (int IRQ, uint32_t mem_base,
|
574 | e1bb04f7 | bellard | uint32_t io_base, uint16_t size) |
575 | a541f297 | bellard | { |
576 | c5df018e | bellard | m48t59_t *s; |
577 | a541f297 | bellard | |
578 | c5df018e | bellard | s = qemu_mallocz(sizeof(m48t59_t));
|
579 | c5df018e | bellard | if (!s)
|
580 | a541f297 | bellard | return NULL; |
581 | c5df018e | bellard | s->buffer = qemu_mallocz(size); |
582 | c5df018e | bellard | if (!s->buffer) {
|
583 | c5df018e | bellard | qemu_free(s); |
584 | c5df018e | bellard | return NULL; |
585 | c5df018e | bellard | } |
586 | c5df018e | bellard | s->IRQ = IRQ; |
587 | c5df018e | bellard | s->size = size; |
588 | e1bb04f7 | bellard | s->mem_base = mem_base; |
589 | c5df018e | bellard | s->io_base = io_base; |
590 | c5df018e | bellard | s->addr = 0;
|
591 | c5df018e | bellard | register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s); |
592 | c5df018e | bellard | register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s); |
593 | e1bb04f7 | bellard | if (mem_base != 0) { |
594 | e1bb04f7 | bellard | s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
|
595 | e1bb04f7 | bellard | cpu_register_physical_memory(mem_base, 0x4000, s->mem_index);
|
596 | e1bb04f7 | bellard | } |
597 | c5df018e | bellard | s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s); |
598 | c5df018e | bellard | s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s); |
599 | 13ab5daa | bellard | s->lock = 0;
|
600 | 13ab5daa | bellard | |
601 | c5df018e | bellard | return s;
|
602 | a541f297 | bellard | } |