root / hw / etraxfs_eth.c @ f6953f13
History | View | Annotate | Download (13.1 kB)
| 1 |
/*
|
|---|---|
| 2 |
* QEMU ETRAX Ethernet Controller.
|
| 3 |
*
|
| 4 |
* Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
|
| 5 |
*
|
| 6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
| 7 |
* of this software and associated documentation files (the "Software"), to deal
|
| 8 |
* in the Software without restriction, including without limitation the rights
|
| 9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
| 10 |
* copies of the Software, and to permit persons to whom the Software is
|
| 11 |
* furnished to do so, subject to the following conditions:
|
| 12 |
*
|
| 13 |
* The above copyright notice and this permission notice shall be included in
|
| 14 |
* all copies or substantial portions of the Software.
|
| 15 |
*
|
| 16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
| 17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
| 18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
| 19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
| 20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
| 21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
| 22 |
* THE SOFTWARE.
|
| 23 |
*/
|
| 24 |
|
| 25 |
#include <stdio.h> |
| 26 |
#include "hw.h" |
| 27 |
#include "net.h" |
| 28 |
|
| 29 |
#include "etraxfs_dma.h" |
| 30 |
|
| 31 |
#define D(x)
|
| 32 |
|
| 33 |
/*
|
| 34 |
* The MDIO extensions in the TDK PHY model were reversed engineered from the
|
| 35 |
* linux driver (PHYID and Diagnostics reg).
|
| 36 |
* TODO: Add friendly names for the register nums.
|
| 37 |
*/
|
| 38 |
struct qemu_phy
|
| 39 |
{
|
| 40 |
uint32_t regs[32];
|
| 41 |
|
| 42 |
unsigned int (*read)(struct qemu_phy *phy, unsigned int req); |
| 43 |
void (*write)(struct qemu_phy *phy, unsigned int req, |
| 44 |
unsigned int data); |
| 45 |
}; |
| 46 |
|
| 47 |
static unsigned int tdk_read(struct qemu_phy *phy, unsigned int req) |
| 48 |
{
|
| 49 |
int regnum;
|
| 50 |
unsigned r = 0; |
| 51 |
|
| 52 |
regnum = req & 0x1f;
|
| 53 |
|
| 54 |
switch (regnum) {
|
| 55 |
case 1: |
| 56 |
/* MR1. */
|
| 57 |
/* Speeds and modes. */
|
| 58 |
r |= (1 << 13) | (1 << 14); |
| 59 |
r |= (1 << 11) | (1 << 12); |
| 60 |
r |= (1 << 5); /* Autoneg complete. */ |
| 61 |
r |= (1 << 3); /* Autoneg able. */ |
| 62 |
r |= (1 << 2); /* Link. */ |
| 63 |
break;
|
| 64 |
case 5: |
| 65 |
/* Link partner ability.
|
| 66 |
We are kind; always agree with whatever best mode
|
| 67 |
the guest advertises. */
|
| 68 |
r = 1 << 14; /* Success. */ |
| 69 |
/* Copy advertised modes. */
|
| 70 |
r |= phy->regs[4] & (15 << 5); |
| 71 |
/* Autoneg support. */
|
| 72 |
r |= 1;
|
| 73 |
break;
|
| 74 |
case 18: |
| 75 |
{
|
| 76 |
/* Diagnostics reg. */
|
| 77 |
int duplex = 0; |
| 78 |
int speed_100 = 0; |
| 79 |
|
| 80 |
/* Are we advertising 100 half or 100 duplex ? */
|
| 81 |
speed_100 = !!(phy->regs[4] & 0x180); |
| 82 |
/* Are we advertising 10 duplex or 100 duplex ? */
|
| 83 |
duplex = !!(phy->regs[4] & 0x180); |
| 84 |
r = (speed_100 << 10) | (duplex << 11); |
| 85 |
} |
| 86 |
break;
|
| 87 |
|
| 88 |
default:
|
| 89 |
r = phy->regs[regnum]; |
| 90 |
break;
|
| 91 |
} |
| 92 |
D(printf("\n%s %x = reg[%d]\n", __func__, r, regnum));
|
| 93 |
return r;
|
| 94 |
} |
| 95 |
|
| 96 |
static void |
| 97 |
tdk_write(struct qemu_phy *phy, unsigned int req, unsigned int data) |
| 98 |
{
|
| 99 |
int regnum;
|
| 100 |
|
| 101 |
regnum = req & 0x1f;
|
| 102 |
D(printf("%s reg[%d] = %x\n", __func__, regnum, data));
|
| 103 |
switch (regnum) {
|
| 104 |
default:
|
| 105 |
phy->regs[regnum] = data; |
| 106 |
break;
|
| 107 |
} |
| 108 |
} |
| 109 |
|
| 110 |
static void |
| 111 |
tdk_init(struct qemu_phy *phy)
|
| 112 |
{
|
| 113 |
phy->regs[0] = 0x3100; |
| 114 |
/* PHY Id. */
|
| 115 |
phy->regs[2] = 0x0300; |
| 116 |
phy->regs[3] = 0xe400; |
| 117 |
/* Autonegotiation advertisement reg. */
|
| 118 |
phy->regs[4] = 0x01E1; |
| 119 |
|
| 120 |
phy->read = tdk_read; |
| 121 |
phy->write = tdk_write; |
| 122 |
} |
| 123 |
|
| 124 |
struct qemu_mdio
|
| 125 |
{
|
| 126 |
/* bus. */
|
| 127 |
int mdc;
|
| 128 |
int mdio;
|
| 129 |
|
| 130 |
/* decoder. */
|
| 131 |
enum {
|
| 132 |
PREAMBLE, |
| 133 |
SOF, |
| 134 |
OPC, |
| 135 |
ADDR, |
| 136 |
REQ, |
| 137 |
TURNAROUND, |
| 138 |
DATA |
| 139 |
} state; |
| 140 |
unsigned int drive; |
| 141 |
|
| 142 |
unsigned int cnt; |
| 143 |
unsigned int addr; |
| 144 |
unsigned int opc; |
| 145 |
unsigned int req; |
| 146 |
unsigned int data; |
| 147 |
|
| 148 |
struct qemu_phy *devs[32]; |
| 149 |
}; |
| 150 |
|
| 151 |
static void |
| 152 |
mdio_attach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr) |
| 153 |
{
|
| 154 |
bus->devs[addr & 0x1f] = phy;
|
| 155 |
} |
| 156 |
|
| 157 |
static void |
| 158 |
mdio_detach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr) |
| 159 |
{
|
| 160 |
bus->devs[addr & 0x1f] = NULL; |
| 161 |
} |
| 162 |
|
| 163 |
static void mdio_read_req(struct qemu_mdio *bus) |
| 164 |
{
|
| 165 |
struct qemu_phy *phy;
|
| 166 |
|
| 167 |
phy = bus->devs[bus->addr]; |
| 168 |
if (phy && phy->read)
|
| 169 |
bus->data = phy->read(phy, bus->req); |
| 170 |
else
|
| 171 |
bus->data = 0xffff;
|
| 172 |
} |
| 173 |
|
| 174 |
static void mdio_write_req(struct qemu_mdio *bus) |
| 175 |
{
|
| 176 |
struct qemu_phy *phy;
|
| 177 |
|
| 178 |
phy = bus->devs[bus->addr]; |
| 179 |
if (phy && phy->write)
|
| 180 |
phy->write(phy, bus->req, bus->data); |
| 181 |
} |
| 182 |
|
| 183 |
static void mdio_cycle(struct qemu_mdio *bus) |
| 184 |
{
|
| 185 |
bus->cnt++; |
| 186 |
|
| 187 |
D(printf("mdc=%d mdio=%d state=%d cnt=%d drv=%d\n",
|
| 188 |
bus->mdc, bus->mdio, bus->state, bus->cnt, bus->drive)); |
| 189 |
#if 0
|
| 190 |
if (bus->mdc)
|
| 191 |
printf("%d", bus->mdio);
|
| 192 |
#endif
|
| 193 |
switch (bus->state)
|
| 194 |
{
|
| 195 |
case PREAMBLE:
|
| 196 |
if (bus->mdc) {
|
| 197 |
if (bus->cnt >= (32 * 2) && !bus->mdio) { |
| 198 |
bus->cnt = 0;
|
| 199 |
bus->state = SOF; |
| 200 |
bus->data = 0;
|
| 201 |
} |
| 202 |
} |
| 203 |
break;
|
| 204 |
case SOF:
|
| 205 |
if (bus->mdc) {
|
| 206 |
if (bus->mdio != 1) |
| 207 |
printf("WARNING: no SOF\n");
|
| 208 |
if (bus->cnt == 1*2) { |
| 209 |
bus->cnt = 0;
|
| 210 |
bus->opc = 0;
|
| 211 |
bus->state = OPC; |
| 212 |
} |
| 213 |
} |
| 214 |
break;
|
| 215 |
case OPC:
|
| 216 |
if (bus->mdc) {
|
| 217 |
bus->opc <<= 1;
|
| 218 |
bus->opc |= bus->mdio & 1;
|
| 219 |
if (bus->cnt == 2*2) { |
| 220 |
bus->cnt = 0;
|
| 221 |
bus->addr = 0;
|
| 222 |
bus->state = ADDR; |
| 223 |
} |
| 224 |
} |
| 225 |
break;
|
| 226 |
case ADDR:
|
| 227 |
if (bus->mdc) {
|
| 228 |
bus->addr <<= 1;
|
| 229 |
bus->addr |= bus->mdio & 1;
|
| 230 |
|
| 231 |
if (bus->cnt == 5*2) { |
| 232 |
bus->cnt = 0;
|
| 233 |
bus->req = 0;
|
| 234 |
bus->state = REQ; |
| 235 |
} |
| 236 |
} |
| 237 |
break;
|
| 238 |
case REQ:
|
| 239 |
if (bus->mdc) {
|
| 240 |
bus->req <<= 1;
|
| 241 |
bus->req |= bus->mdio & 1;
|
| 242 |
if (bus->cnt == 5*2) { |
| 243 |
bus->cnt = 0;
|
| 244 |
bus->state = TURNAROUND; |
| 245 |
} |
| 246 |
} |
| 247 |
break;
|
| 248 |
case TURNAROUND:
|
| 249 |
if (bus->mdc && bus->cnt == 2*2) { |
| 250 |
bus->mdio = 0;
|
| 251 |
bus->cnt = 0;
|
| 252 |
|
| 253 |
if (bus->opc == 2) { |
| 254 |
bus->drive = 1;
|
| 255 |
mdio_read_req(bus); |
| 256 |
bus->mdio = bus->data & 1;
|
| 257 |
} |
| 258 |
bus->state = DATA; |
| 259 |
} |
| 260 |
break;
|
| 261 |
case DATA:
|
| 262 |
if (!bus->mdc) {
|
| 263 |
if (bus->drive) {
|
| 264 |
bus->mdio = !!(bus->data & (1 << 15)); |
| 265 |
bus->data <<= 1;
|
| 266 |
} |
| 267 |
} else {
|
| 268 |
if (!bus->drive) {
|
| 269 |
bus->data <<= 1;
|
| 270 |
bus->data |= bus->mdio; |
| 271 |
} |
| 272 |
if (bus->cnt == 16 * 2) { |
| 273 |
bus->cnt = 0;
|
| 274 |
bus->state = PREAMBLE; |
| 275 |
if (!bus->drive)
|
| 276 |
mdio_write_req(bus); |
| 277 |
bus->drive = 0;
|
| 278 |
} |
| 279 |
} |
| 280 |
break;
|
| 281 |
default:
|
| 282 |
break;
|
| 283 |
} |
| 284 |
} |
| 285 |
|
| 286 |
/* ETRAX-FS Ethernet MAC block starts here. */
|
| 287 |
|
| 288 |
#define RW_MA0_LO 0x00 |
| 289 |
#define RW_MA0_HI 0x04 |
| 290 |
#define RW_MA1_LO 0x08 |
| 291 |
#define RW_MA1_HI 0x0c |
| 292 |
#define RW_GA_LO 0x10 |
| 293 |
#define RW_GA_HI 0x14 |
| 294 |
#define RW_GEN_CTRL 0x18 |
| 295 |
#define RW_REC_CTRL 0x1c |
| 296 |
#define RW_TR_CTRL 0x20 |
| 297 |
#define RW_CLR_ERR 0x24 |
| 298 |
#define RW_MGM_CTRL 0x28 |
| 299 |
#define R_STAT 0x2c |
| 300 |
#define FS_ETH_MAX_REGS 0x5c |
| 301 |
|
| 302 |
struct fs_eth
|
| 303 |
{
|
| 304 |
CPUState *env; |
| 305 |
qemu_irq *irq; |
| 306 |
target_phys_addr_t base; |
| 307 |
VLANClientState *vc; |
| 308 |
int ethregs;
|
| 309 |
|
| 310 |
/* Two addrs in the filter. */
|
| 311 |
uint8_t macaddr[2][6]; |
| 312 |
uint32_t regs[FS_ETH_MAX_REGS]; |
| 313 |
|
| 314 |
unsigned char rx_fifo[1536]; |
| 315 |
int rx_fifo_len;
|
| 316 |
int rx_fifo_pos;
|
| 317 |
|
| 318 |
struct etraxfs_dma_client *dma_out;
|
| 319 |
struct etraxfs_dma_client *dma_in;
|
| 320 |
|
| 321 |
/* MDIO bus. */
|
| 322 |
struct qemu_mdio mdio_bus;
|
| 323 |
/* PHY. */
|
| 324 |
struct qemu_phy phy;
|
| 325 |
}; |
| 326 |
|
| 327 |
static uint32_t eth_rinvalid (void *opaque, target_phys_addr_t addr) |
| 328 |
{
|
| 329 |
struct fs_eth *eth = opaque;
|
| 330 |
CPUState *env = eth->env; |
| 331 |
cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
|
| 332 |
addr, env->pc); |
| 333 |
return 0; |
| 334 |
} |
| 335 |
|
| 336 |
static uint32_t eth_readl (void *opaque, target_phys_addr_t addr) |
| 337 |
{
|
| 338 |
struct fs_eth *eth = opaque;
|
| 339 |
D(CPUState *env = eth->env); |
| 340 |
uint32_t r = 0;
|
| 341 |
|
| 342 |
/* Make addr relative to this instances base. */
|
| 343 |
addr -= eth->base; |
| 344 |
switch (addr) {
|
| 345 |
case R_STAT:
|
| 346 |
/* Attach an MDIO/PHY abstraction. */
|
| 347 |
r = eth->mdio_bus.mdio & 1;
|
| 348 |
break;
|
| 349 |
default:
|
| 350 |
r = eth->regs[addr]; |
| 351 |
D(printf ("%s %x p=%x\n", __func__, addr, env->pc));
|
| 352 |
break;
|
| 353 |
} |
| 354 |
return r;
|
| 355 |
} |
| 356 |
|
| 357 |
static void |
| 358 |
eth_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
|
| 359 |
{
|
| 360 |
struct fs_eth *eth = opaque;
|
| 361 |
CPUState *env = eth->env; |
| 362 |
cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
|
| 363 |
addr, env->pc); |
| 364 |
} |
| 365 |
|
| 366 |
static void eth_update_ma(struct fs_eth *eth, int ma) |
| 367 |
{
|
| 368 |
int reg;
|
| 369 |
int i = 0; |
| 370 |
|
| 371 |
ma &= 1;
|
| 372 |
|
| 373 |
reg = RW_MA0_LO; |
| 374 |
if (ma)
|
| 375 |
reg = RW_MA1_LO; |
| 376 |
|
| 377 |
eth->macaddr[ma][i++] = eth->regs[reg]; |
| 378 |
eth->macaddr[ma][i++] = eth->regs[reg] >> 8;
|
| 379 |
eth->macaddr[ma][i++] = eth->regs[reg] >> 16;
|
| 380 |
eth->macaddr[ma][i++] = eth->regs[reg] >> 24;
|
| 381 |
eth->macaddr[ma][i++] = eth->regs[reg + 4];
|
| 382 |
eth->macaddr[ma][i++] = eth->regs[reg + 4] >> 8; |
| 383 |
|
| 384 |
D(printf("set mac%d=%x.%x.%x.%x.%x.%x\n", ma,
|
| 385 |
eth->macaddr[ma][0], eth->macaddr[ma][1], |
| 386 |
eth->macaddr[ma][2], eth->macaddr[ma][3], |
| 387 |
eth->macaddr[ma][4], eth->macaddr[ma][5])); |
| 388 |
} |
| 389 |
|
| 390 |
static void |
| 391 |
eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
|
| 392 |
{
|
| 393 |
struct fs_eth *eth = opaque;
|
| 394 |
CPUState *env = eth->env; |
| 395 |
|
| 396 |
/* Make addr relative to this instances base. */
|
| 397 |
addr -= eth->base; |
| 398 |
switch (addr)
|
| 399 |
{
|
| 400 |
case RW_MA0_LO:
|
| 401 |
eth->regs[addr] = value; |
| 402 |
eth_update_ma(eth, 0);
|
| 403 |
break;
|
| 404 |
case RW_MA0_HI:
|
| 405 |
eth->regs[addr] = value; |
| 406 |
eth_update_ma(eth, 0);
|
| 407 |
break;
|
| 408 |
case RW_MA1_LO:
|
| 409 |
eth->regs[addr] = value; |
| 410 |
eth_update_ma(eth, 1);
|
| 411 |
break;
|
| 412 |
case RW_MA1_HI:
|
| 413 |
eth->regs[addr] = value; |
| 414 |
eth_update_ma(eth, 1);
|
| 415 |
break;
|
| 416 |
|
| 417 |
case RW_MGM_CTRL:
|
| 418 |
/* Attach an MDIO/PHY abstraction. */
|
| 419 |
if (value & 2) |
| 420 |
eth->mdio_bus.mdio = value & 1;
|
| 421 |
if (eth->mdio_bus.mdc != (value & 4)) |
| 422 |
mdio_cycle(ð->mdio_bus); |
| 423 |
eth->mdio_bus.mdc = !!(value & 4);
|
| 424 |
break;
|
| 425 |
|
| 426 |
default:
|
| 427 |
eth->regs[addr] = value; |
| 428 |
printf ("%s %x %x pc=%x\n",
|
| 429 |
__func__, addr, value, env->pc); |
| 430 |
break;
|
| 431 |
} |
| 432 |
} |
| 433 |
|
| 434 |
/* The ETRAX FS has a groupt address table (GAT) which works like a k=1 bloom
|
| 435 |
filter dropping group addresses we have not joined. The filter has 64
|
| 436 |
bits (m). The has function is a simple nible xor of the group addr. */
|
| 437 |
static int eth_match_groupaddr(struct fs_eth *eth, const unsigned char *sa) |
| 438 |
{
|
| 439 |
unsigned int hsh; |
| 440 |
int m_individual = eth->regs[RW_REC_CTRL] & 4; |
| 441 |
int match;
|
| 442 |
|
| 443 |
/* First bit on the wire of a MAC address signals multicast or
|
| 444 |
physical address. */
|
| 445 |
if (!m_individual && !sa[0] & 1) |
| 446 |
return 0; |
| 447 |
|
| 448 |
/* Calculate the hash index for the GA registers. */
|
| 449 |
hsh = 0;
|
| 450 |
hsh ^= (*sa) & 0x3f;
|
| 451 |
hsh ^= ((*sa) >> 6) & 0x03; |
| 452 |
++sa; |
| 453 |
hsh ^= ((*sa) << 2) & 0x03c; |
| 454 |
hsh ^= ((*sa) >> 4) & 0xf; |
| 455 |
++sa; |
| 456 |
hsh ^= ((*sa) << 4) & 0x30; |
| 457 |
hsh ^= ((*sa) >> 2) & 0x3f; |
| 458 |
++sa; |
| 459 |
hsh ^= (*sa) & 0x3f;
|
| 460 |
hsh ^= ((*sa) >> 6) & 0x03; |
| 461 |
++sa; |
| 462 |
hsh ^= ((*sa) << 2) & 0x03c; |
| 463 |
hsh ^= ((*sa) >> 4) & 0xf; |
| 464 |
++sa; |
| 465 |
hsh ^= ((*sa) << 4) & 0x30; |
| 466 |
hsh ^= ((*sa) >> 2) & 0x3f; |
| 467 |
|
| 468 |
hsh &= 63;
|
| 469 |
if (hsh > 31) |
| 470 |
match = eth->regs[RW_GA_HI] & (1 << (hsh - 32)); |
| 471 |
else
|
| 472 |
match = eth->regs[RW_GA_LO] & (1 << hsh);
|
| 473 |
D(printf("hsh=%x ga=%x.%x mtch=%d\n", hsh,
|
| 474 |
eth->regs[RW_GA_HI], eth->regs[RW_GA_LO], match)); |
| 475 |
return match;
|
| 476 |
} |
| 477 |
|
| 478 |
static int eth_can_receive(void *opaque) |
| 479 |
{
|
| 480 |
struct fs_eth *eth = opaque;
|
| 481 |
int r;
|
| 482 |
|
| 483 |
r = eth->rx_fifo_len == 0;
|
| 484 |
if (!r) {
|
| 485 |
/* TODO: signal fifo overrun. */
|
| 486 |
printf("PACKET LOSS!\n");
|
| 487 |
} |
| 488 |
return r;
|
| 489 |
} |
| 490 |
|
| 491 |
static void eth_receive(void *opaque, const uint8_t *buf, int size) |
| 492 |
{
|
| 493 |
unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
| 494 |
struct fs_eth *eth = opaque;
|
| 495 |
int use_ma0 = eth->regs[RW_REC_CTRL] & 1; |
| 496 |
int use_ma1 = eth->regs[RW_REC_CTRL] & 2; |
| 497 |
int r_bcast = eth->regs[RW_REC_CTRL] & 8; |
| 498 |
|
| 499 |
if (size < 12) |
| 500 |
return;
|
| 501 |
|
| 502 |
D(printf("%x.%x.%x.%x.%x.%x ma=%d %d bc=%d\n",
|
| 503 |
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], |
| 504 |
use_ma0, use_ma1, r_bcast)); |
| 505 |
|
| 506 |
/* Does the frame get through the address filters? */
|
| 507 |
if ((!use_ma0 || memcmp(buf, eth->macaddr[0], 6)) |
| 508 |
&& (!use_ma1 || memcmp(buf, eth->macaddr[1], 6)) |
| 509 |
&& (!r_bcast || memcmp(buf, sa_bcast, 6))
|
| 510 |
&& !eth_match_groupaddr(eth, buf)) |
| 511 |
return;
|
| 512 |
|
| 513 |
if (size > sizeof(eth->rx_fifo)) { |
| 514 |
/* TODO: signal error. */
|
| 515 |
} else if (eth->rx_fifo_len) { |
| 516 |
/* FIFO overrun. */
|
| 517 |
} else {
|
| 518 |
memcpy(eth->rx_fifo, buf, size); |
| 519 |
/* +4, HW passes the CRC to sw. */
|
| 520 |
eth->rx_fifo_len = size + 4;
|
| 521 |
eth->rx_fifo_pos = 0;
|
| 522 |
} |
| 523 |
} |
| 524 |
|
| 525 |
static void eth_rx_pull(void *opaque) |
| 526 |
{
|
| 527 |
struct fs_eth *eth = opaque;
|
| 528 |
int len;
|
| 529 |
if (eth->rx_fifo_len) {
|
| 530 |
D(printf("%s %d\n", __func__, eth->rx_fifo_len));
|
| 531 |
#if 0
|
| 532 |
{
|
| 533 |
int i;
|
| 534 |
for (i = 0; i < 32; i++)
|
| 535 |
printf("%2.2x", eth->rx_fifo[i]);
|
| 536 |
printf("\n");
|
| 537 |
}
|
| 538 |
#endif
|
| 539 |
len = etraxfs_dmac_input(eth->dma_in, |
| 540 |
eth->rx_fifo + eth->rx_fifo_pos, |
| 541 |
eth->rx_fifo_len, 1);
|
| 542 |
eth->rx_fifo_len -= len; |
| 543 |
eth->rx_fifo_pos += len; |
| 544 |
} |
| 545 |
} |
| 546 |
|
| 547 |
static int eth_tx_push(void *opaque, unsigned char *buf, int len) |
| 548 |
{
|
| 549 |
struct fs_eth *eth = opaque;
|
| 550 |
|
| 551 |
D(printf("%s buf=%p len=%d\n", __func__, buf, len));
|
| 552 |
qemu_send_packet(eth->vc, buf, len); |
| 553 |
return len;
|
| 554 |
} |
| 555 |
|
| 556 |
static CPUReadMemoryFunc *eth_read[] = {
|
| 557 |
ð_rinvalid, |
| 558 |
ð_rinvalid, |
| 559 |
ð_readl, |
| 560 |
}; |
| 561 |
|
| 562 |
static CPUWriteMemoryFunc *eth_write[] = {
|
| 563 |
ð_winvalid, |
| 564 |
ð_winvalid, |
| 565 |
ð_writel, |
| 566 |
}; |
| 567 |
|
| 568 |
void *etraxfs_eth_init(NICInfo *nd, CPUState *env,
|
| 569 |
qemu_irq *irq, target_phys_addr_t base) |
| 570 |
{
|
| 571 |
struct etraxfs_dma_client *dma = NULL; |
| 572 |
struct fs_eth *eth = NULL; |
| 573 |
|
| 574 |
dma = qemu_mallocz(sizeof *dma * 2); |
| 575 |
if (!dma)
|
| 576 |
return NULL; |
| 577 |
|
| 578 |
eth = qemu_mallocz(sizeof *eth);
|
| 579 |
if (!eth)
|
| 580 |
goto err;
|
| 581 |
|
| 582 |
dma[0].client.push = eth_tx_push;
|
| 583 |
dma[0].client.opaque = eth;
|
| 584 |
dma[1].client.opaque = eth;
|
| 585 |
dma[1].client.pull = eth_rx_pull;
|
| 586 |
|
| 587 |
eth->env = env; |
| 588 |
eth->base = base; |
| 589 |
eth->irq = irq; |
| 590 |
eth->dma_out = dma; |
| 591 |
eth->dma_in = dma + 1;
|
| 592 |
|
| 593 |
/* Connect the phy. */
|
| 594 |
tdk_init(ð->phy); |
| 595 |
mdio_attach(ð->mdio_bus, ð->phy, 0x1);
|
| 596 |
|
| 597 |
eth->ethregs = cpu_register_io_memory(0, eth_read, eth_write, eth);
|
| 598 |
cpu_register_physical_memory (base, 0x5c, eth->ethregs);
|
| 599 |
|
| 600 |
eth->vc = qemu_new_vlan_client(nd->vlan, |
| 601 |
eth_receive, eth_can_receive, eth); |
| 602 |
|
| 603 |
return dma;
|
| 604 |
err:
|
| 605 |
qemu_free(eth); |
| 606 |
qemu_free(dma); |
| 607 |
return NULL; |
| 608 |
} |