Revision f7350b47

b/target-sparc/op_helper.c
1687 1687 
            }
1688 1688 
            break;
1689 1689 
        }
1690 
    case 0x46: // D-cache data
1691 
    case 0x47: // D-cache tag access
1692 
    case 0x4e: // E-cache tag data
1693 
    case 0x66: // I-cache instruction access
1694 
    case 0x67: // I-cache tag access
1695 
    case 0x6e: // I-cache predecode
1696 
    case 0x6f: // I-cache LRU etc.
1697 
    case 0x76: // E-cache tag
1698 
    case 0x7e: // E-cache tag
1699 
        break;
1690 1700 
    case 0x59: // D-MMU 8k TSB pointer
1691 1701 
    case 0x5a: // D-MMU 64k TSB pointer
1692 1702 
    case 0x5b: // D-MMU data pointer
......
2040 2050 
    case 0x49: // Interrupt data receive
2041 2051 
        // XXX
2042 2052 
        return;
2053 
    case 0x46: // D-cache data
2054 
    case 0x47: // D-cache tag access
2055 
    case 0x4e: // E-cache tag data
2056 
    case 0x66: // I-cache instruction access
2057 
    case 0x67: // I-cache tag access
2058 
    case 0x6e: // I-cache predecode
2059 
    case 0x6f: // I-cache LRU etc.
2060 
    case 0x76: // E-cache tag
2061 
    case 0x7e: // E-cache tag
2062 
        return;
2043 2063 
    case 0x51: // I-MMU 8k TSB pointer, RO
2044 2064 
    case 0x52: // I-MMU 64k TSB pointer, RO
2045 2065 
    case 0x56: // I-MMU tag read, RO

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