Revision f73534a5 target-arm/translate.c

b/target-arm/translate.c
4850 4850 
                    }
4851 4851 
                    neon_store_reg64(cpu_V0, rd + pass);
4852 4852 
                }
4853 
            } else if (op == 15 || op == 16) {
4853 
            } else if (op >= 14) {
4854 4854 
                /* VCVT fixed-point.  */
4855 
                /* We have already masked out the must-be-1 top bit of imm6,
4856 
                 * hence this 32-shift where the ARM ARM has 64-imm6.
4857 
                 */
4858 
                shift = 32 - shift;
4855 4859 
                for (pass = 0; pass < (q ? 4 : 2); pass++) {
4856 4860 
                    tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
4857 
                    if (op & 1) {
4861 
                    if (!(op & 1)) {
4858 4862 
                        if (u)
4859 4863 
                            gen_vfp_ulto(0, shift);
4860 4864 
                        else

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