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/*
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* High Precisition Event Timer emulation
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*
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* Copyright (c) 2007 Alexander Graf
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* Copyright (c) 2008 IBM Corporation
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*
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* Authors: Beth Kon <bkon@us.ibm.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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* *****************************************************************
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*
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* This driver attempts to emulate an HPET device in software.
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "console.h" |
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#include "qemu-timer.h" |
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#include "hpet_emul.h" |
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//#define HPET_DEBUG
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#ifdef HPET_DEBUG
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#define dprintf printf
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#else
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#define dprintf(...)
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#endif
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static HPETState *hpet_statep;
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uint32_t hpet_in_legacy_mode(void)
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{ |
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if (hpet_statep)
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return hpet_statep->config & HPET_CFG_LEGACY;
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else
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return 0; |
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} |
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static uint32_t timer_int_route(struct HPETTimer *timer) |
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{ |
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uint32_t route; |
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route = (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT; |
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return route;
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} |
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static uint32_t hpet_enabled(void) |
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{ |
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return hpet_statep->config & HPET_CFG_ENABLE;
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} |
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static uint32_t timer_is_periodic(HPETTimer *t)
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{ |
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return t->config & HPET_TN_PERIODIC;
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} |
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static uint32_t timer_enabled(HPETTimer *t)
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{ |
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return t->config & HPET_TN_ENABLE;
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} |
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static uint32_t hpet_time_after(uint64_t a, uint64_t b)
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{ |
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return ((int32_t)(b) - (int32_t)(a) < 0); |
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} |
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static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
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{ |
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return ((int64_t)(b) - (int64_t)(a) < 0); |
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} |
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static uint64_t ticks_to_ns(uint64_t value)
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{ |
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return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
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} |
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static uint64_t ns_to_ticks(uint64_t value)
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{ |
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return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
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} |
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static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
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{ |
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new &= mask; |
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new |= old & ~mask; |
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return new;
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} |
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static int activating_bit(uint64_t old, uint64_t new, uint64_t mask) |
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{ |
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return (!(old & mask) && (new & mask));
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} |
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static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask) |
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{ |
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return ((old & mask) && !(new & mask));
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} |
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static uint64_t hpet_get_ticks(void) |
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{ |
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uint64_t ticks; |
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ticks = ns_to_ticks(qemu_get_clock(vm_clock) + hpet_statep->hpet_offset); |
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return ticks;
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} |
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/*
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* calculate diff between comparator value and current ticks
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*/
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static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current) |
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{ |
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if (t->config & HPET_TN_32BIT) {
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uint32_t diff, cmp; |
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cmp = (uint32_t)t->cmp; |
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diff = cmp - (uint32_t)current; |
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diff = (int32_t)diff > 0 ? diff : (uint32_t)0; |
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return (uint64_t)diff;
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} else {
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uint64_t diff, cmp; |
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cmp = t->cmp; |
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diff = cmp - current; |
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diff = (int64_t)diff > 0 ? diff : (uint64_t)0; |
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return diff;
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} |
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} |
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static void update_irq(struct HPETTimer *timer) |
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{ |
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qemu_irq irq; |
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int route;
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if (timer->tn <= 1 && hpet_in_legacy_mode()) { |
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/* if LegacyReplacementRoute bit is set, HPET specification requires
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* timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
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* timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
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*/
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if (timer->tn == 0) { |
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irq=timer->state->irqs[0];
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} else
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irq=timer->state->irqs[8];
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} else {
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route=timer_int_route(timer); |
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irq=timer->state->irqs[route]; |
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} |
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if (timer_enabled(timer) && hpet_enabled()) {
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qemu_irq_pulse(irq); |
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} |
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} |
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static void hpet_pre_save(void *opaque) |
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{ |
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HPETState *s = opaque; |
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/* save current counter value */
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s->hpet_counter = hpet_get_ticks(); |
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} |
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static int hpet_post_load(void *opaque, int version_id) |
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{ |
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HPETState *s = opaque; |
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/* Recalculate the offset between the main counter and guest time */
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s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock); |
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return 0; |
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} |
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static const VMStateDescription vmstate_hpet_timer = { |
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.name = "hpet_timer",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) { |
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VMSTATE_UINT8(tn, HPETTimer), |
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VMSTATE_UINT64(config, HPETTimer), |
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VMSTATE_UINT64(cmp, HPETTimer), |
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VMSTATE_UINT64(fsb, HPETTimer), |
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VMSTATE_UINT64(period, HPETTimer), |
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VMSTATE_UINT8(wrap_flag, HPETTimer), |
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VMSTATE_TIMER(qemu_timer, HPETTimer), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static const VMStateDescription vmstate_hpet = { |
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.name = "hpet",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.pre_save = hpet_pre_save, |
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.post_load = hpet_post_load, |
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.fields = (VMStateField []) { |
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VMSTATE_UINT64(config, HPETState), |
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VMSTATE_UINT64(isr, HPETState), |
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VMSTATE_UINT64(hpet_counter, HPETState), |
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VMSTATE_STRUCT_ARRAY(timer, HPETState, HPET_NUM_TIMERS, 0,
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vmstate_hpet_timer, HPETTimer), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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/*
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* timer expiration callback
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*/
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static void hpet_timer(void *opaque) |
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{ |
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HPETTimer *t = (HPETTimer*)opaque; |
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uint64_t diff; |
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uint64_t period = t->period; |
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uint64_t cur_tick = hpet_get_ticks(); |
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if (timer_is_periodic(t) && period != 0) { |
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if (t->config & HPET_TN_32BIT) {
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while (hpet_time_after(cur_tick, t->cmp))
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t->cmp = (uint32_t)(t->cmp + t->period); |
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} else
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while (hpet_time_after64(cur_tick, t->cmp))
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t->cmp += period; |
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diff = hpet_calculate_diff(t, cur_tick); |
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qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) |
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+ (int64_t)ticks_to_ns(diff)); |
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} else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) { |
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if (t->wrap_flag) {
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diff = hpet_calculate_diff(t, cur_tick); |
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qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) |
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+ (int64_t)ticks_to_ns(diff)); |
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t->wrap_flag = 0;
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} |
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} |
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update_irq(t); |
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} |
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static void hpet_set_timer(HPETTimer *t) |
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{ |
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uint64_t diff; |
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uint32_t wrap_diff; /* how many ticks until we wrap? */
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uint64_t cur_tick = hpet_get_ticks(); |
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/* whenever new timer is being set up, make sure wrap_flag is 0 */
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t->wrap_flag = 0;
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diff = hpet_calculate_diff(t, cur_tick); |
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/* hpet spec says in one-shot 32-bit mode, generate an interrupt when
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* counter wraps in addition to an interrupt with comparator match.
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*/
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if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
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wrap_diff = 0xffffffff - (uint32_t)cur_tick;
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if (wrap_diff < (uint32_t)diff) {
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diff = wrap_diff; |
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t->wrap_flag = 1;
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} |
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} |
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qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) |
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+ (int64_t)ticks_to_ns(diff)); |
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} |
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static void hpet_del_timer(HPETTimer *t) |
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{ |
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qemu_del_timer(t->qemu_timer); |
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} |
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#ifdef HPET_DEBUG
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static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr) |
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{ |
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printf("qemu: hpet_read b at %" PRIx64 "\n", addr); |
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return 0; |
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} |
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static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr) |
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{ |
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printf("qemu: hpet_read w at %" PRIx64 "\n", addr); |
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return 0; |
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} |
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#endif
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static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr) |
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{ |
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HPETState *s = (HPETState *)opaque; |
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uint64_t cur_tick, index; |
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dprintf("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr); |
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index = addr; |
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/*address range of all TN regs*/
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if (index >= 0x100 && index <= 0x3ff) { |
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uint8_t timer_id = (addr - 0x100) / 0x20; |
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if (timer_id > HPET_NUM_TIMERS - 1) { |
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printf("qemu: timer id out of range\n");
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return 0; |
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} |
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HPETTimer *timer = &s->timer[timer_id]; |
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switch ((addr - 0x100) % 0x20) { |
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case HPET_TN_CFG:
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return timer->config;
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case HPET_TN_CFG + 4: // Interrupt capabilities |
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return timer->config >> 32; |
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case HPET_TN_CMP: // comparator register |
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return timer->cmp;
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case HPET_TN_CMP + 4: |
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return timer->cmp >> 32; |
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case HPET_TN_ROUTE:
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return timer->fsb >> 32; |
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default:
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dprintf("qemu: invalid hpet_ram_readl\n");
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break;
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} |
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} else {
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switch (index) {
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case HPET_ID:
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return s->capability;
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case HPET_PERIOD:
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return s->capability >> 32; |
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case HPET_CFG:
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return s->config;
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case HPET_CFG + 4: |
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dprintf("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
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return 0; |
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case HPET_COUNTER:
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if (hpet_enabled())
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cur_tick = hpet_get_ticks(); |
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else
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cur_tick = s->hpet_counter; |
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dprintf("qemu: reading counter = %" PRIx64 "\n", cur_tick); |
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return cur_tick;
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case HPET_COUNTER + 4: |
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if (hpet_enabled())
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cur_tick = hpet_get_ticks(); |
338 |
else
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cur_tick = s->hpet_counter; |
340 |
dprintf("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick); |
341 |
return cur_tick >> 32; |
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case HPET_STATUS:
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return s->isr;
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default:
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dprintf("qemu: invalid hpet_ram_readl\n");
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break;
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} |
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} |
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return 0; |
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} |
351 |
|
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#ifdef HPET_DEBUG
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static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{ |
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printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n", |
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addr, value); |
358 |
} |
359 |
|
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static void hpet_ram_writew(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
362 |
{ |
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printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n", |
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addr, value); |
365 |
} |
366 |
#endif
|
367 |
|
368 |
static void hpet_ram_writel(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
370 |
{ |
371 |
int i;
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HPETState *s = (HPETState *)opaque; |
373 |
uint64_t old_val, new_val, val, index; |
374 |
|
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dprintf("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value); |
376 |
index = addr; |
377 |
old_val = hpet_ram_readl(opaque, addr); |
378 |
new_val = value; |
379 |
|
380 |
/*address range of all TN regs*/
|
381 |
if (index >= 0x100 && index <= 0x3ff) { |
382 |
uint8_t timer_id = (addr - 0x100) / 0x20; |
383 |
dprintf("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
|
384 |
HPETTimer *timer = &s->timer[timer_id]; |
385 |
|
386 |
switch ((addr - 0x100) % 0x20) { |
387 |
case HPET_TN_CFG:
|
388 |
dprintf("qemu: hpet_ram_writel HPET_TN_CFG\n");
|
389 |
val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); |
390 |
timer->config = (timer->config & 0xffffffff00000000ULL) | val;
|
391 |
if (new_val & HPET_TN_32BIT) {
|
392 |
timer->cmp = (uint32_t)timer->cmp; |
393 |
timer->period = (uint32_t)timer->period; |
394 |
} |
395 |
if (new_val & HPET_TIMER_TYPE_LEVEL) {
|
396 |
printf("qemu: level-triggered hpet not supported\n");
|
397 |
exit (-1);
|
398 |
} |
399 |
|
400 |
break;
|
401 |
case HPET_TN_CFG + 4: // Interrupt capabilities |
402 |
dprintf("qemu: invalid HPET_TN_CFG+4 write\n");
|
403 |
break;
|
404 |
case HPET_TN_CMP: // comparator register |
405 |
dprintf("qemu: hpet_ram_writel HPET_TN_CMP \n");
|
406 |
if (timer->config & HPET_TN_32BIT)
|
407 |
new_val = (uint32_t)new_val; |
408 |
if (!timer_is_periodic(timer) ||
|
409 |
(timer->config & HPET_TN_SETVAL)) |
410 |
timer->cmp = (timer->cmp & 0xffffffff00000000ULL)
|
411 |
| new_val; |
412 |
if (timer_is_periodic(timer)) {
|
413 |
/*
|
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* FIXME: Clamp period to reasonable min value?
|
415 |
* Clamp period to reasonable max value
|
416 |
*/
|
417 |
new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; |
418 |
timer->period = (timer->period & 0xffffffff00000000ULL)
|
419 |
| new_val; |
420 |
} |
421 |
timer->config &= ~HPET_TN_SETVAL; |
422 |
if (hpet_enabled())
|
423 |
hpet_set_timer(timer); |
424 |
break;
|
425 |
case HPET_TN_CMP + 4: // comparator register high order |
426 |
dprintf("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
|
427 |
if (!timer_is_periodic(timer) ||
|
428 |
(timer->config & HPET_TN_SETVAL)) |
429 |
timer->cmp = (timer->cmp & 0xffffffffULL)
|
430 |
| new_val << 32;
|
431 |
else {
|
432 |
/*
|
433 |
* FIXME: Clamp period to reasonable min value?
|
434 |
* Clamp period to reasonable max value
|
435 |
*/
|
436 |
new_val &= (timer->config |
437 |
& HPET_TN_32BIT ? ~0u : ~0ull) >> 1; |
438 |
timer->period = (timer->period & 0xffffffffULL)
|
439 |
| new_val << 32;
|
440 |
} |
441 |
timer->config &= ~HPET_TN_SETVAL; |
442 |
if (hpet_enabled())
|
443 |
hpet_set_timer(timer); |
444 |
break;
|
445 |
case HPET_TN_ROUTE + 4: |
446 |
dprintf("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
|
447 |
break;
|
448 |
default:
|
449 |
dprintf("qemu: invalid hpet_ram_writel\n");
|
450 |
break;
|
451 |
} |
452 |
return;
|
453 |
} else {
|
454 |
switch (index) {
|
455 |
case HPET_ID:
|
456 |
return;
|
457 |
case HPET_CFG:
|
458 |
val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK); |
459 |
s->config = (s->config & 0xffffffff00000000ULL) | val;
|
460 |
if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
|
461 |
/* Enable main counter and interrupt generation. */
|
462 |
s->hpet_offset = ticks_to_ns(s->hpet_counter) |
463 |
- qemu_get_clock(vm_clock); |
464 |
for (i = 0; i < HPET_NUM_TIMERS; i++) |
465 |
if ((&s->timer[i])->cmp != ~0ULL) |
466 |
hpet_set_timer(&s->timer[i]); |
467 |
} |
468 |
else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) { |
469 |
/* Halt main counter and disable interrupt generation. */
|
470 |
s->hpet_counter = hpet_get_ticks(); |
471 |
for (i = 0; i < HPET_NUM_TIMERS; i++) |
472 |
hpet_del_timer(&s->timer[i]); |
473 |
} |
474 |
/* i8254 and RTC are disabled when HPET is in legacy mode */
|
475 |
if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
|
476 |
hpet_pit_disable(); |
477 |
} else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) { |
478 |
hpet_pit_enable(); |
479 |
} |
480 |
break;
|
481 |
case HPET_CFG + 4: |
482 |
dprintf("qemu: invalid HPET_CFG+4 write \n");
|
483 |
break;
|
484 |
case HPET_STATUS:
|
485 |
/* FIXME: need to handle level-triggered interrupts */
|
486 |
break;
|
487 |
case HPET_COUNTER:
|
488 |
if (hpet_enabled())
|
489 |
printf("qemu: Writing counter while HPET enabled!\n");
|
490 |
s->hpet_counter = (s->hpet_counter & 0xffffffff00000000ULL)
|
491 |
| value; |
492 |
dprintf("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n", |
493 |
value, s->hpet_counter); |
494 |
break;
|
495 |
case HPET_COUNTER + 4: |
496 |
if (hpet_enabled())
|
497 |
printf("qemu: Writing counter while HPET enabled!\n");
|
498 |
s->hpet_counter = (s->hpet_counter & 0xffffffffULL)
|
499 |
| (((uint64_t)value) << 32);
|
500 |
dprintf("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n", |
501 |
value, s->hpet_counter); |
502 |
break;
|
503 |
default:
|
504 |
dprintf("qemu: invalid hpet_ram_writel\n");
|
505 |
break;
|
506 |
} |
507 |
} |
508 |
} |
509 |
|
510 |
static CPUReadMemoryFunc * const hpet_ram_read[] = { |
511 |
#ifdef HPET_DEBUG
|
512 |
hpet_ram_readb, |
513 |
hpet_ram_readw, |
514 |
#else
|
515 |
NULL,
|
516 |
NULL,
|
517 |
#endif
|
518 |
hpet_ram_readl, |
519 |
}; |
520 |
|
521 |
static CPUWriteMemoryFunc * const hpet_ram_write[] = { |
522 |
#ifdef HPET_DEBUG
|
523 |
hpet_ram_writeb, |
524 |
hpet_ram_writew, |
525 |
#else
|
526 |
NULL,
|
527 |
NULL,
|
528 |
#endif
|
529 |
hpet_ram_writel, |
530 |
}; |
531 |
|
532 |
static void hpet_reset(void *opaque) { |
533 |
HPETState *s = opaque; |
534 |
int i;
|
535 |
static int count = 0; |
536 |
|
537 |
for (i=0; i<HPET_NUM_TIMERS; i++) { |
538 |
HPETTimer *timer = &s->timer[i]; |
539 |
hpet_del_timer(timer); |
540 |
timer->tn = i; |
541 |
timer->cmp = ~0ULL;
|
542 |
timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP; |
543 |
/* advertise availability of ioapic inti2 */
|
544 |
timer->config |= 0x00000004ULL << 32; |
545 |
timer->state = s; |
546 |
timer->period = 0ULL;
|
547 |
timer->wrap_flag = 0;
|
548 |
} |
549 |
|
550 |
s->hpet_counter = 0ULL;
|
551 |
s->hpet_offset = 0ULL;
|
552 |
/* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
|
553 |
s->capability = 0x8086a201ULL;
|
554 |
s->capability |= ((HPET_CLK_PERIOD) << 32);
|
555 |
s->config = 0ULL;
|
556 |
if (count > 0) |
557 |
/* we don't enable pit when hpet_reset is first called (by hpet_init)
|
558 |
* because hpet is taking over for pit here. On subsequent invocations,
|
559 |
* hpet_reset is called due to system reset. At this point control must
|
560 |
* be returned to pit until SW reenables hpet.
|
561 |
*/
|
562 |
hpet_pit_enable(); |
563 |
count = 1;
|
564 |
} |
565 |
|
566 |
|
567 |
void hpet_init(qemu_irq *irq) {
|
568 |
int i, iomemtype;
|
569 |
HPETState *s; |
570 |
|
571 |
dprintf ("hpet_init\n");
|
572 |
|
573 |
s = qemu_mallocz(sizeof(HPETState));
|
574 |
hpet_statep = s; |
575 |
s->irqs = irq; |
576 |
for (i=0; i<HPET_NUM_TIMERS; i++) { |
577 |
HPETTimer *timer = &s->timer[i]; |
578 |
timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer); |
579 |
} |
580 |
vmstate_register(-1, &vmstate_hpet, s);
|
581 |
qemu_register_reset(hpet_reset, s); |
582 |
/* HPET Area */
|
583 |
iomemtype = cpu_register_io_memory(hpet_ram_read, |
584 |
hpet_ram_write, s); |
585 |
cpu_register_physical_memory(HPET_BASE, 0x400, iomemtype);
|
586 |
} |