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1 | 420557e8 | bellard | /*
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2 | 6f7e9aec | bellard | * QEMU TCX Frame buffer
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3 | 5fafdf24 | ths | *
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4 | 6f7e9aec | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "sun4m.h" |
26 | 87ecb68b | pbrook | #include "console.h" |
27 | 94470844 | blueswir1 | #include "pixel_ops.h" |
28 | 420557e8 | bellard | |
29 | 420557e8 | bellard | #define MAXX 1024 |
30 | 420557e8 | bellard | #define MAXY 768 |
31 | 6f7e9aec | bellard | #define TCX_DAC_NREGS 16 |
32 | 8508b89e | blueswir1 | #define TCX_THC_NREGS_8 0x081c |
33 | 8508b89e | blueswir1 | #define TCX_THC_NREGS_24 0x1000 |
34 | 8508b89e | blueswir1 | #define TCX_TEC_NREGS 0x1000 |
35 | 420557e8 | bellard | |
36 | 420557e8 | bellard | typedef struct TCXState { |
37 | 5dcb6b91 | blueswir1 | target_phys_addr_t addr; |
38 | 420557e8 | bellard | DisplayState *ds; |
39 | 8d5f07fa | bellard | uint8_t *vram; |
40 | eee0b836 | blueswir1 | uint32_t *vram24, *cplane; |
41 | eee0b836 | blueswir1 | ram_addr_t vram_offset, vram24_offset, cplane_offset; |
42 | eee0b836 | blueswir1 | uint16_t width, height, depth; |
43 | e80cfcfc | bellard | uint8_t r[256], g[256], b[256]; |
44 | 21206a10 | bellard | uint32_t palette[256];
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45 | 6f7e9aec | bellard | uint8_t dac_index, dac_state; |
46 | 420557e8 | bellard | } TCXState; |
47 | 420557e8 | bellard | |
48 | 95219897 | pbrook | static void tcx_screen_dump(void *opaque, const char *filename); |
49 | eee0b836 | blueswir1 | static void tcx24_screen_dump(void *opaque, const char *filename); |
50 | 97e7df27 | blueswir1 | static void tcx_invalidate_display(void *opaque); |
51 | 97e7df27 | blueswir1 | static void tcx24_invalidate_display(void *opaque); |
52 | 95219897 | pbrook | |
53 | 21206a10 | bellard | static void update_palette_entries(TCXState *s, int start, int end) |
54 | 21206a10 | bellard | { |
55 | 21206a10 | bellard | int i;
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56 | 21206a10 | bellard | for(i = start; i < end; i++) {
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57 | 0e1f5a0c | aliguori | switch(ds_get_bits_per_pixel(s->ds)) {
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58 | 21206a10 | bellard | default:
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59 | 21206a10 | bellard | case 8: |
60 | 21206a10 | bellard | s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]); |
61 | 21206a10 | bellard | break;
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62 | 21206a10 | bellard | case 15: |
63 | 8927bcfd | aliguori | s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]); |
64 | 21206a10 | bellard | break;
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65 | 21206a10 | bellard | case 16: |
66 | 8927bcfd | aliguori | s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]); |
67 | 21206a10 | bellard | break;
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68 | 21206a10 | bellard | case 32: |
69 | 7b5d76da | aliguori | if (is_surface_bgr(s->ds->surface))
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70 | 7b5d76da | aliguori | s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); |
71 | 7b5d76da | aliguori | else
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72 | 7b5d76da | aliguori | s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); |
73 | 21206a10 | bellard | break;
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74 | 21206a10 | bellard | } |
75 | 21206a10 | bellard | } |
76 | 97e7df27 | blueswir1 | if (s->depth == 24) |
77 | 97e7df27 | blueswir1 | tcx24_invalidate_display(s); |
78 | 97e7df27 | blueswir1 | else
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79 | 97e7df27 | blueswir1 | tcx_invalidate_display(s); |
80 | 21206a10 | bellard | } |
81 | 21206a10 | bellard | |
82 | 5fafdf24 | ths | static void tcx_draw_line32(TCXState *s1, uint8_t *d, |
83 | f930d07e | blueswir1 | const uint8_t *s, int width) |
84 | 420557e8 | bellard | { |
85 | e80cfcfc | bellard | int x;
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86 | e80cfcfc | bellard | uint8_t val; |
87 | 8bdc2159 | ths | uint32_t *p = (uint32_t *)d; |
88 | e80cfcfc | bellard | |
89 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
90 | f930d07e | blueswir1 | val = *s++; |
91 | 8bdc2159 | ths | *p++ = s1->palette[val]; |
92 | e80cfcfc | bellard | } |
93 | 420557e8 | bellard | } |
94 | 420557e8 | bellard | |
95 | 5fafdf24 | ths | static void tcx_draw_line16(TCXState *s1, uint8_t *d, |
96 | f930d07e | blueswir1 | const uint8_t *s, int width) |
97 | e80cfcfc | bellard | { |
98 | e80cfcfc | bellard | int x;
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99 | e80cfcfc | bellard | uint8_t val; |
100 | 8bdc2159 | ths | uint16_t *p = (uint16_t *)d; |
101 | 8d5f07fa | bellard | |
102 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
103 | f930d07e | blueswir1 | val = *s++; |
104 | 8bdc2159 | ths | *p++ = s1->palette[val]; |
105 | e80cfcfc | bellard | } |
106 | e80cfcfc | bellard | } |
107 | e80cfcfc | bellard | |
108 | 5fafdf24 | ths | static void tcx_draw_line8(TCXState *s1, uint8_t *d, |
109 | f930d07e | blueswir1 | const uint8_t *s, int width) |
110 | 420557e8 | bellard | { |
111 | e80cfcfc | bellard | int x;
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112 | e80cfcfc | bellard | uint8_t val; |
113 | e80cfcfc | bellard | |
114 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
115 | f930d07e | blueswir1 | val = *s++; |
116 | 21206a10 | bellard | *d++ = s1->palette[val]; |
117 | 420557e8 | bellard | } |
118 | 420557e8 | bellard | } |
119 | 420557e8 | bellard | |
120 | 688ea2eb | blueswir1 | /*
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121 | 688ea2eb | blueswir1 | XXX Could be much more optimal:
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122 | 688ea2eb | blueswir1 | * detect if line/page/whole screen is in 24 bit mode
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123 | 688ea2eb | blueswir1 | * if destination is also BGR, use memcpy
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124 | 688ea2eb | blueswir1 | */
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125 | eee0b836 | blueswir1 | static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, |
126 | eee0b836 | blueswir1 | const uint8_t *s, int width, |
127 | eee0b836 | blueswir1 | const uint32_t *cplane,
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128 | eee0b836 | blueswir1 | const uint32_t *s24)
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129 | eee0b836 | blueswir1 | { |
130 | 7b5d76da | aliguori | int x, bgr, r, g, b;
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131 | 688ea2eb | blueswir1 | uint8_t val, *p8; |
132 | eee0b836 | blueswir1 | uint32_t *p = (uint32_t *)d; |
133 | eee0b836 | blueswir1 | uint32_t dval; |
134 | eee0b836 | blueswir1 | |
135 | 7b5d76da | aliguori | bgr = is_surface_bgr(s1->ds->surface); |
136 | eee0b836 | blueswir1 | for(x = 0; x < width; x++, s++, s24++) { |
137 | 688ea2eb | blueswir1 | if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) { |
138 | 688ea2eb | blueswir1 | // 24-bit direct, BGR order
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139 | 688ea2eb | blueswir1 | p8 = (uint8_t *)s24; |
140 | 688ea2eb | blueswir1 | p8++; |
141 | 688ea2eb | blueswir1 | b = *p8++; |
142 | 688ea2eb | blueswir1 | g = *p8++; |
143 | 688ea2eb | blueswir1 | r = *p8++; |
144 | 7b5d76da | aliguori | if (bgr)
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145 | 7b5d76da | aliguori | dval = rgb_to_pixel32bgr(r, g, b); |
146 | 7b5d76da | aliguori | else
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147 | 7b5d76da | aliguori | dval = rgb_to_pixel32(r, g, b); |
148 | eee0b836 | blueswir1 | } else {
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149 | eee0b836 | blueswir1 | val = *s; |
150 | eee0b836 | blueswir1 | dval = s1->palette[val]; |
151 | eee0b836 | blueswir1 | } |
152 | eee0b836 | blueswir1 | *p++ = dval; |
153 | eee0b836 | blueswir1 | } |
154 | eee0b836 | blueswir1 | } |
155 | eee0b836 | blueswir1 | |
156 | 22548760 | blueswir1 | static inline int check_dirty(ram_addr_t page, ram_addr_t page24, |
157 | eee0b836 | blueswir1 | ram_addr_t cpage) |
158 | eee0b836 | blueswir1 | { |
159 | eee0b836 | blueswir1 | int ret;
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160 | eee0b836 | blueswir1 | unsigned int off; |
161 | eee0b836 | blueswir1 | |
162 | eee0b836 | blueswir1 | ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG); |
163 | eee0b836 | blueswir1 | for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) { |
164 | eee0b836 | blueswir1 | ret |= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG); |
165 | eee0b836 | blueswir1 | ret |= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG); |
166 | eee0b836 | blueswir1 | } |
167 | eee0b836 | blueswir1 | return ret;
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168 | eee0b836 | blueswir1 | } |
169 | eee0b836 | blueswir1 | |
170 | eee0b836 | blueswir1 | static inline void reset_dirty(TCXState *ts, ram_addr_t page_min, |
171 | eee0b836 | blueswir1 | ram_addr_t page_max, ram_addr_t page24, |
172 | eee0b836 | blueswir1 | ram_addr_t cpage) |
173 | eee0b836 | blueswir1 | { |
174 | eee0b836 | blueswir1 | cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
175 | eee0b836 | blueswir1 | VGA_DIRTY_FLAG); |
176 | eee0b836 | blueswir1 | page_min -= ts->vram_offset; |
177 | eee0b836 | blueswir1 | page_max -= ts->vram_offset; |
178 | eee0b836 | blueswir1 | cpu_physical_memory_reset_dirty(page24 + page_min * 4,
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179 | eee0b836 | blueswir1 | page24 + page_max * 4 + TARGET_PAGE_SIZE,
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180 | eee0b836 | blueswir1 | VGA_DIRTY_FLAG); |
181 | eee0b836 | blueswir1 | cpu_physical_memory_reset_dirty(cpage + page_min * 4,
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182 | eee0b836 | blueswir1 | cpage + page_max * 4 + TARGET_PAGE_SIZE,
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183 | eee0b836 | blueswir1 | VGA_DIRTY_FLAG); |
184 | eee0b836 | blueswir1 | } |
185 | eee0b836 | blueswir1 | |
186 | e80cfcfc | bellard | /* Fixed line length 1024 allows us to do nice tricks not possible on
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187 | e80cfcfc | bellard | VGA... */
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188 | 95219897 | pbrook | static void tcx_update_display(void *opaque) |
189 | 420557e8 | bellard | { |
190 | e80cfcfc | bellard | TCXState *ts = opaque; |
191 | 550be127 | bellard | ram_addr_t page, page_min, page_max; |
192 | 550be127 | bellard | int y, y_start, dd, ds;
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193 | e80cfcfc | bellard | uint8_t *d, *s; |
194 | b3ceef24 | blueswir1 | void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); |
195 | e80cfcfc | bellard | |
196 | 0e1f5a0c | aliguori | if (ds_get_bits_per_pixel(ts->ds) == 0) |
197 | f930d07e | blueswir1 | return;
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198 | 6f7e9aec | bellard | page = ts->vram_offset; |
199 | e80cfcfc | bellard | y_start = -1;
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200 | 550be127 | bellard | page_min = 0xffffffff;
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201 | 550be127 | bellard | page_max = 0;
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202 | 0e1f5a0c | aliguori | d = ds_get_data(ts->ds); |
203 | 6f7e9aec | bellard | s = ts->vram; |
204 | 0e1f5a0c | aliguori | dd = ds_get_linesize(ts->ds); |
205 | e80cfcfc | bellard | ds = 1024;
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206 | e80cfcfc | bellard | |
207 | 0e1f5a0c | aliguori | switch (ds_get_bits_per_pixel(ts->ds)) {
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208 | e80cfcfc | bellard | case 32: |
209 | f930d07e | blueswir1 | f = tcx_draw_line32; |
210 | f930d07e | blueswir1 | break;
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211 | 21206a10 | bellard | case 15: |
212 | 21206a10 | bellard | case 16: |
213 | f930d07e | blueswir1 | f = tcx_draw_line16; |
214 | f930d07e | blueswir1 | break;
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215 | e80cfcfc | bellard | default:
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216 | e80cfcfc | bellard | case 8: |
217 | f930d07e | blueswir1 | f = tcx_draw_line8; |
218 | f930d07e | blueswir1 | break;
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219 | e80cfcfc | bellard | case 0: |
220 | f930d07e | blueswir1 | return;
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221 | e80cfcfc | bellard | } |
222 | 3b46e624 | ths | |
223 | 6f7e9aec | bellard | for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { |
224 | f930d07e | blueswir1 | if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
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225 | f930d07e | blueswir1 | if (y_start < 0) |
226 | e80cfcfc | bellard | y_start = y; |
227 | e80cfcfc | bellard | if (page < page_min)
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228 | e80cfcfc | bellard | page_min = page; |
229 | e80cfcfc | bellard | if (page > page_max)
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230 | e80cfcfc | bellard | page_max = page; |
231 | f930d07e | blueswir1 | f(ts, d, s, ts->width); |
232 | f930d07e | blueswir1 | d += dd; |
233 | f930d07e | blueswir1 | s += ds; |
234 | f930d07e | blueswir1 | f(ts, d, s, ts->width); |
235 | f930d07e | blueswir1 | d += dd; |
236 | f930d07e | blueswir1 | s += ds; |
237 | f930d07e | blueswir1 | f(ts, d, s, ts->width); |
238 | f930d07e | blueswir1 | d += dd; |
239 | f930d07e | blueswir1 | s += ds; |
240 | f930d07e | blueswir1 | f(ts, d, s, ts->width); |
241 | f930d07e | blueswir1 | d += dd; |
242 | f930d07e | blueswir1 | s += ds; |
243 | f930d07e | blueswir1 | } else {
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244 | e80cfcfc | bellard | if (y_start >= 0) { |
245 | e80cfcfc | bellard | /* flush to display */
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246 | 5fafdf24 | ths | dpy_update(ts->ds, 0, y_start,
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247 | 6f7e9aec | bellard | ts->width, y - y_start); |
248 | e80cfcfc | bellard | y_start = -1;
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249 | e80cfcfc | bellard | } |
250 | f930d07e | blueswir1 | d += dd * 4;
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251 | f930d07e | blueswir1 | s += ds * 4;
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252 | f930d07e | blueswir1 | } |
253 | e80cfcfc | bellard | } |
254 | e80cfcfc | bellard | if (y_start >= 0) { |
255 | f930d07e | blueswir1 | /* flush to display */
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256 | f930d07e | blueswir1 | dpy_update(ts->ds, 0, y_start,
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257 | f930d07e | blueswir1 | ts->width, y - y_start); |
258 | e80cfcfc | bellard | } |
259 | e80cfcfc | bellard | /* reset modified pages */
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260 | 550be127 | bellard | if (page_min <= page_max) {
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261 | 0a962c02 | bellard | cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
262 | 0a962c02 | bellard | VGA_DIRTY_FLAG); |
263 | e80cfcfc | bellard | } |
264 | 420557e8 | bellard | } |
265 | 420557e8 | bellard | |
266 | eee0b836 | blueswir1 | static void tcx24_update_display(void *opaque) |
267 | eee0b836 | blueswir1 | { |
268 | eee0b836 | blueswir1 | TCXState *ts = opaque; |
269 | eee0b836 | blueswir1 | ram_addr_t page, page_min, page_max, cpage, page24; |
270 | eee0b836 | blueswir1 | int y, y_start, dd, ds;
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271 | eee0b836 | blueswir1 | uint8_t *d, *s; |
272 | eee0b836 | blueswir1 | uint32_t *cptr, *s24; |
273 | eee0b836 | blueswir1 | |
274 | 0e1f5a0c | aliguori | if (ds_get_bits_per_pixel(ts->ds) != 32) |
275 | eee0b836 | blueswir1 | return;
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276 | eee0b836 | blueswir1 | page = ts->vram_offset; |
277 | eee0b836 | blueswir1 | page24 = ts->vram24_offset; |
278 | eee0b836 | blueswir1 | cpage = ts->cplane_offset; |
279 | eee0b836 | blueswir1 | y_start = -1;
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280 | eee0b836 | blueswir1 | page_min = 0xffffffff;
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281 | eee0b836 | blueswir1 | page_max = 0;
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282 | 0e1f5a0c | aliguori | d = ds_get_data(ts->ds); |
283 | eee0b836 | blueswir1 | s = ts->vram; |
284 | eee0b836 | blueswir1 | s24 = ts->vram24; |
285 | eee0b836 | blueswir1 | cptr = ts->cplane; |
286 | 0e1f5a0c | aliguori | dd = ds_get_linesize(ts->ds); |
287 | eee0b836 | blueswir1 | ds = 1024;
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288 | eee0b836 | blueswir1 | |
289 | eee0b836 | blueswir1 | for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE, |
290 | eee0b836 | blueswir1 | page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) { |
291 | 22548760 | blueswir1 | if (check_dirty(page, page24, cpage)) {
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292 | eee0b836 | blueswir1 | if (y_start < 0) |
293 | eee0b836 | blueswir1 | y_start = y; |
294 | eee0b836 | blueswir1 | if (page < page_min)
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295 | eee0b836 | blueswir1 | page_min = page; |
296 | eee0b836 | blueswir1 | if (page > page_max)
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297 | eee0b836 | blueswir1 | page_max = page; |
298 | eee0b836 | blueswir1 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
299 | eee0b836 | blueswir1 | d += dd; |
300 | eee0b836 | blueswir1 | s += ds; |
301 | eee0b836 | blueswir1 | cptr += ds; |
302 | eee0b836 | blueswir1 | s24 += ds; |
303 | eee0b836 | blueswir1 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
304 | eee0b836 | blueswir1 | d += dd; |
305 | eee0b836 | blueswir1 | s += ds; |
306 | eee0b836 | blueswir1 | cptr += ds; |
307 | eee0b836 | blueswir1 | s24 += ds; |
308 | eee0b836 | blueswir1 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
309 | eee0b836 | blueswir1 | d += dd; |
310 | eee0b836 | blueswir1 | s += ds; |
311 | eee0b836 | blueswir1 | cptr += ds; |
312 | eee0b836 | blueswir1 | s24 += ds; |
313 | eee0b836 | blueswir1 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
314 | eee0b836 | blueswir1 | d += dd; |
315 | eee0b836 | blueswir1 | s += ds; |
316 | eee0b836 | blueswir1 | cptr += ds; |
317 | eee0b836 | blueswir1 | s24 += ds; |
318 | eee0b836 | blueswir1 | } else {
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319 | eee0b836 | blueswir1 | if (y_start >= 0) { |
320 | eee0b836 | blueswir1 | /* flush to display */
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321 | eee0b836 | blueswir1 | dpy_update(ts->ds, 0, y_start,
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322 | eee0b836 | blueswir1 | ts->width, y - y_start); |
323 | eee0b836 | blueswir1 | y_start = -1;
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324 | eee0b836 | blueswir1 | } |
325 | eee0b836 | blueswir1 | d += dd * 4;
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326 | eee0b836 | blueswir1 | s += ds * 4;
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327 | eee0b836 | blueswir1 | cptr += ds * 4;
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328 | eee0b836 | blueswir1 | s24 += ds * 4;
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329 | eee0b836 | blueswir1 | } |
330 | eee0b836 | blueswir1 | } |
331 | eee0b836 | blueswir1 | if (y_start >= 0) { |
332 | eee0b836 | blueswir1 | /* flush to display */
|
333 | eee0b836 | blueswir1 | dpy_update(ts->ds, 0, y_start,
|
334 | eee0b836 | blueswir1 | ts->width, y - y_start); |
335 | eee0b836 | blueswir1 | } |
336 | eee0b836 | blueswir1 | /* reset modified pages */
|
337 | eee0b836 | blueswir1 | if (page_min <= page_max) {
|
338 | eee0b836 | blueswir1 | reset_dirty(ts, page_min, page_max, page24, cpage); |
339 | eee0b836 | blueswir1 | } |
340 | eee0b836 | blueswir1 | } |
341 | eee0b836 | blueswir1 | |
342 | 95219897 | pbrook | static void tcx_invalidate_display(void *opaque) |
343 | 420557e8 | bellard | { |
344 | e80cfcfc | bellard | TCXState *s = opaque; |
345 | e80cfcfc | bellard | int i;
|
346 | e80cfcfc | bellard | |
347 | e80cfcfc | bellard | for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) { |
348 | f930d07e | blueswir1 | cpu_physical_memory_set_dirty(s->vram_offset + i); |
349 | e80cfcfc | bellard | } |
350 | 420557e8 | bellard | } |
351 | 420557e8 | bellard | |
352 | eee0b836 | blueswir1 | static void tcx24_invalidate_display(void *opaque) |
353 | eee0b836 | blueswir1 | { |
354 | eee0b836 | blueswir1 | TCXState *s = opaque; |
355 | eee0b836 | blueswir1 | int i;
|
356 | eee0b836 | blueswir1 | |
357 | eee0b836 | blueswir1 | tcx_invalidate_display(s); |
358 | eee0b836 | blueswir1 | for (i = 0; i < MAXX*MAXY * 4; i += TARGET_PAGE_SIZE) { |
359 | eee0b836 | blueswir1 | cpu_physical_memory_set_dirty(s->vram24_offset + i); |
360 | eee0b836 | blueswir1 | cpu_physical_memory_set_dirty(s->cplane_offset + i); |
361 | eee0b836 | blueswir1 | } |
362 | eee0b836 | blueswir1 | } |
363 | eee0b836 | blueswir1 | |
364 | e80cfcfc | bellard | static void tcx_save(QEMUFile *f, void *opaque) |
365 | 420557e8 | bellard | { |
366 | 420557e8 | bellard | TCXState *s = opaque; |
367 | 3b46e624 | ths | |
368 | b6c4f71f | blueswir1 | qemu_put_be16s(f, &s->height); |
369 | b6c4f71f | blueswir1 | qemu_put_be16s(f, &s->width); |
370 | b6c4f71f | blueswir1 | qemu_put_be16s(f, &s->depth); |
371 | e80cfcfc | bellard | qemu_put_buffer(f, s->r, 256);
|
372 | e80cfcfc | bellard | qemu_put_buffer(f, s->g, 256);
|
373 | e80cfcfc | bellard | qemu_put_buffer(f, s->b, 256);
|
374 | 6f7e9aec | bellard | qemu_put_8s(f, &s->dac_index); |
375 | 6f7e9aec | bellard | qemu_put_8s(f, &s->dac_state); |
376 | 420557e8 | bellard | } |
377 | 420557e8 | bellard | |
378 | e80cfcfc | bellard | static int tcx_load(QEMUFile *f, void *opaque, int version_id) |
379 | 420557e8 | bellard | { |
380 | e80cfcfc | bellard | TCXState *s = opaque; |
381 | fda77c2d | blueswir1 | uint32_t dummy; |
382 | fda77c2d | blueswir1 | |
383 | fda77c2d | blueswir1 | if (version_id != 3 && version_id != 4) |
384 | e80cfcfc | bellard | return -EINVAL;
|
385 | e80cfcfc | bellard | |
386 | fda77c2d | blueswir1 | if (version_id == 3) { |
387 | b6c4f71f | blueswir1 | qemu_get_be32s(f, &dummy); |
388 | b6c4f71f | blueswir1 | qemu_get_be32s(f, &dummy); |
389 | b6c4f71f | blueswir1 | qemu_get_be32s(f, &dummy); |
390 | fda77c2d | blueswir1 | } |
391 | b6c4f71f | blueswir1 | qemu_get_be16s(f, &s->height); |
392 | b6c4f71f | blueswir1 | qemu_get_be16s(f, &s->width); |
393 | b6c4f71f | blueswir1 | qemu_get_be16s(f, &s->depth); |
394 | e80cfcfc | bellard | qemu_get_buffer(f, s->r, 256);
|
395 | e80cfcfc | bellard | qemu_get_buffer(f, s->g, 256);
|
396 | e80cfcfc | bellard | qemu_get_buffer(f, s->b, 256);
|
397 | 6f7e9aec | bellard | qemu_get_8s(f, &s->dac_index); |
398 | 6f7e9aec | bellard | qemu_get_8s(f, &s->dac_state); |
399 | 21206a10 | bellard | update_palette_entries(s, 0, 256); |
400 | 97e7df27 | blueswir1 | if (s->depth == 24) |
401 | 97e7df27 | blueswir1 | tcx24_invalidate_display(s); |
402 | 97e7df27 | blueswir1 | else
|
403 | 97e7df27 | blueswir1 | tcx_invalidate_display(s); |
404 | 5425a216 | blueswir1 | |
405 | e80cfcfc | bellard | return 0; |
406 | 420557e8 | bellard | } |
407 | 420557e8 | bellard | |
408 | e80cfcfc | bellard | static void tcx_reset(void *opaque) |
409 | 420557e8 | bellard | { |
410 | e80cfcfc | bellard | TCXState *s = opaque; |
411 | e80cfcfc | bellard | |
412 | e80cfcfc | bellard | /* Initialize palette */
|
413 | e80cfcfc | bellard | memset(s->r, 0, 256); |
414 | e80cfcfc | bellard | memset(s->g, 0, 256); |
415 | e80cfcfc | bellard | memset(s->b, 0, 256); |
416 | e80cfcfc | bellard | s->r[255] = s->g[255] = s->b[255] = 255; |
417 | 21206a10 | bellard | update_palette_entries(s, 0, 256); |
418 | e80cfcfc | bellard | memset(s->vram, 0, MAXX*MAXY);
|
419 | eee0b836 | blueswir1 | cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset + |
420 | eee0b836 | blueswir1 | MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG); |
421 | 6f7e9aec | bellard | s->dac_index = 0;
|
422 | 6f7e9aec | bellard | s->dac_state = 0;
|
423 | 6f7e9aec | bellard | } |
424 | 6f7e9aec | bellard | |
425 | 6f7e9aec | bellard | static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr) |
426 | 6f7e9aec | bellard | { |
427 | 6f7e9aec | bellard | return 0; |
428 | 6f7e9aec | bellard | } |
429 | 6f7e9aec | bellard | |
430 | 6f7e9aec | bellard | static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
431 | 6f7e9aec | bellard | { |
432 | 6f7e9aec | bellard | TCXState *s = opaque; |
433 | 6f7e9aec | bellard | |
434 | e64d7d59 | blueswir1 | switch (addr) {
|
435 | 6f7e9aec | bellard | case 0: |
436 | f930d07e | blueswir1 | s->dac_index = val >> 24;
|
437 | f930d07e | blueswir1 | s->dac_state = 0;
|
438 | f930d07e | blueswir1 | break;
|
439 | e64d7d59 | blueswir1 | case 4: |
440 | f930d07e | blueswir1 | switch (s->dac_state) {
|
441 | f930d07e | blueswir1 | case 0: |
442 | f930d07e | blueswir1 | s->r[s->dac_index] = val >> 24;
|
443 | 21206a10 | bellard | update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
444 | f930d07e | blueswir1 | s->dac_state++; |
445 | f930d07e | blueswir1 | break;
|
446 | f930d07e | blueswir1 | case 1: |
447 | f930d07e | blueswir1 | s->g[s->dac_index] = val >> 24;
|
448 | 21206a10 | bellard | update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
449 | f930d07e | blueswir1 | s->dac_state++; |
450 | f930d07e | blueswir1 | break;
|
451 | f930d07e | blueswir1 | case 2: |
452 | f930d07e | blueswir1 | s->b[s->dac_index] = val >> 24;
|
453 | 21206a10 | bellard | update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
454 | 5c8cdbf8 | blueswir1 | s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement |
455 | f930d07e | blueswir1 | default:
|
456 | f930d07e | blueswir1 | s->dac_state = 0;
|
457 | f930d07e | blueswir1 | break;
|
458 | f930d07e | blueswir1 | } |
459 | f930d07e | blueswir1 | break;
|
460 | 6f7e9aec | bellard | default:
|
461 | f930d07e | blueswir1 | break;
|
462 | 6f7e9aec | bellard | } |
463 | 6f7e9aec | bellard | return;
|
464 | 420557e8 | bellard | } |
465 | 420557e8 | bellard | |
466 | 6f7e9aec | bellard | static CPUReadMemoryFunc *tcx_dac_read[3] = { |
467 | 7c560456 | blueswir1 | NULL,
|
468 | 7c560456 | blueswir1 | NULL,
|
469 | 6f7e9aec | bellard | tcx_dac_readl, |
470 | 6f7e9aec | bellard | }; |
471 | 6f7e9aec | bellard | |
472 | 6f7e9aec | bellard | static CPUWriteMemoryFunc *tcx_dac_write[3] = { |
473 | 7c560456 | blueswir1 | NULL,
|
474 | 7c560456 | blueswir1 | NULL,
|
475 | 6f7e9aec | bellard | tcx_dac_writel, |
476 | 6f7e9aec | bellard | }; |
477 | 6f7e9aec | bellard | |
478 | 8508b89e | blueswir1 | static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr) |
479 | 8508b89e | blueswir1 | { |
480 | 8508b89e | blueswir1 | return 0; |
481 | 8508b89e | blueswir1 | } |
482 | 8508b89e | blueswir1 | |
483 | 8508b89e | blueswir1 | static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr, |
484 | 8508b89e | blueswir1 | uint32_t val) |
485 | 8508b89e | blueswir1 | { |
486 | 8508b89e | blueswir1 | } |
487 | 8508b89e | blueswir1 | |
488 | 8508b89e | blueswir1 | static CPUReadMemoryFunc *tcx_dummy_read[3] = { |
489 | 7c560456 | blueswir1 | NULL,
|
490 | 7c560456 | blueswir1 | NULL,
|
491 | 8508b89e | blueswir1 | tcx_dummy_readl, |
492 | 8508b89e | blueswir1 | }; |
493 | 8508b89e | blueswir1 | |
494 | 8508b89e | blueswir1 | static CPUWriteMemoryFunc *tcx_dummy_write[3] = { |
495 | 7c560456 | blueswir1 | NULL,
|
496 | 7c560456 | blueswir1 | NULL,
|
497 | 8508b89e | blueswir1 | tcx_dummy_writel, |
498 | 8508b89e | blueswir1 | }; |
499 | 8508b89e | blueswir1 | |
500 | 3023f332 | aliguori | void tcx_init(target_phys_addr_t addr, uint8_t *vram_base,
|
501 | eee0b836 | blueswir1 | unsigned long vram_offset, int vram_size, int width, int height, |
502 | eee0b836 | blueswir1 | int depth)
|
503 | 420557e8 | bellard | { |
504 | 420557e8 | bellard | TCXState *s; |
505 | 8508b89e | blueswir1 | int io_memory, dummy_memory;
|
506 | eee0b836 | blueswir1 | int size;
|
507 | 420557e8 | bellard | |
508 | 420557e8 | bellard | s = qemu_mallocz(sizeof(TCXState));
|
509 | 8d5f07fa | bellard | s->addr = addr; |
510 | e80cfcfc | bellard | s->vram_offset = vram_offset; |
511 | 6f7e9aec | bellard | s->width = width; |
512 | 6f7e9aec | bellard | s->height = height; |
513 | eee0b836 | blueswir1 | s->depth = depth; |
514 | eee0b836 | blueswir1 | |
515 | eee0b836 | blueswir1 | // 8-bit plane
|
516 | eee0b836 | blueswir1 | s->vram = vram_base; |
517 | eee0b836 | blueswir1 | size = vram_size; |
518 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x00800000ULL, size, vram_offset);
|
519 | eee0b836 | blueswir1 | vram_offset += size; |
520 | eee0b836 | blueswir1 | vram_base += size; |
521 | e80cfcfc | bellard | |
522 | 6f7e9aec | bellard | io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
|
523 | 77f193da | blueswir1 | cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS,
|
524 | 77f193da | blueswir1 | io_memory); |
525 | eee0b836 | blueswir1 | |
526 | 8508b89e | blueswir1 | dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write,
|
527 | 8508b89e | blueswir1 | s); |
528 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x00700000ULL, TCX_TEC_NREGS,
|
529 | 8508b89e | blueswir1 | dummy_memory); |
530 | eee0b836 | blueswir1 | if (depth == 24) { |
531 | eee0b836 | blueswir1 | // 24-bit plane
|
532 | eee0b836 | blueswir1 | size = vram_size * 4;
|
533 | eee0b836 | blueswir1 | s->vram24 = (uint32_t *)vram_base; |
534 | eee0b836 | blueswir1 | s->vram24_offset = vram_offset; |
535 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x02000000ULL, size, vram_offset);
|
536 | eee0b836 | blueswir1 | vram_offset += size; |
537 | eee0b836 | blueswir1 | vram_base += size; |
538 | eee0b836 | blueswir1 | |
539 | eee0b836 | blueswir1 | // Control plane
|
540 | eee0b836 | blueswir1 | size = vram_size * 4;
|
541 | eee0b836 | blueswir1 | s->cplane = (uint32_t *)vram_base; |
542 | eee0b836 | blueswir1 | s->cplane_offset = vram_offset; |
543 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset);
|
544 | 3023f332 | aliguori | s->ds = graphic_console_init(tcx24_update_display, |
545 | 3023f332 | aliguori | tcx24_invalidate_display, |
546 | 3023f332 | aliguori | tcx24_screen_dump, NULL, s);
|
547 | eee0b836 | blueswir1 | } else {
|
548 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8,
|
549 | 8508b89e | blueswir1 | dummy_memory); |
550 | 3023f332 | aliguori | s->ds = graphic_console_init(tcx_update_display, |
551 | 3023f332 | aliguori | tcx_invalidate_display, |
552 | 3023f332 | aliguori | tcx_screen_dump, NULL, s);
|
553 | eee0b836 | blueswir1 | } |
554 | f96f4c9d | blueswir1 | // NetBSD writes here even with 8-bit display
|
555 | 5dcb6b91 | blueswir1 | cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24,
|
556 | f96f4c9d | blueswir1 | dummy_memory); |
557 | e80cfcfc | bellard | |
558 | fda77c2d | blueswir1 | register_savevm("tcx", addr, 4, tcx_save, tcx_load, s); |
559 | e80cfcfc | bellard | qemu_register_reset(tcx_reset, s); |
560 | e80cfcfc | bellard | tcx_reset(s); |
561 | 3023f332 | aliguori | qemu_console_resize(s->ds, width, height); |
562 | 420557e8 | bellard | } |
563 | 420557e8 | bellard | |
564 | 95219897 | pbrook | static void tcx_screen_dump(void *opaque, const char *filename) |
565 | 8d5f07fa | bellard | { |
566 | e80cfcfc | bellard | TCXState *s = opaque; |
567 | 8d5f07fa | bellard | FILE *f; |
568 | e80cfcfc | bellard | uint8_t *d, *d1, v; |
569 | 8d5f07fa | bellard | int y, x;
|
570 | 8d5f07fa | bellard | |
571 | 8d5f07fa | bellard | f = fopen(filename, "wb");
|
572 | 8d5f07fa | bellard | if (!f)
|
573 | e80cfcfc | bellard | return;
|
574 | 6f7e9aec | bellard | fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
575 | 6f7e9aec | bellard | d1 = s->vram; |
576 | 6f7e9aec | bellard | for(y = 0; y < s->height; y++) { |
577 | 8d5f07fa | bellard | d = d1; |
578 | 6f7e9aec | bellard | for(x = 0; x < s->width; x++) { |
579 | 8d5f07fa | bellard | v = *d; |
580 | e80cfcfc | bellard | fputc(s->r[v], f); |
581 | e80cfcfc | bellard | fputc(s->g[v], f); |
582 | e80cfcfc | bellard | fputc(s->b[v], f); |
583 | 8d5f07fa | bellard | d++; |
584 | 8d5f07fa | bellard | } |
585 | e80cfcfc | bellard | d1 += MAXX; |
586 | 8d5f07fa | bellard | } |
587 | 8d5f07fa | bellard | fclose(f); |
588 | 8d5f07fa | bellard | return;
|
589 | 8d5f07fa | bellard | } |
590 | 8d5f07fa | bellard | |
591 | eee0b836 | blueswir1 | static void tcx24_screen_dump(void *opaque, const char *filename) |
592 | eee0b836 | blueswir1 | { |
593 | eee0b836 | blueswir1 | TCXState *s = opaque; |
594 | eee0b836 | blueswir1 | FILE *f; |
595 | eee0b836 | blueswir1 | uint8_t *d, *d1, v; |
596 | eee0b836 | blueswir1 | uint32_t *s24, *cptr, dval; |
597 | eee0b836 | blueswir1 | int y, x;
|
598 | 8d5f07fa | bellard | |
599 | eee0b836 | blueswir1 | f = fopen(filename, "wb");
|
600 | eee0b836 | blueswir1 | if (!f)
|
601 | eee0b836 | blueswir1 | return;
|
602 | eee0b836 | blueswir1 | fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
603 | eee0b836 | blueswir1 | d1 = s->vram; |
604 | eee0b836 | blueswir1 | s24 = s->vram24; |
605 | eee0b836 | blueswir1 | cptr = s->cplane; |
606 | eee0b836 | blueswir1 | for(y = 0; y < s->height; y++) { |
607 | eee0b836 | blueswir1 | d = d1; |
608 | eee0b836 | blueswir1 | for(x = 0; x < s->width; x++, d++, s24++) { |
609 | eee0b836 | blueswir1 | if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct |
610 | eee0b836 | blueswir1 | dval = *s24 & 0x00ffffff;
|
611 | eee0b836 | blueswir1 | fputc((dval >> 16) & 0xff, f); |
612 | eee0b836 | blueswir1 | fputc((dval >> 8) & 0xff, f); |
613 | eee0b836 | blueswir1 | fputc(dval & 0xff, f);
|
614 | eee0b836 | blueswir1 | } else {
|
615 | eee0b836 | blueswir1 | v = *d; |
616 | eee0b836 | blueswir1 | fputc(s->r[v], f); |
617 | eee0b836 | blueswir1 | fputc(s->g[v], f); |
618 | eee0b836 | blueswir1 | fputc(s->b[v], f); |
619 | eee0b836 | blueswir1 | } |
620 | eee0b836 | blueswir1 | } |
621 | eee0b836 | blueswir1 | d1 += MAXX; |
622 | eee0b836 | blueswir1 | } |
623 | eee0b836 | blueswir1 | fclose(f); |
624 | eee0b836 | blueswir1 | return;
|
625 | eee0b836 | blueswir1 | } |