root / hw / lan9118.c @ f79f2bfc
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1 | 2a424990 | Paul Brook | /*
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2 | 2a424990 | Paul Brook | * SMSC LAN9118 Ethernet interface emulation
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3 | 2a424990 | Paul Brook | *
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4 | 2a424990 | Paul Brook | * Copyright (c) 2009 CodeSourcery, LLC.
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5 | 2a424990 | Paul Brook | * Written by Paul Brook
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6 | 2a424990 | Paul Brook | *
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7 | 8e31bf38 | Matthew Fernandez | * This code is licensed under the GNU GPL v2
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8 | 6b620ca3 | Paolo Bonzini | *
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9 | 6b620ca3 | Paolo Bonzini | * Contributions after 2012-01-13 are licensed under the terms of the
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10 | 6b620ca3 | Paolo Bonzini | * GNU GPL, version 2 or (at your option) any later version.
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11 | 2a424990 | Paul Brook | */
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12 | 2a424990 | Paul Brook | |
13 | 2a424990 | Paul Brook | #include "sysbus.h" |
14 | 2a424990 | Paul Brook | #include "net.h" |
15 | 2a424990 | Paul Brook | #include "devices.h" |
16 | 666daa68 | Markus Armbruster | #include "sysemu.h" |
17 | 49d4d9b6 | Paolo Bonzini | #include "ptimer.h" |
18 | 2a424990 | Paul Brook | /* For crc32 */
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19 | 2a424990 | Paul Brook | #include <zlib.h> |
20 | 2a424990 | Paul Brook | |
21 | 2a424990 | Paul Brook | //#define DEBUG_LAN9118
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22 | 2a424990 | Paul Brook | |
23 | 2a424990 | Paul Brook | #ifdef DEBUG_LAN9118
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24 | 2a424990 | Paul Brook | #define DPRINTF(fmt, ...) \
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25 | 2a424990 | Paul Brook | do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0) |
26 | 2a424990 | Paul Brook | #define BADF(fmt, ...) \
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27 | 2a424990 | Paul Brook | do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0) |
28 | 2a424990 | Paul Brook | #else
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29 | 2a424990 | Paul Brook | #define DPRINTF(fmt, ...) do {} while(0) |
30 | 2a424990 | Paul Brook | #define BADF(fmt, ...) \
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31 | 2a424990 | Paul Brook | do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0) |
32 | 2a424990 | Paul Brook | #endif
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33 | 2a424990 | Paul Brook | |
34 | 2a424990 | Paul Brook | #define CSR_ID_REV 0x50 |
35 | 2a424990 | Paul Brook | #define CSR_IRQ_CFG 0x54 |
36 | 2a424990 | Paul Brook | #define CSR_INT_STS 0x58 |
37 | 2a424990 | Paul Brook | #define CSR_INT_EN 0x5c |
38 | 2a424990 | Paul Brook | #define CSR_BYTE_TEST 0x64 |
39 | 2a424990 | Paul Brook | #define CSR_FIFO_INT 0x68 |
40 | 2a424990 | Paul Brook | #define CSR_RX_CFG 0x6c |
41 | 2a424990 | Paul Brook | #define CSR_TX_CFG 0x70 |
42 | 2a424990 | Paul Brook | #define CSR_HW_CFG 0x74 |
43 | 2a424990 | Paul Brook | #define CSR_RX_DP_CTRL 0x78 |
44 | 2a424990 | Paul Brook | #define CSR_RX_FIFO_INF 0x7c |
45 | 2a424990 | Paul Brook | #define CSR_TX_FIFO_INF 0x80 |
46 | 2a424990 | Paul Brook | #define CSR_PMT_CTRL 0x84 |
47 | 2a424990 | Paul Brook | #define CSR_GPIO_CFG 0x88 |
48 | 209bf965 | Paul Brook | #define CSR_GPT_CFG 0x8c |
49 | 209bf965 | Paul Brook | #define CSR_GPT_CNT 0x90 |
50 | 2a424990 | Paul Brook | #define CSR_WORD_SWAP 0x98 |
51 | 2a424990 | Paul Brook | #define CSR_FREE_RUN 0x9c |
52 | 2a424990 | Paul Brook | #define CSR_RX_DROP 0xa0 |
53 | 2a424990 | Paul Brook | #define CSR_MAC_CSR_CMD 0xa4 |
54 | 2a424990 | Paul Brook | #define CSR_MAC_CSR_DATA 0xa8 |
55 | 2a424990 | Paul Brook | #define CSR_AFC_CFG 0xac |
56 | 2a424990 | Paul Brook | #define CSR_E2P_CMD 0xb0 |
57 | 2a424990 | Paul Brook | #define CSR_E2P_DATA 0xb4 |
58 | 2a424990 | Paul Brook | |
59 | 2a424990 | Paul Brook | /* IRQ_CFG */
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60 | 209bf965 | Paul Brook | #define IRQ_INT 0x00001000 |
61 | 2a424990 | Paul Brook | #define IRQ_EN 0x00000100 |
62 | 2a424990 | Paul Brook | #define IRQ_POL 0x00000010 |
63 | 2a424990 | Paul Brook | #define IRQ_TYPE 0x00000001 |
64 | 2a424990 | Paul Brook | |
65 | 2a424990 | Paul Brook | /* INT_STS/INT_EN */
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66 | 2a424990 | Paul Brook | #define SW_INT 0x80000000 |
67 | 2a424990 | Paul Brook | #define TXSTOP_INT 0x02000000 |
68 | 2a424990 | Paul Brook | #define RXSTOP_INT 0x01000000 |
69 | 2a424990 | Paul Brook | #define RXDFH_INT 0x00800000 |
70 | 2a424990 | Paul Brook | #define TX_IOC_INT 0x00200000 |
71 | 2a424990 | Paul Brook | #define RXD_INT 0x00100000 |
72 | 2a424990 | Paul Brook | #define GPT_INT 0x00080000 |
73 | 2a424990 | Paul Brook | #define PHY_INT 0x00040000 |
74 | 2a424990 | Paul Brook | #define PME_INT 0x00020000 |
75 | 2a424990 | Paul Brook | #define TXSO_INT 0x00010000 |
76 | 2a424990 | Paul Brook | #define RWT_INT 0x00008000 |
77 | 2a424990 | Paul Brook | #define RXE_INT 0x00004000 |
78 | 2a424990 | Paul Brook | #define TXE_INT 0x00002000 |
79 | 2a424990 | Paul Brook | #define TDFU_INT 0x00000800 |
80 | 2a424990 | Paul Brook | #define TDFO_INT 0x00000400 |
81 | 2a424990 | Paul Brook | #define TDFA_INT 0x00000200 |
82 | 2a424990 | Paul Brook | #define TSFF_INT 0x00000100 |
83 | 2a424990 | Paul Brook | #define TSFL_INT 0x00000080 |
84 | 2a424990 | Paul Brook | #define RXDF_INT 0x00000040 |
85 | 2a424990 | Paul Brook | #define RDFL_INT 0x00000020 |
86 | 2a424990 | Paul Brook | #define RSFF_INT 0x00000010 |
87 | 2a424990 | Paul Brook | #define RSFL_INT 0x00000008 |
88 | 2a424990 | Paul Brook | #define GPIO2_INT 0x00000004 |
89 | 2a424990 | Paul Brook | #define GPIO1_INT 0x00000002 |
90 | 2a424990 | Paul Brook | #define GPIO0_INT 0x00000001 |
91 | 2a424990 | Paul Brook | #define RESERVED_INT 0x7c001000 |
92 | 2a424990 | Paul Brook | |
93 | 2a424990 | Paul Brook | #define MAC_CR 1 |
94 | 2a424990 | Paul Brook | #define MAC_ADDRH 2 |
95 | 2a424990 | Paul Brook | #define MAC_ADDRL 3 |
96 | 2a424990 | Paul Brook | #define MAC_HASHH 4 |
97 | 2a424990 | Paul Brook | #define MAC_HASHL 5 |
98 | 2a424990 | Paul Brook | #define MAC_MII_ACC 6 |
99 | 2a424990 | Paul Brook | #define MAC_MII_DATA 7 |
100 | 2a424990 | Paul Brook | #define MAC_FLOW 8 |
101 | 2a424990 | Paul Brook | #define MAC_VLAN1 9 /* TODO */ |
102 | 2a424990 | Paul Brook | #define MAC_VLAN2 10 /* TODO */ |
103 | 2a424990 | Paul Brook | #define MAC_WUFF 11 /* TODO */ |
104 | 2a424990 | Paul Brook | #define MAC_WUCSR 12 /* TODO */ |
105 | 2a424990 | Paul Brook | |
106 | 2a424990 | Paul Brook | #define MAC_CR_RXALL 0x80000000 |
107 | 2a424990 | Paul Brook | #define MAC_CR_RCVOWN 0x00800000 |
108 | 2a424990 | Paul Brook | #define MAC_CR_LOOPBK 0x00200000 |
109 | 2a424990 | Paul Brook | #define MAC_CR_FDPX 0x00100000 |
110 | 2a424990 | Paul Brook | #define MAC_CR_MCPAS 0x00080000 |
111 | 2a424990 | Paul Brook | #define MAC_CR_PRMS 0x00040000 |
112 | 2a424990 | Paul Brook | #define MAC_CR_INVFILT 0x00020000 |
113 | 2a424990 | Paul Brook | #define MAC_CR_PASSBAD 0x00010000 |
114 | 2a424990 | Paul Brook | #define MAC_CR_HO 0x00008000 |
115 | 2a424990 | Paul Brook | #define MAC_CR_HPFILT 0x00002000 |
116 | 2a424990 | Paul Brook | #define MAC_CR_LCOLL 0x00001000 |
117 | 2a424990 | Paul Brook | #define MAC_CR_BCAST 0x00000800 |
118 | 2a424990 | Paul Brook | #define MAC_CR_DISRTY 0x00000400 |
119 | 2a424990 | Paul Brook | #define MAC_CR_PADSTR 0x00000100 |
120 | 2a424990 | Paul Brook | #define MAC_CR_BOLMT 0x000000c0 |
121 | 2a424990 | Paul Brook | #define MAC_CR_DFCHK 0x00000020 |
122 | 2a424990 | Paul Brook | #define MAC_CR_TXEN 0x00000008 |
123 | 2a424990 | Paul Brook | #define MAC_CR_RXEN 0x00000004 |
124 | 2a424990 | Paul Brook | #define MAC_CR_RESERVED 0x7f404213 |
125 | 2a424990 | Paul Brook | |
126 | 209bf965 | Paul Brook | #define PHY_INT_ENERGYON 0x80 |
127 | 209bf965 | Paul Brook | #define PHY_INT_AUTONEG_COMPLETE 0x40 |
128 | 209bf965 | Paul Brook | #define PHY_INT_FAULT 0x20 |
129 | 209bf965 | Paul Brook | #define PHY_INT_DOWN 0x10 |
130 | 209bf965 | Paul Brook | #define PHY_INT_AUTONEG_LP 0x08 |
131 | 209bf965 | Paul Brook | #define PHY_INT_PARFAULT 0x04 |
132 | 209bf965 | Paul Brook | #define PHY_INT_AUTONEG_PAGE 0x02 |
133 | 209bf965 | Paul Brook | |
134 | 209bf965 | Paul Brook | #define GPT_TIMER_EN 0x20000000 |
135 | 209bf965 | Paul Brook | |
136 | 2a424990 | Paul Brook | enum tx_state {
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137 | 2a424990 | Paul Brook | TX_IDLE, |
138 | 2a424990 | Paul Brook | TX_B, |
139 | 2a424990 | Paul Brook | TX_DATA |
140 | 2a424990 | Paul Brook | }; |
141 | 2a424990 | Paul Brook | |
142 | 2a424990 | Paul Brook | typedef struct { |
143 | b09da0c3 | Peter Maydell | /* state is a tx_state but we can't put enums in VMStateDescriptions. */
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144 | b09da0c3 | Peter Maydell | uint32_t state; |
145 | 2a424990 | Paul Brook | uint32_t cmd_a; |
146 | 2a424990 | Paul Brook | uint32_t cmd_b; |
147 | b09da0c3 | Peter Maydell | int32_t buffer_size; |
148 | b09da0c3 | Peter Maydell | int32_t offset; |
149 | b09da0c3 | Peter Maydell | int32_t pad; |
150 | b09da0c3 | Peter Maydell | int32_t fifo_used; |
151 | b09da0c3 | Peter Maydell | int32_t len; |
152 | 2a424990 | Paul Brook | uint8_t data[2048];
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153 | 2a424990 | Paul Brook | } LAN9118Packet; |
154 | 2a424990 | Paul Brook | |
155 | b09da0c3 | Peter Maydell | static const VMStateDescription vmstate_lan9118_packet = { |
156 | b09da0c3 | Peter Maydell | .name = "lan9118_packet",
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157 | b09da0c3 | Peter Maydell | .version_id = 1,
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158 | b09da0c3 | Peter Maydell | .minimum_version_id = 1,
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159 | b09da0c3 | Peter Maydell | .fields = (VMStateField[]) { |
160 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(state, LAN9118Packet), |
161 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(cmd_a, LAN9118Packet), |
162 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(cmd_b, LAN9118Packet), |
163 | b09da0c3 | Peter Maydell | VMSTATE_INT32(buffer_size, LAN9118Packet), |
164 | b09da0c3 | Peter Maydell | VMSTATE_INT32(offset, LAN9118Packet), |
165 | b09da0c3 | Peter Maydell | VMSTATE_INT32(pad, LAN9118Packet), |
166 | b09da0c3 | Peter Maydell | VMSTATE_INT32(fifo_used, LAN9118Packet), |
167 | b09da0c3 | Peter Maydell | VMSTATE_INT32(len, LAN9118Packet), |
168 | b09da0c3 | Peter Maydell | VMSTATE_UINT8_ARRAY(data, LAN9118Packet, 2048),
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169 | b09da0c3 | Peter Maydell | VMSTATE_END_OF_LIST() |
170 | b09da0c3 | Peter Maydell | } |
171 | b09da0c3 | Peter Maydell | }; |
172 | b09da0c3 | Peter Maydell | |
173 | 2a424990 | Paul Brook | typedef struct { |
174 | 2a424990 | Paul Brook | SysBusDevice busdev; |
175 | 83b9f88c | Mark McLoughlin | NICState *nic; |
176 | 2a424990 | Paul Brook | NICConf conf; |
177 | 2a424990 | Paul Brook | qemu_irq irq; |
178 | f0cdd7a9 | Peter Maydell | MemoryRegion mmio; |
179 | 209bf965 | Paul Brook | ptimer_state *timer; |
180 | 2a424990 | Paul Brook | |
181 | 2a424990 | Paul Brook | uint32_t irq_cfg; |
182 | 2a424990 | Paul Brook | uint32_t int_sts; |
183 | 2a424990 | Paul Brook | uint32_t int_en; |
184 | 2a424990 | Paul Brook | uint32_t fifo_int; |
185 | 2a424990 | Paul Brook | uint32_t rx_cfg; |
186 | 2a424990 | Paul Brook | uint32_t tx_cfg; |
187 | 2a424990 | Paul Brook | uint32_t hw_cfg; |
188 | 2a424990 | Paul Brook | uint32_t pmt_ctrl; |
189 | 2a424990 | Paul Brook | uint32_t gpio_cfg; |
190 | 209bf965 | Paul Brook | uint32_t gpt_cfg; |
191 | 2a424990 | Paul Brook | uint32_t word_swap; |
192 | 2a424990 | Paul Brook | uint32_t free_timer_start; |
193 | 2a424990 | Paul Brook | uint32_t mac_cmd; |
194 | 2a424990 | Paul Brook | uint32_t mac_data; |
195 | 2a424990 | Paul Brook | uint32_t afc_cfg; |
196 | 2a424990 | Paul Brook | uint32_t e2p_cmd; |
197 | 2a424990 | Paul Brook | uint32_t e2p_data; |
198 | 2a424990 | Paul Brook | |
199 | 2a424990 | Paul Brook | uint32_t mac_cr; |
200 | 2a424990 | Paul Brook | uint32_t mac_hashh; |
201 | 2a424990 | Paul Brook | uint32_t mac_hashl; |
202 | 2a424990 | Paul Brook | uint32_t mac_mii_acc; |
203 | 2a424990 | Paul Brook | uint32_t mac_mii_data; |
204 | 2a424990 | Paul Brook | uint32_t mac_flow; |
205 | 2a424990 | Paul Brook | |
206 | 2a424990 | Paul Brook | uint32_t phy_status; |
207 | 2a424990 | Paul Brook | uint32_t phy_control; |
208 | 2a424990 | Paul Brook | uint32_t phy_advertise; |
209 | 209bf965 | Paul Brook | uint32_t phy_int; |
210 | 209bf965 | Paul Brook | uint32_t phy_int_mask; |
211 | 2a424990 | Paul Brook | |
212 | b09da0c3 | Peter Maydell | int32_t eeprom_writable; |
213 | c46a3ea0 | Blue Swirl | uint8_t eeprom[128];
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214 | 2a424990 | Paul Brook | |
215 | b09da0c3 | Peter Maydell | int32_t tx_fifo_size; |
216 | 2a424990 | Paul Brook | LAN9118Packet *txp; |
217 | 2a424990 | Paul Brook | LAN9118Packet tx_packet; |
218 | 2a424990 | Paul Brook | |
219 | b09da0c3 | Peter Maydell | int32_t tx_status_fifo_used; |
220 | b09da0c3 | Peter Maydell | int32_t tx_status_fifo_head; |
221 | 2a424990 | Paul Brook | uint32_t tx_status_fifo[512];
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222 | 2a424990 | Paul Brook | |
223 | b09da0c3 | Peter Maydell | int32_t rx_status_fifo_size; |
224 | b09da0c3 | Peter Maydell | int32_t rx_status_fifo_used; |
225 | b09da0c3 | Peter Maydell | int32_t rx_status_fifo_head; |
226 | 2a424990 | Paul Brook | uint32_t rx_status_fifo[896];
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227 | b09da0c3 | Peter Maydell | int32_t rx_fifo_size; |
228 | b09da0c3 | Peter Maydell | int32_t rx_fifo_used; |
229 | b09da0c3 | Peter Maydell | int32_t rx_fifo_head; |
230 | 2a424990 | Paul Brook | uint32_t rx_fifo[3360];
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231 | b09da0c3 | Peter Maydell | int32_t rx_packet_size_head; |
232 | b09da0c3 | Peter Maydell | int32_t rx_packet_size_tail; |
233 | b09da0c3 | Peter Maydell | int32_t rx_packet_size[1024];
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234 | 2a424990 | Paul Brook | |
235 | b09da0c3 | Peter Maydell | int32_t rxp_offset; |
236 | b09da0c3 | Peter Maydell | int32_t rxp_size; |
237 | b09da0c3 | Peter Maydell | int32_t rxp_pad; |
238 | 2a424990 | Paul Brook | } lan9118_state; |
239 | 2a424990 | Paul Brook | |
240 | b09da0c3 | Peter Maydell | static const VMStateDescription vmstate_lan9118 = { |
241 | b09da0c3 | Peter Maydell | .name = "lan9118",
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242 | b09da0c3 | Peter Maydell | .version_id = 1,
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243 | b09da0c3 | Peter Maydell | .minimum_version_id = 1,
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244 | b09da0c3 | Peter Maydell | .fields = (VMStateField[]) { |
245 | b09da0c3 | Peter Maydell | VMSTATE_PTIMER(timer, lan9118_state), |
246 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(irq_cfg, lan9118_state), |
247 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(int_sts, lan9118_state), |
248 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(int_en, lan9118_state), |
249 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(fifo_int, lan9118_state), |
250 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(rx_cfg, lan9118_state), |
251 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(tx_cfg, lan9118_state), |
252 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(hw_cfg, lan9118_state), |
253 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(pmt_ctrl, lan9118_state), |
254 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(gpio_cfg, lan9118_state), |
255 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(gpt_cfg, lan9118_state), |
256 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(word_swap, lan9118_state), |
257 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(free_timer_start, lan9118_state), |
258 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(mac_cmd, lan9118_state), |
259 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(mac_data, lan9118_state), |
260 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(afc_cfg, lan9118_state), |
261 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(e2p_cmd, lan9118_state), |
262 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(e2p_data, lan9118_state), |
263 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(mac_cr, lan9118_state), |
264 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(mac_hashh, lan9118_state), |
265 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(mac_hashl, lan9118_state), |
266 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(mac_mii_acc, lan9118_state), |
267 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(mac_mii_data, lan9118_state), |
268 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(mac_flow, lan9118_state), |
269 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(phy_status, lan9118_state), |
270 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(phy_control, lan9118_state), |
271 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(phy_advertise, lan9118_state), |
272 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(phy_int, lan9118_state), |
273 | b09da0c3 | Peter Maydell | VMSTATE_UINT32(phy_int_mask, lan9118_state), |
274 | b09da0c3 | Peter Maydell | VMSTATE_INT32(eeprom_writable, lan9118_state), |
275 | b09da0c3 | Peter Maydell | VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128),
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276 | b09da0c3 | Peter Maydell | VMSTATE_INT32(tx_fifo_size, lan9118_state), |
277 | b09da0c3 | Peter Maydell | /* txp always points at tx_packet so need not be saved */
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278 | b09da0c3 | Peter Maydell | VMSTATE_STRUCT(tx_packet, lan9118_state, 0,
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279 | b09da0c3 | Peter Maydell | vmstate_lan9118_packet, LAN9118Packet), |
280 | b09da0c3 | Peter Maydell | VMSTATE_INT32(tx_status_fifo_used, lan9118_state), |
281 | b09da0c3 | Peter Maydell | VMSTATE_INT32(tx_status_fifo_head, lan9118_state), |
282 | b09da0c3 | Peter Maydell | VMSTATE_UINT32_ARRAY(tx_status_fifo, lan9118_state, 512),
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283 | b09da0c3 | Peter Maydell | VMSTATE_INT32(rx_status_fifo_size, lan9118_state), |
284 | b09da0c3 | Peter Maydell | VMSTATE_INT32(rx_status_fifo_used, lan9118_state), |
285 | b09da0c3 | Peter Maydell | VMSTATE_INT32(rx_status_fifo_head, lan9118_state), |
286 | b09da0c3 | Peter Maydell | VMSTATE_UINT32_ARRAY(rx_status_fifo, lan9118_state, 896),
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287 | b09da0c3 | Peter Maydell | VMSTATE_INT32(rx_fifo_size, lan9118_state), |
288 | b09da0c3 | Peter Maydell | VMSTATE_INT32(rx_fifo_used, lan9118_state), |
289 | b09da0c3 | Peter Maydell | VMSTATE_INT32(rx_fifo_head, lan9118_state), |
290 | b09da0c3 | Peter Maydell | VMSTATE_UINT32_ARRAY(rx_fifo, lan9118_state, 3360),
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291 | b09da0c3 | Peter Maydell | VMSTATE_INT32(rx_packet_size_head, lan9118_state), |
292 | b09da0c3 | Peter Maydell | VMSTATE_INT32(rx_packet_size_tail, lan9118_state), |
293 | b09da0c3 | Peter Maydell | VMSTATE_INT32_ARRAY(rx_packet_size, lan9118_state, 1024),
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294 | b09da0c3 | Peter Maydell | VMSTATE_INT32(rxp_offset, lan9118_state), |
295 | b09da0c3 | Peter Maydell | VMSTATE_INT32(rxp_size, lan9118_state), |
296 | b09da0c3 | Peter Maydell | VMSTATE_INT32(rxp_pad, lan9118_state), |
297 | b09da0c3 | Peter Maydell | VMSTATE_END_OF_LIST() |
298 | b09da0c3 | Peter Maydell | } |
299 | b09da0c3 | Peter Maydell | }; |
300 | b09da0c3 | Peter Maydell | |
301 | 2a424990 | Paul Brook | static void lan9118_update(lan9118_state *s) |
302 | 2a424990 | Paul Brook | { |
303 | 2a424990 | Paul Brook | int level;
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304 | 2a424990 | Paul Brook | |
305 | 2a424990 | Paul Brook | /* TODO: Implement FIFO level IRQs. */
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306 | 2a424990 | Paul Brook | level = (s->int_sts & s->int_en) != 0;
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307 | 209bf965 | Paul Brook | if (level) {
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308 | 209bf965 | Paul Brook | s->irq_cfg |= IRQ_INT; |
309 | 209bf965 | Paul Brook | } else {
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310 | 209bf965 | Paul Brook | s->irq_cfg &= ~IRQ_INT; |
311 | 209bf965 | Paul Brook | } |
312 | 2a424990 | Paul Brook | if ((s->irq_cfg & IRQ_EN) == 0) { |
313 | 2a424990 | Paul Brook | level = 0;
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314 | 2a424990 | Paul Brook | } |
315 | eb47d7c5 | Peter Maydell | if ((s->irq_cfg & (IRQ_TYPE | IRQ_POL)) != (IRQ_TYPE | IRQ_POL)) {
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316 | eb47d7c5 | Peter Maydell | /* Interrupt is active low unless we're configured as
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317 | eb47d7c5 | Peter Maydell | * active-high polarity, push-pull type.
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318 | eb47d7c5 | Peter Maydell | */
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319 | eb47d7c5 | Peter Maydell | level = !level; |
320 | eb47d7c5 | Peter Maydell | } |
321 | 2a424990 | Paul Brook | qemu_set_irq(s->irq, level); |
322 | 2a424990 | Paul Brook | } |
323 | 2a424990 | Paul Brook | |
324 | 2a424990 | Paul Brook | static void lan9118_mac_changed(lan9118_state *s) |
325 | 2a424990 | Paul Brook | { |
326 | 83b9f88c | Mark McLoughlin | qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
327 | 2a424990 | Paul Brook | } |
328 | 2a424990 | Paul Brook | |
329 | 2a424990 | Paul Brook | static void lan9118_reload_eeprom(lan9118_state *s) |
330 | 2a424990 | Paul Brook | { |
331 | 2a424990 | Paul Brook | int i;
|
332 | 2a424990 | Paul Brook | if (s->eeprom[0] != 0xa5) { |
333 | 2a424990 | Paul Brook | s->e2p_cmd &= ~0x10;
|
334 | 2a424990 | Paul Brook | DPRINTF("MACADDR load failed\n");
|
335 | 2a424990 | Paul Brook | return;
|
336 | 2a424990 | Paul Brook | } |
337 | 2a424990 | Paul Brook | for (i = 0; i < 6; i++) { |
338 | 2a424990 | Paul Brook | s->conf.macaddr.a[i] = s->eeprom[i + 1];
|
339 | 2a424990 | Paul Brook | } |
340 | 2a424990 | Paul Brook | s->e2p_cmd |= 0x10;
|
341 | 2a424990 | Paul Brook | DPRINTF("MACADDR loaded from eeprom\n");
|
342 | 2a424990 | Paul Brook | lan9118_mac_changed(s); |
343 | 2a424990 | Paul Brook | } |
344 | 2a424990 | Paul Brook | |
345 | 209bf965 | Paul Brook | static void phy_update_irq(lan9118_state *s) |
346 | 209bf965 | Paul Brook | { |
347 | 209bf965 | Paul Brook | if (s->phy_int & s->phy_int_mask) {
|
348 | 209bf965 | Paul Brook | s->int_sts |= PHY_INT; |
349 | 209bf965 | Paul Brook | } else {
|
350 | 209bf965 | Paul Brook | s->int_sts &= ~PHY_INT; |
351 | 209bf965 | Paul Brook | } |
352 | 209bf965 | Paul Brook | lan9118_update(s); |
353 | 209bf965 | Paul Brook | } |
354 | 209bf965 | Paul Brook | |
355 | 2a424990 | Paul Brook | static void phy_update_link(lan9118_state *s) |
356 | 2a424990 | Paul Brook | { |
357 | 2a424990 | Paul Brook | /* Autonegotiation status mirrors link status. */
|
358 | 83b9f88c | Mark McLoughlin | if (s->nic->nc.link_down) {
|
359 | 2a424990 | Paul Brook | s->phy_status &= ~0x0024;
|
360 | 209bf965 | Paul Brook | s->phy_int |= PHY_INT_DOWN; |
361 | 2a424990 | Paul Brook | } else {
|
362 | 2a424990 | Paul Brook | s->phy_status |= 0x0024;
|
363 | 209bf965 | Paul Brook | s->phy_int |= PHY_INT_ENERGYON; |
364 | 209bf965 | Paul Brook | s->phy_int |= PHY_INT_AUTONEG_COMPLETE; |
365 | 2a424990 | Paul Brook | } |
366 | 209bf965 | Paul Brook | phy_update_irq(s); |
367 | 2a424990 | Paul Brook | } |
368 | 2a424990 | Paul Brook | |
369 | 83b9f88c | Mark McLoughlin | static void lan9118_set_link(VLANClientState *nc) |
370 | 2a424990 | Paul Brook | { |
371 | 83b9f88c | Mark McLoughlin | phy_update_link(DO_UPCAST(NICState, nc, nc)->opaque); |
372 | 2a424990 | Paul Brook | } |
373 | 2a424990 | Paul Brook | |
374 | 2a424990 | Paul Brook | static void phy_reset(lan9118_state *s) |
375 | 2a424990 | Paul Brook | { |
376 | 209bf965 | Paul Brook | s->phy_status = 0x7809;
|
377 | 2a424990 | Paul Brook | s->phy_control = 0x3000;
|
378 | 2a424990 | Paul Brook | s->phy_advertise = 0x01e1;
|
379 | 209bf965 | Paul Brook | s->phy_int_mask = 0;
|
380 | 209bf965 | Paul Brook | s->phy_int = 0;
|
381 | 2a424990 | Paul Brook | phy_update_link(s); |
382 | 2a424990 | Paul Brook | } |
383 | 2a424990 | Paul Brook | |
384 | 2a424990 | Paul Brook | static void lan9118_reset(DeviceState *d) |
385 | 2a424990 | Paul Brook | { |
386 | 2a424990 | Paul Brook | lan9118_state *s = FROM_SYSBUS(lan9118_state, sysbus_from_qdev(d)); |
387 | eb47d7c5 | Peter Maydell | s->irq_cfg &= (IRQ_TYPE | IRQ_POL); |
388 | 2a424990 | Paul Brook | s->int_sts = 0;
|
389 | 2a424990 | Paul Brook | s->int_en = 0;
|
390 | 2a424990 | Paul Brook | s->fifo_int = 0x48000000;
|
391 | 2a424990 | Paul Brook | s->rx_cfg = 0;
|
392 | 2a424990 | Paul Brook | s->tx_cfg = 0;
|
393 | 2a424990 | Paul Brook | s->hw_cfg = 0x00050000;
|
394 | 2a424990 | Paul Brook | s->pmt_ctrl &= 0x45;
|
395 | 2a424990 | Paul Brook | s->gpio_cfg = 0;
|
396 | 2a424990 | Paul Brook | s->txp->fifo_used = 0;
|
397 | 2a424990 | Paul Brook | s->txp->state = TX_IDLE; |
398 | 2a424990 | Paul Brook | s->txp->cmd_a = 0xffffffffu;
|
399 | 2a424990 | Paul Brook | s->txp->cmd_b = 0xffffffffu;
|
400 | 2a424990 | Paul Brook | s->txp->len = 0;
|
401 | 2a424990 | Paul Brook | s->txp->fifo_used = 0;
|
402 | 2a424990 | Paul Brook | s->tx_fifo_size = 4608;
|
403 | 2a424990 | Paul Brook | s->tx_status_fifo_used = 0;
|
404 | 2a424990 | Paul Brook | s->rx_status_fifo_size = 704;
|
405 | 2a424990 | Paul Brook | s->rx_fifo_size = 2640;
|
406 | 2a424990 | Paul Brook | s->rx_fifo_used = 0;
|
407 | 2a424990 | Paul Brook | s->rx_status_fifo_size = 176;
|
408 | 2a424990 | Paul Brook | s->rx_status_fifo_used = 0;
|
409 | 2a424990 | Paul Brook | s->rxp_offset = 0;
|
410 | 2a424990 | Paul Brook | s->rxp_size = 0;
|
411 | 2a424990 | Paul Brook | s->rxp_pad = 0;
|
412 | 2a424990 | Paul Brook | s->rx_packet_size_tail = s->rx_packet_size_head; |
413 | 2a424990 | Paul Brook | s->rx_packet_size[s->rx_packet_size_head] = 0;
|
414 | 2a424990 | Paul Brook | s->mac_cmd = 0;
|
415 | 2a424990 | Paul Brook | s->mac_data = 0;
|
416 | 2a424990 | Paul Brook | s->afc_cfg = 0;
|
417 | 2a424990 | Paul Brook | s->e2p_cmd = 0;
|
418 | 2a424990 | Paul Brook | s->e2p_data = 0;
|
419 | 74475455 | Paolo Bonzini | s->free_timer_start = qemu_get_clock_ns(vm_clock) / 40;
|
420 | 2a424990 | Paul Brook | |
421 | 209bf965 | Paul Brook | ptimer_stop(s->timer); |
422 | 209bf965 | Paul Brook | ptimer_set_count(s->timer, 0xffff);
|
423 | 209bf965 | Paul Brook | s->gpt_cfg = 0xffff;
|
424 | 209bf965 | Paul Brook | |
425 | 2a424990 | Paul Brook | s->mac_cr = MAC_CR_PRMS; |
426 | 2a424990 | Paul Brook | s->mac_hashh = 0;
|
427 | 2a424990 | Paul Brook | s->mac_hashl = 0;
|
428 | 2a424990 | Paul Brook | s->mac_mii_acc = 0;
|
429 | 2a424990 | Paul Brook | s->mac_mii_data = 0;
|
430 | 2a424990 | Paul Brook | s->mac_flow = 0;
|
431 | 2a424990 | Paul Brook | |
432 | 2a424990 | Paul Brook | phy_reset(s); |
433 | 2a424990 | Paul Brook | |
434 | 2a424990 | Paul Brook | s->eeprom_writable = 0;
|
435 | 2a424990 | Paul Brook | lan9118_reload_eeprom(s); |
436 | 2a424990 | Paul Brook | } |
437 | 2a424990 | Paul Brook | |
438 | 83b9f88c | Mark McLoughlin | static int lan9118_can_receive(VLANClientState *nc) |
439 | 2a424990 | Paul Brook | { |
440 | 2a424990 | Paul Brook | return 1; |
441 | 2a424990 | Paul Brook | } |
442 | 2a424990 | Paul Brook | |
443 | 2a424990 | Paul Brook | static void rx_fifo_push(lan9118_state *s, uint32_t val) |
444 | 2a424990 | Paul Brook | { |
445 | 2a424990 | Paul Brook | int fifo_pos;
|
446 | 2a424990 | Paul Brook | fifo_pos = s->rx_fifo_head + s->rx_fifo_used; |
447 | 2a424990 | Paul Brook | if (fifo_pos >= s->rx_fifo_size)
|
448 | 2a424990 | Paul Brook | fifo_pos -= s->rx_fifo_size; |
449 | 2a424990 | Paul Brook | s->rx_fifo[fifo_pos] = val; |
450 | 2a424990 | Paul Brook | s->rx_fifo_used++; |
451 | 2a424990 | Paul Brook | } |
452 | 2a424990 | Paul Brook | |
453 | 2a424990 | Paul Brook | /* Return nonzero if the packet is accepted by the filter. */
|
454 | 2a424990 | Paul Brook | static int lan9118_filter(lan9118_state *s, const uint8_t *addr) |
455 | 2a424990 | Paul Brook | { |
456 | 2a424990 | Paul Brook | int multicast;
|
457 | 2a424990 | Paul Brook | uint32_t hash; |
458 | 2a424990 | Paul Brook | |
459 | 2a424990 | Paul Brook | if (s->mac_cr & MAC_CR_PRMS) {
|
460 | 2a424990 | Paul Brook | return 1; |
461 | 2a424990 | Paul Brook | } |
462 | 2a424990 | Paul Brook | if (addr[0] == 0xff && addr[1] == 0xff && addr[2] == 0xff && |
463 | 2a424990 | Paul Brook | addr[3] == 0xff && addr[4] == 0xff && addr[5] == 0xff) { |
464 | 2a424990 | Paul Brook | return (s->mac_cr & MAC_CR_BCAST) == 0; |
465 | 2a424990 | Paul Brook | } |
466 | 2a424990 | Paul Brook | |
467 | 2a424990 | Paul Brook | multicast = addr[0] & 1; |
468 | 2a424990 | Paul Brook | if (multicast &&s->mac_cr & MAC_CR_MCPAS) {
|
469 | 2a424990 | Paul Brook | return 1; |
470 | 2a424990 | Paul Brook | } |
471 | 2a424990 | Paul Brook | if (multicast ? (s->mac_cr & MAC_CR_HPFILT) == 0 |
472 | 2a424990 | Paul Brook | : (s->mac_cr & MAC_CR_HO) == 0) {
|
473 | 2a424990 | Paul Brook | /* Exact matching. */
|
474 | 2a424990 | Paul Brook | hash = memcmp(addr, s->conf.macaddr.a, 6);
|
475 | 2a424990 | Paul Brook | if (s->mac_cr & MAC_CR_INVFILT) {
|
476 | 2a424990 | Paul Brook | return hash != 0; |
477 | 2a424990 | Paul Brook | } else {
|
478 | 2a424990 | Paul Brook | return hash == 0; |
479 | 2a424990 | Paul Brook | } |
480 | 2a424990 | Paul Brook | } else {
|
481 | 2a424990 | Paul Brook | /* Hash matching */
|
482 | 2a424990 | Paul Brook | hash = (crc32(~0, addr, 6) >> 26); |
483 | 2a424990 | Paul Brook | if (hash & 0x20) { |
484 | 2a424990 | Paul Brook | return (s->mac_hashh >> (hash & 0x1f)) & 1; |
485 | 2a424990 | Paul Brook | } else {
|
486 | 2a424990 | Paul Brook | return (s->mac_hashl >> (hash & 0x1f)) & 1; |
487 | 2a424990 | Paul Brook | } |
488 | 2a424990 | Paul Brook | } |
489 | 2a424990 | Paul Brook | } |
490 | 2a424990 | Paul Brook | |
491 | 83b9f88c | Mark McLoughlin | static ssize_t lan9118_receive(VLANClientState *nc, const uint8_t *buf, |
492 | 2a424990 | Paul Brook | size_t size) |
493 | 2a424990 | Paul Brook | { |
494 | 83b9f88c | Mark McLoughlin | lan9118_state *s = DO_UPCAST(NICState, nc, nc)->opaque; |
495 | 2a424990 | Paul Brook | int fifo_len;
|
496 | 2a424990 | Paul Brook | int offset;
|
497 | 2a424990 | Paul Brook | int src_pos;
|
498 | 2a424990 | Paul Brook | int n;
|
499 | 2a424990 | Paul Brook | int filter;
|
500 | 2a424990 | Paul Brook | uint32_t val; |
501 | 2a424990 | Paul Brook | uint32_t crc; |
502 | 2a424990 | Paul Brook | uint32_t status; |
503 | 2a424990 | Paul Brook | |
504 | 2a424990 | Paul Brook | if ((s->mac_cr & MAC_CR_RXEN) == 0) { |
505 | 2a424990 | Paul Brook | return -1; |
506 | 2a424990 | Paul Brook | } |
507 | 2a424990 | Paul Brook | |
508 | 2a424990 | Paul Brook | if (size >= 2048 || size < 14) { |
509 | 2a424990 | Paul Brook | return -1; |
510 | 2a424990 | Paul Brook | } |
511 | 2a424990 | Paul Brook | |
512 | 2a424990 | Paul Brook | /* TODO: Implement FIFO overflow notification. */
|
513 | 2a424990 | Paul Brook | if (s->rx_status_fifo_used == s->rx_status_fifo_size) {
|
514 | 2a424990 | Paul Brook | return -1; |
515 | 2a424990 | Paul Brook | } |
516 | 2a424990 | Paul Brook | |
517 | 2a424990 | Paul Brook | filter = lan9118_filter(s, buf); |
518 | 2a424990 | Paul Brook | if (!filter && (s->mac_cr & MAC_CR_RXALL) == 0) { |
519 | 2a424990 | Paul Brook | return size;
|
520 | 2a424990 | Paul Brook | } |
521 | 2a424990 | Paul Brook | |
522 | 2a424990 | Paul Brook | offset = (s->rx_cfg >> 8) & 0x1f; |
523 | 2a424990 | Paul Brook | n = offset & 3;
|
524 | 2a424990 | Paul Brook | fifo_len = (size + n + 3) >> 2; |
525 | 2a424990 | Paul Brook | /* Add a word for the CRC. */
|
526 | 2a424990 | Paul Brook | fifo_len++; |
527 | 2a424990 | Paul Brook | if (s->rx_fifo_size - s->rx_fifo_used < fifo_len) {
|
528 | 2a424990 | Paul Brook | return -1; |
529 | 2a424990 | Paul Brook | } |
530 | 2a424990 | Paul Brook | |
531 | 2a424990 | Paul Brook | DPRINTF("Got packet len:%d fifo:%d filter:%s\n",
|
532 | 2a424990 | Paul Brook | (int)size, fifo_len, filter ? "pass" : "fail"); |
533 | 2a424990 | Paul Brook | val = 0;
|
534 | 2a424990 | Paul Brook | crc = bswap32(crc32(~0, buf, size));
|
535 | 2a424990 | Paul Brook | for (src_pos = 0; src_pos < size; src_pos++) { |
536 | 2a424990 | Paul Brook | val = (val >> 8) | ((uint32_t)buf[src_pos] << 24); |
537 | 2a424990 | Paul Brook | n++; |
538 | 2a424990 | Paul Brook | if (n == 4) { |
539 | 2a424990 | Paul Brook | n = 0;
|
540 | 2a424990 | Paul Brook | rx_fifo_push(s, val); |
541 | 2a424990 | Paul Brook | val = 0;
|
542 | 2a424990 | Paul Brook | } |
543 | 2a424990 | Paul Brook | } |
544 | 2a424990 | Paul Brook | if (n) {
|
545 | 2a424990 | Paul Brook | val >>= ((4 - n) * 8); |
546 | 2a424990 | Paul Brook | val |= crc << (n * 8);
|
547 | 2a424990 | Paul Brook | rx_fifo_push(s, val); |
548 | 2a424990 | Paul Brook | val = crc >> ((4 - n) * 8); |
549 | 2a424990 | Paul Brook | rx_fifo_push(s, val); |
550 | 2a424990 | Paul Brook | } else {
|
551 | 2a424990 | Paul Brook | rx_fifo_push(s, crc); |
552 | 2a424990 | Paul Brook | } |
553 | 2a424990 | Paul Brook | n = s->rx_status_fifo_head + s->rx_status_fifo_used; |
554 | 2a424990 | Paul Brook | if (n >= s->rx_status_fifo_size) {
|
555 | 2a424990 | Paul Brook | n -= s->rx_status_fifo_size; |
556 | 2a424990 | Paul Brook | } |
557 | 2a424990 | Paul Brook | s->rx_packet_size[s->rx_packet_size_tail] = fifo_len; |
558 | 2a424990 | Paul Brook | s->rx_packet_size_tail = (s->rx_packet_size_tail + 1023) & 1023; |
559 | 2a424990 | Paul Brook | s->rx_status_fifo_used++; |
560 | 2a424990 | Paul Brook | |
561 | 2a424990 | Paul Brook | status = (size + 4) << 16; |
562 | 2a424990 | Paul Brook | if (buf[0] == 0xff && buf[1] == 0xff && buf[2] == 0xff && |
563 | 2a424990 | Paul Brook | buf[3] == 0xff && buf[4] == 0xff && buf[5] == 0xff) { |
564 | 2a424990 | Paul Brook | status |= 0x00002000;
|
565 | 2a424990 | Paul Brook | } else if (buf[0] & 1) { |
566 | 2a424990 | Paul Brook | status |= 0x00000400;
|
567 | 2a424990 | Paul Brook | } |
568 | 2a424990 | Paul Brook | if (!filter) {
|
569 | 2a424990 | Paul Brook | status |= 0x40000000;
|
570 | 2a424990 | Paul Brook | } |
571 | 2a424990 | Paul Brook | s->rx_status_fifo[n] = status; |
572 | 2a424990 | Paul Brook | |
573 | 2a424990 | Paul Brook | if (s->rx_status_fifo_used > (s->fifo_int & 0xff)) { |
574 | 2a424990 | Paul Brook | s->int_sts |= RSFL_INT; |
575 | 2a424990 | Paul Brook | } |
576 | 2a424990 | Paul Brook | lan9118_update(s); |
577 | 2a424990 | Paul Brook | |
578 | 2a424990 | Paul Brook | return size;
|
579 | 2a424990 | Paul Brook | } |
580 | 2a424990 | Paul Brook | |
581 | 2a424990 | Paul Brook | static uint32_t rx_fifo_pop(lan9118_state *s)
|
582 | 2a424990 | Paul Brook | { |
583 | 2a424990 | Paul Brook | int n;
|
584 | 2a424990 | Paul Brook | uint32_t val; |
585 | 2a424990 | Paul Brook | |
586 | 2a424990 | Paul Brook | if (s->rxp_size == 0 && s->rxp_pad == 0) { |
587 | 2a424990 | Paul Brook | s->rxp_size = s->rx_packet_size[s->rx_packet_size_head]; |
588 | 2a424990 | Paul Brook | s->rx_packet_size[s->rx_packet_size_head] = 0;
|
589 | 2a424990 | Paul Brook | if (s->rxp_size != 0) { |
590 | 2a424990 | Paul Brook | s->rx_packet_size_head = (s->rx_packet_size_head + 1023) & 1023; |
591 | 2a424990 | Paul Brook | s->rxp_offset = (s->rx_cfg >> 10) & 7; |
592 | 2a424990 | Paul Brook | n = s->rxp_offset + s->rxp_size; |
593 | 2a424990 | Paul Brook | switch (s->rx_cfg >> 30) { |
594 | 2a424990 | Paul Brook | case 1: |
595 | 2a424990 | Paul Brook | n = (-n) & 3;
|
596 | 2a424990 | Paul Brook | break;
|
597 | 2a424990 | Paul Brook | case 2: |
598 | 2a424990 | Paul Brook | n = (-n) & 7;
|
599 | 2a424990 | Paul Brook | break;
|
600 | 2a424990 | Paul Brook | default:
|
601 | 2a424990 | Paul Brook | n = 0;
|
602 | 2a424990 | Paul Brook | break;
|
603 | 2a424990 | Paul Brook | } |
604 | 2a424990 | Paul Brook | s->rxp_pad = n; |
605 | 2a424990 | Paul Brook | DPRINTF("Pop packet size:%d offset:%d pad: %d\n",
|
606 | 2a424990 | Paul Brook | s->rxp_size, s->rxp_offset, s->rxp_pad); |
607 | 2a424990 | Paul Brook | } |
608 | 2a424990 | Paul Brook | } |
609 | 2a424990 | Paul Brook | if (s->rxp_offset > 0) { |
610 | 2a424990 | Paul Brook | s->rxp_offset--; |
611 | 2a424990 | Paul Brook | val = 0;
|
612 | 2a424990 | Paul Brook | } else if (s->rxp_size > 0) { |
613 | 2a424990 | Paul Brook | s->rxp_size--; |
614 | 2a424990 | Paul Brook | val = s->rx_fifo[s->rx_fifo_head++]; |
615 | 2a424990 | Paul Brook | if (s->rx_fifo_head >= s->rx_fifo_size) {
|
616 | 2a424990 | Paul Brook | s->rx_fifo_head -= s->rx_fifo_size; |
617 | 2a424990 | Paul Brook | } |
618 | 2a424990 | Paul Brook | s->rx_fifo_used--; |
619 | 2a424990 | Paul Brook | } else if (s->rxp_pad > 0) { |
620 | 2a424990 | Paul Brook | s->rxp_pad--; |
621 | 2a424990 | Paul Brook | val = 0;
|
622 | 2a424990 | Paul Brook | } else {
|
623 | 2a424990 | Paul Brook | DPRINTF("RX underflow\n");
|
624 | 2a424990 | Paul Brook | s->int_sts |= RXE_INT; |
625 | 2a424990 | Paul Brook | val = 0;
|
626 | 2a424990 | Paul Brook | } |
627 | 2a424990 | Paul Brook | lan9118_update(s); |
628 | 2a424990 | Paul Brook | return val;
|
629 | 2a424990 | Paul Brook | } |
630 | 2a424990 | Paul Brook | |
631 | 2a424990 | Paul Brook | static void do_tx_packet(lan9118_state *s) |
632 | 2a424990 | Paul Brook | { |
633 | 2a424990 | Paul Brook | int n;
|
634 | 2a424990 | Paul Brook | uint32_t status; |
635 | 2a424990 | Paul Brook | |
636 | 2a424990 | Paul Brook | /* FIXME: Honor TX disable, and allow queueing of packets. */
|
637 | 2a424990 | Paul Brook | if (s->phy_control & 0x4000) { |
638 | 2a424990 | Paul Brook | /* This assumes the receive routine doesn't touch the VLANClient. */
|
639 | 83b9f88c | Mark McLoughlin | lan9118_receive(&s->nic->nc, s->txp->data, s->txp->len); |
640 | 2a424990 | Paul Brook | } else {
|
641 | 83b9f88c | Mark McLoughlin | qemu_send_packet(&s->nic->nc, s->txp->data, s->txp->len); |
642 | 2a424990 | Paul Brook | } |
643 | 2a424990 | Paul Brook | s->txp->fifo_used = 0;
|
644 | 2a424990 | Paul Brook | |
645 | 2a424990 | Paul Brook | if (s->tx_status_fifo_used == 512) { |
646 | 2a424990 | Paul Brook | /* Status FIFO full */
|
647 | 2a424990 | Paul Brook | return;
|
648 | 2a424990 | Paul Brook | } |
649 | 2a424990 | Paul Brook | /* Add entry to status FIFO. */
|
650 | 2a424990 | Paul Brook | status = s->txp->cmd_b & 0xffff0000u;
|
651 | 2a424990 | Paul Brook | DPRINTF("Sent packet tag:%04x len %d\n", status >> 16, s->txp->len); |
652 | 2a424990 | Paul Brook | n = (s->tx_status_fifo_head + s->tx_status_fifo_used) & 511;
|
653 | 2a424990 | Paul Brook | s->tx_status_fifo[n] = status; |
654 | 2a424990 | Paul Brook | s->tx_status_fifo_used++; |
655 | 2a424990 | Paul Brook | if (s->tx_status_fifo_used == 512) { |
656 | 2a424990 | Paul Brook | s->int_sts |= TSFF_INT; |
657 | 2a424990 | Paul Brook | /* TODO: Stop transmission. */
|
658 | 2a424990 | Paul Brook | } |
659 | 2a424990 | Paul Brook | } |
660 | 2a424990 | Paul Brook | |
661 | 2a424990 | Paul Brook | static uint32_t rx_status_fifo_pop(lan9118_state *s)
|
662 | 2a424990 | Paul Brook | { |
663 | 2a424990 | Paul Brook | uint32_t val; |
664 | 2a424990 | Paul Brook | |
665 | 2a424990 | Paul Brook | val = s->rx_status_fifo[s->rx_status_fifo_head]; |
666 | 2a424990 | Paul Brook | if (s->rx_status_fifo_used != 0) { |
667 | 2a424990 | Paul Brook | s->rx_status_fifo_used--; |
668 | 2a424990 | Paul Brook | s->rx_status_fifo_head++; |
669 | 2a424990 | Paul Brook | if (s->rx_status_fifo_head >= s->rx_status_fifo_size) {
|
670 | 2a424990 | Paul Brook | s->rx_status_fifo_head -= s->rx_status_fifo_size; |
671 | 2a424990 | Paul Brook | } |
672 | 2a424990 | Paul Brook | /* ??? What value should be returned when the FIFO is empty? */
|
673 | 2a424990 | Paul Brook | DPRINTF("RX status pop 0x%08x\n", val);
|
674 | 2a424990 | Paul Brook | } |
675 | 2a424990 | Paul Brook | return val;
|
676 | 2a424990 | Paul Brook | } |
677 | 2a424990 | Paul Brook | |
678 | 2a424990 | Paul Brook | static uint32_t tx_status_fifo_pop(lan9118_state *s)
|
679 | 2a424990 | Paul Brook | { |
680 | 2a424990 | Paul Brook | uint32_t val; |
681 | 2a424990 | Paul Brook | |
682 | 2a424990 | Paul Brook | val = s->tx_status_fifo[s->tx_status_fifo_head]; |
683 | 2a424990 | Paul Brook | if (s->tx_status_fifo_used != 0) { |
684 | 2a424990 | Paul Brook | s->tx_status_fifo_used--; |
685 | 2a424990 | Paul Brook | s->tx_status_fifo_head = (s->tx_status_fifo_head + 1) & 511; |
686 | 2a424990 | Paul Brook | /* ??? What value should be returned when the FIFO is empty? */
|
687 | 2a424990 | Paul Brook | } |
688 | 2a424990 | Paul Brook | return val;
|
689 | 2a424990 | Paul Brook | } |
690 | 2a424990 | Paul Brook | |
691 | 2a424990 | Paul Brook | static void tx_fifo_push(lan9118_state *s, uint32_t val) |
692 | 2a424990 | Paul Brook | { |
693 | 2a424990 | Paul Brook | int n;
|
694 | 2a424990 | Paul Brook | |
695 | 2a424990 | Paul Brook | if (s->txp->fifo_used == s->tx_fifo_size) {
|
696 | 2a424990 | Paul Brook | s->int_sts |= TDFO_INT; |
697 | 2a424990 | Paul Brook | return;
|
698 | 2a424990 | Paul Brook | } |
699 | 2a424990 | Paul Brook | switch (s->txp->state) {
|
700 | 2a424990 | Paul Brook | case TX_IDLE:
|
701 | 2a424990 | Paul Brook | s->txp->cmd_a = val & 0x831f37ff;
|
702 | 2a424990 | Paul Brook | s->txp->fifo_used++; |
703 | 2a424990 | Paul Brook | s->txp->state = TX_B; |
704 | 2a424990 | Paul Brook | break;
|
705 | 2a424990 | Paul Brook | case TX_B:
|
706 | 2a424990 | Paul Brook | if (s->txp->cmd_a & 0x2000) { |
707 | 2a424990 | Paul Brook | /* First segment */
|
708 | 2a424990 | Paul Brook | s->txp->cmd_b = val; |
709 | 2a424990 | Paul Brook | s->txp->fifo_used++; |
710 | 2a424990 | Paul Brook | s->txp->buffer_size = s->txp->cmd_a & 0x7ff;
|
711 | 2a424990 | Paul Brook | s->txp->offset = (s->txp->cmd_a >> 16) & 0x1f; |
712 | 2a424990 | Paul Brook | /* End alignment does not include command words. */
|
713 | 2a424990 | Paul Brook | n = (s->txp->buffer_size + s->txp->offset + 3) >> 2; |
714 | 2a424990 | Paul Brook | switch ((n >> 24) & 3) { |
715 | 2a424990 | Paul Brook | case 1: |
716 | 2a424990 | Paul Brook | n = (-n) & 3;
|
717 | 2a424990 | Paul Brook | break;
|
718 | 2a424990 | Paul Brook | case 2: |
719 | 2a424990 | Paul Brook | n = (-n) & 7;
|
720 | 2a424990 | Paul Brook | break;
|
721 | 2a424990 | Paul Brook | default:
|
722 | 2a424990 | Paul Brook | n = 0;
|
723 | 2a424990 | Paul Brook | } |
724 | 2a424990 | Paul Brook | s->txp->pad = n; |
725 | 2a424990 | Paul Brook | s->txp->len = 0;
|
726 | 2a424990 | Paul Brook | } |
727 | 2a424990 | Paul Brook | DPRINTF("Block len:%d offset:%d pad:%d cmd %08x\n",
|
728 | 2a424990 | Paul Brook | s->txp->buffer_size, s->txp->offset, s->txp->pad, |
729 | 2a424990 | Paul Brook | s->txp->cmd_a); |
730 | 2a424990 | Paul Brook | s->txp->state = TX_DATA; |
731 | 2a424990 | Paul Brook | break;
|
732 | 2a424990 | Paul Brook | case TX_DATA:
|
733 | 2a424990 | Paul Brook | if (s->txp->offset >= 4) { |
734 | 2a424990 | Paul Brook | s->txp->offset -= 4;
|
735 | 2a424990 | Paul Brook | break;
|
736 | 2a424990 | Paul Brook | } |
737 | 2a424990 | Paul Brook | if (s->txp->buffer_size <= 0 && s->txp->pad != 0) { |
738 | 2a424990 | Paul Brook | s->txp->pad--; |
739 | 2a424990 | Paul Brook | } else {
|
740 | 2a424990 | Paul Brook | n = 4;
|
741 | 2a424990 | Paul Brook | while (s->txp->offset) {
|
742 | 2a424990 | Paul Brook | val >>= 8;
|
743 | 2a424990 | Paul Brook | n--; |
744 | 2a424990 | Paul Brook | s->txp->offset--; |
745 | 2a424990 | Paul Brook | } |
746 | 2a424990 | Paul Brook | /* Documentation is somewhat unclear on the ordering of bytes
|
747 | 2a424990 | Paul Brook | in FIFO words. Empirical results show it to be little-endian.
|
748 | 2a424990 | Paul Brook | */
|
749 | 2a424990 | Paul Brook | /* TODO: FIFO overflow checking. */
|
750 | 2a424990 | Paul Brook | while (n--) {
|
751 | 2a424990 | Paul Brook | s->txp->data[s->txp->len] = val & 0xff;
|
752 | 2a424990 | Paul Brook | s->txp->len++; |
753 | 2a424990 | Paul Brook | val >>= 8;
|
754 | 2a424990 | Paul Brook | s->txp->buffer_size--; |
755 | 2a424990 | Paul Brook | } |
756 | 2a424990 | Paul Brook | s->txp->fifo_used++; |
757 | 2a424990 | Paul Brook | } |
758 | 2a424990 | Paul Brook | if (s->txp->buffer_size <= 0 && s->txp->pad == 0) { |
759 | 2a424990 | Paul Brook | if (s->txp->cmd_a & 0x1000) { |
760 | 2a424990 | Paul Brook | do_tx_packet(s); |
761 | 2a424990 | Paul Brook | } |
762 | 2a424990 | Paul Brook | if (s->txp->cmd_a & 0x80000000) { |
763 | 2a424990 | Paul Brook | s->int_sts |= TX_IOC_INT; |
764 | 2a424990 | Paul Brook | } |
765 | 2a424990 | Paul Brook | s->txp->state = TX_IDLE; |
766 | 2a424990 | Paul Brook | } |
767 | 2a424990 | Paul Brook | break;
|
768 | 2a424990 | Paul Brook | } |
769 | 2a424990 | Paul Brook | } |
770 | 2a424990 | Paul Brook | |
771 | 2a424990 | Paul Brook | static uint32_t do_phy_read(lan9118_state *s, int reg) |
772 | 2a424990 | Paul Brook | { |
773 | 209bf965 | Paul Brook | uint32_t val; |
774 | 209bf965 | Paul Brook | |
775 | 2a424990 | Paul Brook | switch (reg) {
|
776 | 2a424990 | Paul Brook | case 0: /* Basic Control */ |
777 | 2a424990 | Paul Brook | return s->phy_control;
|
778 | 2a424990 | Paul Brook | case 1: /* Basic Status */ |
779 | 2a424990 | Paul Brook | return s->phy_status;
|
780 | 2a424990 | Paul Brook | case 2: /* ID1 */ |
781 | 2a424990 | Paul Brook | return 0x0007; |
782 | 2a424990 | Paul Brook | case 3: /* ID2 */ |
783 | 2a424990 | Paul Brook | return 0xc0d1; |
784 | 66a0a2cb | Dong Xu Wang | case 4: /* Auto-neg advertisement */ |
785 | 2a424990 | Paul Brook | return s->phy_advertise;
|
786 | 2a424990 | Paul Brook | case 5: /* Auto-neg Link Partner Ability */ |
787 | 2a424990 | Paul Brook | return 0x0f71; |
788 | 2a424990 | Paul Brook | case 6: /* Auto-neg Expansion */ |
789 | 2a424990 | Paul Brook | return 1; |
790 | 2a424990 | Paul Brook | /* TODO 17, 18, 27, 29, 30, 31 */
|
791 | 209bf965 | Paul Brook | case 29: /* Interrupt source. */ |
792 | 209bf965 | Paul Brook | val = s->phy_int; |
793 | 209bf965 | Paul Brook | s->phy_int = 0;
|
794 | 209bf965 | Paul Brook | phy_update_irq(s); |
795 | 209bf965 | Paul Brook | return val;
|
796 | 209bf965 | Paul Brook | case 30: /* Interrupt mask */ |
797 | 209bf965 | Paul Brook | return s->phy_int_mask;
|
798 | 2a424990 | Paul Brook | default:
|
799 | 2a424990 | Paul Brook | BADF("PHY read reg %d\n", reg);
|
800 | 2a424990 | Paul Brook | return 0; |
801 | 2a424990 | Paul Brook | } |
802 | 2a424990 | Paul Brook | } |
803 | 2a424990 | Paul Brook | |
804 | 2a424990 | Paul Brook | static void do_phy_write(lan9118_state *s, int reg, uint32_t val) |
805 | 2a424990 | Paul Brook | { |
806 | 2a424990 | Paul Brook | switch (reg) {
|
807 | 2a424990 | Paul Brook | case 0: /* Basic Control */ |
808 | 2a424990 | Paul Brook | if (val & 0x8000) { |
809 | 2a424990 | Paul Brook | phy_reset(s); |
810 | 2a424990 | Paul Brook | break;
|
811 | 2a424990 | Paul Brook | } |
812 | 2a424990 | Paul Brook | s->phy_control = val & 0x7980;
|
813 | 4b71051e | Stefan Weil | /* Complete autonegotiation immediately. */
|
814 | 2a424990 | Paul Brook | if (val & 0x1000) { |
815 | 2a424990 | Paul Brook | s->phy_status |= 0x0020;
|
816 | 2a424990 | Paul Brook | } |
817 | 2a424990 | Paul Brook | break;
|
818 | 66a0a2cb | Dong Xu Wang | case 4: /* Auto-neg advertisement */ |
819 | 2a424990 | Paul Brook | s->phy_advertise = (val & 0x2d7f) | 0x80; |
820 | 2a424990 | Paul Brook | break;
|
821 | 209bf965 | Paul Brook | /* TODO 17, 18, 27, 31 */
|
822 | 209bf965 | Paul Brook | case 30: /* Interrupt mask */ |
823 | 209bf965 | Paul Brook | s->phy_int_mask = val & 0xff;
|
824 | 209bf965 | Paul Brook | phy_update_irq(s); |
825 | 209bf965 | Paul Brook | break;
|
826 | 2a424990 | Paul Brook | default:
|
827 | 2a424990 | Paul Brook | BADF("PHY write reg %d = 0x%04x\n", reg, val);
|
828 | 2a424990 | Paul Brook | } |
829 | 2a424990 | Paul Brook | } |
830 | 2a424990 | Paul Brook | |
831 | 2a424990 | Paul Brook | static void do_mac_write(lan9118_state *s, int reg, uint32_t val) |
832 | 2a424990 | Paul Brook | { |
833 | 2a424990 | Paul Brook | switch (reg) {
|
834 | 2a424990 | Paul Brook | case MAC_CR:
|
835 | 2a424990 | Paul Brook | if ((s->mac_cr & MAC_CR_RXEN) != 0 && (val & MAC_CR_RXEN) == 0) { |
836 | 2a424990 | Paul Brook | s->int_sts |= RXSTOP_INT; |
837 | 2a424990 | Paul Brook | } |
838 | 2a424990 | Paul Brook | s->mac_cr = val & ~MAC_CR_RESERVED; |
839 | 2a424990 | Paul Brook | DPRINTF("MAC_CR: %08x\n", val);
|
840 | 2a424990 | Paul Brook | break;
|
841 | 2a424990 | Paul Brook | case MAC_ADDRH:
|
842 | 2a424990 | Paul Brook | s->conf.macaddr.a[4] = val & 0xff; |
843 | 2a424990 | Paul Brook | s->conf.macaddr.a[5] = (val >> 8) & 0xff; |
844 | 2a424990 | Paul Brook | lan9118_mac_changed(s); |
845 | 2a424990 | Paul Brook | break;
|
846 | 2a424990 | Paul Brook | case MAC_ADDRL:
|
847 | 2a424990 | Paul Brook | s->conf.macaddr.a[0] = val & 0xff; |
848 | 2a424990 | Paul Brook | s->conf.macaddr.a[1] = (val >> 8) & 0xff; |
849 | 2a424990 | Paul Brook | s->conf.macaddr.a[2] = (val >> 16) & 0xff; |
850 | 2a424990 | Paul Brook | s->conf.macaddr.a[3] = (val >> 24) & 0xff; |
851 | 2a424990 | Paul Brook | lan9118_mac_changed(s); |
852 | 2a424990 | Paul Brook | break;
|
853 | 2a424990 | Paul Brook | case MAC_HASHH:
|
854 | 2a424990 | Paul Brook | s->mac_hashh = val; |
855 | 2a424990 | Paul Brook | break;
|
856 | 2a424990 | Paul Brook | case MAC_HASHL:
|
857 | 2a424990 | Paul Brook | s->mac_hashl = val; |
858 | 2a424990 | Paul Brook | break;
|
859 | 2a424990 | Paul Brook | case MAC_MII_ACC:
|
860 | 2a424990 | Paul Brook | s->mac_mii_acc = val & 0xffc2;
|
861 | 2a424990 | Paul Brook | if (val & 2) { |
862 | 2a424990 | Paul Brook | DPRINTF("PHY write %d = 0x%04x\n",
|
863 | 2a424990 | Paul Brook | (val >> 6) & 0x1f, s->mac_mii_data); |
864 | 2a424990 | Paul Brook | do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data); |
865 | 2a424990 | Paul Brook | } else {
|
866 | 2a424990 | Paul Brook | s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f); |
867 | 2a424990 | Paul Brook | DPRINTF("PHY read %d = 0x%04x\n",
|
868 | 2a424990 | Paul Brook | (val >> 6) & 0x1f, s->mac_mii_data); |
869 | 2a424990 | Paul Brook | } |
870 | 2a424990 | Paul Brook | break;
|
871 | 2a424990 | Paul Brook | case MAC_MII_DATA:
|
872 | 2a424990 | Paul Brook | s->mac_mii_data = val & 0xffff;
|
873 | 2a424990 | Paul Brook | break;
|
874 | 2a424990 | Paul Brook | case MAC_FLOW:
|
875 | 2a424990 | Paul Brook | s->mac_flow = val & 0xffff0000;
|
876 | 2a424990 | Paul Brook | break;
|
877 | a0313c00 | Atsushi Nemoto | case MAC_VLAN1:
|
878 | a0313c00 | Atsushi Nemoto | /* Writing to this register changes a condition for
|
879 | a0313c00 | Atsushi Nemoto | * FrameTooLong bit in rx_status. Since we do not set
|
880 | a0313c00 | Atsushi Nemoto | * FrameTooLong anyway, just ignore write to this.
|
881 | a0313c00 | Atsushi Nemoto | */
|
882 | a0313c00 | Atsushi Nemoto | break;
|
883 | 2a424990 | Paul Brook | default:
|
884 | 2a424990 | Paul Brook | hw_error("lan9118: Unimplemented MAC register write: %d = 0x%x\n",
|
885 | 2a424990 | Paul Brook | s->mac_cmd & 0xf, val);
|
886 | 2a424990 | Paul Brook | } |
887 | 2a424990 | Paul Brook | } |
888 | 2a424990 | Paul Brook | |
889 | 2a424990 | Paul Brook | static uint32_t do_mac_read(lan9118_state *s, int reg) |
890 | 2a424990 | Paul Brook | { |
891 | 2a424990 | Paul Brook | switch (reg) {
|
892 | 2a424990 | Paul Brook | case MAC_CR:
|
893 | 2a424990 | Paul Brook | return s->mac_cr;
|
894 | 2a424990 | Paul Brook | case MAC_ADDRH:
|
895 | 2a424990 | Paul Brook | return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8); |
896 | 2a424990 | Paul Brook | case MAC_ADDRL:
|
897 | 2a424990 | Paul Brook | return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8) |
898 | 2a424990 | Paul Brook | | (s->conf.macaddr.a[2] << 16) | (s->conf.macaddr.a[3] << 24); |
899 | 2a424990 | Paul Brook | case MAC_HASHH:
|
900 | 2a424990 | Paul Brook | return s->mac_hashh;
|
901 | 2a424990 | Paul Brook | break;
|
902 | 2a424990 | Paul Brook | case MAC_HASHL:
|
903 | 2a424990 | Paul Brook | return s->mac_hashl;
|
904 | 2a424990 | Paul Brook | break;
|
905 | 2a424990 | Paul Brook | case MAC_MII_ACC:
|
906 | 2a424990 | Paul Brook | return s->mac_mii_acc;
|
907 | 2a424990 | Paul Brook | case MAC_MII_DATA:
|
908 | 2a424990 | Paul Brook | return s->mac_mii_data;
|
909 | 2a424990 | Paul Brook | case MAC_FLOW:
|
910 | 2a424990 | Paul Brook | return s->mac_flow;
|
911 | 2a424990 | Paul Brook | default:
|
912 | 2a424990 | Paul Brook | hw_error("lan9118: Unimplemented MAC register read: %d\n",
|
913 | 2a424990 | Paul Brook | s->mac_cmd & 0xf);
|
914 | 2a424990 | Paul Brook | } |
915 | 2a424990 | Paul Brook | } |
916 | 2a424990 | Paul Brook | |
917 | 2a424990 | Paul Brook | static void lan9118_eeprom_cmd(lan9118_state *s, int cmd, int addr) |
918 | 2a424990 | Paul Brook | { |
919 | 2a424990 | Paul Brook | s->e2p_cmd = (s->e2p_cmd & 0x10) | (cmd << 28) | addr; |
920 | 2a424990 | Paul Brook | switch (cmd) {
|
921 | 2a424990 | Paul Brook | case 0: |
922 | 2a424990 | Paul Brook | s->e2p_data = s->eeprom[addr]; |
923 | 2a424990 | Paul Brook | DPRINTF("EEPROM Read %d = 0x%02x\n", addr, s->e2p_data);
|
924 | 2a424990 | Paul Brook | break;
|
925 | 2a424990 | Paul Brook | case 1: |
926 | 2a424990 | Paul Brook | s->eeprom_writable = 0;
|
927 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write Disable\n");
|
928 | 2a424990 | Paul Brook | break;
|
929 | 2a424990 | Paul Brook | case 2: /* EWEN */ |
930 | 2a424990 | Paul Brook | s->eeprom_writable = 1;
|
931 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write Enable\n");
|
932 | 2a424990 | Paul Brook | break;
|
933 | 2a424990 | Paul Brook | case 3: /* WRITE */ |
934 | 2a424990 | Paul Brook | if (s->eeprom_writable) {
|
935 | 2a424990 | Paul Brook | s->eeprom[addr] &= s->e2p_data; |
936 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write %d = 0x%02x\n", addr, s->e2p_data);
|
937 | 2a424990 | Paul Brook | } else {
|
938 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write %d (ignored)\n", addr);
|
939 | 2a424990 | Paul Brook | } |
940 | 2a424990 | Paul Brook | break;
|
941 | 2a424990 | Paul Brook | case 4: /* WRAL */ |
942 | 2a424990 | Paul Brook | if (s->eeprom_writable) {
|
943 | 2a424990 | Paul Brook | for (addr = 0; addr < 128; addr++) { |
944 | 2a424990 | Paul Brook | s->eeprom[addr] &= s->e2p_data; |
945 | 2a424990 | Paul Brook | } |
946 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write All 0x%02x\n", s->e2p_data);
|
947 | 2a424990 | Paul Brook | } else {
|
948 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write All (ignored)\n");
|
949 | 2a424990 | Paul Brook | } |
950 | 0e3b800e | Peter Maydell | break;
|
951 | 2a424990 | Paul Brook | case 5: /* ERASE */ |
952 | 2a424990 | Paul Brook | if (s->eeprom_writable) {
|
953 | 2a424990 | Paul Brook | s->eeprom[addr] = 0xff;
|
954 | 2a424990 | Paul Brook | DPRINTF("EEPROM Erase %d\n", addr);
|
955 | 2a424990 | Paul Brook | } else {
|
956 | 2a424990 | Paul Brook | DPRINTF("EEPROM Erase %d (ignored)\n", addr);
|
957 | 2a424990 | Paul Brook | } |
958 | 2a424990 | Paul Brook | break;
|
959 | 2a424990 | Paul Brook | case 6: /* ERAL */ |
960 | 2a424990 | Paul Brook | if (s->eeprom_writable) {
|
961 | 2a424990 | Paul Brook | memset(s->eeprom, 0xff, 128); |
962 | 2a424990 | Paul Brook | DPRINTF("EEPROM Erase All\n");
|
963 | 2a424990 | Paul Brook | } else {
|
964 | 2a424990 | Paul Brook | DPRINTF("EEPROM Erase All (ignored)\n");
|
965 | 2a424990 | Paul Brook | } |
966 | 2a424990 | Paul Brook | break;
|
967 | 2a424990 | Paul Brook | case 7: /* RELOAD */ |
968 | 2a424990 | Paul Brook | lan9118_reload_eeprom(s); |
969 | 2a424990 | Paul Brook | break;
|
970 | 2a424990 | Paul Brook | } |
971 | 2a424990 | Paul Brook | } |
972 | 2a424990 | Paul Brook | |
973 | 209bf965 | Paul Brook | static void lan9118_tick(void *opaque) |
974 | 209bf965 | Paul Brook | { |
975 | 209bf965 | Paul Brook | lan9118_state *s = (lan9118_state *)opaque; |
976 | 209bf965 | Paul Brook | if (s->int_en & GPT_INT) {
|
977 | 209bf965 | Paul Brook | s->int_sts |= GPT_INT; |
978 | 209bf965 | Paul Brook | } |
979 | 209bf965 | Paul Brook | lan9118_update(s); |
980 | 209bf965 | Paul Brook | } |
981 | 209bf965 | Paul Brook | |
982 | 2a424990 | Paul Brook | static void lan9118_writel(void *opaque, target_phys_addr_t offset, |
983 | f0cdd7a9 | Peter Maydell | uint64_t val, unsigned size)
|
984 | 2a424990 | Paul Brook | { |
985 | 2a424990 | Paul Brook | lan9118_state *s = (lan9118_state *)opaque; |
986 | 2a424990 | Paul Brook | offset &= 0xff;
|
987 | 2a424990 | Paul Brook | |
988 | 2a424990 | Paul Brook | //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
|
989 | 2a424990 | Paul Brook | if (offset >= 0x20 && offset < 0x40) { |
990 | 2a424990 | Paul Brook | /* TX FIFO */
|
991 | 2a424990 | Paul Brook | tx_fifo_push(s, val); |
992 | 2a424990 | Paul Brook | return;
|
993 | 2a424990 | Paul Brook | } |
994 | 2a424990 | Paul Brook | switch (offset) {
|
995 | 2a424990 | Paul Brook | case CSR_IRQ_CFG:
|
996 | 2a424990 | Paul Brook | /* TODO: Implement interrupt deassertion intervals. */
|
997 | eb47d7c5 | Peter Maydell | val &= (IRQ_EN | IRQ_POL | IRQ_TYPE); |
998 | eb47d7c5 | Peter Maydell | s->irq_cfg = (s->irq_cfg & IRQ_INT) | val; |
999 | 2a424990 | Paul Brook | break;
|
1000 | 2a424990 | Paul Brook | case CSR_INT_STS:
|
1001 | 2a424990 | Paul Brook | s->int_sts &= ~val; |
1002 | 2a424990 | Paul Brook | break;
|
1003 | 2a424990 | Paul Brook | case CSR_INT_EN:
|
1004 | 2a424990 | Paul Brook | s->int_en = val & ~RESERVED_INT; |
1005 | 2a424990 | Paul Brook | s->int_sts |= val & SW_INT; |
1006 | 2a424990 | Paul Brook | break;
|
1007 | 2a424990 | Paul Brook | case CSR_FIFO_INT:
|
1008 | 2a424990 | Paul Brook | DPRINTF("FIFO INT levels %08x\n", val);
|
1009 | 2a424990 | Paul Brook | s->fifo_int = val; |
1010 | 2a424990 | Paul Brook | break;
|
1011 | 2a424990 | Paul Brook | case CSR_RX_CFG:
|
1012 | 2a424990 | Paul Brook | if (val & 0x8000) { |
1013 | 2a424990 | Paul Brook | /* RX_DUMP */
|
1014 | 2a424990 | Paul Brook | s->rx_fifo_used = 0;
|
1015 | 2a424990 | Paul Brook | s->rx_status_fifo_used = 0;
|
1016 | 2a424990 | Paul Brook | s->rx_packet_size_tail = s->rx_packet_size_head; |
1017 | 2a424990 | Paul Brook | s->rx_packet_size[s->rx_packet_size_head] = 0;
|
1018 | 2a424990 | Paul Brook | } |
1019 | 2a424990 | Paul Brook | s->rx_cfg = val & 0xcfff1ff0;
|
1020 | 2a424990 | Paul Brook | break;
|
1021 | 2a424990 | Paul Brook | case CSR_TX_CFG:
|
1022 | 2a424990 | Paul Brook | if (val & 0x8000) { |
1023 | 2a424990 | Paul Brook | s->tx_status_fifo_used = 0;
|
1024 | 2a424990 | Paul Brook | } |
1025 | 2a424990 | Paul Brook | if (val & 0x4000) { |
1026 | 2a424990 | Paul Brook | s->txp->state = TX_IDLE; |
1027 | 2a424990 | Paul Brook | s->txp->fifo_used = 0;
|
1028 | 2a424990 | Paul Brook | s->txp->cmd_a = 0xffffffff;
|
1029 | 2a424990 | Paul Brook | } |
1030 | 2a424990 | Paul Brook | s->tx_cfg = val & 6;
|
1031 | 2a424990 | Paul Brook | break;
|
1032 | 2a424990 | Paul Brook | case CSR_HW_CFG:
|
1033 | 2a424990 | Paul Brook | if (val & 1) { |
1034 | 2a424990 | Paul Brook | /* SRST */
|
1035 | 2a424990 | Paul Brook | lan9118_reset(&s->busdev.qdev); |
1036 | 2a424990 | Paul Brook | } else {
|
1037 | 2a424990 | Paul Brook | s->hw_cfg = val & 0x003f300;
|
1038 | 2a424990 | Paul Brook | } |
1039 | 2a424990 | Paul Brook | break;
|
1040 | 2a424990 | Paul Brook | case CSR_RX_DP_CTRL:
|
1041 | 2a424990 | Paul Brook | if (val & 0x80000000) { |
1042 | 2a424990 | Paul Brook | /* Skip forward to next packet. */
|
1043 | 2a424990 | Paul Brook | s->rxp_pad = 0;
|
1044 | 2a424990 | Paul Brook | s->rxp_offset = 0;
|
1045 | 2a424990 | Paul Brook | if (s->rxp_size == 0) { |
1046 | 2a424990 | Paul Brook | /* Pop a word to start the next packet. */
|
1047 | 2a424990 | Paul Brook | rx_fifo_pop(s); |
1048 | 2a424990 | Paul Brook | s->rxp_pad = 0;
|
1049 | 2a424990 | Paul Brook | s->rxp_offset = 0;
|
1050 | 2a424990 | Paul Brook | } |
1051 | 2a424990 | Paul Brook | s->rx_fifo_head += s->rxp_size; |
1052 | 2a424990 | Paul Brook | if (s->rx_fifo_head >= s->rx_fifo_size) {
|
1053 | 2a424990 | Paul Brook | s->rx_fifo_head -= s->rx_fifo_size; |
1054 | 2a424990 | Paul Brook | } |
1055 | 2a424990 | Paul Brook | } |
1056 | 2a424990 | Paul Brook | break;
|
1057 | 2a424990 | Paul Brook | case CSR_PMT_CTRL:
|
1058 | 2a424990 | Paul Brook | if (val & 0x400) { |
1059 | 2a424990 | Paul Brook | phy_reset(s); |
1060 | 2a424990 | Paul Brook | } |
1061 | 2a424990 | Paul Brook | s->pmt_ctrl &= ~0x34e;
|
1062 | 2a424990 | Paul Brook | s->pmt_ctrl |= (val & 0x34e);
|
1063 | 2a424990 | Paul Brook | break;
|
1064 | 2a424990 | Paul Brook | case CSR_GPIO_CFG:
|
1065 | 2a424990 | Paul Brook | /* Probably just enabling LEDs. */
|
1066 | 2a424990 | Paul Brook | s->gpio_cfg = val & 0x7777071f;
|
1067 | 2a424990 | Paul Brook | break;
|
1068 | 209bf965 | Paul Brook | case CSR_GPT_CFG:
|
1069 | 209bf965 | Paul Brook | if ((s->gpt_cfg ^ val) & GPT_TIMER_EN) {
|
1070 | 209bf965 | Paul Brook | if (val & GPT_TIMER_EN) {
|
1071 | 209bf965 | Paul Brook | ptimer_set_count(s->timer, val & 0xffff);
|
1072 | 209bf965 | Paul Brook | ptimer_run(s->timer, 0);
|
1073 | 209bf965 | Paul Brook | } else {
|
1074 | 209bf965 | Paul Brook | ptimer_stop(s->timer); |
1075 | 209bf965 | Paul Brook | ptimer_set_count(s->timer, 0xffff);
|
1076 | 209bf965 | Paul Brook | } |
1077 | 209bf965 | Paul Brook | } |
1078 | 209bf965 | Paul Brook | s->gpt_cfg = val & (GPT_TIMER_EN | 0xffff);
|
1079 | 209bf965 | Paul Brook | break;
|
1080 | 2a424990 | Paul Brook | case CSR_WORD_SWAP:
|
1081 | 2a424990 | Paul Brook | /* Ignored because we're in 32-bit mode. */
|
1082 | 2a424990 | Paul Brook | s->word_swap = val; |
1083 | 2a424990 | Paul Brook | break;
|
1084 | 2a424990 | Paul Brook | case CSR_MAC_CSR_CMD:
|
1085 | 2a424990 | Paul Brook | s->mac_cmd = val & 0x4000000f;
|
1086 | 2a424990 | Paul Brook | if (val & 0x80000000) { |
1087 | 2a424990 | Paul Brook | if (val & 0x40000000) { |
1088 | 2a424990 | Paul Brook | s->mac_data = do_mac_read(s, val & 0xf);
|
1089 | 2a424990 | Paul Brook | DPRINTF("MAC read %d = 0x%08x\n", val & 0xf, s->mac_data); |
1090 | 2a424990 | Paul Brook | } else {
|
1091 | 2a424990 | Paul Brook | DPRINTF("MAC write %d = 0x%08x\n", val & 0xf, s->mac_data); |
1092 | 2a424990 | Paul Brook | do_mac_write(s, val & 0xf, s->mac_data);
|
1093 | 2a424990 | Paul Brook | } |
1094 | 2a424990 | Paul Brook | } |
1095 | 2a424990 | Paul Brook | break;
|
1096 | 2a424990 | Paul Brook | case CSR_MAC_CSR_DATA:
|
1097 | 2a424990 | Paul Brook | s->mac_data = val; |
1098 | 2a424990 | Paul Brook | break;
|
1099 | 2a424990 | Paul Brook | case CSR_AFC_CFG:
|
1100 | 2a424990 | Paul Brook | s->afc_cfg = val & 0x00ffffff;
|
1101 | 2a424990 | Paul Brook | break;
|
1102 | 2a424990 | Paul Brook | case CSR_E2P_CMD:
|
1103 | c46a3ea0 | Blue Swirl | lan9118_eeprom_cmd(s, (val >> 28) & 7, val & 0x7f); |
1104 | 2a424990 | Paul Brook | break;
|
1105 | 2a424990 | Paul Brook | case CSR_E2P_DATA:
|
1106 | 2a424990 | Paul Brook | s->e2p_data = val & 0xff;
|
1107 | 2a424990 | Paul Brook | break;
|
1108 | 2a424990 | Paul Brook | |
1109 | 2a424990 | Paul Brook | default:
|
1110 | f0cdd7a9 | Peter Maydell | hw_error("lan9118_write: Bad reg 0x%x = %x\n", (int)offset, (int)val); |
1111 | 2a424990 | Paul Brook | break;
|
1112 | 2a424990 | Paul Brook | } |
1113 | 2a424990 | Paul Brook | lan9118_update(s); |
1114 | 2a424990 | Paul Brook | } |
1115 | 2a424990 | Paul Brook | |
1116 | f0cdd7a9 | Peter Maydell | static uint64_t lan9118_readl(void *opaque, target_phys_addr_t offset, |
1117 | f0cdd7a9 | Peter Maydell | unsigned size)
|
1118 | 2a424990 | Paul Brook | { |
1119 | 2a424990 | Paul Brook | lan9118_state *s = (lan9118_state *)opaque; |
1120 | 2a424990 | Paul Brook | |
1121 | 2a424990 | Paul Brook | //DPRINTF("Read reg 0x%02x\n", (int)offset);
|
1122 | 2a424990 | Paul Brook | if (offset < 0x20) { |
1123 | 2a424990 | Paul Brook | /* RX FIFO */
|
1124 | 2a424990 | Paul Brook | return rx_fifo_pop(s);
|
1125 | 2a424990 | Paul Brook | } |
1126 | 2a424990 | Paul Brook | switch (offset) {
|
1127 | 2a424990 | Paul Brook | case 0x40: |
1128 | 2a424990 | Paul Brook | return rx_status_fifo_pop(s);
|
1129 | 2a424990 | Paul Brook | case 0x44: |
1130 | 2a424990 | Paul Brook | return s->rx_status_fifo[s->tx_status_fifo_head];
|
1131 | 2a424990 | Paul Brook | case 0x48: |
1132 | 2a424990 | Paul Brook | return tx_status_fifo_pop(s);
|
1133 | 2a424990 | Paul Brook | case 0x4c: |
1134 | 2a424990 | Paul Brook | return s->tx_status_fifo[s->tx_status_fifo_head];
|
1135 | 2a424990 | Paul Brook | case CSR_ID_REV:
|
1136 | 2a424990 | Paul Brook | return 0x01180001; |
1137 | 2a424990 | Paul Brook | case CSR_IRQ_CFG:
|
1138 | 2a424990 | Paul Brook | return s->irq_cfg;
|
1139 | 2a424990 | Paul Brook | case CSR_INT_STS:
|
1140 | 2a424990 | Paul Brook | return s->int_sts;
|
1141 | 2a424990 | Paul Brook | case CSR_INT_EN:
|
1142 | 2a424990 | Paul Brook | return s->int_en;
|
1143 | 2a424990 | Paul Brook | case CSR_BYTE_TEST:
|
1144 | 2a424990 | Paul Brook | return 0x87654321; |
1145 | 2a424990 | Paul Brook | case CSR_FIFO_INT:
|
1146 | 2a424990 | Paul Brook | return s->fifo_int;
|
1147 | 2a424990 | Paul Brook | case CSR_RX_CFG:
|
1148 | 2a424990 | Paul Brook | return s->rx_cfg;
|
1149 | 2a424990 | Paul Brook | case CSR_TX_CFG:
|
1150 | 2a424990 | Paul Brook | return s->tx_cfg;
|
1151 | 2a424990 | Paul Brook | case CSR_HW_CFG:
|
1152 | 2a424990 | Paul Brook | return s->hw_cfg | 0x4; |
1153 | 2a424990 | Paul Brook | case CSR_RX_DP_CTRL:
|
1154 | 2a424990 | Paul Brook | return 0; |
1155 | 2a424990 | Paul Brook | case CSR_RX_FIFO_INF:
|
1156 | 2a424990 | Paul Brook | return (s->rx_status_fifo_used << 16) | (s->rx_fifo_used << 2); |
1157 | 2a424990 | Paul Brook | case CSR_TX_FIFO_INF:
|
1158 | 2a424990 | Paul Brook | return (s->tx_status_fifo_used << 16) |
1159 | 2a424990 | Paul Brook | | (s->tx_fifo_size - s->txp->fifo_used); |
1160 | 2a424990 | Paul Brook | case CSR_PMT_CTRL:
|
1161 | 2a424990 | Paul Brook | return s->pmt_ctrl;
|
1162 | 2a424990 | Paul Brook | case CSR_GPIO_CFG:
|
1163 | 2a424990 | Paul Brook | return s->gpio_cfg;
|
1164 | 209bf965 | Paul Brook | case CSR_GPT_CFG:
|
1165 | 209bf965 | Paul Brook | return s->gpt_cfg;
|
1166 | 209bf965 | Paul Brook | case CSR_GPT_CNT:
|
1167 | 209bf965 | Paul Brook | return ptimer_get_count(s->timer);
|
1168 | 2a424990 | Paul Brook | case CSR_WORD_SWAP:
|
1169 | 2a424990 | Paul Brook | return s->word_swap;
|
1170 | 2a424990 | Paul Brook | case CSR_FREE_RUN:
|
1171 | 74475455 | Paolo Bonzini | return (qemu_get_clock_ns(vm_clock) / 40) - s->free_timer_start; |
1172 | 2a424990 | Paul Brook | case CSR_RX_DROP:
|
1173 | 2a424990 | Paul Brook | /* TODO: Implement dropped frames counter. */
|
1174 | 2a424990 | Paul Brook | return 0; |
1175 | 2a424990 | Paul Brook | case CSR_MAC_CSR_CMD:
|
1176 | 2a424990 | Paul Brook | return s->mac_cmd;
|
1177 | 2a424990 | Paul Brook | case CSR_MAC_CSR_DATA:
|
1178 | 2a424990 | Paul Brook | return s->mac_data;
|
1179 | 2a424990 | Paul Brook | case CSR_AFC_CFG:
|
1180 | 2a424990 | Paul Brook | return s->afc_cfg;
|
1181 | 2a424990 | Paul Brook | case CSR_E2P_CMD:
|
1182 | 2a424990 | Paul Brook | return s->e2p_cmd;
|
1183 | 2a424990 | Paul Brook | case CSR_E2P_DATA:
|
1184 | 2a424990 | Paul Brook | return s->e2p_data;
|
1185 | 2a424990 | Paul Brook | } |
1186 | 2a424990 | Paul Brook | hw_error("lan9118_read: Bad reg 0x%x\n", (int)offset); |
1187 | 2a424990 | Paul Brook | return 0; |
1188 | 2a424990 | Paul Brook | } |
1189 | 2a424990 | Paul Brook | |
1190 | f0cdd7a9 | Peter Maydell | static const MemoryRegionOps lan9118_mem_ops = { |
1191 | f0cdd7a9 | Peter Maydell | .read = lan9118_readl, |
1192 | f0cdd7a9 | Peter Maydell | .write = lan9118_writel, |
1193 | f0cdd7a9 | Peter Maydell | .endianness = DEVICE_NATIVE_ENDIAN, |
1194 | 2a424990 | Paul Brook | }; |
1195 | 2a424990 | Paul Brook | |
1196 | 83b9f88c | Mark McLoughlin | static void lan9118_cleanup(VLANClientState *nc) |
1197 | 2a424990 | Paul Brook | { |
1198 | 83b9f88c | Mark McLoughlin | lan9118_state *s = DO_UPCAST(NICState, nc, nc)->opaque; |
1199 | 2a424990 | Paul Brook | |
1200 | 83b9f88c | Mark McLoughlin | s->nic = NULL;
|
1201 | 2a424990 | Paul Brook | } |
1202 | 2a424990 | Paul Brook | |
1203 | 83b9f88c | Mark McLoughlin | static NetClientInfo net_lan9118_info = {
|
1204 | 83b9f88c | Mark McLoughlin | .type = NET_CLIENT_TYPE_NIC, |
1205 | 83b9f88c | Mark McLoughlin | .size = sizeof(NICState),
|
1206 | 83b9f88c | Mark McLoughlin | .can_receive = lan9118_can_receive, |
1207 | 83b9f88c | Mark McLoughlin | .receive = lan9118_receive, |
1208 | 83b9f88c | Mark McLoughlin | .cleanup = lan9118_cleanup, |
1209 | 83b9f88c | Mark McLoughlin | .link_status_changed = lan9118_set_link, |
1210 | 83b9f88c | Mark McLoughlin | }; |
1211 | 83b9f88c | Mark McLoughlin | |
1212 | 2a424990 | Paul Brook | static int lan9118_init1(SysBusDevice *dev) |
1213 | 2a424990 | Paul Brook | { |
1214 | 2a424990 | Paul Brook | lan9118_state *s = FROM_SYSBUS(lan9118_state, dev); |
1215 | 209bf965 | Paul Brook | QEMUBH *bh; |
1216 | 2a424990 | Paul Brook | int i;
|
1217 | 2a424990 | Paul Brook | |
1218 | f0cdd7a9 | Peter Maydell | memory_region_init_io(&s->mmio, &lan9118_mem_ops, s, "lan9118-mmio", 0x100); |
1219 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->mmio); |
1220 | 2a424990 | Paul Brook | sysbus_init_irq(dev, &s->irq); |
1221 | 2a424990 | Paul Brook | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
1222 | 2a424990 | Paul Brook | |
1223 | 83b9f88c | Mark McLoughlin | s->nic = qemu_new_nic(&net_lan9118_info, &s->conf, |
1224 | f79f2bfc | Anthony Liguori | object_get_typename(OBJECT(dev)), dev->qdev.id, s); |
1225 | 83b9f88c | Mark McLoughlin | qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
1226 | 2a424990 | Paul Brook | s->eeprom[0] = 0xa5; |
1227 | 2a424990 | Paul Brook | for (i = 0; i < 6; i++) { |
1228 | 2a424990 | Paul Brook | s->eeprom[i + 1] = s->conf.macaddr.a[i];
|
1229 | 2a424990 | Paul Brook | } |
1230 | 2a424990 | Paul Brook | s->pmt_ctrl = 1;
|
1231 | 2a424990 | Paul Brook | s->txp = &s->tx_packet; |
1232 | 2a424990 | Paul Brook | |
1233 | 209bf965 | Paul Brook | bh = qemu_bh_new(lan9118_tick, s); |
1234 | 209bf965 | Paul Brook | s->timer = ptimer_init(bh); |
1235 | 209bf965 | Paul Brook | ptimer_set_freq(s->timer, 10000);
|
1236 | 209bf965 | Paul Brook | ptimer_set_limit(s->timer, 0xffff, 1); |
1237 | 209bf965 | Paul Brook | |
1238 | 2a424990 | Paul Brook | return 0; |
1239 | 2a424990 | Paul Brook | } |
1240 | 2a424990 | Paul Brook | |
1241 | 2a424990 | Paul Brook | static SysBusDeviceInfo lan9118_info = {
|
1242 | 2a424990 | Paul Brook | .init = lan9118_init1, |
1243 | 2a424990 | Paul Brook | .qdev.name = "lan9118",
|
1244 | 2a424990 | Paul Brook | .qdev.size = sizeof(lan9118_state),
|
1245 | 2a424990 | Paul Brook | .qdev.reset = lan9118_reset, |
1246 | b09da0c3 | Peter Maydell | .qdev.vmsd = &vmstate_lan9118, |
1247 | 2a424990 | Paul Brook | .qdev.props = (Property[]) { |
1248 | 2a424990 | Paul Brook | DEFINE_NIC_PROPERTIES(lan9118_state, conf), |
1249 | 2a424990 | Paul Brook | DEFINE_PROP_END_OF_LIST(), |
1250 | 2a424990 | Paul Brook | } |
1251 | 2a424990 | Paul Brook | }; |
1252 | 2a424990 | Paul Brook | |
1253 | 2a424990 | Paul Brook | static void lan9118_register_devices(void) |
1254 | 2a424990 | Paul Brook | { |
1255 | 2a424990 | Paul Brook | sysbus_register_withprop(&lan9118_info); |
1256 | 2a424990 | Paul Brook | } |
1257 | 2a424990 | Paul Brook | |
1258 | 2a424990 | Paul Brook | /* Legacy helper function. Should go away when machine config files are
|
1259 | 2a424990 | Paul Brook | implemented. */
|
1260 | 2a424990 | Paul Brook | void lan9118_init(NICInfo *nd, uint32_t base, qemu_irq irq)
|
1261 | 2a424990 | Paul Brook | { |
1262 | 2a424990 | Paul Brook | DeviceState *dev; |
1263 | 2a424990 | Paul Brook | SysBusDevice *s; |
1264 | 2a424990 | Paul Brook | |
1265 | 2a424990 | Paul Brook | qemu_check_nic_model(nd, "lan9118");
|
1266 | 2a424990 | Paul Brook | dev = qdev_create(NULL, "lan9118"); |
1267 | 2a424990 | Paul Brook | qdev_set_nic_properties(dev, nd); |
1268 | 2a424990 | Paul Brook | qdev_init_nofail(dev); |
1269 | 2a424990 | Paul Brook | s = sysbus_from_qdev(dev); |
1270 | 2a424990 | Paul Brook | sysbus_mmio_map(s, 0, base);
|
1271 | 2a424990 | Paul Brook | sysbus_connect_irq(s, 0, irq);
|
1272 | 2a424990 | Paul Brook | } |
1273 | 2a424990 | Paul Brook | |
1274 | 2a424990 | Paul Brook | device_init(lan9118_register_devices) |