root / target-i386 / misc_helper.c @ f7b2429f
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/*
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* x86 misc helpers
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h" |
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#include "dyngen-exec.h" |
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#include "ioport.h" |
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#include "helper.h" |
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#if !defined(CONFIG_USER_ONLY)
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#include "softmmu_exec.h" |
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#endif /* !defined(CONFIG_USER_ONLY) */ |
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/* check if Port I/O is allowed in TSS */
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static inline void check_io(int addr, int size) |
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{ |
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int io_offset, val, mask;
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/* TSS must be a valid 32 bit one */
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if (!(env->tr.flags & DESC_P_MASK) ||
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((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 || |
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env->tr.limit < 103) {
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goto fail;
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} |
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io_offset = lduw_kernel(env->tr.base + 0x66);
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io_offset += (addr >> 3);
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/* Note: the check needs two bytes */
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if ((io_offset + 1) > env->tr.limit) { |
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goto fail;
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} |
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val = lduw_kernel(env->tr.base + io_offset); |
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val >>= (addr & 7);
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mask = (1 << size) - 1; |
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/* all bits must be zero to allow the I/O */
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if ((val & mask) != 0) { |
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fail:
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raise_exception_err(env, EXCP0D_GPF, 0);
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} |
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} |
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|
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void helper_check_iob(uint32_t t0)
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{ |
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check_io(t0, 1);
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} |
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void helper_check_iow(uint32_t t0)
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{ |
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check_io(t0, 2);
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} |
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void helper_check_iol(uint32_t t0)
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{ |
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check_io(t0, 4);
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} |
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void helper_outb(uint32_t port, uint32_t data)
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{ |
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cpu_outb(port, data & 0xff);
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} |
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target_ulong helper_inb(uint32_t port) |
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{ |
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return cpu_inb(port);
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} |
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|
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void helper_outw(uint32_t port, uint32_t data)
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{ |
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cpu_outw(port, data & 0xffff);
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} |
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|
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target_ulong helper_inw(uint32_t port) |
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{ |
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return cpu_inw(port);
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} |
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void helper_outl(uint32_t port, uint32_t data)
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{ |
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cpu_outl(port, data); |
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} |
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target_ulong helper_inl(uint32_t port) |
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{ |
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return cpu_inl(port);
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} |
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void helper_into(int next_eip_addend) |
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{ |
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int eflags;
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|
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eflags = helper_cc_compute_all(CC_OP); |
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if (eflags & CC_O) {
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raise_interrupt(env, EXCP04_INTO, 1, 0, next_eip_addend); |
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} |
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} |
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void helper_single_step(void) |
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{ |
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#ifndef CONFIG_USER_ONLY
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check_hw_breakpoints(env, 1);
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env->dr[6] |= DR6_BS;
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#endif
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raise_exception(env, EXCP01_DB); |
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} |
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|
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void helper_cpuid(void) |
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{ |
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uint32_t eax, ebx, ecx, edx; |
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|
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cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0);
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cpu_x86_cpuid(env, (uint32_t)EAX, (uint32_t)ECX, &eax, &ebx, &ecx, &edx); |
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EAX = eax; |
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EBX = ebx; |
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ECX = ecx; |
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EDX = edx; |
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} |
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#if defined(CONFIG_USER_ONLY)
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target_ulong helper_read_crN(int reg)
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{ |
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return 0; |
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} |
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void helper_write_crN(int reg, target_ulong t0) |
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{ |
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} |
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void helper_movl_drN_T0(int reg, target_ulong t0) |
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{ |
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} |
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#else
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target_ulong helper_read_crN(int reg)
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{ |
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target_ulong val; |
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cpu_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0);
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switch (reg) {
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default:
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val = env->cr[reg]; |
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break;
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case 8: |
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if (!(env->hflags2 & HF2_VINTR_MASK)) {
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val = cpu_get_apic_tpr(env->apic_state); |
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} else {
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val = env->v_tpr; |
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} |
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break;
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} |
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return val;
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} |
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void helper_write_crN(int reg, target_ulong t0) |
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{ |
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cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0);
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switch (reg) {
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case 0: |
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cpu_x86_update_cr0(env, t0); |
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break;
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case 3: |
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cpu_x86_update_cr3(env, t0); |
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break;
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case 4: |
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cpu_x86_update_cr4(env, t0); |
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break;
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case 8: |
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if (!(env->hflags2 & HF2_VINTR_MASK)) {
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cpu_set_apic_tpr(env->apic_state, t0); |
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} |
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env->v_tpr = t0 & 0x0f;
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break;
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default:
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env->cr[reg] = t0; |
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break;
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} |
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} |
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|
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void helper_movl_drN_T0(int reg, target_ulong t0) |
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{ |
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int i;
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if (reg < 4) { |
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hw_breakpoint_remove(env, reg); |
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env->dr[reg] = t0; |
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hw_breakpoint_insert(env, reg); |
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} else if (reg == 7) { |
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for (i = 0; i < 4; i++) { |
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hw_breakpoint_remove(env, i); |
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} |
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env->dr[7] = t0;
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for (i = 0; i < 4; i++) { |
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hw_breakpoint_insert(env, i); |
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} |
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} else {
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env->dr[reg] = t0; |
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} |
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} |
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#endif
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void helper_lmsw(target_ulong t0)
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{ |
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/* only 4 lower bits of CR0 are modified. PE cannot be set to zero
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if already set to one. */
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t0 = (env->cr[0] & ~0xe) | (t0 & 0xf); |
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helper_write_crN(0, t0);
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} |
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void helper_invlpg(target_ulong addr)
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{ |
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cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0);
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tlb_flush_page(env, addr); |
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} |
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void helper_rdtsc(void) |
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{ |
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uint64_t val; |
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|
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if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) { |
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raise_exception(env, EXCP0D_GPF); |
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} |
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cpu_svm_check_intercept_param(env, SVM_EXIT_RDTSC, 0);
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|
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val = cpu_get_tsc(env) + env->tsc_offset; |
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EAX = (uint32_t)(val); |
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EDX = (uint32_t)(val >> 32);
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} |
241 |
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void helper_rdtscp(void) |
243 |
{ |
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helper_rdtsc(); |
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ECX = (uint32_t)(env->tsc_aux); |
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} |
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void helper_rdpmc(void) |
249 |
{ |
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if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) { |
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raise_exception(env, EXCP0D_GPF); |
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} |
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cpu_svm_check_intercept_param(env, SVM_EXIT_RDPMC, 0);
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/* currently unimplemented */
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qemu_log_mask(LOG_UNIMP, "x86: unimplemented rdpmc\n");
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raise_exception_err(env, EXCP06_ILLOP, 0);
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} |
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#if defined(CONFIG_USER_ONLY)
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void helper_wrmsr(void) |
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{ |
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} |
264 |
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void helper_rdmsr(void) |
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{ |
267 |
} |
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#else
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void helper_wrmsr(void) |
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{ |
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uint64_t val; |
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cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1);
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val = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
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switch ((uint32_t)ECX) {
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case MSR_IA32_SYSENTER_CS:
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env->sysenter_cs = val & 0xffff;
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break;
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case MSR_IA32_SYSENTER_ESP:
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env->sysenter_esp = val; |
283 |
break;
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case MSR_IA32_SYSENTER_EIP:
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env->sysenter_eip = val; |
286 |
break;
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case MSR_IA32_APICBASE:
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cpu_set_apic_base(env->apic_state, val); |
289 |
break;
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case MSR_EFER:
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{ |
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uint64_t update_mask; |
293 |
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update_mask = 0;
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if (env->cpuid_ext2_features & CPUID_EXT2_SYSCALL) {
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update_mask |= MSR_EFER_SCE; |
297 |
} |
298 |
if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
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update_mask |= MSR_EFER_LME; |
300 |
} |
301 |
if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR) {
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update_mask |= MSR_EFER_FFXSR; |
303 |
} |
304 |
if (env->cpuid_ext2_features & CPUID_EXT2_NX) {
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update_mask |= MSR_EFER_NXE; |
306 |
} |
307 |
if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
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update_mask |= MSR_EFER_SVME; |
309 |
} |
310 |
if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR) {
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311 |
update_mask |= MSR_EFER_FFXSR; |
312 |
} |
313 |
cpu_load_efer(env, (env->efer & ~update_mask) | |
314 |
(val & update_mask)); |
315 |
} |
316 |
break;
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317 |
case MSR_STAR:
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318 |
env->star = val; |
319 |
break;
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320 |
case MSR_PAT:
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321 |
env->pat = val; |
322 |
break;
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323 |
case MSR_VM_HSAVE_PA:
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env->vm_hsave = val; |
325 |
break;
|
326 |
#ifdef TARGET_X86_64
|
327 |
case MSR_LSTAR:
|
328 |
env->lstar = val; |
329 |
break;
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330 |
case MSR_CSTAR:
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331 |
env->cstar = val; |
332 |
break;
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333 |
case MSR_FMASK:
|
334 |
env->fmask = val; |
335 |
break;
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336 |
case MSR_FSBASE:
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337 |
env->segs[R_FS].base = val; |
338 |
break;
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339 |
case MSR_GSBASE:
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340 |
env->segs[R_GS].base = val; |
341 |
break;
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342 |
case MSR_KERNELGSBASE:
|
343 |
env->kernelgsbase = val; |
344 |
break;
|
345 |
#endif
|
346 |
case MSR_MTRRphysBase(0): |
347 |
case MSR_MTRRphysBase(1): |
348 |
case MSR_MTRRphysBase(2): |
349 |
case MSR_MTRRphysBase(3): |
350 |
case MSR_MTRRphysBase(4): |
351 |
case MSR_MTRRphysBase(5): |
352 |
case MSR_MTRRphysBase(6): |
353 |
case MSR_MTRRphysBase(7): |
354 |
env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysBase(0)) / 2].base = val; |
355 |
break;
|
356 |
case MSR_MTRRphysMask(0): |
357 |
case MSR_MTRRphysMask(1): |
358 |
case MSR_MTRRphysMask(2): |
359 |
case MSR_MTRRphysMask(3): |
360 |
case MSR_MTRRphysMask(4): |
361 |
case MSR_MTRRphysMask(5): |
362 |
case MSR_MTRRphysMask(6): |
363 |
case MSR_MTRRphysMask(7): |
364 |
env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysMask(0)) / 2].mask = val; |
365 |
break;
|
366 |
case MSR_MTRRfix64K_00000:
|
367 |
env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix64K_00000] = val; |
368 |
break;
|
369 |
case MSR_MTRRfix16K_80000:
|
370 |
case MSR_MTRRfix16K_A0000:
|
371 |
env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix16K_80000 + 1] = val;
|
372 |
break;
|
373 |
case MSR_MTRRfix4K_C0000:
|
374 |
case MSR_MTRRfix4K_C8000:
|
375 |
case MSR_MTRRfix4K_D0000:
|
376 |
case MSR_MTRRfix4K_D8000:
|
377 |
case MSR_MTRRfix4K_E0000:
|
378 |
case MSR_MTRRfix4K_E8000:
|
379 |
case MSR_MTRRfix4K_F0000:
|
380 |
case MSR_MTRRfix4K_F8000:
|
381 |
env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix4K_C0000 + 3] = val;
|
382 |
break;
|
383 |
case MSR_MTRRdefType:
|
384 |
env->mtrr_deftype = val; |
385 |
break;
|
386 |
case MSR_MCG_STATUS:
|
387 |
env->mcg_status = val; |
388 |
break;
|
389 |
case MSR_MCG_CTL:
|
390 |
if ((env->mcg_cap & MCG_CTL_P)
|
391 |
&& (val == 0 || val == ~(uint64_t)0)) { |
392 |
env->mcg_ctl = val; |
393 |
} |
394 |
break;
|
395 |
case MSR_TSC_AUX:
|
396 |
env->tsc_aux = val; |
397 |
break;
|
398 |
case MSR_IA32_MISC_ENABLE:
|
399 |
env->msr_ia32_misc_enable = val; |
400 |
break;
|
401 |
default:
|
402 |
if ((uint32_t)ECX >= MSR_MC0_CTL
|
403 |
&& (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) { |
404 |
uint32_t offset = (uint32_t)ECX - MSR_MC0_CTL; |
405 |
if ((offset & 0x3) != 0 |
406 |
|| (val == 0 || val == ~(uint64_t)0)) { |
407 |
env->mce_banks[offset] = val; |
408 |
} |
409 |
break;
|
410 |
} |
411 |
/* XXX: exception? */
|
412 |
break;
|
413 |
} |
414 |
} |
415 |
|
416 |
void helper_rdmsr(void) |
417 |
{ |
418 |
uint64_t val; |
419 |
|
420 |
cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0);
|
421 |
|
422 |
switch ((uint32_t)ECX) {
|
423 |
case MSR_IA32_SYSENTER_CS:
|
424 |
val = env->sysenter_cs; |
425 |
break;
|
426 |
case MSR_IA32_SYSENTER_ESP:
|
427 |
val = env->sysenter_esp; |
428 |
break;
|
429 |
case MSR_IA32_SYSENTER_EIP:
|
430 |
val = env->sysenter_eip; |
431 |
break;
|
432 |
case MSR_IA32_APICBASE:
|
433 |
val = cpu_get_apic_base(env->apic_state); |
434 |
break;
|
435 |
case MSR_EFER:
|
436 |
val = env->efer; |
437 |
break;
|
438 |
case MSR_STAR:
|
439 |
val = env->star; |
440 |
break;
|
441 |
case MSR_PAT:
|
442 |
val = env->pat; |
443 |
break;
|
444 |
case MSR_VM_HSAVE_PA:
|
445 |
val = env->vm_hsave; |
446 |
break;
|
447 |
case MSR_IA32_PERF_STATUS:
|
448 |
/* tsc_increment_by_tick */
|
449 |
val = 1000ULL;
|
450 |
/* CPU multiplier */
|
451 |
val |= (((uint64_t)4ULL) << 40); |
452 |
break;
|
453 |
#ifdef TARGET_X86_64
|
454 |
case MSR_LSTAR:
|
455 |
val = env->lstar; |
456 |
break;
|
457 |
case MSR_CSTAR:
|
458 |
val = env->cstar; |
459 |
break;
|
460 |
case MSR_FMASK:
|
461 |
val = env->fmask; |
462 |
break;
|
463 |
case MSR_FSBASE:
|
464 |
val = env->segs[R_FS].base; |
465 |
break;
|
466 |
case MSR_GSBASE:
|
467 |
val = env->segs[R_GS].base; |
468 |
break;
|
469 |
case MSR_KERNELGSBASE:
|
470 |
val = env->kernelgsbase; |
471 |
break;
|
472 |
case MSR_TSC_AUX:
|
473 |
val = env->tsc_aux; |
474 |
break;
|
475 |
#endif
|
476 |
case MSR_MTRRphysBase(0): |
477 |
case MSR_MTRRphysBase(1): |
478 |
case MSR_MTRRphysBase(2): |
479 |
case MSR_MTRRphysBase(3): |
480 |
case MSR_MTRRphysBase(4): |
481 |
case MSR_MTRRphysBase(5): |
482 |
case MSR_MTRRphysBase(6): |
483 |
case MSR_MTRRphysBase(7): |
484 |
val = env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysBase(0)) / 2].base; |
485 |
break;
|
486 |
case MSR_MTRRphysMask(0): |
487 |
case MSR_MTRRphysMask(1): |
488 |
case MSR_MTRRphysMask(2): |
489 |
case MSR_MTRRphysMask(3): |
490 |
case MSR_MTRRphysMask(4): |
491 |
case MSR_MTRRphysMask(5): |
492 |
case MSR_MTRRphysMask(6): |
493 |
case MSR_MTRRphysMask(7): |
494 |
val = env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysMask(0)) / 2].mask; |
495 |
break;
|
496 |
case MSR_MTRRfix64K_00000:
|
497 |
val = env->mtrr_fixed[0];
|
498 |
break;
|
499 |
case MSR_MTRRfix16K_80000:
|
500 |
case MSR_MTRRfix16K_A0000:
|
501 |
val = env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix16K_80000 + 1];
|
502 |
break;
|
503 |
case MSR_MTRRfix4K_C0000:
|
504 |
case MSR_MTRRfix4K_C8000:
|
505 |
case MSR_MTRRfix4K_D0000:
|
506 |
case MSR_MTRRfix4K_D8000:
|
507 |
case MSR_MTRRfix4K_E0000:
|
508 |
case MSR_MTRRfix4K_E8000:
|
509 |
case MSR_MTRRfix4K_F0000:
|
510 |
case MSR_MTRRfix4K_F8000:
|
511 |
val = env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix4K_C0000 + 3];
|
512 |
break;
|
513 |
case MSR_MTRRdefType:
|
514 |
val = env->mtrr_deftype; |
515 |
break;
|
516 |
case MSR_MTRRcap:
|
517 |
if (env->cpuid_features & CPUID_MTRR) {
|
518 |
val = MSR_MTRRcap_VCNT | MSR_MTRRcap_FIXRANGE_SUPPORT | |
519 |
MSR_MTRRcap_WC_SUPPORTED; |
520 |
} else {
|
521 |
/* XXX: exception? */
|
522 |
val = 0;
|
523 |
} |
524 |
break;
|
525 |
case MSR_MCG_CAP:
|
526 |
val = env->mcg_cap; |
527 |
break;
|
528 |
case MSR_MCG_CTL:
|
529 |
if (env->mcg_cap & MCG_CTL_P) {
|
530 |
val = env->mcg_ctl; |
531 |
} else {
|
532 |
val = 0;
|
533 |
} |
534 |
break;
|
535 |
case MSR_MCG_STATUS:
|
536 |
val = env->mcg_status; |
537 |
break;
|
538 |
case MSR_IA32_MISC_ENABLE:
|
539 |
val = env->msr_ia32_misc_enable; |
540 |
break;
|
541 |
default:
|
542 |
if ((uint32_t)ECX >= MSR_MC0_CTL
|
543 |
&& (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) { |
544 |
uint32_t offset = (uint32_t)ECX - MSR_MC0_CTL; |
545 |
val = env->mce_banks[offset]; |
546 |
break;
|
547 |
} |
548 |
/* XXX: exception? */
|
549 |
val = 0;
|
550 |
break;
|
551 |
} |
552 |
EAX = (uint32_t)(val); |
553 |
EDX = (uint32_t)(val >> 32);
|
554 |
} |
555 |
#endif
|
556 |
|
557 |
static void do_hlt(void) |
558 |
{ |
559 |
env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
|
560 |
env->halted = 1;
|
561 |
env->exception_index = EXCP_HLT; |
562 |
cpu_loop_exit(env); |
563 |
} |
564 |
|
565 |
void helper_hlt(int next_eip_addend) |
566 |
{ |
567 |
cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0);
|
568 |
EIP += next_eip_addend; |
569 |
|
570 |
do_hlt(); |
571 |
} |
572 |
|
573 |
void helper_monitor(target_ulong ptr)
|
574 |
{ |
575 |
if ((uint32_t)ECX != 0) { |
576 |
raise_exception(env, EXCP0D_GPF); |
577 |
} |
578 |
/* XXX: store address? */
|
579 |
cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0);
|
580 |
} |
581 |
|
582 |
void helper_mwait(int next_eip_addend) |
583 |
{ |
584 |
if ((uint32_t)ECX != 0) { |
585 |
raise_exception(env, EXCP0D_GPF); |
586 |
} |
587 |
cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0);
|
588 |
EIP += next_eip_addend; |
589 |
|
590 |
/* XXX: not complete but not completely erroneous */
|
591 |
if (env->cpu_index != 0 || env->next_cpu != NULL) { |
592 |
/* more than one CPU: do not sleep because another CPU may
|
593 |
wake this one */
|
594 |
} else {
|
595 |
do_hlt(); |
596 |
} |
597 |
} |
598 |
|
599 |
void helper_debug(void) |
600 |
{ |
601 |
env->exception_index = EXCP_DEBUG; |
602 |
cpu_loop_exit(env); |
603 |
} |