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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU NE2000 emulation
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3 | 5fafdf24 | ths | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pci.h" |
26 | 9596ebb7 | pbrook | #include "pc.h" |
27 | 87ecb68b | pbrook | #include "net.h" |
28 | 80cabfad | bellard | |
29 | 80cabfad | bellard | /* debug NE2000 card */
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30 | 80cabfad | bellard | //#define DEBUG_NE2000
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31 | 80cabfad | bellard | |
32 | b41a2cd1 | bellard | #define MAX_ETH_FRAME_SIZE 1514 |
33 | 80cabfad | bellard | |
34 | 80cabfad | bellard | #define E8390_CMD 0x00 /* The command register (for all pages) */ |
35 | 80cabfad | bellard | /* Page 0 register offsets. */
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36 | 80cabfad | bellard | #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ |
37 | 80cabfad | bellard | #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ |
38 | 80cabfad | bellard | #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ |
39 | 80cabfad | bellard | #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ |
40 | 80cabfad | bellard | #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ |
41 | 80cabfad | bellard | #define EN0_TSR 0x04 /* Transmit status reg RD */ |
42 | 80cabfad | bellard | #define EN0_TPSR 0x04 /* Transmit starting page WR */ |
43 | 80cabfad | bellard | #define EN0_NCR 0x05 /* Number of collision reg RD */ |
44 | 80cabfad | bellard | #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ |
45 | 80cabfad | bellard | #define EN0_FIFO 0x06 /* FIFO RD */ |
46 | 80cabfad | bellard | #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ |
47 | 80cabfad | bellard | #define EN0_ISR 0x07 /* Interrupt status reg RD WR */ |
48 | 80cabfad | bellard | #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ |
49 | 80cabfad | bellard | #define EN0_RSARLO 0x08 /* Remote start address reg 0 */ |
50 | 80cabfad | bellard | #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ |
51 | 80cabfad | bellard | #define EN0_RSARHI 0x09 /* Remote start address reg 1 */ |
52 | 80cabfad | bellard | #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ |
53 | 089af991 | bellard | #define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */ |
54 | 80cabfad | bellard | #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ |
55 | 089af991 | bellard | #define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */ |
56 | 80cabfad | bellard | #define EN0_RSR 0x0c /* rx status reg RD */ |
57 | 80cabfad | bellard | #define EN0_RXCR 0x0c /* RX configuration reg WR */ |
58 | 80cabfad | bellard | #define EN0_TXCR 0x0d /* TX configuration reg WR */ |
59 | 80cabfad | bellard | #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ |
60 | 80cabfad | bellard | #define EN0_DCFG 0x0e /* Data configuration reg WR */ |
61 | 80cabfad | bellard | #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ |
62 | 80cabfad | bellard | #define EN0_IMR 0x0f /* Interrupt mask reg WR */ |
63 | 80cabfad | bellard | #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ |
64 | 80cabfad | bellard | |
65 | 80cabfad | bellard | #define EN1_PHYS 0x11 |
66 | 80cabfad | bellard | #define EN1_CURPAG 0x17 |
67 | 80cabfad | bellard | #define EN1_MULT 0x18 |
68 | 80cabfad | bellard | |
69 | a343df16 | bellard | #define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */ |
70 | a343df16 | bellard | #define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */ |
71 | a343df16 | bellard | |
72 | 089af991 | bellard | #define EN3_CONFIG0 0x33 |
73 | 089af991 | bellard | #define EN3_CONFIG1 0x34 |
74 | 089af991 | bellard | #define EN3_CONFIG2 0x35 |
75 | 089af991 | bellard | #define EN3_CONFIG3 0x36 |
76 | 089af991 | bellard | |
77 | 80cabfad | bellard | /* Register accessed at EN_CMD, the 8390 base addr. */
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78 | 80cabfad | bellard | #define E8390_STOP 0x01 /* Stop and reset the chip */ |
79 | 80cabfad | bellard | #define E8390_START 0x02 /* Start the chip, clear reset */ |
80 | 80cabfad | bellard | #define E8390_TRANS 0x04 /* Transmit a frame */ |
81 | 80cabfad | bellard | #define E8390_RREAD 0x08 /* Remote read */ |
82 | 80cabfad | bellard | #define E8390_RWRITE 0x10 /* Remote write */ |
83 | 80cabfad | bellard | #define E8390_NODMA 0x20 /* Remote DMA */ |
84 | 80cabfad | bellard | #define E8390_PAGE0 0x00 /* Select page chip registers */ |
85 | 80cabfad | bellard | #define E8390_PAGE1 0x40 /* using the two high-order bits */ |
86 | 80cabfad | bellard | #define E8390_PAGE2 0x80 /* Page 3 is invalid. */ |
87 | 80cabfad | bellard | |
88 | 80cabfad | bellard | /* Bits in EN0_ISR - Interrupt status register */
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89 | 80cabfad | bellard | #define ENISR_RX 0x01 /* Receiver, no error */ |
90 | 80cabfad | bellard | #define ENISR_TX 0x02 /* Transmitter, no error */ |
91 | 80cabfad | bellard | #define ENISR_RX_ERR 0x04 /* Receiver, with error */ |
92 | 80cabfad | bellard | #define ENISR_TX_ERR 0x08 /* Transmitter, with error */ |
93 | 80cabfad | bellard | #define ENISR_OVER 0x10 /* Receiver overwrote the ring */ |
94 | 80cabfad | bellard | #define ENISR_COUNTERS 0x20 /* Counters need emptying */ |
95 | 80cabfad | bellard | #define ENISR_RDC 0x40 /* remote dma complete */ |
96 | 80cabfad | bellard | #define ENISR_RESET 0x80 /* Reset completed */ |
97 | 80cabfad | bellard | #define ENISR_ALL 0x3f /* Interrupts we will enable */ |
98 | 80cabfad | bellard | |
99 | 80cabfad | bellard | /* Bits in received packet status byte and EN0_RSR*/
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100 | 80cabfad | bellard | #define ENRSR_RXOK 0x01 /* Received a good packet */ |
101 | 80cabfad | bellard | #define ENRSR_CRC 0x02 /* CRC error */ |
102 | 80cabfad | bellard | #define ENRSR_FAE 0x04 /* frame alignment error */ |
103 | 80cabfad | bellard | #define ENRSR_FO 0x08 /* FIFO overrun */ |
104 | 80cabfad | bellard | #define ENRSR_MPA 0x10 /* missed pkt */ |
105 | 80cabfad | bellard | #define ENRSR_PHY 0x20 /* physical/multicast address */ |
106 | 80cabfad | bellard | #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ |
107 | 80cabfad | bellard | #define ENRSR_DEF 0x80 /* deferring */ |
108 | 80cabfad | bellard | |
109 | 80cabfad | bellard | /* Transmitted packet status, EN0_TSR. */
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110 | 80cabfad | bellard | #define ENTSR_PTX 0x01 /* Packet transmitted without error */ |
111 | 80cabfad | bellard | #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ |
112 | 80cabfad | bellard | #define ENTSR_COL 0x04 /* The transmit collided at least once. */ |
113 | 80cabfad | bellard | #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ |
114 | 80cabfad | bellard | #define ENTSR_CRS 0x10 /* The carrier sense was lost. */ |
115 | 80cabfad | bellard | #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ |
116 | 80cabfad | bellard | #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ |
117 | 80cabfad | bellard | #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ |
118 | 80cabfad | bellard | |
119 | ee9dbb29 | bellard | #define NE2000_PMEM_SIZE (32*1024) |
120 | ee9dbb29 | bellard | #define NE2000_PMEM_START (16*1024) |
121 | ee9dbb29 | bellard | #define NE2000_PMEM_END (NE2000_PMEM_SIZE+NE2000_PMEM_START)
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122 | ee9dbb29 | bellard | #define NE2000_MEM_SIZE NE2000_PMEM_END
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123 | 80cabfad | bellard | |
124 | 80cabfad | bellard | typedef struct NE2000State { |
125 | 80cabfad | bellard | uint8_t cmd; |
126 | 80cabfad | bellard | uint32_t start; |
127 | 80cabfad | bellard | uint32_t stop; |
128 | 80cabfad | bellard | uint8_t boundary; |
129 | 80cabfad | bellard | uint8_t tsr; |
130 | 80cabfad | bellard | uint8_t tpsr; |
131 | 80cabfad | bellard | uint16_t tcnt; |
132 | 80cabfad | bellard | uint16_t rcnt; |
133 | 80cabfad | bellard | uint32_t rsar; |
134 | 8d6c7eb8 | bellard | uint8_t rsr; |
135 | 7c9d8e07 | bellard | uint8_t rxcr; |
136 | 80cabfad | bellard | uint8_t isr; |
137 | 80cabfad | bellard | uint8_t dcfg; |
138 | 80cabfad | bellard | uint8_t imr; |
139 | 80cabfad | bellard | uint8_t phys[6]; /* mac address */ |
140 | 80cabfad | bellard | uint8_t curpag; |
141 | 80cabfad | bellard | uint8_t mult[8]; /* multicast mask array */ |
142 | d537cf6c | pbrook | qemu_irq irq; |
143 | b946a153 | aliguori | int isa_io_base;
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144 | 7c9d8e07 | bellard | VLANClientState *vc; |
145 | 7c9d8e07 | bellard | uint8_t macaddr[6];
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146 | 80cabfad | bellard | uint8_t mem[NE2000_MEM_SIZE]; |
147 | 80cabfad | bellard | } NE2000State; |
148 | 80cabfad | bellard | |
149 | 2b7a050a | Juan Quintela | typedef struct PCINE2000State { |
150 | 2b7a050a | Juan Quintela | PCIDevice dev; |
151 | 2b7a050a | Juan Quintela | NE2000State ne2000; |
152 | 2b7a050a | Juan Quintela | } PCINE2000State; |
153 | 2b7a050a | Juan Quintela | |
154 | 80cabfad | bellard | static void ne2000_reset(NE2000State *s) |
155 | 80cabfad | bellard | { |
156 | 80cabfad | bellard | int i;
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157 | 80cabfad | bellard | |
158 | 80cabfad | bellard | s->isr = ENISR_RESET; |
159 | 7c9d8e07 | bellard | memcpy(s->mem, s->macaddr, 6);
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160 | 80cabfad | bellard | s->mem[14] = 0x57; |
161 | 80cabfad | bellard | s->mem[15] = 0x57; |
162 | 80cabfad | bellard | |
163 | 80cabfad | bellard | /* duplicate prom data */
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164 | 80cabfad | bellard | for(i = 15;i >= 0; i--) { |
165 | 80cabfad | bellard | s->mem[2 * i] = s->mem[i];
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166 | 80cabfad | bellard | s->mem[2 * i + 1] = s->mem[i]; |
167 | 80cabfad | bellard | } |
168 | 80cabfad | bellard | } |
169 | 80cabfad | bellard | |
170 | 80cabfad | bellard | static void ne2000_update_irq(NE2000State *s) |
171 | 80cabfad | bellard | { |
172 | 80cabfad | bellard | int isr;
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173 | a343df16 | bellard | isr = (s->isr & s->imr) & 0x7f;
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174 | a541f297 | bellard | #if defined(DEBUG_NE2000)
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175 | d537cf6c | pbrook | printf("NE2000: Set IRQ to %d (%02x %02x)\n",
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176 | d537cf6c | pbrook | isr ? 1 : 0, s->isr, s->imr); |
177 | a541f297 | bellard | #endif
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178 | d537cf6c | pbrook | qemu_set_irq(s->irq, (isr != 0));
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179 | 80cabfad | bellard | } |
180 | 80cabfad | bellard | |
181 | 7c9d8e07 | bellard | #define POLYNOMIAL 0x04c11db6 |
182 | 7c9d8e07 | bellard | |
183 | 7c9d8e07 | bellard | /* From FreeBSD */
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184 | 7c9d8e07 | bellard | /* XXX: optimize */
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185 | 7c9d8e07 | bellard | static int compute_mcast_idx(const uint8_t *ep) |
186 | 7c9d8e07 | bellard | { |
187 | 7c9d8e07 | bellard | uint32_t crc; |
188 | 7c9d8e07 | bellard | int carry, i, j;
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189 | 7c9d8e07 | bellard | uint8_t b; |
190 | 7c9d8e07 | bellard | |
191 | 7c9d8e07 | bellard | crc = 0xffffffff;
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192 | 7c9d8e07 | bellard | for (i = 0; i < 6; i++) { |
193 | 7c9d8e07 | bellard | b = *ep++; |
194 | 7c9d8e07 | bellard | for (j = 0; j < 8; j++) { |
195 | 7c9d8e07 | bellard | carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); |
196 | 7c9d8e07 | bellard | crc <<= 1;
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197 | 7c9d8e07 | bellard | b >>= 1;
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198 | 7c9d8e07 | bellard | if (carry)
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199 | 7c9d8e07 | bellard | crc = ((crc ^ POLYNOMIAL) | carry); |
200 | 7c9d8e07 | bellard | } |
201 | 7c9d8e07 | bellard | } |
202 | 7c9d8e07 | bellard | return (crc >> 26); |
203 | 7c9d8e07 | bellard | } |
204 | 7c9d8e07 | bellard | |
205 | d861b05e | pbrook | static int ne2000_buffer_full(NE2000State *s) |
206 | 80cabfad | bellard | { |
207 | 80cabfad | bellard | int avail, index, boundary;
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208 | d861b05e | pbrook | |
209 | 80cabfad | bellard | index = s->curpag << 8;
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210 | 80cabfad | bellard | boundary = s->boundary << 8;
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211 | 28c1c656 | ths | if (index < boundary)
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212 | 80cabfad | bellard | avail = boundary - index; |
213 | 80cabfad | bellard | else
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214 | 80cabfad | bellard | avail = (s->stop - s->start) - (index - boundary); |
215 | 80cabfad | bellard | if (avail < (MAX_ETH_FRAME_SIZE + 4)) |
216 | d861b05e | pbrook | return 1; |
217 | d861b05e | pbrook | return 0; |
218 | d861b05e | pbrook | } |
219 | d861b05e | pbrook | |
220 | e3f5ec2b | Mark McLoughlin | static int ne2000_can_receive(VLANClientState *vc) |
221 | d861b05e | pbrook | { |
222 | e3f5ec2b | Mark McLoughlin | NE2000State *s = vc->opaque; |
223 | 3b46e624 | ths | |
224 | d861b05e | pbrook | if (s->cmd & E8390_STOP)
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225 | e89f00e6 | aurel32 | return 1; |
226 | d861b05e | pbrook | return !ne2000_buffer_full(s);
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227 | 80cabfad | bellard | } |
228 | 80cabfad | bellard | |
229 | b41a2cd1 | bellard | #define MIN_BUF_SIZE 60 |
230 | b41a2cd1 | bellard | |
231 | 4f1c942b | Mark McLoughlin | static ssize_t ne2000_receive(VLANClientState *vc, const uint8_t *buf, size_t size_) |
232 | 80cabfad | bellard | { |
233 | e3f5ec2b | Mark McLoughlin | NE2000State *s = vc->opaque; |
234 | 4f1c942b | Mark McLoughlin | int size = size_;
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235 | 80cabfad | bellard | uint8_t *p; |
236 | 0ae045ae | ths | unsigned int total_len, next, avail, len, index, mcast_idx; |
237 | b41a2cd1 | bellard | uint8_t buf1[60];
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238 | 5fafdf24 | ths | static const uint8_t broadcast_macaddr[6] = |
239 | 7c9d8e07 | bellard | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
240 | 3b46e624 | ths | |
241 | 80cabfad | bellard | #if defined(DEBUG_NE2000)
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242 | 80cabfad | bellard | printf("NE2000: received len=%d\n", size);
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243 | 80cabfad | bellard | #endif
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244 | 80cabfad | bellard | |
245 | d861b05e | pbrook | if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
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246 | 4f1c942b | Mark McLoughlin | return -1; |
247 | 3b46e624 | ths | |
248 | 7c9d8e07 | bellard | /* XXX: check this */
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249 | 7c9d8e07 | bellard | if (s->rxcr & 0x10) { |
250 | 7c9d8e07 | bellard | /* promiscuous: receive all */
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251 | 7c9d8e07 | bellard | } else {
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252 | 7c9d8e07 | bellard | if (!memcmp(buf, broadcast_macaddr, 6)) { |
253 | 7c9d8e07 | bellard | /* broadcast address */
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254 | 7c9d8e07 | bellard | if (!(s->rxcr & 0x04)) |
255 | 4f1c942b | Mark McLoughlin | return size;
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256 | 7c9d8e07 | bellard | } else if (buf[0] & 0x01) { |
257 | 7c9d8e07 | bellard | /* multicast */
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258 | 7c9d8e07 | bellard | if (!(s->rxcr & 0x08)) |
259 | 4f1c942b | Mark McLoughlin | return size;
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260 | 7c9d8e07 | bellard | mcast_idx = compute_mcast_idx(buf); |
261 | 7c9d8e07 | bellard | if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) |
262 | 4f1c942b | Mark McLoughlin | return size;
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263 | 7c9d8e07 | bellard | } else if (s->mem[0] == buf[0] && |
264 | 3b46e624 | ths | s->mem[2] == buf[1] && |
265 | 3b46e624 | ths | s->mem[4] == buf[2] && |
266 | 3b46e624 | ths | s->mem[6] == buf[3] && |
267 | 3b46e624 | ths | s->mem[8] == buf[4] && |
268 | 7c9d8e07 | bellard | s->mem[10] == buf[5]) { |
269 | 7c9d8e07 | bellard | /* match */
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270 | 7c9d8e07 | bellard | } else {
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271 | 4f1c942b | Mark McLoughlin | return size;
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272 | 7c9d8e07 | bellard | } |
273 | 7c9d8e07 | bellard | } |
274 | 7c9d8e07 | bellard | |
275 | 7c9d8e07 | bellard | |
276 | b41a2cd1 | bellard | /* if too small buffer, then expand it */
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277 | b41a2cd1 | bellard | if (size < MIN_BUF_SIZE) {
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278 | b41a2cd1 | bellard | memcpy(buf1, buf, size); |
279 | b41a2cd1 | bellard | memset(buf1 + size, 0, MIN_BUF_SIZE - size);
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280 | b41a2cd1 | bellard | buf = buf1; |
281 | b41a2cd1 | bellard | size = MIN_BUF_SIZE; |
282 | b41a2cd1 | bellard | } |
283 | b41a2cd1 | bellard | |
284 | 80cabfad | bellard | index = s->curpag << 8;
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285 | 80cabfad | bellard | /* 4 bytes for header */
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286 | 80cabfad | bellard | total_len = size + 4;
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287 | 80cabfad | bellard | /* address for next packet (4 bytes for CRC) */
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288 | 80cabfad | bellard | next = index + ((total_len + 4 + 255) & ~0xff); |
289 | 80cabfad | bellard | if (next >= s->stop)
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290 | 80cabfad | bellard | next -= (s->stop - s->start); |
291 | 80cabfad | bellard | /* prepare packet header */
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292 | 80cabfad | bellard | p = s->mem + index; |
293 | 8d6c7eb8 | bellard | s->rsr = ENRSR_RXOK; /* receive status */
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294 | 8d6c7eb8 | bellard | /* XXX: check this */
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295 | 8d6c7eb8 | bellard | if (buf[0] & 0x01) |
296 | 8d6c7eb8 | bellard | s->rsr |= ENRSR_PHY; |
297 | 8d6c7eb8 | bellard | p[0] = s->rsr;
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298 | 80cabfad | bellard | p[1] = next >> 8; |
299 | 80cabfad | bellard | p[2] = total_len;
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300 | 80cabfad | bellard | p[3] = total_len >> 8; |
301 | 80cabfad | bellard | index += 4;
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302 | 80cabfad | bellard | |
303 | 80cabfad | bellard | /* write packet data */
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304 | 80cabfad | bellard | while (size > 0) { |
305 | 0ae045ae | ths | if (index <= s->stop)
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306 | 0ae045ae | ths | avail = s->stop - index; |
307 | 0ae045ae | ths | else
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308 | 0ae045ae | ths | avail = 0;
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309 | 80cabfad | bellard | len = size; |
310 | 80cabfad | bellard | if (len > avail)
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311 | 80cabfad | bellard | len = avail; |
312 | 80cabfad | bellard | memcpy(s->mem + index, buf, len); |
313 | 80cabfad | bellard | buf += len; |
314 | 80cabfad | bellard | index += len; |
315 | 80cabfad | bellard | if (index == s->stop)
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316 | 80cabfad | bellard | index = s->start; |
317 | 80cabfad | bellard | size -= len; |
318 | 80cabfad | bellard | } |
319 | 80cabfad | bellard | s->curpag = next >> 8;
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320 | 8d6c7eb8 | bellard | |
321 | 9f083493 | ths | /* now we can signal we have received something */
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322 | 80cabfad | bellard | s->isr |= ENISR_RX; |
323 | 80cabfad | bellard | ne2000_update_irq(s); |
324 | 4f1c942b | Mark McLoughlin | |
325 | 4f1c942b | Mark McLoughlin | return size_;
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326 | 80cabfad | bellard | } |
327 | 80cabfad | bellard | |
328 | b41a2cd1 | bellard | static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
329 | 80cabfad | bellard | { |
330 | b41a2cd1 | bellard | NE2000State *s = opaque; |
331 | 40545f84 | bellard | int offset, page, index;
|
332 | 80cabfad | bellard | |
333 | 80cabfad | bellard | addr &= 0xf;
|
334 | 80cabfad | bellard | #ifdef DEBUG_NE2000
|
335 | 80cabfad | bellard | printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
|
336 | 80cabfad | bellard | #endif
|
337 | 80cabfad | bellard | if (addr == E8390_CMD) {
|
338 | 80cabfad | bellard | /* control register */
|
339 | 80cabfad | bellard | s->cmd = val; |
340 | a343df16 | bellard | if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */ |
341 | ee9dbb29 | bellard | s->isr &= ~ENISR_RESET; |
342 | e91c8a77 | ths | /* test specific case: zero length transfer */
|
343 | 80cabfad | bellard | if ((val & (E8390_RREAD | E8390_RWRITE)) &&
|
344 | 80cabfad | bellard | s->rcnt == 0) {
|
345 | 80cabfad | bellard | s->isr |= ENISR_RDC; |
346 | 80cabfad | bellard | ne2000_update_irq(s); |
347 | 80cabfad | bellard | } |
348 | 80cabfad | bellard | if (val & E8390_TRANS) {
|
349 | 40545f84 | bellard | index = (s->tpsr << 8);
|
350 | 5fafdf24 | ths | /* XXX: next 2 lines are a hack to make netware 3.11 work */
|
351 | 40545f84 | bellard | if (index >= NE2000_PMEM_END)
|
352 | 40545f84 | bellard | index -= NE2000_PMEM_SIZE; |
353 | 40545f84 | bellard | /* fail safe: check range on the transmitted length */
|
354 | 40545f84 | bellard | if (index + s->tcnt <= NE2000_PMEM_END) {
|
355 | 7c9d8e07 | bellard | qemu_send_packet(s->vc, s->mem + index, s->tcnt); |
356 | 40545f84 | bellard | } |
357 | e91c8a77 | ths | /* signal end of transfer */
|
358 | 80cabfad | bellard | s->tsr = ENTSR_PTX; |
359 | 80cabfad | bellard | s->isr |= ENISR_TX; |
360 | 5fafdf24 | ths | s->cmd &= ~E8390_TRANS; |
361 | 80cabfad | bellard | ne2000_update_irq(s); |
362 | 80cabfad | bellard | } |
363 | 80cabfad | bellard | } |
364 | 80cabfad | bellard | } else {
|
365 | 80cabfad | bellard | page = s->cmd >> 6;
|
366 | 80cabfad | bellard | offset = addr | (page << 4);
|
367 | 80cabfad | bellard | switch(offset) {
|
368 | 80cabfad | bellard | case EN0_STARTPG:
|
369 | 80cabfad | bellard | s->start = val << 8;
|
370 | 80cabfad | bellard | break;
|
371 | 80cabfad | bellard | case EN0_STOPPG:
|
372 | 80cabfad | bellard | s->stop = val << 8;
|
373 | 80cabfad | bellard | break;
|
374 | 80cabfad | bellard | case EN0_BOUNDARY:
|
375 | 80cabfad | bellard | s->boundary = val; |
376 | 80cabfad | bellard | break;
|
377 | 80cabfad | bellard | case EN0_IMR:
|
378 | 80cabfad | bellard | s->imr = val; |
379 | 80cabfad | bellard | ne2000_update_irq(s); |
380 | 80cabfad | bellard | break;
|
381 | 80cabfad | bellard | case EN0_TPSR:
|
382 | 80cabfad | bellard | s->tpsr = val; |
383 | 80cabfad | bellard | break;
|
384 | 80cabfad | bellard | case EN0_TCNTLO:
|
385 | 80cabfad | bellard | s->tcnt = (s->tcnt & 0xff00) | val;
|
386 | 80cabfad | bellard | break;
|
387 | 80cabfad | bellard | case EN0_TCNTHI:
|
388 | 80cabfad | bellard | s->tcnt = (s->tcnt & 0x00ff) | (val << 8); |
389 | 80cabfad | bellard | break;
|
390 | 80cabfad | bellard | case EN0_RSARLO:
|
391 | 80cabfad | bellard | s->rsar = (s->rsar & 0xff00) | val;
|
392 | 80cabfad | bellard | break;
|
393 | 80cabfad | bellard | case EN0_RSARHI:
|
394 | 80cabfad | bellard | s->rsar = (s->rsar & 0x00ff) | (val << 8); |
395 | 80cabfad | bellard | break;
|
396 | 80cabfad | bellard | case EN0_RCNTLO:
|
397 | 80cabfad | bellard | s->rcnt = (s->rcnt & 0xff00) | val;
|
398 | 80cabfad | bellard | break;
|
399 | 80cabfad | bellard | case EN0_RCNTHI:
|
400 | 80cabfad | bellard | s->rcnt = (s->rcnt & 0x00ff) | (val << 8); |
401 | 80cabfad | bellard | break;
|
402 | 7c9d8e07 | bellard | case EN0_RXCR:
|
403 | 7c9d8e07 | bellard | s->rxcr = val; |
404 | 7c9d8e07 | bellard | break;
|
405 | 80cabfad | bellard | case EN0_DCFG:
|
406 | 80cabfad | bellard | s->dcfg = val; |
407 | 80cabfad | bellard | break;
|
408 | 80cabfad | bellard | case EN0_ISR:
|
409 | ee9dbb29 | bellard | s->isr &= ~(val & 0x7f);
|
410 | 80cabfad | bellard | ne2000_update_irq(s); |
411 | 80cabfad | bellard | break;
|
412 | 80cabfad | bellard | case EN1_PHYS ... EN1_PHYS + 5: |
413 | 80cabfad | bellard | s->phys[offset - EN1_PHYS] = val; |
414 | 80cabfad | bellard | break;
|
415 | 80cabfad | bellard | case EN1_CURPAG:
|
416 | 80cabfad | bellard | s->curpag = val; |
417 | 80cabfad | bellard | break;
|
418 | 80cabfad | bellard | case EN1_MULT ... EN1_MULT + 7: |
419 | 80cabfad | bellard | s->mult[offset - EN1_MULT] = val; |
420 | 80cabfad | bellard | break;
|
421 | 80cabfad | bellard | } |
422 | 80cabfad | bellard | } |
423 | 80cabfad | bellard | } |
424 | 80cabfad | bellard | |
425 | b41a2cd1 | bellard | static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr) |
426 | 80cabfad | bellard | { |
427 | b41a2cd1 | bellard | NE2000State *s = opaque; |
428 | 80cabfad | bellard | int offset, page, ret;
|
429 | 80cabfad | bellard | |
430 | 80cabfad | bellard | addr &= 0xf;
|
431 | 80cabfad | bellard | if (addr == E8390_CMD) {
|
432 | 80cabfad | bellard | ret = s->cmd; |
433 | 80cabfad | bellard | } else {
|
434 | 80cabfad | bellard | page = s->cmd >> 6;
|
435 | 80cabfad | bellard | offset = addr | (page << 4);
|
436 | 80cabfad | bellard | switch(offset) {
|
437 | 80cabfad | bellard | case EN0_TSR:
|
438 | 80cabfad | bellard | ret = s->tsr; |
439 | 80cabfad | bellard | break;
|
440 | 80cabfad | bellard | case EN0_BOUNDARY:
|
441 | 80cabfad | bellard | ret = s->boundary; |
442 | 80cabfad | bellard | break;
|
443 | 80cabfad | bellard | case EN0_ISR:
|
444 | 80cabfad | bellard | ret = s->isr; |
445 | 80cabfad | bellard | break;
|
446 | ee9dbb29 | bellard | case EN0_RSARLO:
|
447 | ee9dbb29 | bellard | ret = s->rsar & 0x00ff;
|
448 | ee9dbb29 | bellard | break;
|
449 | ee9dbb29 | bellard | case EN0_RSARHI:
|
450 | ee9dbb29 | bellard | ret = s->rsar >> 8;
|
451 | ee9dbb29 | bellard | break;
|
452 | 80cabfad | bellard | case EN1_PHYS ... EN1_PHYS + 5: |
453 | 80cabfad | bellard | ret = s->phys[offset - EN1_PHYS]; |
454 | 80cabfad | bellard | break;
|
455 | 80cabfad | bellard | case EN1_CURPAG:
|
456 | 80cabfad | bellard | ret = s->curpag; |
457 | 80cabfad | bellard | break;
|
458 | 80cabfad | bellard | case EN1_MULT ... EN1_MULT + 7: |
459 | 80cabfad | bellard | ret = s->mult[offset - EN1_MULT]; |
460 | 80cabfad | bellard | break;
|
461 | 8d6c7eb8 | bellard | case EN0_RSR:
|
462 | 8d6c7eb8 | bellard | ret = s->rsr; |
463 | 8d6c7eb8 | bellard | break;
|
464 | a343df16 | bellard | case EN2_STARTPG:
|
465 | a343df16 | bellard | ret = s->start >> 8;
|
466 | a343df16 | bellard | break;
|
467 | a343df16 | bellard | case EN2_STOPPG:
|
468 | a343df16 | bellard | ret = s->stop >> 8;
|
469 | a343df16 | bellard | break;
|
470 | 089af991 | bellard | case EN0_RTL8029ID0:
|
471 | 089af991 | bellard | ret = 0x50;
|
472 | 089af991 | bellard | break;
|
473 | 089af991 | bellard | case EN0_RTL8029ID1:
|
474 | 089af991 | bellard | ret = 0x43;
|
475 | 089af991 | bellard | break;
|
476 | 089af991 | bellard | case EN3_CONFIG0:
|
477 | 089af991 | bellard | ret = 0; /* 10baseT media */ |
478 | 089af991 | bellard | break;
|
479 | 089af991 | bellard | case EN3_CONFIG2:
|
480 | 089af991 | bellard | ret = 0x40; /* 10baseT active */ |
481 | 089af991 | bellard | break;
|
482 | 089af991 | bellard | case EN3_CONFIG3:
|
483 | 089af991 | bellard | ret = 0x40; /* Full duplex */ |
484 | 089af991 | bellard | break;
|
485 | 80cabfad | bellard | default:
|
486 | 80cabfad | bellard | ret = 0x00;
|
487 | 80cabfad | bellard | break;
|
488 | 80cabfad | bellard | } |
489 | 80cabfad | bellard | } |
490 | 80cabfad | bellard | #ifdef DEBUG_NE2000
|
491 | 80cabfad | bellard | printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
|
492 | 80cabfad | bellard | #endif
|
493 | 80cabfad | bellard | return ret;
|
494 | 80cabfad | bellard | } |
495 | 80cabfad | bellard | |
496 | 5fafdf24 | ths | static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr, |
497 | 69b91039 | bellard | uint32_t val) |
498 | ee9dbb29 | bellard | { |
499 | 5fafdf24 | ths | if (addr < 32 || |
500 | ee9dbb29 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
501 | ee9dbb29 | bellard | s->mem[addr] = val; |
502 | ee9dbb29 | bellard | } |
503 | ee9dbb29 | bellard | } |
504 | ee9dbb29 | bellard | |
505 | 5fafdf24 | ths | static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr, |
506 | ee9dbb29 | bellard | uint32_t val) |
507 | ee9dbb29 | bellard | { |
508 | ee9dbb29 | bellard | addr &= ~1; /* XXX: check exact behaviour if not even */ |
509 | 5fafdf24 | ths | if (addr < 32 || |
510 | ee9dbb29 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
511 | 69b91039 | bellard | *(uint16_t *)(s->mem + addr) = cpu_to_le16(val); |
512 | 69b91039 | bellard | } |
513 | 69b91039 | bellard | } |
514 | 69b91039 | bellard | |
515 | 5fafdf24 | ths | static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr, |
516 | 69b91039 | bellard | uint32_t val) |
517 | 69b91039 | bellard | { |
518 | 57ccbabe | bellard | addr &= ~1; /* XXX: check exact behaviour if not even */ |
519 | 5fafdf24 | ths | if (addr < 32 || |
520 | 69b91039 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
521 | 57ccbabe | bellard | cpu_to_le32wu((uint32_t *)(s->mem + addr), val); |
522 | ee9dbb29 | bellard | } |
523 | ee9dbb29 | bellard | } |
524 | ee9dbb29 | bellard | |
525 | ee9dbb29 | bellard | static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr) |
526 | ee9dbb29 | bellard | { |
527 | 5fafdf24 | ths | if (addr < 32 || |
528 | ee9dbb29 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
529 | ee9dbb29 | bellard | return s->mem[addr];
|
530 | ee9dbb29 | bellard | } else {
|
531 | ee9dbb29 | bellard | return 0xff; |
532 | ee9dbb29 | bellard | } |
533 | ee9dbb29 | bellard | } |
534 | ee9dbb29 | bellard | |
535 | ee9dbb29 | bellard | static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr) |
536 | ee9dbb29 | bellard | { |
537 | ee9dbb29 | bellard | addr &= ~1; /* XXX: check exact behaviour if not even */ |
538 | 5fafdf24 | ths | if (addr < 32 || |
539 | ee9dbb29 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
540 | 69b91039 | bellard | return le16_to_cpu(*(uint16_t *)(s->mem + addr));
|
541 | ee9dbb29 | bellard | } else {
|
542 | ee9dbb29 | bellard | return 0xffff; |
543 | ee9dbb29 | bellard | } |
544 | ee9dbb29 | bellard | } |
545 | ee9dbb29 | bellard | |
546 | 69b91039 | bellard | static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr) |
547 | 69b91039 | bellard | { |
548 | 57ccbabe | bellard | addr &= ~1; /* XXX: check exact behaviour if not even */ |
549 | 5fafdf24 | ths | if (addr < 32 || |
550 | 69b91039 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
551 | 57ccbabe | bellard | return le32_to_cpupu((uint32_t *)(s->mem + addr));
|
552 | 69b91039 | bellard | } else {
|
553 | 69b91039 | bellard | return 0xffffffff; |
554 | 69b91039 | bellard | } |
555 | 69b91039 | bellard | } |
556 | 69b91039 | bellard | |
557 | 3df3f6fd | bellard | static inline void ne2000_dma_update(NE2000State *s, int len) |
558 | 3df3f6fd | bellard | { |
559 | 3df3f6fd | bellard | s->rsar += len; |
560 | 3df3f6fd | bellard | /* wrap */
|
561 | 3df3f6fd | bellard | /* XXX: check what to do if rsar > stop */
|
562 | 3df3f6fd | bellard | if (s->rsar == s->stop)
|
563 | 3df3f6fd | bellard | s->rsar = s->start; |
564 | 3df3f6fd | bellard | |
565 | 3df3f6fd | bellard | if (s->rcnt <= len) {
|
566 | 3df3f6fd | bellard | s->rcnt = 0;
|
567 | e91c8a77 | ths | /* signal end of transfer */
|
568 | 3df3f6fd | bellard | s->isr |= ENISR_RDC; |
569 | 3df3f6fd | bellard | ne2000_update_irq(s); |
570 | 3df3f6fd | bellard | } else {
|
571 | 3df3f6fd | bellard | s->rcnt -= len; |
572 | 3df3f6fd | bellard | } |
573 | 3df3f6fd | bellard | } |
574 | 3df3f6fd | bellard | |
575 | b41a2cd1 | bellard | static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
576 | 80cabfad | bellard | { |
577 | b41a2cd1 | bellard | NE2000State *s = opaque; |
578 | 80cabfad | bellard | |
579 | 80cabfad | bellard | #ifdef DEBUG_NE2000
|
580 | 80cabfad | bellard | printf("NE2000: asic write val=0x%04x\n", val);
|
581 | 80cabfad | bellard | #endif
|
582 | ee9dbb29 | bellard | if (s->rcnt == 0) |
583 | 3df3f6fd | bellard | return;
|
584 | 80cabfad | bellard | if (s->dcfg & 0x01) { |
585 | 80cabfad | bellard | /* 16 bit access */
|
586 | ee9dbb29 | bellard | ne2000_mem_writew(s, s->rsar, val); |
587 | 3df3f6fd | bellard | ne2000_dma_update(s, 2);
|
588 | 80cabfad | bellard | } else {
|
589 | 80cabfad | bellard | /* 8 bit access */
|
590 | ee9dbb29 | bellard | ne2000_mem_writeb(s, s->rsar, val); |
591 | 3df3f6fd | bellard | ne2000_dma_update(s, 1);
|
592 | 80cabfad | bellard | } |
593 | 80cabfad | bellard | } |
594 | 80cabfad | bellard | |
595 | b41a2cd1 | bellard | static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr) |
596 | 80cabfad | bellard | { |
597 | b41a2cd1 | bellard | NE2000State *s = opaque; |
598 | 80cabfad | bellard | int ret;
|
599 | 80cabfad | bellard | |
600 | 80cabfad | bellard | if (s->dcfg & 0x01) { |
601 | 80cabfad | bellard | /* 16 bit access */
|
602 | ee9dbb29 | bellard | ret = ne2000_mem_readw(s, s->rsar); |
603 | 3df3f6fd | bellard | ne2000_dma_update(s, 2);
|
604 | 80cabfad | bellard | } else {
|
605 | 80cabfad | bellard | /* 8 bit access */
|
606 | ee9dbb29 | bellard | ret = ne2000_mem_readb(s, s->rsar); |
607 | 3df3f6fd | bellard | ne2000_dma_update(s, 1);
|
608 | 80cabfad | bellard | } |
609 | 80cabfad | bellard | #ifdef DEBUG_NE2000
|
610 | 80cabfad | bellard | printf("NE2000: asic read val=0x%04x\n", ret);
|
611 | 80cabfad | bellard | #endif
|
612 | 80cabfad | bellard | return ret;
|
613 | 80cabfad | bellard | } |
614 | 80cabfad | bellard | |
615 | 69b91039 | bellard | static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
616 | 69b91039 | bellard | { |
617 | 69b91039 | bellard | NE2000State *s = opaque; |
618 | 69b91039 | bellard | |
619 | 69b91039 | bellard | #ifdef DEBUG_NE2000
|
620 | 69b91039 | bellard | printf("NE2000: asic writel val=0x%04x\n", val);
|
621 | 69b91039 | bellard | #endif
|
622 | 69b91039 | bellard | if (s->rcnt == 0) |
623 | 3df3f6fd | bellard | return;
|
624 | 69b91039 | bellard | /* 32 bit access */
|
625 | 69b91039 | bellard | ne2000_mem_writel(s, s->rsar, val); |
626 | 3df3f6fd | bellard | ne2000_dma_update(s, 4);
|
627 | 69b91039 | bellard | } |
628 | 69b91039 | bellard | |
629 | 69b91039 | bellard | static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr) |
630 | 69b91039 | bellard | { |
631 | 69b91039 | bellard | NE2000State *s = opaque; |
632 | 69b91039 | bellard | int ret;
|
633 | 69b91039 | bellard | |
634 | 69b91039 | bellard | /* 32 bit access */
|
635 | 69b91039 | bellard | ret = ne2000_mem_readl(s, s->rsar); |
636 | 3df3f6fd | bellard | ne2000_dma_update(s, 4);
|
637 | 69b91039 | bellard | #ifdef DEBUG_NE2000
|
638 | 69b91039 | bellard | printf("NE2000: asic readl val=0x%04x\n", ret);
|
639 | 69b91039 | bellard | #endif
|
640 | 69b91039 | bellard | return ret;
|
641 | 69b91039 | bellard | } |
642 | 69b91039 | bellard | |
643 | b41a2cd1 | bellard | static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
644 | 80cabfad | bellard | { |
645 | 80cabfad | bellard | /* nothing to do (end of reset pulse) */
|
646 | 80cabfad | bellard | } |
647 | 80cabfad | bellard | |
648 | b41a2cd1 | bellard | static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr) |
649 | 80cabfad | bellard | { |
650 | b41a2cd1 | bellard | NE2000State *s = opaque; |
651 | 80cabfad | bellard | ne2000_reset(s); |
652 | 80cabfad | bellard | return 0; |
653 | 80cabfad | bellard | } |
654 | 80cabfad | bellard | |
655 | a60380a5 | Juan Quintela | static void ne2000_save(QEMUFile* f, void* opaque) |
656 | 30ca2aab | bellard | { |
657 | a10fcec6 | Juan Quintela | NE2000State* s = opaque; |
658 | 60fe76f3 | ths | uint32_t tmp; |
659 | 30ca2aab | bellard | |
660 | acff9df6 | bellard | qemu_put_8s(f, &s->rxcr); |
661 | acff9df6 | bellard | |
662 | 30ca2aab | bellard | qemu_put_8s(f, &s->cmd); |
663 | 30ca2aab | bellard | qemu_put_be32s(f, &s->start); |
664 | 30ca2aab | bellard | qemu_put_be32s(f, &s->stop); |
665 | 30ca2aab | bellard | qemu_put_8s(f, &s->boundary); |
666 | 30ca2aab | bellard | qemu_put_8s(f, &s->tsr); |
667 | 30ca2aab | bellard | qemu_put_8s(f, &s->tpsr); |
668 | 30ca2aab | bellard | qemu_put_be16s(f, &s->tcnt); |
669 | 30ca2aab | bellard | qemu_put_be16s(f, &s->rcnt); |
670 | 30ca2aab | bellard | qemu_put_be32s(f, &s->rsar); |
671 | 30ca2aab | bellard | qemu_put_8s(f, &s->rsr); |
672 | 30ca2aab | bellard | qemu_put_8s(f, &s->isr); |
673 | 30ca2aab | bellard | qemu_put_8s(f, &s->dcfg); |
674 | 30ca2aab | bellard | qemu_put_8s(f, &s->imr); |
675 | 30ca2aab | bellard | qemu_put_buffer(f, s->phys, 6);
|
676 | 30ca2aab | bellard | qemu_put_8s(f, &s->curpag); |
677 | 30ca2aab | bellard | qemu_put_buffer(f, s->mult, 8);
|
678 | d537cf6c | pbrook | tmp = 0;
|
679 | d537cf6c | pbrook | qemu_put_be32s(f, &tmp); /* ignored, was irq */
|
680 | 30ca2aab | bellard | qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE); |
681 | 30ca2aab | bellard | } |
682 | 30ca2aab | bellard | |
683 | a60380a5 | Juan Quintela | static int ne2000_load(QEMUFile* f, void* opaque, int version_id) |
684 | 30ca2aab | bellard | { |
685 | a10fcec6 | Juan Quintela | NE2000State* s = opaque; |
686 | 60fe76f3 | ths | uint32_t tmp; |
687 | 1941d19c | bellard | |
688 | 1941d19c | bellard | if (version_id > 3) |
689 | 1941d19c | bellard | return -EINVAL;
|
690 | 1941d19c | bellard | |
691 | 1941d19c | bellard | if (version_id >= 2) { |
692 | acff9df6 | bellard | qemu_get_8s(f, &s->rxcr); |
693 | acff9df6 | bellard | } else {
|
694 | 1941d19c | bellard | s->rxcr = 0x0c;
|
695 | acff9df6 | bellard | } |
696 | 30ca2aab | bellard | |
697 | 30ca2aab | bellard | qemu_get_8s(f, &s->cmd); |
698 | 30ca2aab | bellard | qemu_get_be32s(f, &s->start); |
699 | 30ca2aab | bellard | qemu_get_be32s(f, &s->stop); |
700 | 30ca2aab | bellard | qemu_get_8s(f, &s->boundary); |
701 | 30ca2aab | bellard | qemu_get_8s(f, &s->tsr); |
702 | 30ca2aab | bellard | qemu_get_8s(f, &s->tpsr); |
703 | 30ca2aab | bellard | qemu_get_be16s(f, &s->tcnt); |
704 | 30ca2aab | bellard | qemu_get_be16s(f, &s->rcnt); |
705 | 30ca2aab | bellard | qemu_get_be32s(f, &s->rsar); |
706 | 30ca2aab | bellard | qemu_get_8s(f, &s->rsr); |
707 | 30ca2aab | bellard | qemu_get_8s(f, &s->isr); |
708 | 30ca2aab | bellard | qemu_get_8s(f, &s->dcfg); |
709 | 30ca2aab | bellard | qemu_get_8s(f, &s->imr); |
710 | 30ca2aab | bellard | qemu_get_buffer(f, s->phys, 6);
|
711 | 30ca2aab | bellard | qemu_get_8s(f, &s->curpag); |
712 | 30ca2aab | bellard | qemu_get_buffer(f, s->mult, 8);
|
713 | d537cf6c | pbrook | qemu_get_be32s(f, &tmp); /* ignored */
|
714 | 30ca2aab | bellard | qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE); |
715 | 30ca2aab | bellard | |
716 | 30ca2aab | bellard | return 0; |
717 | 30ca2aab | bellard | } |
718 | 30ca2aab | bellard | |
719 | a60380a5 | Juan Quintela | static void pci_ne2000_save(QEMUFile* f, void* opaque) |
720 | a60380a5 | Juan Quintela | { |
721 | a60380a5 | Juan Quintela | PCINE2000State* s = opaque; |
722 | a60380a5 | Juan Quintela | |
723 | a60380a5 | Juan Quintela | pci_device_save(&s->dev, f); |
724 | a60380a5 | Juan Quintela | ne2000_save(f, &s->ne2000); |
725 | a60380a5 | Juan Quintela | } |
726 | a60380a5 | Juan Quintela | |
727 | a60380a5 | Juan Quintela | static int pci_ne2000_load(QEMUFile* f, void* opaque, int version_id) |
728 | a60380a5 | Juan Quintela | { |
729 | a60380a5 | Juan Quintela | PCINE2000State* s = opaque; |
730 | a60380a5 | Juan Quintela | int ret;
|
731 | a60380a5 | Juan Quintela | |
732 | a60380a5 | Juan Quintela | if (version_id > 3) |
733 | a60380a5 | Juan Quintela | return -EINVAL;
|
734 | a60380a5 | Juan Quintela | |
735 | a60380a5 | Juan Quintela | if (version_id >= 3) { |
736 | a60380a5 | Juan Quintela | ret = pci_device_load(&s->dev, f); |
737 | a60380a5 | Juan Quintela | if (ret < 0) |
738 | a60380a5 | Juan Quintela | return ret;
|
739 | a60380a5 | Juan Quintela | } |
740 | a60380a5 | Juan Quintela | |
741 | a60380a5 | Juan Quintela | return ne2000_load(f, &s->ne2000, version_id);
|
742 | a60380a5 | Juan Quintela | } |
743 | a60380a5 | Juan Quintela | |
744 | b946a153 | aliguori | static void isa_ne2000_cleanup(VLANClientState *vc) |
745 | b946a153 | aliguori | { |
746 | b946a153 | aliguori | NE2000State *s = vc->opaque; |
747 | b946a153 | aliguori | |
748 | b946a153 | aliguori | unregister_savevm("ne2000", s);
|
749 | b946a153 | aliguori | |
750 | b946a153 | aliguori | isa_unassign_ioport(s->isa_io_base, 16);
|
751 | b946a153 | aliguori | isa_unassign_ioport(s->isa_io_base + 0x10, 2); |
752 | b946a153 | aliguori | isa_unassign_ioport(s->isa_io_base + 0x1f, 1); |
753 | b946a153 | aliguori | |
754 | b946a153 | aliguori | qemu_free(s); |
755 | b946a153 | aliguori | } |
756 | b946a153 | aliguori | |
757 | d537cf6c | pbrook | void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd) |
758 | 80cabfad | bellard | { |
759 | b41a2cd1 | bellard | NE2000State *s; |
760 | 3b46e624 | ths | |
761 | 0ae18cee | aliguori | qemu_check_nic_model(nd, "ne2k_isa");
|
762 | 0ae18cee | aliguori | |
763 | b41a2cd1 | bellard | s = qemu_mallocz(sizeof(NE2000State));
|
764 | 3b46e624 | ths | |
765 | b41a2cd1 | bellard | register_ioport_write(base, 16, 1, ne2000_ioport_write, s); |
766 | b41a2cd1 | bellard | register_ioport_read(base, 16, 1, ne2000_ioport_read, s); |
767 | 80cabfad | bellard | |
768 | b41a2cd1 | bellard | register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s); |
769 | b41a2cd1 | bellard | register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s); |
770 | b41a2cd1 | bellard | register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s); |
771 | b41a2cd1 | bellard | register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s); |
772 | 80cabfad | bellard | |
773 | b41a2cd1 | bellard | register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s); |
774 | b41a2cd1 | bellard | register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s); |
775 | b946a153 | aliguori | s->isa_io_base = base; |
776 | 80cabfad | bellard | s->irq = irq; |
777 | 7c9d8e07 | bellard | memcpy(s->macaddr, nd->macaddr, 6);
|
778 | 80cabfad | bellard | |
779 | 80cabfad | bellard | ne2000_reset(s); |
780 | b41a2cd1 | bellard | |
781 | ae50b274 | Mark McLoughlin | s->vc = nd->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name, |
782 | ae50b274 | Mark McLoughlin | ne2000_can_receive, ne2000_receive, |
783 | ae50b274 | Mark McLoughlin | NULL, isa_ne2000_cleanup, s);
|
784 | 7c9d8e07 | bellard | |
785 | 7cb7434b | aliguori | qemu_format_nic_info_str(s->vc, s->macaddr); |
786 | 3b46e624 | ths | |
787 | 18fdb1c5 | ths | register_savevm("ne2000", -1, 2, ne2000_save, ne2000_load, s); |
788 | 80cabfad | bellard | } |
789 | 69b91039 | bellard | |
790 | 69b91039 | bellard | /***********************************************************/
|
791 | 69b91039 | bellard | /* PCI NE2000 definitions */
|
792 | 69b91039 | bellard | |
793 | 5fafdf24 | ths | static void ne2000_map(PCIDevice *pci_dev, int region_num, |
794 | 69b91039 | bellard | uint32_t addr, uint32_t size, int type)
|
795 | 69b91039 | bellard | { |
796 | 377a7f06 | Juan Quintela | PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev); |
797 | 69b91039 | bellard | NE2000State *s = &d->ne2000; |
798 | 69b91039 | bellard | |
799 | 69b91039 | bellard | register_ioport_write(addr, 16, 1, ne2000_ioport_write, s); |
800 | 69b91039 | bellard | register_ioport_read(addr, 16, 1, ne2000_ioport_read, s); |
801 | 69b91039 | bellard | |
802 | 69b91039 | bellard | register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s); |
803 | 69b91039 | bellard | register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s); |
804 | 69b91039 | bellard | register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s); |
805 | 69b91039 | bellard | register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s); |
806 | 69b91039 | bellard | register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s); |
807 | 69b91039 | bellard | register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s); |
808 | 69b91039 | bellard | |
809 | 69b91039 | bellard | register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s); |
810 | 69b91039 | bellard | register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s); |
811 | 69b91039 | bellard | } |
812 | 69b91039 | bellard | |
813 | b946a153 | aliguori | static void ne2000_cleanup(VLANClientState *vc) |
814 | b946a153 | aliguori | { |
815 | b946a153 | aliguori | NE2000State *s = vc->opaque; |
816 | b946a153 | aliguori | |
817 | b946a153 | aliguori | unregister_savevm("ne2000", s);
|
818 | b946a153 | aliguori | } |
819 | b946a153 | aliguori | |
820 | 81a322d4 | Gerd Hoffmann | static int pci_ne2000_init(PCIDevice *pci_dev) |
821 | 69b91039 | bellard | { |
822 | 377a7f06 | Juan Quintela | PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev); |
823 | 69b91039 | bellard | NE2000State *s; |
824 | 69b91039 | bellard | uint8_t *pci_conf; |
825 | 3b46e624 | ths | |
826 | 69b91039 | bellard | pci_conf = d->dev.config; |
827 | deb54399 | aliguori | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK); |
828 | a770dc7e | aliguori | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8029); |
829 | 173a543b | blueswir1 | pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
830 | 6407f373 | Isaku Yamahata | pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
|
831 | 4a9c9687 | bellard | pci_conf[0x3d] = 1; // interrupt pin 0 |
832 | 3b46e624 | ths | |
833 | 28c2c264 | Avi Kivity | pci_register_bar(&d->dev, 0, 0x100, |
834 | 69b91039 | bellard | PCI_ADDRESS_SPACE_IO, ne2000_map); |
835 | 69b91039 | bellard | s = &d->ne2000; |
836 | d537cf6c | pbrook | s->irq = d->dev.irq[0];
|
837 | 9d07d757 | Paul Brook | qdev_get_macaddr(&d->dev.qdev, s->macaddr); |
838 | 69b91039 | bellard | ne2000_reset(s); |
839 | 9d07d757 | Paul Brook | s->vc = qdev_get_vlan_client(&d->dev.qdev, |
840 | 463af534 | Mark McLoughlin | ne2000_can_receive, ne2000_receive, NULL,
|
841 | b946a153 | aliguori | ne2000_cleanup, s); |
842 | 7c9d8e07 | bellard | |
843 | 7cb7434b | aliguori | qemu_format_nic_info_str(s->vc, s->macaddr); |
844 | 3b46e624 | ths | |
845 | a60380a5 | Juan Quintela | register_savevm("ne2000", -1, 3, pci_ne2000_save, pci_ne2000_load, d); |
846 | 81a322d4 | Gerd Hoffmann | return 0; |
847 | 9d07d757 | Paul Brook | } |
848 | 72da4208 | aliguori | |
849 | 0aab0d3a | Gerd Hoffmann | static PCIDeviceInfo ne2000_info = {
|
850 | 0aab0d3a | Gerd Hoffmann | .qdev.name = "ne2k_pci",
|
851 | 0aab0d3a | Gerd Hoffmann | .qdev.size = sizeof(PCINE2000State),
|
852 | 0aab0d3a | Gerd Hoffmann | .init = pci_ne2000_init, |
853 | 0aab0d3a | Gerd Hoffmann | }; |
854 | 0aab0d3a | Gerd Hoffmann | |
855 | 9d07d757 | Paul Brook | static void ne2000_register_devices(void) |
856 | 9d07d757 | Paul Brook | { |
857 | 0aab0d3a | Gerd Hoffmann | pci_qdev_register(&ne2000_info); |
858 | 69b91039 | bellard | } |
859 | 9d07d757 | Paul Brook | |
860 | 9d07d757 | Paul Brook | device_init(ne2000_register_devices) |