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1 | 6508fe59 | bellard | /*
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2 | 6508fe59 | bellard | * QEMU Parallel PORT emulation
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3 | 5fafdf24 | ths | *
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4 | e57a8c0e | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5867c88a | ths | * Copyright (c) 2007 Marko Kohtala
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6 | 5fafdf24 | ths | *
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7 | 6508fe59 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | 6508fe59 | bellard | * of this software and associated documentation files (the "Software"), to deal
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9 | 6508fe59 | bellard | * in the Software without restriction, including without limitation the rights
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10 | 6508fe59 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 6508fe59 | bellard | * copies of the Software, and to permit persons to whom the Software is
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12 | 6508fe59 | bellard | * furnished to do so, subject to the following conditions:
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13 | 6508fe59 | bellard | *
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14 | 6508fe59 | bellard | * The above copyright notice and this permission notice shall be included in
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15 | 6508fe59 | bellard | * all copies or substantial portions of the Software.
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16 | 6508fe59 | bellard | *
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17 | 6508fe59 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 6508fe59 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 6508fe59 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 6508fe59 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 6508fe59 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | 6508fe59 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | 6508fe59 | bellard | * THE SOFTWARE.
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24 | 6508fe59 | bellard | */
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25 | 87ecb68b | pbrook | #include "hw.h" |
26 | 87ecb68b | pbrook | #include "qemu-char.h" |
27 | 87ecb68b | pbrook | #include "isa.h" |
28 | 87ecb68b | pbrook | #include "pc.h" |
29 | 6508fe59 | bellard | |
30 | 6508fe59 | bellard | //#define DEBUG_PARALLEL
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31 | 6508fe59 | bellard | |
32 | 5867c88a | ths | #ifdef DEBUG_PARALLEL
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33 | 001faf32 | Blue Swirl | #define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__) |
34 | 5867c88a | ths | #else
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35 | 001faf32 | Blue Swirl | #define pdebug(fmt, ...) ((void)0) |
36 | 5867c88a | ths | #endif
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37 | 5867c88a | ths | |
38 | 5867c88a | ths | #define PARA_REG_DATA 0 |
39 | 5867c88a | ths | #define PARA_REG_STS 1 |
40 | 5867c88a | ths | #define PARA_REG_CTR 2 |
41 | 5867c88a | ths | #define PARA_REG_EPP_ADDR 3 |
42 | 5867c88a | ths | #define PARA_REG_EPP_DATA 4 |
43 | 5867c88a | ths | |
44 | 6508fe59 | bellard | /*
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45 | 6508fe59 | bellard | * These are the definitions for the Printer Status Register
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46 | 6508fe59 | bellard | */
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47 | 6508fe59 | bellard | #define PARA_STS_BUSY 0x80 /* Busy complement */ |
48 | 6508fe59 | bellard | #define PARA_STS_ACK 0x40 /* Acknowledge */ |
49 | 6508fe59 | bellard | #define PARA_STS_PAPER 0x20 /* Out of paper */ |
50 | 6508fe59 | bellard | #define PARA_STS_ONLINE 0x10 /* Online */ |
51 | 6508fe59 | bellard | #define PARA_STS_ERROR 0x08 /* Error complement */ |
52 | 5867c88a | ths | #define PARA_STS_TMOUT 0x01 /* EPP timeout */ |
53 | 6508fe59 | bellard | |
54 | 6508fe59 | bellard | /*
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55 | 6508fe59 | bellard | * These are the definitions for the Printer Control Register
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56 | 6508fe59 | bellard | */
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57 | 5867c88a | ths | #define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */ |
58 | 6508fe59 | bellard | #define PARA_CTR_INTEN 0x10 /* IRQ Enable */ |
59 | 6508fe59 | bellard | #define PARA_CTR_SELECT 0x08 /* Select In complement */ |
60 | 6508fe59 | bellard | #define PARA_CTR_INIT 0x04 /* Initialize Printer complement */ |
61 | 6508fe59 | bellard | #define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */ |
62 | 6508fe59 | bellard | #define PARA_CTR_STROBE 0x01 /* Strobe complement */ |
63 | 6508fe59 | bellard | |
64 | 5867c88a | ths | #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
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65 | 5867c88a | ths | |
66 | 6508fe59 | bellard | struct ParallelState {
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67 | 5867c88a | ths | uint8_t dataw; |
68 | 5867c88a | ths | uint8_t datar; |
69 | 5867c88a | ths | uint8_t status; |
70 | 6508fe59 | bellard | uint8_t control; |
71 | d537cf6c | pbrook | qemu_irq irq; |
72 | 6508fe59 | bellard | int irq_pending;
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73 | 6508fe59 | bellard | CharDriverState *chr; |
74 | e57a8c0e | bellard | int hw_driver;
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75 | 5867c88a | ths | int epp_timeout;
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76 | 5867c88a | ths | uint32_t last_read_offset; /* For debugging */
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77 | d60532ca | ths | /* Memory-mapped interface */
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78 | d60532ca | ths | int it_shift;
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79 | 6508fe59 | bellard | }; |
80 | 6508fe59 | bellard | |
81 | 6508fe59 | bellard | static void parallel_update_irq(ParallelState *s) |
82 | 6508fe59 | bellard | { |
83 | 6508fe59 | bellard | if (s->irq_pending)
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84 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
85 | 6508fe59 | bellard | else
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86 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
87 | 6508fe59 | bellard | } |
88 | 6508fe59 | bellard | |
89 | 5867c88a | ths | static void |
90 | 5867c88a | ths | parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
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91 | 6508fe59 | bellard | { |
92 | 6508fe59 | bellard | ParallelState *s = opaque; |
93 | 3b46e624 | ths | |
94 | 5867c88a | ths | pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
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95 | 5867c88a | ths | |
96 | 5867c88a | ths | addr &= 7;
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97 | 5867c88a | ths | switch(addr) {
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98 | 5867c88a | ths | case PARA_REG_DATA:
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99 | 0fa7f157 | ths | s->dataw = val; |
100 | 0fa7f157 | ths | parallel_update_irq(s); |
101 | 5867c88a | ths | break;
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102 | 5867c88a | ths | case PARA_REG_CTR:
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103 | 52ccc5e0 | balrog | val |= 0xc0;
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104 | 0fa7f157 | ths | if ((val & PARA_CTR_INIT) == 0 ) { |
105 | 0fa7f157 | ths | s->status = PARA_STS_BUSY; |
106 | 0fa7f157 | ths | s->status |= PARA_STS_ACK; |
107 | 0fa7f157 | ths | s->status |= PARA_STS_ONLINE; |
108 | 0fa7f157 | ths | s->status |= PARA_STS_ERROR; |
109 | 0fa7f157 | ths | } |
110 | 0fa7f157 | ths | else if (val & PARA_CTR_SELECT) { |
111 | 0fa7f157 | ths | if (val & PARA_CTR_STROBE) {
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112 | 0fa7f157 | ths | s->status &= ~PARA_STS_BUSY; |
113 | 0fa7f157 | ths | if ((s->control & PARA_CTR_STROBE) == 0) |
114 | 0fa7f157 | ths | qemu_chr_write(s->chr, &s->dataw, 1);
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115 | 0fa7f157 | ths | } else {
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116 | 0fa7f157 | ths | if (s->control & PARA_CTR_INTEN) {
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117 | 0fa7f157 | ths | s->irq_pending = 1;
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118 | 0fa7f157 | ths | } |
119 | 0fa7f157 | ths | } |
120 | 0fa7f157 | ths | } |
121 | 0fa7f157 | ths | parallel_update_irq(s); |
122 | 0fa7f157 | ths | s->control = val; |
123 | 5867c88a | ths | break;
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124 | 5867c88a | ths | } |
125 | 5867c88a | ths | } |
126 | 5867c88a | ths | |
127 | 5867c88a | ths | static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) |
128 | 5867c88a | ths | { |
129 | 5867c88a | ths | ParallelState *s = opaque; |
130 | 5867c88a | ths | uint8_t parm = val; |
131 | 563e3c6e | aurel32 | int dir;
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132 | 5867c88a | ths | |
133 | 5867c88a | ths | /* Sometimes programs do several writes for timing purposes on old
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134 | 5867c88a | ths | HW. Take care not to waste time on writes that do nothing. */
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135 | 5867c88a | ths | |
136 | 5867c88a | ths | s->last_read_offset = ~0U;
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137 | 5867c88a | ths | |
138 | 6508fe59 | bellard | addr &= 7;
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139 | 6508fe59 | bellard | switch(addr) {
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140 | 5867c88a | ths | case PARA_REG_DATA:
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141 | 5867c88a | ths | if (s->dataw == val)
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142 | 0fa7f157 | ths | return;
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143 | 0fa7f157 | ths | pdebug("wd%02x\n", val);
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144 | 0fa7f157 | ths | qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm); |
145 | 0fa7f157 | ths | s->dataw = val; |
146 | 6508fe59 | bellard | break;
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147 | 5867c88a | ths | case PARA_REG_STS:
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148 | 0fa7f157 | ths | pdebug("ws%02x\n", val);
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149 | 0fa7f157 | ths | if (val & PARA_STS_TMOUT)
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150 | 0fa7f157 | ths | s->epp_timeout = 0;
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151 | 0fa7f157 | ths | break;
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152 | 5867c88a | ths | case PARA_REG_CTR:
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153 | 5867c88a | ths | val |= 0xc0;
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154 | 5867c88a | ths | if (s->control == val)
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155 | 0fa7f157 | ths | return;
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156 | 0fa7f157 | ths | pdebug("wc%02x\n", val);
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157 | 563e3c6e | aurel32 | |
158 | 563e3c6e | aurel32 | if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
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159 | 563e3c6e | aurel32 | if (val & PARA_CTR_DIR) {
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160 | 563e3c6e | aurel32 | dir = 1;
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161 | 563e3c6e | aurel32 | } else {
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162 | 563e3c6e | aurel32 | dir = 0;
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163 | 563e3c6e | aurel32 | } |
164 | 563e3c6e | aurel32 | qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir); |
165 | 563e3c6e | aurel32 | parm &= ~PARA_CTR_DIR; |
166 | 563e3c6e | aurel32 | } |
167 | 563e3c6e | aurel32 | |
168 | 0fa7f157 | ths | qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm); |
169 | 0fa7f157 | ths | s->control = val; |
170 | 6508fe59 | bellard | break;
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171 | 5867c88a | ths | case PARA_REG_EPP_ADDR:
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172 | 0fa7f157 | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
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173 | 0fa7f157 | ths | /* Controls not correct for EPP address cycle, so do nothing */
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174 | 0fa7f157 | ths | pdebug("wa%02x s\n", val);
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175 | 0fa7f157 | ths | else {
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176 | 0fa7f157 | ths | struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; |
177 | 0fa7f157 | ths | if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
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178 | 0fa7f157 | ths | s->epp_timeout = 1;
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179 | 0fa7f157 | ths | pdebug("wa%02x t\n", val);
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180 | 0fa7f157 | ths | } |
181 | 0fa7f157 | ths | else
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182 | 0fa7f157 | ths | pdebug("wa%02x\n", val);
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183 | 0fa7f157 | ths | } |
184 | 0fa7f157 | ths | break;
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185 | 5867c88a | ths | case PARA_REG_EPP_DATA:
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186 | 0fa7f157 | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
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187 | 0fa7f157 | ths | /* Controls not correct for EPP data cycle, so do nothing */
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188 | 0fa7f157 | ths | pdebug("we%02x s\n", val);
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189 | 0fa7f157 | ths | else {
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190 | 0fa7f157 | ths | struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; |
191 | 0fa7f157 | ths | if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
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192 | 0fa7f157 | ths | s->epp_timeout = 1;
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193 | 0fa7f157 | ths | pdebug("we%02x t\n", val);
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194 | 0fa7f157 | ths | } |
195 | 0fa7f157 | ths | else
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196 | 0fa7f157 | ths | pdebug("we%02x\n", val);
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197 | 0fa7f157 | ths | } |
198 | 0fa7f157 | ths | break;
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199 | 5867c88a | ths | } |
200 | 5867c88a | ths | } |
201 | 5867c88a | ths | |
202 | 5867c88a | ths | static void |
203 | 5867c88a | ths | parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
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204 | 5867c88a | ths | { |
205 | 5867c88a | ths | ParallelState *s = opaque; |
206 | 5867c88a | ths | uint16_t eppdata = cpu_to_le16(val); |
207 | 5867c88a | ths | int err;
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208 | 5867c88a | ths | struct ParallelIOArg ioarg = {
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209 | 0fa7f157 | ths | .buffer = &eppdata, .count = sizeof(eppdata)
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210 | 5867c88a | ths | }; |
211 | 5867c88a | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
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212 | 0fa7f157 | ths | /* Controls not correct for EPP data cycle, so do nothing */
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213 | 0fa7f157 | ths | pdebug("we%04x s\n", val);
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214 | 0fa7f157 | ths | return;
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215 | 5867c88a | ths | } |
216 | 5867c88a | ths | err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); |
217 | 5867c88a | ths | if (err) {
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218 | 0fa7f157 | ths | s->epp_timeout = 1;
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219 | 0fa7f157 | ths | pdebug("we%04x t\n", val);
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220 | 5867c88a | ths | } |
221 | 5867c88a | ths | else
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222 | 0fa7f157 | ths | pdebug("we%04x\n", val);
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223 | 5867c88a | ths | } |
224 | 5867c88a | ths | |
225 | 5867c88a | ths | static void |
226 | 5867c88a | ths | parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
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227 | 5867c88a | ths | { |
228 | 5867c88a | ths | ParallelState *s = opaque; |
229 | 5867c88a | ths | uint32_t eppdata = cpu_to_le32(val); |
230 | 5867c88a | ths | int err;
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231 | 5867c88a | ths | struct ParallelIOArg ioarg = {
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232 | 0fa7f157 | ths | .buffer = &eppdata, .count = sizeof(eppdata)
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233 | 5867c88a | ths | }; |
234 | 5867c88a | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
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235 | 0fa7f157 | ths | /* Controls not correct for EPP data cycle, so do nothing */
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236 | 0fa7f157 | ths | pdebug("we%08x s\n", val);
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237 | 0fa7f157 | ths | return;
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238 | 5867c88a | ths | } |
239 | 5867c88a | ths | err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); |
240 | 5867c88a | ths | if (err) {
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241 | 0fa7f157 | ths | s->epp_timeout = 1;
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242 | 0fa7f157 | ths | pdebug("we%08x t\n", val);
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243 | 6508fe59 | bellard | } |
244 | 5867c88a | ths | else
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245 | 0fa7f157 | ths | pdebug("we%08x\n", val);
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246 | 6508fe59 | bellard | } |
247 | 6508fe59 | bellard | |
248 | 5867c88a | ths | static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr) |
249 | 6508fe59 | bellard | { |
250 | 6508fe59 | bellard | ParallelState *s = opaque; |
251 | 6508fe59 | bellard | uint32_t ret = 0xff;
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252 | 6508fe59 | bellard | |
253 | 6508fe59 | bellard | addr &= 7;
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254 | 6508fe59 | bellard | switch(addr) {
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255 | 5867c88a | ths | case PARA_REG_DATA:
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256 | 0fa7f157 | ths | if (s->control & PARA_CTR_DIR)
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257 | 0fa7f157 | ths | ret = s->datar; |
258 | 0fa7f157 | ths | else
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259 | 0fa7f157 | ths | ret = s->dataw; |
260 | 6508fe59 | bellard | break;
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261 | 5867c88a | ths | case PARA_REG_STS:
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262 | 0fa7f157 | ths | ret = s->status; |
263 | 0fa7f157 | ths | s->irq_pending = 0;
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264 | 0fa7f157 | ths | if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) { |
265 | 0fa7f157 | ths | /* XXX Fixme: wait 5 microseconds */
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266 | 0fa7f157 | ths | if (s->status & PARA_STS_ACK)
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267 | 0fa7f157 | ths | s->status &= ~PARA_STS_ACK; |
268 | 0fa7f157 | ths | else {
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269 | 0fa7f157 | ths | /* XXX Fixme: wait 5 microseconds */
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270 | 0fa7f157 | ths | s->status |= PARA_STS_ACK; |
271 | 0fa7f157 | ths | s->status |= PARA_STS_BUSY; |
272 | 0fa7f157 | ths | } |
273 | 0fa7f157 | ths | } |
274 | 0fa7f157 | ths | parallel_update_irq(s); |
275 | 6508fe59 | bellard | break;
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276 | 5867c88a | ths | case PARA_REG_CTR:
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277 | 6508fe59 | bellard | ret = s->control; |
278 | 6508fe59 | bellard | break;
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279 | 6508fe59 | bellard | } |
280 | 5867c88a | ths | pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
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281 | 5867c88a | ths | return ret;
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282 | 5867c88a | ths | } |
283 | 5867c88a | ths | |
284 | 5867c88a | ths | static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) |
285 | 5867c88a | ths | { |
286 | 5867c88a | ths | ParallelState *s = opaque; |
287 | 5867c88a | ths | uint8_t ret = 0xff;
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288 | 5867c88a | ths | addr &= 7;
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289 | 5867c88a | ths | switch(addr) {
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290 | 5867c88a | ths | case PARA_REG_DATA:
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291 | 0fa7f157 | ths | qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret); |
292 | 0fa7f157 | ths | if (s->last_read_offset != addr || s->datar != ret)
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293 | 0fa7f157 | ths | pdebug("rd%02x\n", ret);
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294 | 5867c88a | ths | s->datar = ret; |
295 | 5867c88a | ths | break;
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296 | 5867c88a | ths | case PARA_REG_STS:
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297 | 0fa7f157 | ths | qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret); |
298 | 0fa7f157 | ths | ret &= ~PARA_STS_TMOUT; |
299 | 0fa7f157 | ths | if (s->epp_timeout)
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300 | 0fa7f157 | ths | ret |= PARA_STS_TMOUT; |
301 | 0fa7f157 | ths | if (s->last_read_offset != addr || s->status != ret)
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302 | 0fa7f157 | ths | pdebug("rs%02x\n", ret);
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303 | 0fa7f157 | ths | s->status = ret; |
304 | 5867c88a | ths | break;
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305 | 5867c88a | ths | case PARA_REG_CTR:
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306 | 5867c88a | ths | /* s->control has some bits fixed to 1. It is zero only when
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307 | 0fa7f157 | ths | it has not been yet written to. */
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308 | 0fa7f157 | ths | if (s->control == 0) { |
309 | 0fa7f157 | ths | qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret); |
310 | 0fa7f157 | ths | if (s->last_read_offset != addr)
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311 | 0fa7f157 | ths | pdebug("rc%02x\n", ret);
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312 | 0fa7f157 | ths | s->control = ret; |
313 | 0fa7f157 | ths | } |
314 | 0fa7f157 | ths | else {
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315 | 0fa7f157 | ths | ret = s->control; |
316 | 0fa7f157 | ths | if (s->last_read_offset != addr)
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317 | 0fa7f157 | ths | pdebug("rc%02x\n", ret);
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318 | 0fa7f157 | ths | } |
319 | 5867c88a | ths | break;
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320 | 5867c88a | ths | case PARA_REG_EPP_ADDR:
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321 | 0fa7f157 | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
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322 | 0fa7f157 | ths | /* Controls not correct for EPP addr cycle, so do nothing */
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323 | 0fa7f157 | ths | pdebug("ra%02x s\n", ret);
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324 | 0fa7f157 | ths | else {
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325 | 0fa7f157 | ths | struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; |
326 | 0fa7f157 | ths | if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
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327 | 0fa7f157 | ths | s->epp_timeout = 1;
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328 | 0fa7f157 | ths | pdebug("ra%02x t\n", ret);
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329 | 0fa7f157 | ths | } |
330 | 0fa7f157 | ths | else
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331 | 0fa7f157 | ths | pdebug("ra%02x\n", ret);
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332 | 0fa7f157 | ths | } |
333 | 0fa7f157 | ths | break;
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334 | 5867c88a | ths | case PARA_REG_EPP_DATA:
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335 | 0fa7f157 | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
|
336 | 0fa7f157 | ths | /* Controls not correct for EPP data cycle, so do nothing */
|
337 | 0fa7f157 | ths | pdebug("re%02x s\n", ret);
|
338 | 0fa7f157 | ths | else {
|
339 | 0fa7f157 | ths | struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; |
340 | 0fa7f157 | ths | if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
|
341 | 0fa7f157 | ths | s->epp_timeout = 1;
|
342 | 0fa7f157 | ths | pdebug("re%02x t\n", ret);
|
343 | 0fa7f157 | ths | } |
344 | 0fa7f157 | ths | else
|
345 | 0fa7f157 | ths | pdebug("re%02x\n", ret);
|
346 | 0fa7f157 | ths | } |
347 | 0fa7f157 | ths | break;
|
348 | 5867c88a | ths | } |
349 | 5867c88a | ths | s->last_read_offset = addr; |
350 | 5867c88a | ths | return ret;
|
351 | 5867c88a | ths | } |
352 | 5867c88a | ths | |
353 | 5867c88a | ths | static uint32_t
|
354 | 5867c88a | ths | parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
|
355 | 5867c88a | ths | { |
356 | 5867c88a | ths | ParallelState *s = opaque; |
357 | 5867c88a | ths | uint32_t ret; |
358 | 5867c88a | ths | uint16_t eppdata = ~0;
|
359 | 5867c88a | ths | int err;
|
360 | 5867c88a | ths | struct ParallelIOArg ioarg = {
|
361 | 0fa7f157 | ths | .buffer = &eppdata, .count = sizeof(eppdata)
|
362 | 5867c88a | ths | }; |
363 | 5867c88a | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
|
364 | 0fa7f157 | ths | /* Controls not correct for EPP data cycle, so do nothing */
|
365 | 0fa7f157 | ths | pdebug("re%04x s\n", eppdata);
|
366 | 0fa7f157 | ths | return eppdata;
|
367 | 5867c88a | ths | } |
368 | 5867c88a | ths | err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); |
369 | 5867c88a | ths | ret = le16_to_cpu(eppdata); |
370 | 5867c88a | ths | |
371 | 5867c88a | ths | if (err) {
|
372 | 0fa7f157 | ths | s->epp_timeout = 1;
|
373 | 0fa7f157 | ths | pdebug("re%04x t\n", ret);
|
374 | 5867c88a | ths | } |
375 | 5867c88a | ths | else
|
376 | 0fa7f157 | ths | pdebug("re%04x\n", ret);
|
377 | 5867c88a | ths | return ret;
|
378 | 5867c88a | ths | } |
379 | 5867c88a | ths | |
380 | 5867c88a | ths | static uint32_t
|
381 | 5867c88a | ths | parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
|
382 | 5867c88a | ths | { |
383 | 5867c88a | ths | ParallelState *s = opaque; |
384 | 5867c88a | ths | uint32_t ret; |
385 | 5867c88a | ths | uint32_t eppdata = ~0U;
|
386 | 5867c88a | ths | int err;
|
387 | 5867c88a | ths | struct ParallelIOArg ioarg = {
|
388 | 0fa7f157 | ths | .buffer = &eppdata, .count = sizeof(eppdata)
|
389 | 5867c88a | ths | }; |
390 | 5867c88a | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
|
391 | 0fa7f157 | ths | /* Controls not correct for EPP data cycle, so do nothing */
|
392 | 0fa7f157 | ths | pdebug("re%08x s\n", eppdata);
|
393 | 0fa7f157 | ths | return eppdata;
|
394 | 5867c88a | ths | } |
395 | 5867c88a | ths | err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); |
396 | 5867c88a | ths | ret = le32_to_cpu(eppdata); |
397 | 5867c88a | ths | |
398 | 5867c88a | ths | if (err) {
|
399 | 0fa7f157 | ths | s->epp_timeout = 1;
|
400 | 0fa7f157 | ths | pdebug("re%08x t\n", ret);
|
401 | 5867c88a | ths | } |
402 | 5867c88a | ths | else
|
403 | 0fa7f157 | ths | pdebug("re%08x\n", ret);
|
404 | 5867c88a | ths | return ret;
|
405 | 5867c88a | ths | } |
406 | 5867c88a | ths | |
407 | 5867c88a | ths | static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val) |
408 | 5867c88a | ths | { |
409 | 5867c88a | ths | addr &= 7;
|
410 | 5867c88a | ths | pdebug("wecp%d=%02x\n", addr, val);
|
411 | 5867c88a | ths | } |
412 | 5867c88a | ths | |
413 | 5867c88a | ths | static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr) |
414 | 5867c88a | ths | { |
415 | 5867c88a | ths | uint8_t ret = 0xff;
|
416 | 5867c88a | ths | addr &= 7;
|
417 | 5867c88a | ths | pdebug("recp%d:%02x\n", addr, ret);
|
418 | 6508fe59 | bellard | return ret;
|
419 | 6508fe59 | bellard | } |
420 | 6508fe59 | bellard | |
421 | 33093a0a | aurel32 | static void parallel_reset(void *opaque) |
422 | 6508fe59 | bellard | { |
423 | 33093a0a | aurel32 | ParallelState *s = opaque; |
424 | 33093a0a | aurel32 | |
425 | 5867c88a | ths | s->datar = ~0;
|
426 | 5867c88a | ths | s->dataw = ~0;
|
427 | 6508fe59 | bellard | s->status = PARA_STS_BUSY; |
428 | 6508fe59 | bellard | s->status |= PARA_STS_ACK; |
429 | 6508fe59 | bellard | s->status |= PARA_STS_ONLINE; |
430 | 6508fe59 | bellard | s->status |= PARA_STS_ERROR; |
431 | 52ccc5e0 | balrog | s->status |= PARA_STS_TMOUT; |
432 | 6508fe59 | bellard | s->control = PARA_CTR_SELECT; |
433 | 6508fe59 | bellard | s->control |= PARA_CTR_INIT; |
434 | 52ccc5e0 | balrog | s->control |= 0xc0;
|
435 | 5867c88a | ths | s->irq_pending = 0;
|
436 | 5867c88a | ths | s->hw_driver = 0;
|
437 | 5867c88a | ths | s->epp_timeout = 0;
|
438 | 5867c88a | ths | s->last_read_offset = ~0U;
|
439 | d60532ca | ths | } |
440 | d60532ca | ths | |
441 | d60532ca | ths | /* If fd is zero, it means that the parallel device uses the console */
|
442 | d60532ca | ths | ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
|
443 | d60532ca | ths | { |
444 | d60532ca | ths | ParallelState *s; |
445 | d60532ca | ths | uint8_t dummy; |
446 | d60532ca | ths | |
447 | d60532ca | ths | s = qemu_mallocz(sizeof(ParallelState));
|
448 | 33093a0a | aurel32 | s->irq = irq; |
449 | 33093a0a | aurel32 | s->chr = chr; |
450 | 33093a0a | aurel32 | parallel_reset(s); |
451 | a08d4367 | Jan Kiszka | qemu_register_reset(parallel_reset, s); |
452 | 6508fe59 | bellard | |
453 | 5867c88a | ths | if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { |
454 | 5867c88a | ths | s->hw_driver = 1;
|
455 | 0fa7f157 | ths | s->status = dummy; |
456 | 5867c88a | ths | } |
457 | 5867c88a | ths | |
458 | 5867c88a | ths | if (s->hw_driver) {
|
459 | 0fa7f157 | ths | register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s); |
460 | 0fa7f157 | ths | register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s); |
461 | 0fa7f157 | ths | register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s); |
462 | 0fa7f157 | ths | register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s); |
463 | 0fa7f157 | ths | register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s); |
464 | 0fa7f157 | ths | register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s); |
465 | 0fa7f157 | ths | register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s); |
466 | 0fa7f157 | ths | register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s); |
467 | 5867c88a | ths | } |
468 | 5867c88a | ths | else {
|
469 | 0fa7f157 | ths | register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s); |
470 | 0fa7f157 | ths | register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s); |
471 | 5867c88a | ths | } |
472 | 6508fe59 | bellard | return s;
|
473 | 6508fe59 | bellard | } |
474 | d60532ca | ths | |
475 | d60532ca | ths | /* Memory mapped interface */
|
476 | 9596ebb7 | pbrook | static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr) |
477 | d60532ca | ths | { |
478 | d60532ca | ths | ParallelState *s = opaque; |
479 | d60532ca | ths | |
480 | 8da3ff18 | pbrook | return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF; |
481 | d60532ca | ths | } |
482 | d60532ca | ths | |
483 | 9596ebb7 | pbrook | static void parallel_mm_writeb (void *opaque, |
484 | 9596ebb7 | pbrook | target_phys_addr_t addr, uint32_t value) |
485 | d60532ca | ths | { |
486 | d60532ca | ths | ParallelState *s = opaque; |
487 | d60532ca | ths | |
488 | 8da3ff18 | pbrook | parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
|
489 | d60532ca | ths | } |
490 | d60532ca | ths | |
491 | 9596ebb7 | pbrook | static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr) |
492 | d60532ca | ths | { |
493 | d60532ca | ths | ParallelState *s = opaque; |
494 | d60532ca | ths | |
495 | 8da3ff18 | pbrook | return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF; |
496 | d60532ca | ths | } |
497 | d60532ca | ths | |
498 | 9596ebb7 | pbrook | static void parallel_mm_writew (void *opaque, |
499 | 9596ebb7 | pbrook | target_phys_addr_t addr, uint32_t value) |
500 | d60532ca | ths | { |
501 | d60532ca | ths | ParallelState *s = opaque; |
502 | d60532ca | ths | |
503 | 8da3ff18 | pbrook | parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
|
504 | d60532ca | ths | } |
505 | d60532ca | ths | |
506 | 9596ebb7 | pbrook | static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr) |
507 | d60532ca | ths | { |
508 | d60532ca | ths | ParallelState *s = opaque; |
509 | d60532ca | ths | |
510 | 8da3ff18 | pbrook | return parallel_ioport_read_sw(s, addr >> s->it_shift);
|
511 | d60532ca | ths | } |
512 | d60532ca | ths | |
513 | 9596ebb7 | pbrook | static void parallel_mm_writel (void *opaque, |
514 | 9596ebb7 | pbrook | target_phys_addr_t addr, uint32_t value) |
515 | d60532ca | ths | { |
516 | d60532ca | ths | ParallelState *s = opaque; |
517 | d60532ca | ths | |
518 | 8da3ff18 | pbrook | parallel_ioport_write_sw(s, addr >> s->it_shift, value); |
519 | d60532ca | ths | } |
520 | d60532ca | ths | |
521 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const parallel_mm_read_sw[] = { |
522 | d60532ca | ths | ¶llel_mm_readb, |
523 | d60532ca | ths | ¶llel_mm_readw, |
524 | d60532ca | ths | ¶llel_mm_readl, |
525 | d60532ca | ths | }; |
526 | d60532ca | ths | |
527 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const parallel_mm_write_sw[] = { |
528 | d60532ca | ths | ¶llel_mm_writeb, |
529 | d60532ca | ths | ¶llel_mm_writew, |
530 | d60532ca | ths | ¶llel_mm_writel, |
531 | d60532ca | ths | }; |
532 | d60532ca | ths | |
533 | d60532ca | ths | /* If fd is zero, it means that the parallel device uses the console */
|
534 | d60532ca | ths | ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr)
|
535 | d60532ca | ths | { |
536 | d60532ca | ths | ParallelState *s; |
537 | d60532ca | ths | int io_sw;
|
538 | d60532ca | ths | |
539 | d60532ca | ths | s = qemu_mallocz(sizeof(ParallelState));
|
540 | 33093a0a | aurel32 | s->irq = irq; |
541 | 33093a0a | aurel32 | s->chr = chr; |
542 | d60532ca | ths | s->it_shift = it_shift; |
543 | 33093a0a | aurel32 | parallel_reset(s); |
544 | a08d4367 | Jan Kiszka | qemu_register_reset(parallel_reset, s); |
545 | d60532ca | ths | |
546 | 1eed09cb | Avi Kivity | io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw, s); |
547 | d60532ca | ths | cpu_register_physical_memory(base, 8 << it_shift, io_sw);
|
548 | d60532ca | ths | return s;
|
549 | d60532ca | ths | } |