root / hw / sun4u.c @ f7b4f61f
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1 | 3475187d | bellard | /*
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2 | c7ba218d | blueswir1 | * QEMU Sun4u/Sun4v System Emulator
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3 | 5fafdf24 | ths | *
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4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
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9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
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12 | 3475187d | bellard | *
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13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 3475187d | bellard | * all copies or substantial portions of the Software.
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15 | 3475187d | bellard | *
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16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 3475187d | bellard | * THE SOFTWARE.
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23 | 3475187d | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pci.h" |
26 | 87ecb68b | pbrook | #include "pc.h" |
27 | 87ecb68b | pbrook | #include "nvram.h" |
28 | 87ecb68b | pbrook | #include "fdc.h" |
29 | 87ecb68b | pbrook | #include "net.h" |
30 | 87ecb68b | pbrook | #include "qemu-timer.h" |
31 | 87ecb68b | pbrook | #include "sysemu.h" |
32 | 87ecb68b | pbrook | #include "boards.h" |
33 | d2c63fc1 | blueswir1 | #include "firmware_abi.h" |
34 | 3cce6243 | blueswir1 | #include "fw_cfg.h" |
35 | 1baffa46 | Blue Swirl | #include "sysbus.h" |
36 | 977e1244 | Gerd Hoffmann | #include "ide.h" |
37 | 3475187d | bellard | |
38 | 9d926598 | blueswir1 | //#define DEBUG_IRQ
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39 | 9d926598 | blueswir1 | |
40 | 9d926598 | blueswir1 | #ifdef DEBUG_IRQ
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41 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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42 | 001faf32 | Blue Swirl | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) |
43 | 9d926598 | blueswir1 | #else
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44 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...)
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45 | 9d926598 | blueswir1 | #endif
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46 | 9d926598 | blueswir1 | |
47 | 83469015 | bellard | #define KERNEL_LOAD_ADDR 0x00404000 |
48 | 83469015 | bellard | #define CMDLINE_ADDR 0x003ff000 |
49 | 83469015 | bellard | #define INITRD_LOAD_ADDR 0x00300000 |
50 | ac2e9d66 | blueswir1 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
51 | f930d07e | blueswir1 | #define PROM_VADDR 0x000ffd00000ULL |
52 | 83469015 | bellard | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
53 | f930d07e | blueswir1 | #define APB_MEM_BASE 0x1ff00000000ULL |
54 | f930d07e | blueswir1 | #define VGA_BASE (APB_MEM_BASE + 0x400000ULL) |
55 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc64" |
56 | 83469015 | bellard | #define NVRAM_SIZE 0x2000 |
57 | e4bcb14c | ths | #define MAX_IDE_BUS 2 |
58 | 3cce6243 | blueswir1 | #define BIOS_CFG_IOPORT 0x510 |
59 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
60 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) |
61 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) |
62 | 3475187d | bellard | |
63 | 9d926598 | blueswir1 | #define MAX_PILS 16 |
64 | 9d926598 | blueswir1 | |
65 | 8fa211e8 | blueswir1 | #define TICK_INT_DIS 0x8000000000000000ULL |
66 | 8fa211e8 | blueswir1 | #define TICK_MAX 0x7fffffffffffffffULL |
67 | 8fa211e8 | blueswir1 | |
68 | c7ba218d | blueswir1 | struct hwdef {
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69 | c7ba218d | blueswir1 | const char * const default_cpu_model; |
70 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
71 | e87231d4 | blueswir1 | uint64_t prom_addr; |
72 | e87231d4 | blueswir1 | uint64_t console_serial_base; |
73 | c7ba218d | blueswir1 | }; |
74 | c7ba218d | blueswir1 | |
75 | 3475187d | bellard | int DMA_get_channel_mode (int nchan) |
76 | 3475187d | bellard | { |
77 | 3475187d | bellard | return 0; |
78 | 3475187d | bellard | } |
79 | 3475187d | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
80 | 3475187d | bellard | { |
81 | 3475187d | bellard | return 0; |
82 | 3475187d | bellard | } |
83 | 3475187d | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
84 | 3475187d | bellard | { |
85 | 3475187d | bellard | return 0; |
86 | 3475187d | bellard | } |
87 | 3475187d | bellard | void DMA_hold_DREQ (int nchan) {} |
88 | 3475187d | bellard | void DMA_release_DREQ (int nchan) {} |
89 | 3475187d | bellard | void DMA_schedule(int nchan) {} |
90 | 3475187d | bellard | void DMA_init (int high_page_enable) {} |
91 | 3475187d | bellard | void DMA_register_channel (int nchan, |
92 | 3475187d | bellard | DMA_transfer_handler transfer_handler, |
93 | 3475187d | bellard | void *opaque)
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94 | 3475187d | bellard | { |
95 | 3475187d | bellard | } |
96 | 3475187d | bellard | |
97 | 513f789f | blueswir1 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
98 | 81864572 | blueswir1 | { |
99 | 513f789f | blueswir1 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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100 | 81864572 | blueswir1 | return 0; |
101 | 81864572 | blueswir1 | } |
102 | 81864572 | blueswir1 | |
103 | d2c63fc1 | blueswir1 | static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size, |
104 | e7fb1406 | blueswir1 | const char *arch, |
105 | 77f193da | blueswir1 | ram_addr_t RAM_size, |
106 | 77f193da | blueswir1 | const char *boot_devices, |
107 | d2c63fc1 | blueswir1 | uint32_t kernel_image, uint32_t kernel_size, |
108 | d2c63fc1 | blueswir1 | const char *cmdline, |
109 | d2c63fc1 | blueswir1 | uint32_t initrd_image, uint32_t initrd_size, |
110 | d2c63fc1 | blueswir1 | uint32_t NVRAM_image, |
111 | 0d31cb99 | blueswir1 | int width, int height, int depth, |
112 | 0d31cb99 | blueswir1 | const uint8_t *macaddr)
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113 | 83469015 | bellard | { |
114 | 66508601 | blueswir1 | unsigned int i; |
115 | 66508601 | blueswir1 | uint32_t start, end; |
116 | d2c63fc1 | blueswir1 | uint8_t image[0x1ff0];
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117 | d2c63fc1 | blueswir1 | struct OpenBIOS_nvpart_v1 *part_header;
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118 | d2c63fc1 | blueswir1 | |
119 | d2c63fc1 | blueswir1 | memset(image, '\0', sizeof(image)); |
120 | d2c63fc1 | blueswir1 | |
121 | 513f789f | blueswir1 | start = 0;
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122 | 83469015 | bellard | |
123 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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124 | 66508601 | blueswir1 | // Variable partition
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125 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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126 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_SYSTEM; |
127 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
128 | 66508601 | blueswir1 | |
129 | d2c63fc1 | blueswir1 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
130 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
131 | d2c63fc1 | blueswir1 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
132 | d2c63fc1 | blueswir1 | |
133 | d2c63fc1 | blueswir1 | // End marker
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134 | d2c63fc1 | blueswir1 | image[end++] = '\0';
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135 | 66508601 | blueswir1 | |
136 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
137 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
138 | 66508601 | blueswir1 | |
139 | 66508601 | blueswir1 | // free partition
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140 | 66508601 | blueswir1 | start = end; |
141 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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142 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_FREE; |
143 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
144 | 66508601 | blueswir1 | |
145 | 66508601 | blueswir1 | end = 0x1fd0;
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146 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
147 | d2c63fc1 | blueswir1 | |
148 | 0d31cb99 | blueswir1 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
149 | 0d31cb99 | blueswir1 | |
150 | d2c63fc1 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
151 | d2c63fc1 | blueswir1 | m48t59_write(nvram, i, image[i]); |
152 | 66508601 | blueswir1 | |
153 | 83469015 | bellard | return 0; |
154 | 3475187d | bellard | } |
155 | 636aa70a | Blue Swirl | static unsigned long sun4u_load_kernel(const char *kernel_filename, |
156 | 636aa70a | Blue Swirl | const char *initrd_filename, |
157 | 636aa70a | Blue Swirl | ram_addr_t RAM_size, long *initrd_size)
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158 | 636aa70a | Blue Swirl | { |
159 | 636aa70a | Blue Swirl | int linux_boot;
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160 | 636aa70a | Blue Swirl | unsigned int i; |
161 | 636aa70a | Blue Swirl | long kernel_size;
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162 | 636aa70a | Blue Swirl | |
163 | 636aa70a | Blue Swirl | linux_boot = (kernel_filename != NULL);
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164 | 636aa70a | Blue Swirl | |
165 | 636aa70a | Blue Swirl | kernel_size = 0;
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166 | 636aa70a | Blue Swirl | if (linux_boot) {
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167 | 636aa70a | Blue Swirl | kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL); |
168 | 636aa70a | Blue Swirl | if (kernel_size < 0) |
169 | 636aa70a | Blue Swirl | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
170 | 636aa70a | Blue Swirl | RAM_size - KERNEL_LOAD_ADDR); |
171 | 636aa70a | Blue Swirl | if (kernel_size < 0) |
172 | 636aa70a | Blue Swirl | kernel_size = load_image_targphys(kernel_filename, |
173 | 636aa70a | Blue Swirl | KERNEL_LOAD_ADDR, |
174 | 636aa70a | Blue Swirl | RAM_size - KERNEL_LOAD_ADDR); |
175 | 636aa70a | Blue Swirl | if (kernel_size < 0) { |
176 | 636aa70a | Blue Swirl | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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177 | 636aa70a | Blue Swirl | kernel_filename); |
178 | 636aa70a | Blue Swirl | exit(1);
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179 | 636aa70a | Blue Swirl | } |
180 | 636aa70a | Blue Swirl | |
181 | 636aa70a | Blue Swirl | /* load initrd */
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182 | 636aa70a | Blue Swirl | *initrd_size = 0;
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183 | 636aa70a | Blue Swirl | if (initrd_filename) {
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184 | 636aa70a | Blue Swirl | *initrd_size = load_image_targphys(initrd_filename, |
185 | 636aa70a | Blue Swirl | INITRD_LOAD_ADDR, |
186 | 636aa70a | Blue Swirl | RAM_size - INITRD_LOAD_ADDR); |
187 | 636aa70a | Blue Swirl | if (*initrd_size < 0) { |
188 | 636aa70a | Blue Swirl | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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189 | 636aa70a | Blue Swirl | initrd_filename); |
190 | 636aa70a | Blue Swirl | exit(1);
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191 | 636aa70a | Blue Swirl | } |
192 | 636aa70a | Blue Swirl | } |
193 | 636aa70a | Blue Swirl | if (*initrd_size > 0) { |
194 | 636aa70a | Blue Swirl | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
195 | 636aa70a | Blue Swirl | if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS |
196 | 636aa70a | Blue Swirl | stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
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197 | 636aa70a | Blue Swirl | stl_phys(KERNEL_LOAD_ADDR + i + 20, *initrd_size);
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198 | 636aa70a | Blue Swirl | break;
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199 | 636aa70a | Blue Swirl | } |
200 | 636aa70a | Blue Swirl | } |
201 | 636aa70a | Blue Swirl | } |
202 | 636aa70a | Blue Swirl | } |
203 | 636aa70a | Blue Swirl | return kernel_size;
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204 | 636aa70a | Blue Swirl | } |
205 | 3475187d | bellard | |
206 | b4950060 | blueswir1 | void pic_info(Monitor *mon)
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207 | 3475187d | bellard | { |
208 | 3475187d | bellard | } |
209 | 3475187d | bellard | |
210 | b4950060 | blueswir1 | void irq_info(Monitor *mon)
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211 | 3475187d | bellard | { |
212 | 3475187d | bellard | } |
213 | 3475187d | bellard | |
214 | 9d926598 | blueswir1 | void cpu_check_irqs(CPUState *env)
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215 | 9d926598 | blueswir1 | { |
216 | 9d926598 | blueswir1 | uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) | |
217 | 9d926598 | blueswir1 | ((env->softint & SOFTINT_TIMER) << 14);
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218 | 9d926598 | blueswir1 | |
219 | 9d926598 | blueswir1 | if (pil && (env->interrupt_index == 0 || |
220 | 9d926598 | blueswir1 | (env->interrupt_index & ~15) == TT_EXTINT)) {
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221 | 9d926598 | blueswir1 | unsigned int i; |
222 | 9d926598 | blueswir1 | |
223 | 9d926598 | blueswir1 | for (i = 15; i > 0; i--) { |
224 | 9d926598 | blueswir1 | if (pil & (1 << i)) { |
225 | 9d926598 | blueswir1 | int old_interrupt = env->interrupt_index;
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226 | 9d926598 | blueswir1 | |
227 | 9d926598 | blueswir1 | env->interrupt_index = TT_EXTINT | i; |
228 | 9d926598 | blueswir1 | if (old_interrupt != env->interrupt_index) {
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229 | 9d926598 | blueswir1 | DPRINTF("Set CPU IRQ %d\n", i);
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230 | 9d926598 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
231 | 9d926598 | blueswir1 | } |
232 | 9d926598 | blueswir1 | break;
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233 | 9d926598 | blueswir1 | } |
234 | 9d926598 | blueswir1 | } |
235 | 9d926598 | blueswir1 | } else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) { |
236 | 9d926598 | blueswir1 | DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); |
237 | 9d926598 | blueswir1 | env->interrupt_index = 0;
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238 | 9d926598 | blueswir1 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
239 | 9d926598 | blueswir1 | } |
240 | 9d926598 | blueswir1 | } |
241 | 9d926598 | blueswir1 | |
242 | 9d926598 | blueswir1 | static void cpu_set_irq(void *opaque, int irq, int level) |
243 | 9d926598 | blueswir1 | { |
244 | 9d926598 | blueswir1 | CPUState *env = opaque; |
245 | 9d926598 | blueswir1 | |
246 | 9d926598 | blueswir1 | if (level) {
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247 | 9d926598 | blueswir1 | DPRINTF("Raise CPU IRQ %d\n", irq);
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248 | 9d926598 | blueswir1 | env->halted = 0;
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249 | 9d926598 | blueswir1 | env->pil_in |= 1 << irq;
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250 | 9d926598 | blueswir1 | cpu_check_irqs(env); |
251 | 9d926598 | blueswir1 | } else {
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252 | 9d926598 | blueswir1 | DPRINTF("Lower CPU IRQ %d\n", irq);
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253 | 9d926598 | blueswir1 | env->pil_in &= ~(1 << irq);
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254 | 9d926598 | blueswir1 | cpu_check_irqs(env); |
255 | 9d926598 | blueswir1 | } |
256 | 9d926598 | blueswir1 | } |
257 | 9d926598 | blueswir1 | |
258 | e87231d4 | blueswir1 | typedef struct ResetData { |
259 | e87231d4 | blueswir1 | CPUState *env; |
260 | e87231d4 | blueswir1 | uint64_t reset_addr; |
261 | e87231d4 | blueswir1 | } ResetData; |
262 | e87231d4 | blueswir1 | |
263 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
264 | c68ea704 | bellard | { |
265 | e87231d4 | blueswir1 | ResetData *s = (ResetData *)opaque; |
266 | e87231d4 | blueswir1 | CPUState *env = s->env; |
267 | 20c9f095 | blueswir1 | |
268 | c68ea704 | bellard | cpu_reset(env); |
269 | 8fa211e8 | blueswir1 | env->tick_cmpr = TICK_INT_DIS | 0;
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270 | 8fa211e8 | blueswir1 | ptimer_set_limit(env->tick, TICK_MAX, 1);
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271 | 2f43e00e | blueswir1 | ptimer_run(env->tick, 1);
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272 | 8fa211e8 | blueswir1 | env->stick_cmpr = TICK_INT_DIS | 0;
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273 | 8fa211e8 | blueswir1 | ptimer_set_limit(env->stick, TICK_MAX, 1);
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274 | 2f43e00e | blueswir1 | ptimer_run(env->stick, 1);
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275 | 8fa211e8 | blueswir1 | env->hstick_cmpr = TICK_INT_DIS | 0;
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276 | 8fa211e8 | blueswir1 | ptimer_set_limit(env->hstick, TICK_MAX, 1);
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277 | 2f43e00e | blueswir1 | ptimer_run(env->hstick, 1);
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278 | e87231d4 | blueswir1 | env->gregs[1] = 0; // Memory start |
279 | e87231d4 | blueswir1 | env->gregs[2] = ram_size; // Memory size |
280 | e87231d4 | blueswir1 | env->gregs[3] = 0; // Machine description XXX |
281 | e87231d4 | blueswir1 | env->pc = s->reset_addr; |
282 | e87231d4 | blueswir1 | env->npc = env->pc + 4;
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283 | 20c9f095 | blueswir1 | } |
284 | 20c9f095 | blueswir1 | |
285 | 22548760 | blueswir1 | static void tick_irq(void *opaque) |
286 | 20c9f095 | blueswir1 | { |
287 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
288 | 20c9f095 | blueswir1 | |
289 | 8fa211e8 | blueswir1 | if (!(env->tick_cmpr & TICK_INT_DIS)) {
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290 | 8fa211e8 | blueswir1 | env->softint |= SOFTINT_TIMER; |
291 | 8fa211e8 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
292 | 8fa211e8 | blueswir1 | } |
293 | 20c9f095 | blueswir1 | } |
294 | 20c9f095 | blueswir1 | |
295 | 22548760 | blueswir1 | static void stick_irq(void *opaque) |
296 | 20c9f095 | blueswir1 | { |
297 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
298 | 20c9f095 | blueswir1 | |
299 | 8fa211e8 | blueswir1 | if (!(env->stick_cmpr & TICK_INT_DIS)) {
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300 | 8fa211e8 | blueswir1 | env->softint |= SOFTINT_STIMER; |
301 | 8fa211e8 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
302 | 8fa211e8 | blueswir1 | } |
303 | 20c9f095 | blueswir1 | } |
304 | 20c9f095 | blueswir1 | |
305 | 22548760 | blueswir1 | static void hstick_irq(void *opaque) |
306 | 20c9f095 | blueswir1 | { |
307 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
308 | 20c9f095 | blueswir1 | |
309 | 8fa211e8 | blueswir1 | if (!(env->hstick_cmpr & TICK_INT_DIS)) {
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310 | 8fa211e8 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
311 | 8fa211e8 | blueswir1 | } |
312 | c68ea704 | bellard | } |
313 | c68ea704 | bellard | |
314 | f4b1a842 | blueswir1 | void cpu_tick_set_count(void *opaque, uint64_t count) |
315 | f4b1a842 | blueswir1 | { |
316 | f4b1a842 | blueswir1 | ptimer_set_count(opaque, -count); |
317 | f4b1a842 | blueswir1 | } |
318 | f4b1a842 | blueswir1 | |
319 | f4b1a842 | blueswir1 | uint64_t cpu_tick_get_count(void *opaque)
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320 | f4b1a842 | blueswir1 | { |
321 | f4b1a842 | blueswir1 | return -ptimer_get_count(opaque);
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322 | f4b1a842 | blueswir1 | } |
323 | f4b1a842 | blueswir1 | |
324 | f4b1a842 | blueswir1 | void cpu_tick_set_limit(void *opaque, uint64_t limit) |
325 | f4b1a842 | blueswir1 | { |
326 | f4b1a842 | blueswir1 | ptimer_set_limit(opaque, -limit, 0);
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327 | f4b1a842 | blueswir1 | } |
328 | f4b1a842 | blueswir1 | |
329 | 83469015 | bellard | static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
330 | 83469015 | bellard | static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
331 | 83469015 | bellard | |
332 | 83469015 | bellard | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
333 | 83469015 | bellard | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; |
334 | 83469015 | bellard | |
335 | c190ea07 | blueswir1 | static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num, |
336 | c190ea07 | blueswir1 | uint32_t addr, uint32_t size, int type)
|
337 | c190ea07 | blueswir1 | { |
338 | c190ea07 | blueswir1 | DPRINTF("Mapping region %d registers at %08x\n", region_num, addr);
|
339 | c190ea07 | blueswir1 | switch (region_num) {
|
340 | c190ea07 | blueswir1 | case 0: |
341 | c190ea07 | blueswir1 | isa_mmio_init(addr, 0x1000000);
|
342 | c190ea07 | blueswir1 | break;
|
343 | c190ea07 | blueswir1 | case 1: |
344 | c190ea07 | blueswir1 | isa_mmio_init(addr, 0x800000);
|
345 | c190ea07 | blueswir1 | break;
|
346 | c190ea07 | blueswir1 | } |
347 | c190ea07 | blueswir1 | } |
348 | c190ea07 | blueswir1 | |
349 | 1387fe4a | Blue Swirl | static void dummy_isa_irq_handler(void *opaque, int n, int level) |
350 | 1387fe4a | Blue Swirl | { |
351 | 1387fe4a | Blue Swirl | } |
352 | 1387fe4a | Blue Swirl | |
353 | c190ea07 | blueswir1 | /* EBUS (Eight bit bus) bridge */
|
354 | c190ea07 | blueswir1 | static void |
355 | c190ea07 | blueswir1 | pci_ebus_init(PCIBus *bus, int devfn)
|
356 | c190ea07 | blueswir1 | { |
357 | 1387fe4a | Blue Swirl | qemu_irq *isa_irq; |
358 | 1387fe4a | Blue Swirl | |
359 | 53e3c4f9 | Blue Swirl | pci_create_simple(bus, devfn, "ebus");
|
360 | 1387fe4a | Blue Swirl | isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16); |
361 | 1387fe4a | Blue Swirl | isa_bus_irqs(isa_irq); |
362 | 53e3c4f9 | Blue Swirl | } |
363 | c190ea07 | blueswir1 | |
364 | 81a322d4 | Gerd Hoffmann | static int |
365 | 53e3c4f9 | Blue Swirl | pci_ebus_init1(PCIDevice *s) |
366 | 53e3c4f9 | Blue Swirl | { |
367 | 0c5b8d83 | Blue Swirl | isa_bus_new(&s->qdev); |
368 | 0c5b8d83 | Blue Swirl | |
369 | deb54399 | aliguori | pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN); |
370 | deb54399 | aliguori | pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS); |
371 | c190ea07 | blueswir1 | s->config[0x04] = 0x06; // command = bus master, pci mem |
372 | c190ea07 | blueswir1 | s->config[0x05] = 0x00; |
373 | c190ea07 | blueswir1 | s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
374 | c190ea07 | blueswir1 | s->config[0x07] = 0x03; // status = medium devsel |
375 | c190ea07 | blueswir1 | s->config[0x08] = 0x01; // revision |
376 | c190ea07 | blueswir1 | s->config[0x09] = 0x00; // programming i/f |
377 | 173a543b | blueswir1 | pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER); |
378 | c190ea07 | blueswir1 | s->config[0x0D] = 0x0a; // latency_timer |
379 | 6407f373 | Isaku Yamahata | s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
|
380 | c190ea07 | blueswir1 | |
381 | 28c2c264 | Avi Kivity | pci_register_bar(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM, |
382 | c190ea07 | blueswir1 | ebus_mmio_mapfunc); |
383 | 28c2c264 | Avi Kivity | pci_register_bar(s, 1, 0x800000, PCI_ADDRESS_SPACE_MEM, |
384 | c190ea07 | blueswir1 | ebus_mmio_mapfunc); |
385 | 81a322d4 | Gerd Hoffmann | return 0; |
386 | c190ea07 | blueswir1 | } |
387 | c190ea07 | blueswir1 | |
388 | 53e3c4f9 | Blue Swirl | static PCIDeviceInfo ebus_info = {
|
389 | 53e3c4f9 | Blue Swirl | .qdev.name = "ebus",
|
390 | 53e3c4f9 | Blue Swirl | .qdev.size = sizeof(PCIDevice),
|
391 | 53e3c4f9 | Blue Swirl | .init = pci_ebus_init1, |
392 | 53e3c4f9 | Blue Swirl | }; |
393 | 53e3c4f9 | Blue Swirl | |
394 | 53e3c4f9 | Blue Swirl | static void pci_ebus_register(void) |
395 | 53e3c4f9 | Blue Swirl | { |
396 | 53e3c4f9 | Blue Swirl | pci_qdev_register(&ebus_info); |
397 | 53e3c4f9 | Blue Swirl | } |
398 | 53e3c4f9 | Blue Swirl | |
399 | 53e3c4f9 | Blue Swirl | device_init(pci_ebus_register); |
400 | 53e3c4f9 | Blue Swirl | |
401 | 1baffa46 | Blue Swirl | /* Boot PROM (OpenBIOS) */
|
402 | 1baffa46 | Blue Swirl | static void prom_init(target_phys_addr_t addr, const char *bios_name) |
403 | 1baffa46 | Blue Swirl | { |
404 | 1baffa46 | Blue Swirl | DeviceState *dev; |
405 | 1baffa46 | Blue Swirl | SysBusDevice *s; |
406 | 1baffa46 | Blue Swirl | char *filename;
|
407 | 1baffa46 | Blue Swirl | int ret;
|
408 | 1baffa46 | Blue Swirl | |
409 | 1baffa46 | Blue Swirl | dev = qdev_create(NULL, "openprom"); |
410 | 1baffa46 | Blue Swirl | qdev_init(dev); |
411 | 1baffa46 | Blue Swirl | s = sysbus_from_qdev(dev); |
412 | 1baffa46 | Blue Swirl | |
413 | 1baffa46 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
414 | 1baffa46 | Blue Swirl | |
415 | 1baffa46 | Blue Swirl | /* load boot prom */
|
416 | 1baffa46 | Blue Swirl | if (bios_name == NULL) { |
417 | 1baffa46 | Blue Swirl | bios_name = PROM_FILENAME; |
418 | 1baffa46 | Blue Swirl | } |
419 | 1baffa46 | Blue Swirl | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
420 | 1baffa46 | Blue Swirl | if (filename) {
|
421 | 1baffa46 | Blue Swirl | ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL); |
422 | 1baffa46 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
423 | 1baffa46 | Blue Swirl | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); |
424 | 1baffa46 | Blue Swirl | } |
425 | 1baffa46 | Blue Swirl | qemu_free(filename); |
426 | 1baffa46 | Blue Swirl | } else {
|
427 | 1baffa46 | Blue Swirl | ret = -1;
|
428 | 1baffa46 | Blue Swirl | } |
429 | 1baffa46 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
430 | 1baffa46 | Blue Swirl | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
431 | 1baffa46 | Blue Swirl | exit(1);
|
432 | 1baffa46 | Blue Swirl | } |
433 | 1baffa46 | Blue Swirl | } |
434 | 1baffa46 | Blue Swirl | |
435 | 81a322d4 | Gerd Hoffmann | static int prom_init1(SysBusDevice *dev) |
436 | 1baffa46 | Blue Swirl | { |
437 | 1baffa46 | Blue Swirl | ram_addr_t prom_offset; |
438 | 1baffa46 | Blue Swirl | |
439 | 1baffa46 | Blue Swirl | prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); |
440 | 1baffa46 | Blue Swirl | sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM); |
441 | 81a322d4 | Gerd Hoffmann | return 0; |
442 | 1baffa46 | Blue Swirl | } |
443 | 1baffa46 | Blue Swirl | |
444 | 1baffa46 | Blue Swirl | static SysBusDeviceInfo prom_info = {
|
445 | 1baffa46 | Blue Swirl | .init = prom_init1, |
446 | 1baffa46 | Blue Swirl | .qdev.name = "openprom",
|
447 | 1baffa46 | Blue Swirl | .qdev.size = sizeof(SysBusDevice),
|
448 | 1baffa46 | Blue Swirl | .qdev.props = (Property[]) { |
449 | 1baffa46 | Blue Swirl | {/* end of property list */}
|
450 | 1baffa46 | Blue Swirl | } |
451 | 1baffa46 | Blue Swirl | }; |
452 | 1baffa46 | Blue Swirl | |
453 | 1baffa46 | Blue Swirl | static void prom_register_devices(void) |
454 | 1baffa46 | Blue Swirl | { |
455 | 1baffa46 | Blue Swirl | sysbus_register_withprop(&prom_info); |
456 | 1baffa46 | Blue Swirl | } |
457 | 1baffa46 | Blue Swirl | |
458 | 1baffa46 | Blue Swirl | device_init(prom_register_devices); |
459 | 1baffa46 | Blue Swirl | |
460 | bda42033 | Blue Swirl | |
461 | bda42033 | Blue Swirl | typedef struct RamDevice |
462 | bda42033 | Blue Swirl | { |
463 | bda42033 | Blue Swirl | SysBusDevice busdev; |
464 | 04843626 | Blue Swirl | uint64_t size; |
465 | bda42033 | Blue Swirl | } RamDevice; |
466 | bda42033 | Blue Swirl | |
467 | bda42033 | Blue Swirl | /* System RAM */
|
468 | 81a322d4 | Gerd Hoffmann | static int ram_init1(SysBusDevice *dev) |
469 | bda42033 | Blue Swirl | { |
470 | bda42033 | Blue Swirl | ram_addr_t RAM_size, ram_offset; |
471 | bda42033 | Blue Swirl | RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
472 | bda42033 | Blue Swirl | |
473 | bda42033 | Blue Swirl | RAM_size = d->size; |
474 | bda42033 | Blue Swirl | |
475 | bda42033 | Blue Swirl | ram_offset = qemu_ram_alloc(RAM_size); |
476 | bda42033 | Blue Swirl | sysbus_init_mmio(dev, RAM_size, ram_offset); |
477 | 81a322d4 | Gerd Hoffmann | return 0; |
478 | bda42033 | Blue Swirl | } |
479 | bda42033 | Blue Swirl | |
480 | bda42033 | Blue Swirl | static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size) |
481 | bda42033 | Blue Swirl | { |
482 | bda42033 | Blue Swirl | DeviceState *dev; |
483 | bda42033 | Blue Swirl | SysBusDevice *s; |
484 | bda42033 | Blue Swirl | RamDevice *d; |
485 | bda42033 | Blue Swirl | |
486 | bda42033 | Blue Swirl | /* allocate RAM */
|
487 | bda42033 | Blue Swirl | dev = qdev_create(NULL, "memory"); |
488 | bda42033 | Blue Swirl | s = sysbus_from_qdev(dev); |
489 | bda42033 | Blue Swirl | |
490 | bda42033 | Blue Swirl | d = FROM_SYSBUS(RamDevice, s); |
491 | bda42033 | Blue Swirl | d->size = RAM_size; |
492 | bda42033 | Blue Swirl | qdev_init(dev); |
493 | bda42033 | Blue Swirl | |
494 | bda42033 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
495 | bda42033 | Blue Swirl | } |
496 | bda42033 | Blue Swirl | |
497 | bda42033 | Blue Swirl | static SysBusDeviceInfo ram_info = {
|
498 | bda42033 | Blue Swirl | .init = ram_init1, |
499 | bda42033 | Blue Swirl | .qdev.name = "memory",
|
500 | bda42033 | Blue Swirl | .qdev.size = sizeof(RamDevice),
|
501 | bda42033 | Blue Swirl | .qdev.props = (Property[]) { |
502 | 32a7ee98 | Gerd Hoffmann | DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
503 | 32a7ee98 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
504 | bda42033 | Blue Swirl | } |
505 | bda42033 | Blue Swirl | }; |
506 | bda42033 | Blue Swirl | |
507 | bda42033 | Blue Swirl | static void ram_register_devices(void) |
508 | bda42033 | Blue Swirl | { |
509 | bda42033 | Blue Swirl | sysbus_register_withprop(&ram_info); |
510 | bda42033 | Blue Swirl | } |
511 | bda42033 | Blue Swirl | |
512 | bda42033 | Blue Swirl | device_init(ram_register_devices); |
513 | bda42033 | Blue Swirl | |
514 | 7b833f5b | Blue Swirl | static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) |
515 | 3475187d | bellard | { |
516 | c68ea704 | bellard | CPUState *env; |
517 | 20c9f095 | blueswir1 | QEMUBH *bh; |
518 | e87231d4 | blueswir1 | ResetData *reset_info; |
519 | 3475187d | bellard | |
520 | c7ba218d | blueswir1 | if (!cpu_model)
|
521 | c7ba218d | blueswir1 | cpu_model = hwdef->default_cpu_model; |
522 | aaed909a | bellard | env = cpu_init(cpu_model); |
523 | aaed909a | bellard | if (!env) {
|
524 | 62724a37 | blueswir1 | fprintf(stderr, "Unable to find Sparc CPU definition\n");
|
525 | 62724a37 | blueswir1 | exit(1);
|
526 | 62724a37 | blueswir1 | } |
527 | 20c9f095 | blueswir1 | bh = qemu_bh_new(tick_irq, env); |
528 | 20c9f095 | blueswir1 | env->tick = ptimer_init(bh); |
529 | 20c9f095 | blueswir1 | ptimer_set_period(env->tick, 1ULL);
|
530 | 20c9f095 | blueswir1 | |
531 | 20c9f095 | blueswir1 | bh = qemu_bh_new(stick_irq, env); |
532 | 20c9f095 | blueswir1 | env->stick = ptimer_init(bh); |
533 | 20c9f095 | blueswir1 | ptimer_set_period(env->stick, 1ULL);
|
534 | 20c9f095 | blueswir1 | |
535 | 20c9f095 | blueswir1 | bh = qemu_bh_new(hstick_irq, env); |
536 | 20c9f095 | blueswir1 | env->hstick = ptimer_init(bh); |
537 | 20c9f095 | blueswir1 | ptimer_set_period(env->hstick, 1ULL);
|
538 | e87231d4 | blueswir1 | |
539 | e87231d4 | blueswir1 | reset_info = qemu_mallocz(sizeof(ResetData));
|
540 | e87231d4 | blueswir1 | reset_info->env = env; |
541 | e87231d4 | blueswir1 | reset_info->reset_addr = hwdef->prom_addr + 0x40ULL;
|
542 | a08d4367 | Jan Kiszka | qemu_register_reset(main_cpu_reset, reset_info); |
543 | e87231d4 | blueswir1 | main_cpu_reset(reset_info); |
544 | e87231d4 | blueswir1 | // Override warm reset address with cold start address
|
545 | e87231d4 | blueswir1 | env->pc = hwdef->prom_addr + 0x20ULL;
|
546 | e87231d4 | blueswir1 | env->npc = env->pc + 4;
|
547 | c68ea704 | bellard | |
548 | 7b833f5b | Blue Swirl | return env;
|
549 | 7b833f5b | Blue Swirl | } |
550 | 7b833f5b | Blue Swirl | |
551 | 7b833f5b | Blue Swirl | static void sun4uv_init(ram_addr_t RAM_size, |
552 | 7b833f5b | Blue Swirl | const char *boot_devices, |
553 | 7b833f5b | Blue Swirl | const char *kernel_filename, const char *kernel_cmdline, |
554 | 7b833f5b | Blue Swirl | const char *initrd_filename, const char *cpu_model, |
555 | 7b833f5b | Blue Swirl | const struct hwdef *hwdef) |
556 | 7b833f5b | Blue Swirl | { |
557 | 7b833f5b | Blue Swirl | CPUState *env; |
558 | 7b833f5b | Blue Swirl | m48t59_t *nvram; |
559 | 7b833f5b | Blue Swirl | unsigned int i; |
560 | 7b833f5b | Blue Swirl | long initrd_size, kernel_size;
|
561 | 7b833f5b | Blue Swirl | PCIBus *pci_bus, *pci_bus2, *pci_bus3; |
562 | 7b833f5b | Blue Swirl | qemu_irq *irq; |
563 | f455e98c | Gerd Hoffmann | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
564 | 7b833f5b | Blue Swirl | BlockDriverState *fd[MAX_FD]; |
565 | 7b833f5b | Blue Swirl | void *fw_cfg;
|
566 | 751c6a17 | Gerd Hoffmann | DriveInfo *dinfo; |
567 | 7b833f5b | Blue Swirl | |
568 | 7b833f5b | Blue Swirl | /* init CPUs */
|
569 | 7b833f5b | Blue Swirl | env = cpu_devinit(cpu_model, hwdef); |
570 | 7b833f5b | Blue Swirl | |
571 | bda42033 | Blue Swirl | /* set up devices */
|
572 | bda42033 | Blue Swirl | ram_init(0, RAM_size);
|
573 | 3475187d | bellard | |
574 | 1baffa46 | Blue Swirl | prom_init(hwdef->prom_addr, bios_name); |
575 | 3475187d | bellard | |
576 | 7d55273f | Igor Kovalenko | |
577 | 7d55273f | Igor Kovalenko | irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
578 | 7d55273f | Igor Kovalenko | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2, |
579 | c190ea07 | blueswir1 | &pci_bus3); |
580 | 83469015 | bellard | isa_mem_base = VGA_BASE; |
581 | fbe1b595 | Paul Brook | pci_vga_init(pci_bus, 0, 0); |
582 | 83469015 | bellard | |
583 | c190ea07 | blueswir1 | // XXX Should be pci_bus3
|
584 | c190ea07 | blueswir1 | pci_ebus_init(pci_bus, -1);
|
585 | c190ea07 | blueswir1 | |
586 | e87231d4 | blueswir1 | i = 0;
|
587 | e87231d4 | blueswir1 | if (hwdef->console_serial_base) {
|
588 | e87231d4 | blueswir1 | serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200, |
589 | e87231d4 | blueswir1 | serial_hds[i], 1);
|
590 | e87231d4 | blueswir1 | i++; |
591 | e87231d4 | blueswir1 | } |
592 | e87231d4 | blueswir1 | for(; i < MAX_SERIAL_PORTS; i++) {
|
593 | 83469015 | bellard | if (serial_hds[i]) {
|
594 | cbf5c748 | blueswir1 | serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200, |
595 | cbf5c748 | blueswir1 | serial_hds[i]); |
596 | 83469015 | bellard | } |
597 | 83469015 | bellard | } |
598 | 83469015 | bellard | |
599 | 83469015 | bellard | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
600 | 83469015 | bellard | if (parallel_hds[i]) {
|
601 | 77f193da | blueswir1 | parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, |
602 | 77f193da | blueswir1 | parallel_hds[i]); |
603 | 83469015 | bellard | } |
604 | 83469015 | bellard | } |
605 | 83469015 | bellard | |
606 | cb457d76 | aliguori | for(i = 0; i < nb_nics; i++) |
607 | 6d53bfd1 | Igor V. Kovalenko | pci_nic_init(&nd_table[i], "ne2k_pci", NULL); |
608 | 83469015 | bellard | |
609 | e4bcb14c | ths | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
610 | e4bcb14c | ths | fprintf(stderr, "qemu: too many IDE bus\n");
|
611 | e4bcb14c | ths | exit(1);
|
612 | e4bcb14c | ths | } |
613 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
614 | f455e98c | Gerd Hoffmann | hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, |
615 | 751c6a17 | Gerd Hoffmann | i % MAX_IDE_DEVS); |
616 | e4bcb14c | ths | } |
617 | e4bcb14c | ths | |
618 | 3b898dda | blueswir1 | pci_cmd646_ide_init(pci_bus, hd, 1);
|
619 | 3b898dda | blueswir1 | |
620 | 2e15e23b | Gerd Hoffmann | isa_create_simple("i8042");
|
621 | e4bcb14c | ths | for(i = 0; i < MAX_FD; i++) { |
622 | 751c6a17 | Gerd Hoffmann | dinfo = drive_get(IF_FLOPPY, 0, i);
|
623 | 751c6a17 | Gerd Hoffmann | fd[i] = dinfo ? dinfo->bdrv : NULL;
|
624 | e4bcb14c | ths | } |
625 | 86c86157 | Gerd Hoffmann | fdctrl_init_isa(fd); |
626 | 1e43a8e4 | Blue Swirl | /* FIXME: wire up interrupts. */
|
627 | d537cf6c | pbrook | nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59); |
628 | 636aa70a | Blue Swirl | |
629 | 636aa70a | Blue Swirl | initrd_size = 0;
|
630 | 636aa70a | Blue Swirl | kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename, |
631 | 636aa70a | Blue Swirl | ram_size, &initrd_size); |
632 | 636aa70a | Blue Swirl | |
633 | 22548760 | blueswir1 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
|
634 | 0d31cb99 | blueswir1 | KERNEL_LOAD_ADDR, kernel_size, |
635 | 0d31cb99 | blueswir1 | kernel_cmdline, |
636 | 0d31cb99 | blueswir1 | INITRD_LOAD_ADDR, initrd_size, |
637 | 0d31cb99 | blueswir1 | /* XXX: need an option to load a NVRAM image */
|
638 | 0d31cb99 | blueswir1 | 0,
|
639 | 0d31cb99 | blueswir1 | graphic_width, graphic_height, graphic_depth, |
640 | 0d31cb99 | blueswir1 | (uint8_t *)&nd_table[0].macaddr);
|
641 | 83469015 | bellard | |
642 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
643 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
644 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
645 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
646 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
647 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
648 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
649 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
650 | 513f789f | blueswir1 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); |
651 | 513f789f | blueswir1 | } else {
|
652 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
653 | 513f789f | blueswir1 | } |
654 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
655 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
656 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
|
657 | 7589690c | Blue Swirl | |
658 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); |
659 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); |
660 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); |
661 | 7589690c | Blue Swirl | |
662 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
663 | 3475187d | bellard | } |
664 | 3475187d | bellard | |
665 | 905fdcb5 | blueswir1 | enum {
|
666 | 905fdcb5 | blueswir1 | sun4u_id = 0,
|
667 | 905fdcb5 | blueswir1 | sun4v_id = 64,
|
668 | e87231d4 | blueswir1 | niagara_id, |
669 | 905fdcb5 | blueswir1 | }; |
670 | 905fdcb5 | blueswir1 | |
671 | c7ba218d | blueswir1 | static const struct hwdef hwdefs[] = { |
672 | c7ba218d | blueswir1 | /* Sun4u generic PC-like machine */
|
673 | c7ba218d | blueswir1 | { |
674 | c7ba218d | blueswir1 | .default_cpu_model = "TI UltraSparc II",
|
675 | 905fdcb5 | blueswir1 | .machine_id = sun4u_id, |
676 | e87231d4 | blueswir1 | .prom_addr = 0x1fff0000000ULL,
|
677 | e87231d4 | blueswir1 | .console_serial_base = 0,
|
678 | c7ba218d | blueswir1 | }, |
679 | c7ba218d | blueswir1 | /* Sun4v generic PC-like machine */
|
680 | c7ba218d | blueswir1 | { |
681 | c7ba218d | blueswir1 | .default_cpu_model = "Sun UltraSparc T1",
|
682 | 905fdcb5 | blueswir1 | .machine_id = sun4v_id, |
683 | e87231d4 | blueswir1 | .prom_addr = 0x1fff0000000ULL,
|
684 | e87231d4 | blueswir1 | .console_serial_base = 0,
|
685 | e87231d4 | blueswir1 | }, |
686 | e87231d4 | blueswir1 | /* Sun4v generic Niagara machine */
|
687 | e87231d4 | blueswir1 | { |
688 | e87231d4 | blueswir1 | .default_cpu_model = "Sun UltraSparc T1",
|
689 | e87231d4 | blueswir1 | .machine_id = niagara_id, |
690 | e87231d4 | blueswir1 | .prom_addr = 0xfff0000000ULL,
|
691 | e87231d4 | blueswir1 | .console_serial_base = 0xfff0c2c000ULL,
|
692 | c7ba218d | blueswir1 | }, |
693 | c7ba218d | blueswir1 | }; |
694 | c7ba218d | blueswir1 | |
695 | c7ba218d | blueswir1 | /* Sun4u hardware initialisation */
|
696 | fbe1b595 | Paul Brook | static void sun4u_init(ram_addr_t RAM_size, |
697 | 3023f332 | aliguori | const char *boot_devices, |
698 | c7ba218d | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
699 | c7ba218d | blueswir1 | const char *initrd_filename, const char *cpu_model) |
700 | c7ba218d | blueswir1 | { |
701 | fbe1b595 | Paul Brook | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
702 | c7ba218d | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
|
703 | c7ba218d | blueswir1 | } |
704 | c7ba218d | blueswir1 | |
705 | c7ba218d | blueswir1 | /* Sun4v hardware initialisation */
|
706 | fbe1b595 | Paul Brook | static void sun4v_init(ram_addr_t RAM_size, |
707 | 3023f332 | aliguori | const char *boot_devices, |
708 | c7ba218d | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
709 | c7ba218d | blueswir1 | const char *initrd_filename, const char *cpu_model) |
710 | c7ba218d | blueswir1 | { |
711 | fbe1b595 | Paul Brook | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
712 | c7ba218d | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
|
713 | c7ba218d | blueswir1 | } |
714 | c7ba218d | blueswir1 | |
715 | e87231d4 | blueswir1 | /* Niagara hardware initialisation */
|
716 | fbe1b595 | Paul Brook | static void niagara_init(ram_addr_t RAM_size, |
717 | 3023f332 | aliguori | const char *boot_devices, |
718 | e87231d4 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
719 | e87231d4 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
720 | e87231d4 | blueswir1 | { |
721 | fbe1b595 | Paul Brook | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
722 | e87231d4 | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
|
723 | e87231d4 | blueswir1 | } |
724 | e87231d4 | blueswir1 | |
725 | f80f9ec9 | Anthony Liguori | static QEMUMachine sun4u_machine = {
|
726 | 66de733b | blueswir1 | .name = "sun4u",
|
727 | 66de733b | blueswir1 | .desc = "Sun4u platform",
|
728 | 66de733b | blueswir1 | .init = sun4u_init, |
729 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
730 | 0c257437 | Anthony Liguori | .is_default = 1,
|
731 | 3475187d | bellard | }; |
732 | c7ba218d | blueswir1 | |
733 | f80f9ec9 | Anthony Liguori | static QEMUMachine sun4v_machine = {
|
734 | 66de733b | blueswir1 | .name = "sun4v",
|
735 | 66de733b | blueswir1 | .desc = "Sun4v platform",
|
736 | 66de733b | blueswir1 | .init = sun4v_init, |
737 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
738 | c7ba218d | blueswir1 | }; |
739 | e87231d4 | blueswir1 | |
740 | f80f9ec9 | Anthony Liguori | static QEMUMachine niagara_machine = {
|
741 | e87231d4 | blueswir1 | .name = "Niagara",
|
742 | e87231d4 | blueswir1 | .desc = "Sun4v platform, Niagara",
|
743 | e87231d4 | blueswir1 | .init = niagara_init, |
744 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
745 | e87231d4 | blueswir1 | }; |
746 | f80f9ec9 | Anthony Liguori | |
747 | f80f9ec9 | Anthony Liguori | static void sun4u_machine_init(void) |
748 | f80f9ec9 | Anthony Liguori | { |
749 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&sun4u_machine); |
750 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&sun4v_machine); |
751 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&niagara_machine); |
752 | f80f9ec9 | Anthony Liguori | } |
753 | f80f9ec9 | Anthony Liguori | |
754 | f80f9ec9 | Anthony Liguori | machine_init(sun4u_machine_init); |