root / hw / mcf5208.c @ f8274971
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1 | 5fafdf24 | ths | /*
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2 | 20dcee94 | pbrook | * Motorola ColdFire MCF5208 SoC emulation.
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3 | 20dcee94 | pbrook | *
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4 | 20dcee94 | pbrook | * Copyright (c) 2007 CodeSourcery.
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5 | 20dcee94 | pbrook | *
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6 | 20dcee94 | pbrook | * This code is licenced under the GPL
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7 | 20dcee94 | pbrook | */
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8 | 87ecb68b | pbrook | #include "hw.h" |
9 | 87ecb68b | pbrook | #include "mcf.h" |
10 | 87ecb68b | pbrook | #include "qemu-timer.h" |
11 | 87ecb68b | pbrook | #include "sysemu.h" |
12 | 87ecb68b | pbrook | #include "net.h" |
13 | 87ecb68b | pbrook | #include "boards.h" |
14 | 20dcee94 | pbrook | |
15 | 20dcee94 | pbrook | #define SYS_FREQ 66000000 |
16 | 20dcee94 | pbrook | |
17 | 20dcee94 | pbrook | #define PCSR_EN 0x0001 |
18 | 20dcee94 | pbrook | #define PCSR_RLD 0x0002 |
19 | 20dcee94 | pbrook | #define PCSR_PIF 0x0004 |
20 | 20dcee94 | pbrook | #define PCSR_PIE 0x0008 |
21 | 20dcee94 | pbrook | #define PCSR_OVW 0x0010 |
22 | 20dcee94 | pbrook | #define PCSR_DBG 0x0020 |
23 | 20dcee94 | pbrook | #define PCSR_DOZE 0x0040 |
24 | 20dcee94 | pbrook | #define PCSR_PRE_SHIFT 8 |
25 | 20dcee94 | pbrook | #define PCSR_PRE_MASK 0x0f00 |
26 | 20dcee94 | pbrook | |
27 | 20dcee94 | pbrook | typedef struct { |
28 | 20dcee94 | pbrook | qemu_irq irq; |
29 | 20dcee94 | pbrook | ptimer_state *timer; |
30 | 20dcee94 | pbrook | uint16_t pcsr; |
31 | 20dcee94 | pbrook | uint16_t pmr; |
32 | 20dcee94 | pbrook | uint16_t pcntr; |
33 | 20dcee94 | pbrook | } m5208_timer_state; |
34 | 20dcee94 | pbrook | |
35 | 20dcee94 | pbrook | static void m5208_timer_update(m5208_timer_state *s) |
36 | 20dcee94 | pbrook | { |
37 | 20dcee94 | pbrook | if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF))
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38 | 20dcee94 | pbrook | qemu_irq_raise(s->irq); |
39 | 20dcee94 | pbrook | else
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40 | 20dcee94 | pbrook | qemu_irq_lower(s->irq); |
41 | 20dcee94 | pbrook | } |
42 | 20dcee94 | pbrook | |
43 | 8da3ff18 | pbrook | static void m5208_timer_write(void *opaque, target_phys_addr_t offset, |
44 | 20dcee94 | pbrook | uint32_t value) |
45 | 20dcee94 | pbrook | { |
46 | 8da3ff18 | pbrook | m5208_timer_state *s = (m5208_timer_state *)opaque; |
47 | 20dcee94 | pbrook | int prescale;
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48 | 20dcee94 | pbrook | int limit;
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49 | 20dcee94 | pbrook | switch (offset) {
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50 | 20dcee94 | pbrook | case 0: |
51 | 20dcee94 | pbrook | /* The PIF bit is set-to-clear. */
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52 | 20dcee94 | pbrook | if (value & PCSR_PIF) {
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53 | 20dcee94 | pbrook | s->pcsr &= ~PCSR_PIF; |
54 | 20dcee94 | pbrook | value &= ~PCSR_PIF; |
55 | 20dcee94 | pbrook | } |
56 | 20dcee94 | pbrook | /* Avoid frobbing the timer if we're just twiddling IRQ bits. */
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57 | 20dcee94 | pbrook | if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) { |
58 | 20dcee94 | pbrook | s->pcsr = value; |
59 | 20dcee94 | pbrook | m5208_timer_update(s); |
60 | 20dcee94 | pbrook | return;
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61 | 20dcee94 | pbrook | } |
62 | 20dcee94 | pbrook | |
63 | 20dcee94 | pbrook | if (s->pcsr & PCSR_EN)
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64 | 20dcee94 | pbrook | ptimer_stop(s->timer); |
65 | 20dcee94 | pbrook | |
66 | 20dcee94 | pbrook | s->pcsr = value; |
67 | 20dcee94 | pbrook | |
68 | 20dcee94 | pbrook | prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT);
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69 | 20dcee94 | pbrook | ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale);
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70 | 20dcee94 | pbrook | if (s->pcsr & PCSR_RLD)
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71 | 20dcee94 | pbrook | limit = s->pmr; |
72 | 6d9db39c | pbrook | else
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73 | 6d9db39c | pbrook | limit = 0xffff;
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74 | 20dcee94 | pbrook | ptimer_set_limit(s->timer, limit, 0);
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75 | 20dcee94 | pbrook | |
76 | 20dcee94 | pbrook | if (s->pcsr & PCSR_EN)
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77 | 20dcee94 | pbrook | ptimer_run(s->timer, 0);
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78 | 20dcee94 | pbrook | break;
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79 | 20dcee94 | pbrook | case 2: |
80 | 20dcee94 | pbrook | s->pmr = value; |
81 | 20dcee94 | pbrook | s->pcsr &= ~PCSR_PIF; |
82 | 6d9db39c | pbrook | if ((s->pcsr & PCSR_RLD) == 0) { |
83 | 6d9db39c | pbrook | if (s->pcsr & PCSR_OVW)
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84 | 6d9db39c | pbrook | ptimer_set_count(s->timer, value); |
85 | 6d9db39c | pbrook | } else {
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86 | 6d9db39c | pbrook | ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW); |
87 | 6d9db39c | pbrook | } |
88 | 20dcee94 | pbrook | break;
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89 | 20dcee94 | pbrook | case 4: |
90 | 20dcee94 | pbrook | break;
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91 | 20dcee94 | pbrook | default:
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92 | 2ac71179 | Paul Brook | hw_error("m5208_timer_write: Bad offset 0x%x\n", (int)offset); |
93 | 8da3ff18 | pbrook | break;
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94 | 20dcee94 | pbrook | } |
95 | 20dcee94 | pbrook | m5208_timer_update(s); |
96 | 20dcee94 | pbrook | } |
97 | 20dcee94 | pbrook | |
98 | 20dcee94 | pbrook | static void m5208_timer_trigger(void *opaque) |
99 | 20dcee94 | pbrook | { |
100 | 20dcee94 | pbrook | m5208_timer_state *s = (m5208_timer_state *)opaque; |
101 | 20dcee94 | pbrook | s->pcsr |= PCSR_PIF; |
102 | 20dcee94 | pbrook | m5208_timer_update(s); |
103 | 20dcee94 | pbrook | } |
104 | 20dcee94 | pbrook | |
105 | 8da3ff18 | pbrook | static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr) |
106 | 8da3ff18 | pbrook | { |
107 | 8da3ff18 | pbrook | m5208_timer_state *s = (m5208_timer_state *)opaque; |
108 | 8da3ff18 | pbrook | switch (addr) {
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109 | 8da3ff18 | pbrook | case 0: |
110 | 8da3ff18 | pbrook | return s->pcsr;
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111 | 8da3ff18 | pbrook | case 2: |
112 | 8da3ff18 | pbrook | return s->pmr;
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113 | 8da3ff18 | pbrook | case 4: |
114 | 8da3ff18 | pbrook | return ptimer_get_count(s->timer);
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115 | 8da3ff18 | pbrook | default:
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116 | 2ac71179 | Paul Brook | hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr); |
117 | 8da3ff18 | pbrook | return 0; |
118 | 8da3ff18 | pbrook | } |
119 | 8da3ff18 | pbrook | } |
120 | 8da3ff18 | pbrook | |
121 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const m5208_timer_readfn[] = { |
122 | 8da3ff18 | pbrook | m5208_timer_read, |
123 | 8da3ff18 | pbrook | m5208_timer_read, |
124 | 8da3ff18 | pbrook | m5208_timer_read |
125 | 8da3ff18 | pbrook | }; |
126 | 8da3ff18 | pbrook | |
127 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const m5208_timer_writefn[] = { |
128 | 8da3ff18 | pbrook | m5208_timer_write, |
129 | 8da3ff18 | pbrook | m5208_timer_write, |
130 | 8da3ff18 | pbrook | m5208_timer_write |
131 | 8da3ff18 | pbrook | }; |
132 | 20dcee94 | pbrook | |
133 | 20dcee94 | pbrook | static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr) |
134 | 20dcee94 | pbrook | { |
135 | 20dcee94 | pbrook | switch (addr) {
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136 | 8da3ff18 | pbrook | case 0x110: /* SDCS0 */ |
137 | 20dcee94 | pbrook | { |
138 | 20dcee94 | pbrook | int n;
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139 | 20dcee94 | pbrook | for (n = 0; n < 32; n++) { |
140 | 20dcee94 | pbrook | if (ram_size < (2u << n)) |
141 | 20dcee94 | pbrook | break;
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142 | 20dcee94 | pbrook | } |
143 | 20dcee94 | pbrook | return (n - 1) | 0x40000000; |
144 | 20dcee94 | pbrook | } |
145 | 8da3ff18 | pbrook | case 0x114: /* SDCS1 */ |
146 | 20dcee94 | pbrook | return 0; |
147 | 20dcee94 | pbrook | |
148 | 20dcee94 | pbrook | default:
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149 | 2ac71179 | Paul Brook | hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr); |
150 | 20dcee94 | pbrook | return 0; |
151 | 20dcee94 | pbrook | } |
152 | 20dcee94 | pbrook | } |
153 | 20dcee94 | pbrook | |
154 | 20dcee94 | pbrook | static void m5208_sys_write(void *opaque, target_phys_addr_t addr, |
155 | 20dcee94 | pbrook | uint32_t value) |
156 | 20dcee94 | pbrook | { |
157 | 2ac71179 | Paul Brook | hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr); |
158 | 20dcee94 | pbrook | } |
159 | 20dcee94 | pbrook | |
160 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const m5208_sys_readfn[] = { |
161 | 20dcee94 | pbrook | m5208_sys_read, |
162 | 20dcee94 | pbrook | m5208_sys_read, |
163 | 20dcee94 | pbrook | m5208_sys_read |
164 | 20dcee94 | pbrook | }; |
165 | 20dcee94 | pbrook | |
166 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const m5208_sys_writefn[] = { |
167 | 20dcee94 | pbrook | m5208_sys_write, |
168 | 20dcee94 | pbrook | m5208_sys_write, |
169 | 20dcee94 | pbrook | m5208_sys_write |
170 | 20dcee94 | pbrook | }; |
171 | 20dcee94 | pbrook | |
172 | 20dcee94 | pbrook | static void mcf5208_sys_init(qemu_irq *pic) |
173 | 20dcee94 | pbrook | { |
174 | 20dcee94 | pbrook | int iomemtype;
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175 | 8da3ff18 | pbrook | m5208_timer_state *s; |
176 | 20dcee94 | pbrook | QEMUBH *bh; |
177 | 20dcee94 | pbrook | int i;
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178 | 20dcee94 | pbrook | |
179 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(m5208_sys_readfn, |
180 | 8da3ff18 | pbrook | m5208_sys_writefn, NULL);
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181 | 20dcee94 | pbrook | /* SDRAMC. */
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182 | 20dcee94 | pbrook | cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype); |
183 | 20dcee94 | pbrook | /* Timers. */
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184 | 20dcee94 | pbrook | for (i = 0; i < 2; i++) { |
185 | 8da3ff18 | pbrook | s = (m5208_timer_state *)qemu_mallocz(sizeof(m5208_timer_state));
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186 | 8da3ff18 | pbrook | bh = qemu_bh_new(m5208_timer_trigger, s); |
187 | 8da3ff18 | pbrook | s->timer = ptimer_init(bh); |
188 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(m5208_timer_readfn, |
189 | 8da3ff18 | pbrook | m5208_timer_writefn, s); |
190 | 20dcee94 | pbrook | cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000, |
191 | 20dcee94 | pbrook | iomemtype); |
192 | 8da3ff18 | pbrook | s->irq = pic[4 + i];
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193 | 20dcee94 | pbrook | } |
194 | 20dcee94 | pbrook | } |
195 | 20dcee94 | pbrook | |
196 | fbe1b595 | Paul Brook | static void mcf5208evb_init(ram_addr_t ram_size, |
197 | 3023f332 | aliguori | const char *boot_device, |
198 | 20dcee94 | pbrook | const char *kernel_filename, const char *kernel_cmdline, |
199 | 20dcee94 | pbrook | const char *initrd_filename, const char *cpu_model) |
200 | 20dcee94 | pbrook | { |
201 | 20dcee94 | pbrook | CPUState *env; |
202 | 20dcee94 | pbrook | int kernel_size;
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203 | 20dcee94 | pbrook | uint64_t elf_entry; |
204 | 20dcee94 | pbrook | target_ulong entry; |
205 | 20dcee94 | pbrook | qemu_irq *pic; |
206 | 20dcee94 | pbrook | |
207 | 20dcee94 | pbrook | if (!cpu_model)
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208 | 20dcee94 | pbrook | cpu_model = "m5208";
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209 | aaed909a | bellard | env = cpu_init(cpu_model); |
210 | aaed909a | bellard | if (!env) {
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211 | aaed909a | bellard | fprintf(stderr, "Unable to find m68k CPU definition\n");
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212 | aaed909a | bellard | exit(1);
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213 | 20dcee94 | pbrook | } |
214 | 20dcee94 | pbrook | |
215 | 20dcee94 | pbrook | /* Initialize CPU registers. */
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216 | 20dcee94 | pbrook | env->vbr = 0;
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217 | 20dcee94 | pbrook | /* TODO: Configure BARs. */
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218 | 20dcee94 | pbrook | |
219 | dcac9679 | pbrook | /* DRAM at 0x40000000 */
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220 | 20dcee94 | pbrook | cpu_register_physical_memory(0x40000000, ram_size,
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221 | 20dcee94 | pbrook | qemu_ram_alloc(ram_size) | IO_MEM_RAM); |
222 | 20dcee94 | pbrook | |
223 | 20dcee94 | pbrook | /* Internal SRAM. */
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224 | 20dcee94 | pbrook | cpu_register_physical_memory(0x80000000, 16384, |
225 | 20dcee94 | pbrook | qemu_ram_alloc(16384) | IO_MEM_RAM);
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226 | 20dcee94 | pbrook | |
227 | 20dcee94 | pbrook | /* Internal peripherals. */
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228 | 20dcee94 | pbrook | pic = mcf_intc_init(0xfc048000, env);
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229 | 20dcee94 | pbrook | |
230 | 20dcee94 | pbrook | mcf_uart_mm_init(0xfc060000, pic[26], serial_hds[0]); |
231 | 20dcee94 | pbrook | mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]); |
232 | 20dcee94 | pbrook | mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]); |
233 | 20dcee94 | pbrook | |
234 | 20dcee94 | pbrook | mcf5208_sys_init(pic); |
235 | 20dcee94 | pbrook | |
236 | 7e049b8a | pbrook | if (nb_nics > 1) { |
237 | 7e049b8a | pbrook | fprintf(stderr, "Too many NICs\n");
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238 | 7e049b8a | pbrook | exit(1);
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239 | 7e049b8a | pbrook | } |
240 | 0ae18cee | aliguori | if (nd_table[0].vlan) |
241 | 0ae18cee | aliguori | mcf_fec_init(&nd_table[0], 0xfc030000, pic + 36); |
242 | 7e049b8a | pbrook | |
243 | 20dcee94 | pbrook | /* 0xfc000000 SCM. */
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244 | 20dcee94 | pbrook | /* 0xfc004000 XBS. */
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245 | 20dcee94 | pbrook | /* 0xfc008000 FlexBus CS. */
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246 | 7e049b8a | pbrook | /* 0xfc030000 FEC. */
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247 | 20dcee94 | pbrook | /* 0xfc040000 SCM + Power management. */
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248 | 20dcee94 | pbrook | /* 0xfc044000 eDMA. */
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249 | 20dcee94 | pbrook | /* 0xfc048000 INTC. */
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250 | 20dcee94 | pbrook | /* 0xfc058000 I2C. */
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251 | 20dcee94 | pbrook | /* 0xfc05c000 QSPI. */
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252 | 20dcee94 | pbrook | /* 0xfc060000 UART0. */
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253 | 20dcee94 | pbrook | /* 0xfc064000 UART0. */
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254 | 20dcee94 | pbrook | /* 0xfc068000 UART0. */
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255 | 20dcee94 | pbrook | /* 0xfc070000 DMA timers. */
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256 | 20dcee94 | pbrook | /* 0xfc080000 PIT0. */
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257 | 20dcee94 | pbrook | /* 0xfc084000 PIT1. */
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258 | 20dcee94 | pbrook | /* 0xfc088000 EPORT. */
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259 | 20dcee94 | pbrook | /* 0xfc08c000 Watchdog. */
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260 | 20dcee94 | pbrook | /* 0xfc090000 clock module. */
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261 | 20dcee94 | pbrook | /* 0xfc0a0000 CCM + reset. */
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262 | 20dcee94 | pbrook | /* 0xfc0a4000 GPIO. */
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263 | 20dcee94 | pbrook | /* 0xfc0a8000 SDRAM controller. */
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264 | 20dcee94 | pbrook | |
265 | 20dcee94 | pbrook | /* Load kernel. */
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266 | 20dcee94 | pbrook | if (!kernel_filename) {
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267 | 20dcee94 | pbrook | fprintf(stderr, "Kernel image must be specified\n");
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268 | 20dcee94 | pbrook | exit(1);
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269 | 20dcee94 | pbrook | } |
270 | 20dcee94 | pbrook | |
271 | 20dcee94 | pbrook | kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL); |
272 | 20dcee94 | pbrook | entry = elf_entry; |
273 | 20dcee94 | pbrook | if (kernel_size < 0) { |
274 | 5a9154e0 | aliguori | kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL); |
275 | 20dcee94 | pbrook | } |
276 | 20dcee94 | pbrook | if (kernel_size < 0) { |
277 | dcac9679 | pbrook | kernel_size = load_image_targphys(kernel_filename, 0x40000000,
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278 | dcac9679 | pbrook | ram_size); |
279 | dcac9679 | pbrook | entry = 0x40000000;
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280 | 20dcee94 | pbrook | } |
281 | 20dcee94 | pbrook | if (kernel_size < 0) { |
282 | 20dcee94 | pbrook | fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
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283 | 20dcee94 | pbrook | exit(1);
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284 | 20dcee94 | pbrook | } |
285 | 20dcee94 | pbrook | |
286 | 20dcee94 | pbrook | env->pc = entry; |
287 | 20dcee94 | pbrook | } |
288 | 20dcee94 | pbrook | |
289 | f80f9ec9 | Anthony Liguori | static QEMUMachine mcf5208evb_machine = {
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290 | 4b32e168 | aliguori | .name = "mcf5208evb",
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291 | 4b32e168 | aliguori | .desc = "MCF5206EVB",
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292 | 4b32e168 | aliguori | .init = mcf5208evb_init, |
293 | 0c257437 | Anthony Liguori | .is_default = 1,
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294 | 20dcee94 | pbrook | }; |
295 | f80f9ec9 | Anthony Liguori | |
296 | f80f9ec9 | Anthony Liguori | static void mcf5208evb_machine_init(void) |
297 | f80f9ec9 | Anthony Liguori | { |
298 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&mcf5208evb_machine); |
299 | f80f9ec9 | Anthony Liguori | } |
300 | f80f9ec9 | Anthony Liguori | |
301 | f80f9ec9 | Anthony Liguori | machine_init(mcf5208evb_machine_init); |