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/*
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* QEMU Floppy disk emulator (Intel 82078)
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*
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* Copyright (c) 2003, 2007 Jocelyn Mayer
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* Copyright (c) 2008 Herv? Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* The controller is used in Sun4m systems in a slightly different
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* way. There are changes in DOR register and DMA is not available.
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*/
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#include "hw.h" |
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#include "fdc.h" |
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#include "block.h" |
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#include "qemu-timer.h" |
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#include "isa.h" |
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#include "sysbus.h" |
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#include "qdev-addr.h" |
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/********************************************************/
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/* debug Floppy devices */
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//#define DEBUG_FLOPPY
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#ifdef DEBUG_FLOPPY
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#define FLOPPY_DPRINTF(fmt, ...) \
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do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define FLOPPY_DPRINTF(fmt, ...)
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#endif
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#define FLOPPY_ERROR(fmt, ...) \
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do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) |
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/********************************************************/
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/* Floppy drive emulation */
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#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
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#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
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/* Will always be a fixed parameter for us */
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#define FD_SECTOR_LEN 512 |
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#define FD_SECTOR_SC 2 /* Sector size code */ |
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#define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */ |
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/* Floppy disk drive emulation */
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typedef enum fdisk_type_t { |
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FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */ |
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FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */ |
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FDRIVE_DISK_720 = 0x03, /* 720 kB disk */ |
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FDRIVE_DISK_USER = 0x04, /* User defined geometry */ |
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FDRIVE_DISK_NONE = 0x05, /* No disk */ |
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} fdisk_type_t; |
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typedef enum fdrive_type_t { |
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FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */ |
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FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */ |
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FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */ |
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FDRIVE_DRV_NONE = 0x03, /* No drive connected */ |
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} fdrive_type_t; |
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typedef enum fdisk_flags_t { |
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FDISK_DBL_SIDES = 0x01,
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} fdisk_flags_t; |
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typedef struct fdrive_t { |
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BlockDriverState *bs; |
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/* Drive status */
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fdrive_type_t drive; |
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uint8_t perpendicular; /* 2.88 MB access mode */
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/* Position */
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uint8_t head; |
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uint8_t track; |
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uint8_t sect; |
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/* Media */
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fdisk_flags_t flags; |
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uint8_t last_sect; /* Nb sector per track */
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uint8_t max_track; /* Nb of tracks */
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uint16_t bps; /* Bytes per sector */
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uint8_t ro; /* Is read-only */
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} fdrive_t; |
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static void fd_init (fdrive_t *drv, BlockDriverState *bs) |
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{ |
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/* Drive */
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drv->bs = bs; |
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drv->drive = FDRIVE_DRV_NONE; |
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drv->perpendicular = 0;
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/* Disk */
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drv->last_sect = 0;
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drv->max_track = 0;
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} |
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static int _fd_sector (uint8_t head, uint8_t track, |
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uint8_t sect, uint8_t last_sect) |
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{ |
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return (((track * 2) + head) * last_sect) + sect - 1; |
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} |
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/* Returns current position, in sectors, for given drive */
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static int fd_sector (fdrive_t *drv) |
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{ |
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return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
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} |
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/* Seek to a new position:
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* returns 0 if already on right track
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* returns 1 if track changed
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* returns 2 if track is invalid
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* returns 3 if sector is invalid
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* returns 4 if seek is disabled
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*/
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static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect, |
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int enable_seek)
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{ |
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uint32_t sector; |
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int ret;
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if (track > drv->max_track ||
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(head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) { |
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FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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head, track, sect, 1,
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(drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, |
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drv->max_track, drv->last_sect); |
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return 2; |
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} |
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if (sect > drv->last_sect) {
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FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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head, track, sect, 1,
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(drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, |
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drv->max_track, drv->last_sect); |
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return 3; |
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} |
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sector = _fd_sector(head, track, sect, drv->last_sect); |
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ret = 0;
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if (sector != fd_sector(drv)) {
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#if 0
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if (!enable_seek) {
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FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
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head, track, sect, 1, drv->max_track, drv->last_sect);
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return 4;
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}
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#endif
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drv->head = head; |
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if (drv->track != track)
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ret = 1;
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drv->track = track; |
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drv->sect = sect; |
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} |
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return ret;
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} |
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/* Set drive back to track 0 */
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static void fd_recalibrate (fdrive_t *drv) |
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{ |
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FLOPPY_DPRINTF("recalibrate\n");
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drv->head = 0;
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drv->track = 0;
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drv->sect = 1;
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} |
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/* Recognize floppy formats */
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typedef struct fd_format_t { |
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fdrive_type_t drive; |
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fdisk_type_t disk; |
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uint8_t last_sect; |
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uint8_t max_track; |
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uint8_t max_head; |
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const char *str; |
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} fd_format_t; |
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static const fd_format_t fd_formats[] = { |
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/* First entry is default format */
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/* 1.44 MB 3"1/2 floppy disks */
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{ FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", }, |
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{ FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1, "1.6 MB 3\"1/2", }, |
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{ FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", }, |
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{ FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", }, |
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{ FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", }, |
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{ FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", }, |
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{ FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", }, |
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{ FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", }, |
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/* 2.88 MB 3"1/2 floppy disks */
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{ FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", }, |
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{ FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", }, |
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{ FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1, "3.2 MB 3\"1/2", }, |
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{ FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", }, |
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{ FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", }, |
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/* 720 kB 3"1/2 floppy disks */
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{ FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 1, "720 kB 3\"1/2", }, |
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{ FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1, "800 kB 3\"1/2", }, |
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{ FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1, "820 kB 3\"1/2", }, |
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{ FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1, "830 kB 3\"1/2", }, |
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{ FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", }, |
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{ FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", }, |
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/* 1.2 MB 5"1/4 floppy disks */
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{ FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1, "1.2 kB 5\"1/4", }, |
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{ FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", }, |
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{ FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", }, |
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{ FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", }, |
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{ FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1, "1.6 MB 5\"1/4", }, |
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/* 720 kB 5"1/4 floppy disks */
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{ FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 80, 1, "720 kB 5\"1/4", }, |
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{ FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1, "880 kB 5\"1/4", }, |
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/* 360 kB 5"1/4 floppy disks */
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{ FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 1, "360 kB 5\"1/4", }, |
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{ FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 0, "180 kB 5\"1/4", }, |
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{ FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1, "410 kB 5\"1/4", }, |
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{ FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1, "420 kB 5\"1/4", }, |
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/* 320 kB 5"1/4 floppy disks */
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{ FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 1, "320 kB 5\"1/4", }, |
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{ FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 0, "160 kB 5\"1/4", }, |
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/* 360 kB must match 5"1/4 better than 3"1/2... */
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{ FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 0, "360 kB 3\"1/2", }, |
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/* end */
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{ FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, }, |
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}; |
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/* Revalidate a disk drive after a disk change */
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static void fd_revalidate (fdrive_t *drv) |
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{ |
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const fd_format_t *parse;
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uint64_t nb_sectors, size; |
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int i, first_match, match;
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int nb_heads, max_track, last_sect, ro;
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FLOPPY_DPRINTF("revalidate\n");
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if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) { |
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ro = bdrv_is_read_only(drv->bs); |
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bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect); |
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if (nb_heads != 0 && max_track != 0 && last_sect != 0) { |
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FLOPPY_DPRINTF("User defined disk (%d %d %d)",
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nb_heads - 1, max_track, last_sect);
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} else {
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bdrv_get_geometry(drv->bs, &nb_sectors); |
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match = -1;
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first_match = -1;
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for (i = 0;; i++) { |
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parse = &fd_formats[i]; |
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if (parse->drive == FDRIVE_DRV_NONE)
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break;
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if (drv->drive == parse->drive ||
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drv->drive == FDRIVE_DRV_NONE) { |
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size = (parse->max_head + 1) * parse->max_track *
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parse->last_sect; |
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if (nb_sectors == size) {
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match = i; |
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break;
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} |
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if (first_match == -1) |
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first_match = i; |
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} |
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} |
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if (match == -1) { |
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if (first_match == -1) |
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match = 1;
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else
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match = first_match; |
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parse = &fd_formats[match]; |
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} |
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nb_heads = parse->max_head + 1;
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max_track = parse->max_track; |
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last_sect = parse->last_sect; |
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drv->drive = parse->drive; |
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FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
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nb_heads, max_track, last_sect, ro ? "ro" : "rw"); |
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} |
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if (nb_heads == 1) { |
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drv->flags &= ~FDISK_DBL_SIDES; |
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} else {
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drv->flags |= FDISK_DBL_SIDES; |
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} |
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drv->max_track = max_track; |
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drv->last_sect = last_sect; |
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drv->ro = ro; |
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} else {
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FLOPPY_DPRINTF("No disk in drive\n");
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drv->last_sect = 0;
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drv->max_track = 0;
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drv->flags &= ~FDISK_DBL_SIDES; |
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} |
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} |
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/********************************************************/
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/* Intel 82078 floppy disk controller emulation */
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static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq); |
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static void fdctrl_reset_fifo (fdctrl_t *fdctrl); |
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static int fdctrl_transfer_handler (void *opaque, int nchan, |
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int dma_pos, int dma_len); |
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static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0); |
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static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
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static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
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static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
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static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value); |
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static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
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static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value); |
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static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
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static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value); |
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static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
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static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value); |
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static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
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enum {
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FD_DIR_WRITE = 0,
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FD_DIR_READ = 1,
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FD_DIR_SCANE = 2,
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FD_DIR_SCANL = 3,
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FD_DIR_SCANH = 4,
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}; |
330 |
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enum {
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FD_STATE_MULTI = 0x01, /* multi track flag */ |
333 |
FD_STATE_FORMAT = 0x02, /* format flag */ |
334 |
FD_STATE_SEEK = 0x04, /* seek flag */ |
335 |
}; |
336 |
|
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enum {
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FD_REG_SRA = 0x00,
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FD_REG_SRB = 0x01,
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FD_REG_DOR = 0x02,
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FD_REG_TDR = 0x03,
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FD_REG_MSR = 0x04,
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FD_REG_DSR = 0x04,
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FD_REG_FIFO = 0x05,
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FD_REG_DIR = 0x07,
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}; |
347 |
|
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enum {
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FD_CMD_READ_TRACK = 0x02,
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FD_CMD_SPECIFY = 0x03,
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FD_CMD_SENSE_DRIVE_STATUS = 0x04,
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FD_CMD_WRITE = 0x05,
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FD_CMD_READ = 0x06,
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FD_CMD_RECALIBRATE = 0x07,
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FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
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FD_CMD_WRITE_DELETED = 0x09,
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FD_CMD_READ_ID = 0x0a,
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358 |
FD_CMD_READ_DELETED = 0x0c,
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359 |
FD_CMD_FORMAT_TRACK = 0x0d,
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360 |
FD_CMD_DUMPREG = 0x0e,
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361 |
FD_CMD_SEEK = 0x0f,
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362 |
FD_CMD_VERSION = 0x10,
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363 |
FD_CMD_SCAN_EQUAL = 0x11,
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364 |
FD_CMD_PERPENDICULAR_MODE = 0x12,
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365 |
FD_CMD_CONFIGURE = 0x13,
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366 |
FD_CMD_LOCK = 0x14,
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367 |
FD_CMD_VERIFY = 0x16,
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368 |
FD_CMD_POWERDOWN_MODE = 0x17,
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369 |
FD_CMD_PART_ID = 0x18,
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370 |
FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
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371 |
FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
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372 |
FD_CMD_SAVE = 0x2c,
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373 |
FD_CMD_OPTION = 0x33,
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374 |
FD_CMD_RESTORE = 0x4c,
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375 |
FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
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376 |
FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
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377 |
FD_CMD_FORMAT_AND_WRITE = 0xcd,
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378 |
FD_CMD_RELATIVE_SEEK_IN = 0xcf,
|
379 |
}; |
380 |
|
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enum {
|
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FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */ |
383 |
FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */ |
384 |
FD_CONFIG_POLL = 0x10, /* Poll enabled */ |
385 |
FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */ |
386 |
FD_CONFIG_EIS = 0x40, /* No implied seeks */ |
387 |
}; |
388 |
|
389 |
enum {
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390 |
FD_SR0_EQPMT = 0x10,
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391 |
FD_SR0_SEEK = 0x20,
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392 |
FD_SR0_ABNTERM = 0x40,
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FD_SR0_INVCMD = 0x80,
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FD_SR0_RDYCHG = 0xc0,
|
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}; |
396 |
|
397 |
enum {
|
398 |
FD_SR1_EC = 0x80, /* End of cylinder */ |
399 |
}; |
400 |
|
401 |
enum {
|
402 |
FD_SR2_SNS = 0x04, /* Scan not satisfied */ |
403 |
FD_SR2_SEH = 0x08, /* Scan equal hit */ |
404 |
}; |
405 |
|
406 |
enum {
|
407 |
FD_SRA_DIR = 0x01,
|
408 |
FD_SRA_nWP = 0x02,
|
409 |
FD_SRA_nINDX = 0x04,
|
410 |
FD_SRA_HDSEL = 0x08,
|
411 |
FD_SRA_nTRK0 = 0x10,
|
412 |
FD_SRA_STEP = 0x20,
|
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FD_SRA_nDRV2 = 0x40,
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FD_SRA_INTPEND = 0x80,
|
415 |
}; |
416 |
|
417 |
enum {
|
418 |
FD_SRB_MTR0 = 0x01,
|
419 |
FD_SRB_MTR1 = 0x02,
|
420 |
FD_SRB_WGATE = 0x04,
|
421 |
FD_SRB_RDATA = 0x08,
|
422 |
FD_SRB_WDATA = 0x10,
|
423 |
FD_SRB_DR0 = 0x20,
|
424 |
}; |
425 |
|
426 |
enum {
|
427 |
#if MAX_FD == 4 |
428 |
FD_DOR_SELMASK = 0x03,
|
429 |
#else
|
430 |
FD_DOR_SELMASK = 0x01,
|
431 |
#endif
|
432 |
FD_DOR_nRESET = 0x04,
|
433 |
FD_DOR_DMAEN = 0x08,
|
434 |
FD_DOR_MOTEN0 = 0x10,
|
435 |
FD_DOR_MOTEN1 = 0x20,
|
436 |
FD_DOR_MOTEN2 = 0x40,
|
437 |
FD_DOR_MOTEN3 = 0x80,
|
438 |
}; |
439 |
|
440 |
enum {
|
441 |
#if MAX_FD == 4 |
442 |
FD_TDR_BOOTSEL = 0x0c,
|
443 |
#else
|
444 |
FD_TDR_BOOTSEL = 0x04,
|
445 |
#endif
|
446 |
}; |
447 |
|
448 |
enum {
|
449 |
FD_DSR_DRATEMASK= 0x03,
|
450 |
FD_DSR_PWRDOWN = 0x40,
|
451 |
FD_DSR_SWRESET = 0x80,
|
452 |
}; |
453 |
|
454 |
enum {
|
455 |
FD_MSR_DRV0BUSY = 0x01,
|
456 |
FD_MSR_DRV1BUSY = 0x02,
|
457 |
FD_MSR_DRV2BUSY = 0x04,
|
458 |
FD_MSR_DRV3BUSY = 0x08,
|
459 |
FD_MSR_CMDBUSY = 0x10,
|
460 |
FD_MSR_NONDMA = 0x20,
|
461 |
FD_MSR_DIO = 0x40,
|
462 |
FD_MSR_RQM = 0x80,
|
463 |
}; |
464 |
|
465 |
enum {
|
466 |
FD_DIR_DSKCHG = 0x80,
|
467 |
}; |
468 |
|
469 |
#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
|
470 |
#define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
|
471 |
#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
|
472 |
|
473 |
struct fdctrl_t {
|
474 |
/* Controller's identification */
|
475 |
uint8_t version; |
476 |
/* HW */
|
477 |
qemu_irq irq; |
478 |
int dma_chann;
|
479 |
/* Controller state */
|
480 |
QEMUTimer *result_timer; |
481 |
uint8_t sra; |
482 |
uint8_t srb; |
483 |
uint8_t dor; |
484 |
uint8_t tdr; |
485 |
uint8_t dsr; |
486 |
uint8_t msr; |
487 |
uint8_t cur_drv; |
488 |
uint8_t status0; |
489 |
uint8_t status1; |
490 |
uint8_t status2; |
491 |
/* Command FIFO */
|
492 |
uint8_t *fifo; |
493 |
uint32_t data_pos; |
494 |
uint32_t data_len; |
495 |
uint8_t data_state; |
496 |
uint8_t data_dir; |
497 |
uint8_t eot; /* last wanted sector */
|
498 |
/* States kept only to be returned back */
|
499 |
/* Timers state */
|
500 |
uint8_t timer0; |
501 |
uint8_t timer1; |
502 |
/* precompensation */
|
503 |
uint8_t precomp_trk; |
504 |
uint8_t config; |
505 |
uint8_t lock; |
506 |
/* Power down config (also with status regB access mode */
|
507 |
uint8_t pwrd; |
508 |
/* Sun4m quirks? */
|
509 |
int sun4m;
|
510 |
/* Floppy drives */
|
511 |
fdrive_t drives[MAX_FD]; |
512 |
int reset_sensei;
|
513 |
}; |
514 |
|
515 |
typedef struct fdctrl_sysbus_t { |
516 |
SysBusDevice busdev; |
517 |
struct fdctrl_t state;
|
518 |
} fdctrl_sysbus_t; |
519 |
|
520 |
typedef struct fdctrl_isabus_t { |
521 |
ISADevice busdev; |
522 |
struct fdctrl_t state;
|
523 |
} fdctrl_isabus_t; |
524 |
|
525 |
static uint32_t fdctrl_read (void *opaque, uint32_t reg) |
526 |
{ |
527 |
fdctrl_t *fdctrl = opaque; |
528 |
uint32_t retval; |
529 |
|
530 |
switch (reg) {
|
531 |
case FD_REG_SRA:
|
532 |
retval = fdctrl_read_statusA(fdctrl); |
533 |
break;
|
534 |
case FD_REG_SRB:
|
535 |
retval = fdctrl_read_statusB(fdctrl); |
536 |
break;
|
537 |
case FD_REG_DOR:
|
538 |
retval = fdctrl_read_dor(fdctrl); |
539 |
break;
|
540 |
case FD_REG_TDR:
|
541 |
retval = fdctrl_read_tape(fdctrl); |
542 |
break;
|
543 |
case FD_REG_MSR:
|
544 |
retval = fdctrl_read_main_status(fdctrl); |
545 |
break;
|
546 |
case FD_REG_FIFO:
|
547 |
retval = fdctrl_read_data(fdctrl); |
548 |
break;
|
549 |
case FD_REG_DIR:
|
550 |
retval = fdctrl_read_dir(fdctrl); |
551 |
break;
|
552 |
default:
|
553 |
retval = (uint32_t)(-1);
|
554 |
break;
|
555 |
} |
556 |
FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval); |
557 |
|
558 |
return retval;
|
559 |
} |
560 |
|
561 |
static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value) |
562 |
{ |
563 |
fdctrl_t *fdctrl = opaque; |
564 |
|
565 |
FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value); |
566 |
|
567 |
switch (reg) {
|
568 |
case FD_REG_DOR:
|
569 |
fdctrl_write_dor(fdctrl, value); |
570 |
break;
|
571 |
case FD_REG_TDR:
|
572 |
fdctrl_write_tape(fdctrl, value); |
573 |
break;
|
574 |
case FD_REG_DSR:
|
575 |
fdctrl_write_rate(fdctrl, value); |
576 |
break;
|
577 |
case FD_REG_FIFO:
|
578 |
fdctrl_write_data(fdctrl, value); |
579 |
break;
|
580 |
default:
|
581 |
break;
|
582 |
} |
583 |
} |
584 |
|
585 |
static uint32_t fdctrl_read_port (void *opaque, uint32_t reg) |
586 |
{ |
587 |
return fdctrl_read(opaque, reg & 7); |
588 |
} |
589 |
|
590 |
static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value) |
591 |
{ |
592 |
fdctrl_write(opaque, reg & 7, value);
|
593 |
} |
594 |
|
595 |
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg) |
596 |
{ |
597 |
return fdctrl_read(opaque, (uint32_t)reg);
|
598 |
} |
599 |
|
600 |
static void fdctrl_write_mem (void *opaque, |
601 |
target_phys_addr_t reg, uint32_t value) |
602 |
{ |
603 |
fdctrl_write(opaque, (uint32_t)reg, value); |
604 |
} |
605 |
|
606 |
static CPUReadMemoryFunc * const fdctrl_mem_read[3] = { |
607 |
fdctrl_read_mem, |
608 |
fdctrl_read_mem, |
609 |
fdctrl_read_mem, |
610 |
}; |
611 |
|
612 |
static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = { |
613 |
fdctrl_write_mem, |
614 |
fdctrl_write_mem, |
615 |
fdctrl_write_mem, |
616 |
}; |
617 |
|
618 |
static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = { |
619 |
fdctrl_read_mem, |
620 |
NULL,
|
621 |
NULL,
|
622 |
}; |
623 |
|
624 |
static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = { |
625 |
fdctrl_write_mem, |
626 |
NULL,
|
627 |
NULL,
|
628 |
}; |
629 |
|
630 |
static void fd_save (QEMUFile *f, fdrive_t *fd) |
631 |
{ |
632 |
qemu_put_8s(f, &fd->head); |
633 |
qemu_put_8s(f, &fd->track); |
634 |
qemu_put_8s(f, &fd->sect); |
635 |
} |
636 |
|
637 |
static void fdc_save (QEMUFile *f, void *opaque) |
638 |
{ |
639 |
fdctrl_t *s = opaque; |
640 |
uint8_t tmp; |
641 |
int i;
|
642 |
uint8_t dor = s->dor | GET_CUR_DRV(s); |
643 |
|
644 |
/* Controller state */
|
645 |
qemu_put_8s(f, &s->sra); |
646 |
qemu_put_8s(f, &s->srb); |
647 |
qemu_put_8s(f, &dor); |
648 |
qemu_put_8s(f, &s->tdr); |
649 |
qemu_put_8s(f, &s->dsr); |
650 |
qemu_put_8s(f, &s->msr); |
651 |
qemu_put_8s(f, &s->status0); |
652 |
qemu_put_8s(f, &s->status1); |
653 |
qemu_put_8s(f, &s->status2); |
654 |
/* Command FIFO */
|
655 |
qemu_put_buffer(f, s->fifo, FD_SECTOR_LEN); |
656 |
qemu_put_be32s(f, &s->data_pos); |
657 |
qemu_put_be32s(f, &s->data_len); |
658 |
qemu_put_8s(f, &s->data_state); |
659 |
qemu_put_8s(f, &s->data_dir); |
660 |
qemu_put_8s(f, &s->eot); |
661 |
/* States kept only to be returned back */
|
662 |
qemu_put_8s(f, &s->timer0); |
663 |
qemu_put_8s(f, &s->timer1); |
664 |
qemu_put_8s(f, &s->precomp_trk); |
665 |
qemu_put_8s(f, &s->config); |
666 |
qemu_put_8s(f, &s->lock); |
667 |
qemu_put_8s(f, &s->pwrd); |
668 |
|
669 |
tmp = MAX_FD; |
670 |
qemu_put_8s(f, &tmp); |
671 |
for (i = 0; i < MAX_FD; i++) |
672 |
fd_save(f, &s->drives[i]); |
673 |
} |
674 |
|
675 |
static int fd_load (QEMUFile *f, fdrive_t *fd) |
676 |
{ |
677 |
qemu_get_8s(f, &fd->head); |
678 |
qemu_get_8s(f, &fd->track); |
679 |
qemu_get_8s(f, &fd->sect); |
680 |
|
681 |
return 0; |
682 |
} |
683 |
|
684 |
static int fdc_load (QEMUFile *f, void *opaque, int version_id) |
685 |
{ |
686 |
fdctrl_t *s = opaque; |
687 |
int i, ret = 0; |
688 |
uint8_t n; |
689 |
|
690 |
if (version_id != 2) |
691 |
return -EINVAL;
|
692 |
|
693 |
/* Controller state */
|
694 |
qemu_get_8s(f, &s->sra); |
695 |
qemu_get_8s(f, &s->srb); |
696 |
qemu_get_8s(f, &s->dor); |
697 |
SET_CUR_DRV(s, s->dor & FD_DOR_SELMASK); |
698 |
s->dor &= ~FD_DOR_SELMASK; |
699 |
qemu_get_8s(f, &s->tdr); |
700 |
qemu_get_8s(f, &s->dsr); |
701 |
qemu_get_8s(f, &s->msr); |
702 |
qemu_get_8s(f, &s->status0); |
703 |
qemu_get_8s(f, &s->status1); |
704 |
qemu_get_8s(f, &s->status2); |
705 |
/* Command FIFO */
|
706 |
qemu_get_buffer(f, s->fifo, FD_SECTOR_LEN); |
707 |
qemu_get_be32s(f, &s->data_pos); |
708 |
qemu_get_be32s(f, &s->data_len); |
709 |
qemu_get_8s(f, &s->data_state); |
710 |
qemu_get_8s(f, &s->data_dir); |
711 |
qemu_get_8s(f, &s->eot); |
712 |
/* States kept only to be returned back */
|
713 |
qemu_get_8s(f, &s->timer0); |
714 |
qemu_get_8s(f, &s->timer1); |
715 |
qemu_get_8s(f, &s->precomp_trk); |
716 |
qemu_get_8s(f, &s->config); |
717 |
qemu_get_8s(f, &s->lock); |
718 |
qemu_get_8s(f, &s->pwrd); |
719 |
qemu_get_8s(f, &n); |
720 |
|
721 |
if (n > MAX_FD)
|
722 |
return -EINVAL;
|
723 |
|
724 |
for (i = 0; i < n; i++) { |
725 |
ret = fd_load(f, &s->drives[i]); |
726 |
if (ret != 0) |
727 |
break;
|
728 |
} |
729 |
|
730 |
return ret;
|
731 |
} |
732 |
|
733 |
static void fdctrl_external_reset(void *opaque) |
734 |
{ |
735 |
fdctrl_t *s = opaque; |
736 |
|
737 |
fdctrl_reset(s, 0);
|
738 |
} |
739 |
|
740 |
static void fdctrl_handle_tc(void *opaque, int irq, int level) |
741 |
{ |
742 |
//fdctrl_t *s = opaque;
|
743 |
|
744 |
if (level) {
|
745 |
// XXX
|
746 |
FLOPPY_DPRINTF("TC pulsed\n");
|
747 |
} |
748 |
} |
749 |
|
750 |
/* XXX: may change if moved to bdrv */
|
751 |
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num) |
752 |
{ |
753 |
return fdctrl->drives[drive_num].drive;
|
754 |
} |
755 |
|
756 |
/* Change IRQ state */
|
757 |
static void fdctrl_reset_irq (fdctrl_t *fdctrl) |
758 |
{ |
759 |
if (!(fdctrl->sra & FD_SRA_INTPEND))
|
760 |
return;
|
761 |
FLOPPY_DPRINTF("Reset interrupt\n");
|
762 |
qemu_set_irq(fdctrl->irq, 0);
|
763 |
fdctrl->sra &= ~FD_SRA_INTPEND; |
764 |
} |
765 |
|
766 |
static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0) |
767 |
{ |
768 |
/* Sparc mutation */
|
769 |
if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
|
770 |
/* XXX: not sure */
|
771 |
fdctrl->msr &= ~FD_MSR_CMDBUSY; |
772 |
fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; |
773 |
fdctrl->status0 = status0; |
774 |
return;
|
775 |
} |
776 |
if (!(fdctrl->sra & FD_SRA_INTPEND)) {
|
777 |
qemu_set_irq(fdctrl->irq, 1);
|
778 |
fdctrl->sra |= FD_SRA_INTPEND; |
779 |
} |
780 |
fdctrl->reset_sensei = 0;
|
781 |
fdctrl->status0 = status0; |
782 |
FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
|
783 |
} |
784 |
|
785 |
/* Reset controller */
|
786 |
static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq) |
787 |
{ |
788 |
int i;
|
789 |
|
790 |
FLOPPY_DPRINTF("reset controller\n");
|
791 |
fdctrl_reset_irq(fdctrl); |
792 |
/* Initialise controller */
|
793 |
fdctrl->sra = 0;
|
794 |
fdctrl->srb = 0xc0;
|
795 |
if (!fdctrl->drives[1].bs) |
796 |
fdctrl->sra |= FD_SRA_nDRV2; |
797 |
fdctrl->cur_drv = 0;
|
798 |
fdctrl->dor = FD_DOR_nRESET; |
799 |
fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0; |
800 |
fdctrl->msr = FD_MSR_RQM; |
801 |
/* FIFO state */
|
802 |
fdctrl->data_pos = 0;
|
803 |
fdctrl->data_len = 0;
|
804 |
fdctrl->data_state = 0;
|
805 |
fdctrl->data_dir = FD_DIR_WRITE; |
806 |
for (i = 0; i < MAX_FD; i++) |
807 |
fd_recalibrate(&fdctrl->drives[i]); |
808 |
fdctrl_reset_fifo(fdctrl); |
809 |
if (do_irq) {
|
810 |
fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG); |
811 |
fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT; |
812 |
} |
813 |
} |
814 |
|
815 |
static inline fdrive_t *drv0 (fdctrl_t *fdctrl) |
816 |
{ |
817 |
return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2]; |
818 |
} |
819 |
|
820 |
static inline fdrive_t *drv1 (fdctrl_t *fdctrl) |
821 |
{ |
822 |
if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2)) |
823 |
return &fdctrl->drives[1]; |
824 |
else
|
825 |
return &fdctrl->drives[0]; |
826 |
} |
827 |
|
828 |
#if MAX_FD == 4 |
829 |
static inline fdrive_t *drv2 (fdctrl_t *fdctrl) |
830 |
{ |
831 |
if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2)) |
832 |
return &fdctrl->drives[2]; |
833 |
else
|
834 |
return &fdctrl->drives[1]; |
835 |
} |
836 |
|
837 |
static inline fdrive_t *drv3 (fdctrl_t *fdctrl) |
838 |
{ |
839 |
if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2)) |
840 |
return &fdctrl->drives[3]; |
841 |
else
|
842 |
return &fdctrl->drives[2]; |
843 |
} |
844 |
#endif
|
845 |
|
846 |
static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
|
847 |
{ |
848 |
switch (fdctrl->cur_drv) {
|
849 |
case 0: return drv0(fdctrl); |
850 |
case 1: return drv1(fdctrl); |
851 |
#if MAX_FD == 4 |
852 |
case 2: return drv2(fdctrl); |
853 |
case 3: return drv3(fdctrl); |
854 |
#endif
|
855 |
default: return NULL; |
856 |
} |
857 |
} |
858 |
|
859 |
/* Status A register : 0x00 (read-only) */
|
860 |
static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
|
861 |
{ |
862 |
uint32_t retval = fdctrl->sra; |
863 |
|
864 |
FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
|
865 |
|
866 |
return retval;
|
867 |
} |
868 |
|
869 |
/* Status B register : 0x01 (read-only) */
|
870 |
static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
|
871 |
{ |
872 |
uint32_t retval = fdctrl->srb; |
873 |
|
874 |
FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
|
875 |
|
876 |
return retval;
|
877 |
} |
878 |
|
879 |
/* Digital output register : 0x02 */
|
880 |
static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
|
881 |
{ |
882 |
uint32_t retval = fdctrl->dor; |
883 |
|
884 |
/* Selected drive */
|
885 |
retval |= fdctrl->cur_drv; |
886 |
FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
|
887 |
|
888 |
return retval;
|
889 |
} |
890 |
|
891 |
static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value) |
892 |
{ |
893 |
FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
|
894 |
|
895 |
/* Motors */
|
896 |
if (value & FD_DOR_MOTEN0)
|
897 |
fdctrl->srb |= FD_SRB_MTR0; |
898 |
else
|
899 |
fdctrl->srb &= ~FD_SRB_MTR0; |
900 |
if (value & FD_DOR_MOTEN1)
|
901 |
fdctrl->srb |= FD_SRB_MTR1; |
902 |
else
|
903 |
fdctrl->srb &= ~FD_SRB_MTR1; |
904 |
|
905 |
/* Drive */
|
906 |
if (value & 1) |
907 |
fdctrl->srb |= FD_SRB_DR0; |
908 |
else
|
909 |
fdctrl->srb &= ~FD_SRB_DR0; |
910 |
|
911 |
/* Reset */
|
912 |
if (!(value & FD_DOR_nRESET)) {
|
913 |
if (fdctrl->dor & FD_DOR_nRESET) {
|
914 |
FLOPPY_DPRINTF("controller enter RESET state\n");
|
915 |
} |
916 |
} else {
|
917 |
if (!(fdctrl->dor & FD_DOR_nRESET)) {
|
918 |
FLOPPY_DPRINTF("controller out of RESET state\n");
|
919 |
fdctrl_reset(fdctrl, 1);
|
920 |
fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
921 |
} |
922 |
} |
923 |
/* Selected drive */
|
924 |
fdctrl->cur_drv = value & FD_DOR_SELMASK; |
925 |
|
926 |
fdctrl->dor = value; |
927 |
} |
928 |
|
929 |
/* Tape drive register : 0x03 */
|
930 |
static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
|
931 |
{ |
932 |
uint32_t retval = fdctrl->tdr; |
933 |
|
934 |
FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
|
935 |
|
936 |
return retval;
|
937 |
} |
938 |
|
939 |
static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value) |
940 |
{ |
941 |
/* Reset mode */
|
942 |
if (!(fdctrl->dor & FD_DOR_nRESET)) {
|
943 |
FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
|
944 |
return;
|
945 |
} |
946 |
FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
|
947 |
/* Disk boot selection indicator */
|
948 |
fdctrl->tdr = value & FD_TDR_BOOTSEL; |
949 |
/* Tape indicators: never allow */
|
950 |
} |
951 |
|
952 |
/* Main status register : 0x04 (read) */
|
953 |
static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
|
954 |
{ |
955 |
uint32_t retval = fdctrl->msr; |
956 |
|
957 |
fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
958 |
fdctrl->dor |= FD_DOR_nRESET; |
959 |
|
960 |
FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
|
961 |
|
962 |
return retval;
|
963 |
} |
964 |
|
965 |
/* Data select rate register : 0x04 (write) */
|
966 |
static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value) |
967 |
{ |
968 |
/* Reset mode */
|
969 |
if (!(fdctrl->dor & FD_DOR_nRESET)) {
|
970 |
FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
|
971 |
return;
|
972 |
} |
973 |
FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
|
974 |
/* Reset: autoclear */
|
975 |
if (value & FD_DSR_SWRESET) {
|
976 |
fdctrl->dor &= ~FD_DOR_nRESET; |
977 |
fdctrl_reset(fdctrl, 1);
|
978 |
fdctrl->dor |= FD_DOR_nRESET; |
979 |
} |
980 |
if (value & FD_DSR_PWRDOWN) {
|
981 |
fdctrl_reset(fdctrl, 1);
|
982 |
} |
983 |
fdctrl->dsr = value; |
984 |
} |
985 |
|
986 |
static int fdctrl_media_changed(fdrive_t *drv) |
987 |
{ |
988 |
int ret;
|
989 |
|
990 |
if (!drv->bs)
|
991 |
return 0; |
992 |
ret = bdrv_media_changed(drv->bs); |
993 |
if (ret) {
|
994 |
fd_revalidate(drv); |
995 |
} |
996 |
return ret;
|
997 |
} |
998 |
|
999 |
/* Digital input register : 0x07 (read-only) */
|
1000 |
static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
|
1001 |
{ |
1002 |
uint32_t retval = 0;
|
1003 |
|
1004 |
if (fdctrl_media_changed(drv0(fdctrl))
|
1005 |
|| fdctrl_media_changed(drv1(fdctrl)) |
1006 |
#if MAX_FD == 4 |
1007 |
|| fdctrl_media_changed(drv2(fdctrl)) |
1008 |
|| fdctrl_media_changed(drv3(fdctrl)) |
1009 |
#endif
|
1010 |
) |
1011 |
retval |= FD_DIR_DSKCHG; |
1012 |
if (retval != 0) |
1013 |
FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
|
1014 |
|
1015 |
return retval;
|
1016 |
} |
1017 |
|
1018 |
/* FIFO state control */
|
1019 |
static void fdctrl_reset_fifo (fdctrl_t *fdctrl) |
1020 |
{ |
1021 |
fdctrl->data_dir = FD_DIR_WRITE; |
1022 |
fdctrl->data_pos = 0;
|
1023 |
fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO); |
1024 |
} |
1025 |
|
1026 |
/* Set FIFO status for the host to read */
|
1027 |
static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq) |
1028 |
{ |
1029 |
fdctrl->data_dir = FD_DIR_READ; |
1030 |
fdctrl->data_len = fifo_len; |
1031 |
fdctrl->data_pos = 0;
|
1032 |
fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO; |
1033 |
if (do_irq)
|
1034 |
fdctrl_raise_irq(fdctrl, 0x00);
|
1035 |
} |
1036 |
|
1037 |
/* Set an error: unimplemented/unknown command */
|
1038 |
static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction) |
1039 |
{ |
1040 |
FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]); |
1041 |
fdctrl->fifo[0] = FD_SR0_INVCMD;
|
1042 |
fdctrl_set_fifo(fdctrl, 1, 0); |
1043 |
} |
1044 |
|
1045 |
/* Seek to next sector */
|
1046 |
static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv) |
1047 |
{ |
1048 |
FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
|
1049 |
cur_drv->head, cur_drv->track, cur_drv->sect, |
1050 |
fd_sector(cur_drv)); |
1051 |
/* XXX: cur_drv->sect >= cur_drv->last_sect should be an
|
1052 |
error in fact */
|
1053 |
if (cur_drv->sect >= cur_drv->last_sect ||
|
1054 |
cur_drv->sect == fdctrl->eot) { |
1055 |
cur_drv->sect = 1;
|
1056 |
if (FD_MULTI_TRACK(fdctrl->data_state)) {
|
1057 |
if (cur_drv->head == 0 && |
1058 |
(cur_drv->flags & FDISK_DBL_SIDES) != 0) {
|
1059 |
cur_drv->head = 1;
|
1060 |
} else {
|
1061 |
cur_drv->head = 0;
|
1062 |
cur_drv->track++; |
1063 |
if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) |
1064 |
return 0; |
1065 |
} |
1066 |
} else {
|
1067 |
cur_drv->track++; |
1068 |
return 0; |
1069 |
} |
1070 |
FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
|
1071 |
cur_drv->head, cur_drv->track, |
1072 |
cur_drv->sect, fd_sector(cur_drv)); |
1073 |
} else {
|
1074 |
cur_drv->sect++; |
1075 |
} |
1076 |
return 1; |
1077 |
} |
1078 |
|
1079 |
/* Callback for transfer end (stop or abort) */
|
1080 |
static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0, |
1081 |
uint8_t status1, uint8_t status2) |
1082 |
{ |
1083 |
fdrive_t *cur_drv; |
1084 |
|
1085 |
cur_drv = get_cur_drv(fdctrl); |
1086 |
FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
|
1087 |
status0, status1, status2, |
1088 |
status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
|
1089 |
fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl); |
1090 |
fdctrl->fifo[1] = status1;
|
1091 |
fdctrl->fifo[2] = status2;
|
1092 |
fdctrl->fifo[3] = cur_drv->track;
|
1093 |
fdctrl->fifo[4] = cur_drv->head;
|
1094 |
fdctrl->fifo[5] = cur_drv->sect;
|
1095 |
fdctrl->fifo[6] = FD_SECTOR_SC;
|
1096 |
fdctrl->data_dir = FD_DIR_READ; |
1097 |
if (!(fdctrl->msr & FD_MSR_NONDMA)) {
|
1098 |
DMA_release_DREQ(fdctrl->dma_chann); |
1099 |
} |
1100 |
fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; |
1101 |
fdctrl->msr &= ~FD_MSR_NONDMA; |
1102 |
fdctrl_set_fifo(fdctrl, 7, 1); |
1103 |
} |
1104 |
|
1105 |
/* Prepare a data transfer (either DMA or FIFO) */
|
1106 |
static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction) |
1107 |
{ |
1108 |
fdrive_t *cur_drv; |
1109 |
uint8_t kh, kt, ks; |
1110 |
int did_seek = 0; |
1111 |
|
1112 |
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1113 |
cur_drv = get_cur_drv(fdctrl); |
1114 |
kt = fdctrl->fifo[2];
|
1115 |
kh = fdctrl->fifo[3];
|
1116 |
ks = fdctrl->fifo[4];
|
1117 |
FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
|
1118 |
GET_CUR_DRV(fdctrl), kh, kt, ks, |
1119 |
_fd_sector(kh, kt, ks, cur_drv->last_sect)); |
1120 |
switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
|
1121 |
case 2: |
1122 |
/* sect too big */
|
1123 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
1124 |
fdctrl->fifo[3] = kt;
|
1125 |
fdctrl->fifo[4] = kh;
|
1126 |
fdctrl->fifo[5] = ks;
|
1127 |
return;
|
1128 |
case 3: |
1129 |
/* track too big */
|
1130 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
|
1131 |
fdctrl->fifo[3] = kt;
|
1132 |
fdctrl->fifo[4] = kh;
|
1133 |
fdctrl->fifo[5] = ks;
|
1134 |
return;
|
1135 |
case 4: |
1136 |
/* No seek enabled */
|
1137 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
1138 |
fdctrl->fifo[3] = kt;
|
1139 |
fdctrl->fifo[4] = kh;
|
1140 |
fdctrl->fifo[5] = ks;
|
1141 |
return;
|
1142 |
case 1: |
1143 |
did_seek = 1;
|
1144 |
break;
|
1145 |
default:
|
1146 |
break;
|
1147 |
} |
1148 |
|
1149 |
/* Set the FIFO state */
|
1150 |
fdctrl->data_dir = direction; |
1151 |
fdctrl->data_pos = 0;
|
1152 |
fdctrl->msr |= FD_MSR_CMDBUSY; |
1153 |
if (fdctrl->fifo[0] & 0x80) |
1154 |
fdctrl->data_state |= FD_STATE_MULTI; |
1155 |
else
|
1156 |
fdctrl->data_state &= ~FD_STATE_MULTI; |
1157 |
if (did_seek)
|
1158 |
fdctrl->data_state |= FD_STATE_SEEK; |
1159 |
else
|
1160 |
fdctrl->data_state &= ~FD_STATE_SEEK; |
1161 |
if (fdctrl->fifo[5] == 00) { |
1162 |
fdctrl->data_len = fdctrl->fifo[8];
|
1163 |
} else {
|
1164 |
int tmp;
|
1165 |
fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]); |
1166 |
tmp = (fdctrl->fifo[6] - ks + 1); |
1167 |
if (fdctrl->fifo[0] & 0x80) |
1168 |
tmp += fdctrl->fifo[6];
|
1169 |
fdctrl->data_len *= tmp; |
1170 |
} |
1171 |
fdctrl->eot = fdctrl->fifo[6];
|
1172 |
if (fdctrl->dor & FD_DOR_DMAEN) {
|
1173 |
int dma_mode;
|
1174 |
/* DMA transfer are enabled. Check if DMA channel is well programmed */
|
1175 |
dma_mode = DMA_get_channel_mode(fdctrl->dma_chann); |
1176 |
dma_mode = (dma_mode >> 2) & 3; |
1177 |
FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
|
1178 |
dma_mode, direction, |
1179 |
(128 << fdctrl->fifo[5]) * |
1180 |
(cur_drv->last_sect - ks + 1), fdctrl->data_len);
|
1181 |
if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
|
1182 |
direction == FD_DIR_SCANH) && dma_mode == 0) ||
|
1183 |
(direction == FD_DIR_WRITE && dma_mode == 2) ||
|
1184 |
(direction == FD_DIR_READ && dma_mode == 1)) {
|
1185 |
/* No access is allowed until DMA transfer has completed */
|
1186 |
fdctrl->msr &= ~FD_MSR_RQM; |
1187 |
/* Now, we just have to wait for the DMA controller to
|
1188 |
* recall us...
|
1189 |
*/
|
1190 |
DMA_hold_DREQ(fdctrl->dma_chann); |
1191 |
DMA_schedule(fdctrl->dma_chann); |
1192 |
return;
|
1193 |
} else {
|
1194 |
FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
|
1195 |
} |
1196 |
} |
1197 |
FLOPPY_DPRINTF("start non-DMA transfer\n");
|
1198 |
fdctrl->msr |= FD_MSR_NONDMA; |
1199 |
if (direction != FD_DIR_WRITE)
|
1200 |
fdctrl->msr |= FD_MSR_DIO; |
1201 |
/* IO based transfer: calculate len */
|
1202 |
fdctrl_raise_irq(fdctrl, 0x00);
|
1203 |
|
1204 |
return;
|
1205 |
} |
1206 |
|
1207 |
/* Prepare a transfer of deleted data */
|
1208 |
static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction) |
1209 |
{ |
1210 |
FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
|
1211 |
|
1212 |
/* We don't handle deleted data,
|
1213 |
* so we don't return *ANYTHING*
|
1214 |
*/
|
1215 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
1216 |
} |
1217 |
|
1218 |
/* handlers for DMA transfers */
|
1219 |
static int fdctrl_transfer_handler (void *opaque, int nchan, |
1220 |
int dma_pos, int dma_len) |
1221 |
{ |
1222 |
fdctrl_t *fdctrl; |
1223 |
fdrive_t *cur_drv; |
1224 |
int len, start_pos, rel_pos;
|
1225 |
uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00; |
1226 |
|
1227 |
fdctrl = opaque; |
1228 |
if (fdctrl->msr & FD_MSR_RQM) {
|
1229 |
FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
|
1230 |
return 0; |
1231 |
} |
1232 |
cur_drv = get_cur_drv(fdctrl); |
1233 |
if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
|
1234 |
fdctrl->data_dir == FD_DIR_SCANH) |
1235 |
status2 = FD_SR2_SNS; |
1236 |
if (dma_len > fdctrl->data_len)
|
1237 |
dma_len = fdctrl->data_len; |
1238 |
if (cur_drv->bs == NULL) { |
1239 |
if (fdctrl->data_dir == FD_DIR_WRITE)
|
1240 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
1241 |
else
|
1242 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
1243 |
len = 0;
|
1244 |
goto transfer_error;
|
1245 |
} |
1246 |
rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; |
1247 |
for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
|
1248 |
len = dma_len - fdctrl->data_pos; |
1249 |
if (len + rel_pos > FD_SECTOR_LEN)
|
1250 |
len = FD_SECTOR_LEN - rel_pos; |
1251 |
FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
|
1252 |
"(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
|
1253 |
fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head, |
1254 |
cur_drv->track, cur_drv->sect, fd_sector(cur_drv), |
1255 |
fd_sector(cur_drv) * FD_SECTOR_LEN); |
1256 |
if (fdctrl->data_dir != FD_DIR_WRITE ||
|
1257 |
len < FD_SECTOR_LEN || rel_pos != 0) {
|
1258 |
/* READ & SCAN commands and realign to a sector for WRITE */
|
1259 |
if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
|
1260 |
fdctrl->fifo, 1) < 0) { |
1261 |
FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
|
1262 |
fd_sector(cur_drv)); |
1263 |
/* Sure, image size is too small... */
|
1264 |
memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
|
1265 |
} |
1266 |
} |
1267 |
switch (fdctrl->data_dir) {
|
1268 |
case FD_DIR_READ:
|
1269 |
/* READ commands */
|
1270 |
DMA_write_memory (nchan, fdctrl->fifo + rel_pos, |
1271 |
fdctrl->data_pos, len); |
1272 |
break;
|
1273 |
case FD_DIR_WRITE:
|
1274 |
/* WRITE commands */
|
1275 |
DMA_read_memory (nchan, fdctrl->fifo + rel_pos, |
1276 |
fdctrl->data_pos, len); |
1277 |
if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
|
1278 |
fdctrl->fifo, 1) < 0) { |
1279 |
FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
|
1280 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
1281 |
goto transfer_error;
|
1282 |
} |
1283 |
break;
|
1284 |
default:
|
1285 |
/* SCAN commands */
|
1286 |
{ |
1287 |
uint8_t tmpbuf[FD_SECTOR_LEN]; |
1288 |
int ret;
|
1289 |
DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len); |
1290 |
ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len); |
1291 |
if (ret == 0) { |
1292 |
status2 = FD_SR2_SEH; |
1293 |
goto end_transfer;
|
1294 |
} |
1295 |
if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) || |
1296 |
(ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
|
1297 |
status2 = 0x00;
|
1298 |
goto end_transfer;
|
1299 |
} |
1300 |
} |
1301 |
break;
|
1302 |
} |
1303 |
fdctrl->data_pos += len; |
1304 |
rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; |
1305 |
if (rel_pos == 0) { |
1306 |
/* Seek to next sector */
|
1307 |
if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
|
1308 |
break;
|
1309 |
} |
1310 |
} |
1311 |
end_transfer:
|
1312 |
len = fdctrl->data_pos - start_pos; |
1313 |
FLOPPY_DPRINTF("end transfer %d %d %d\n",
|
1314 |
fdctrl->data_pos, len, fdctrl->data_len); |
1315 |
if (fdctrl->data_dir == FD_DIR_SCANE ||
|
1316 |
fdctrl->data_dir == FD_DIR_SCANL || |
1317 |
fdctrl->data_dir == FD_DIR_SCANH) |
1318 |
status2 = FD_SR2_SEH; |
1319 |
if (FD_DID_SEEK(fdctrl->data_state))
|
1320 |
status0 |= FD_SR0_SEEK; |
1321 |
fdctrl->data_len -= len; |
1322 |
fdctrl_stop_transfer(fdctrl, status0, status1, status2); |
1323 |
transfer_error:
|
1324 |
|
1325 |
return len;
|
1326 |
} |
1327 |
|
1328 |
/* Data register : 0x05 */
|
1329 |
static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
|
1330 |
{ |
1331 |
fdrive_t *cur_drv; |
1332 |
uint32_t retval = 0;
|
1333 |
int pos;
|
1334 |
|
1335 |
cur_drv = get_cur_drv(fdctrl); |
1336 |
fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
1337 |
if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
|
1338 |
FLOPPY_ERROR("controller not ready for reading\n");
|
1339 |
return 0; |
1340 |
} |
1341 |
pos = fdctrl->data_pos; |
1342 |
if (fdctrl->msr & FD_MSR_NONDMA) {
|
1343 |
pos %= FD_SECTOR_LEN; |
1344 |
if (pos == 0) { |
1345 |
if (fdctrl->data_pos != 0) |
1346 |
if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
|
1347 |
FLOPPY_DPRINTF("error seeking to next sector %d\n",
|
1348 |
fd_sector(cur_drv)); |
1349 |
return 0; |
1350 |
} |
1351 |
if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { |
1352 |
FLOPPY_DPRINTF("error getting sector %d\n",
|
1353 |
fd_sector(cur_drv)); |
1354 |
/* Sure, image size is too small... */
|
1355 |
memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
|
1356 |
} |
1357 |
} |
1358 |
} |
1359 |
retval = fdctrl->fifo[pos]; |
1360 |
if (++fdctrl->data_pos == fdctrl->data_len) {
|
1361 |
fdctrl->data_pos = 0;
|
1362 |
/* Switch from transfer mode to status mode
|
1363 |
* then from status mode to command mode
|
1364 |
*/
|
1365 |
if (fdctrl->msr & FD_MSR_NONDMA) {
|
1366 |
fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00); |
1367 |
} else {
|
1368 |
fdctrl_reset_fifo(fdctrl); |
1369 |
fdctrl_reset_irq(fdctrl); |
1370 |
} |
1371 |
} |
1372 |
FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
|
1373 |
|
1374 |
return retval;
|
1375 |
} |
1376 |
|
1377 |
static void fdctrl_format_sector (fdctrl_t *fdctrl) |
1378 |
{ |
1379 |
fdrive_t *cur_drv; |
1380 |
uint8_t kh, kt, ks; |
1381 |
|
1382 |
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1383 |
cur_drv = get_cur_drv(fdctrl); |
1384 |
kt = fdctrl->fifo[6];
|
1385 |
kh = fdctrl->fifo[7];
|
1386 |
ks = fdctrl->fifo[8];
|
1387 |
FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
|
1388 |
GET_CUR_DRV(fdctrl), kh, kt, ks, |
1389 |
_fd_sector(kh, kt, ks, cur_drv->last_sect)); |
1390 |
switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
|
1391 |
case 2: |
1392 |
/* sect too big */
|
1393 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
1394 |
fdctrl->fifo[3] = kt;
|
1395 |
fdctrl->fifo[4] = kh;
|
1396 |
fdctrl->fifo[5] = ks;
|
1397 |
return;
|
1398 |
case 3: |
1399 |
/* track too big */
|
1400 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
|
1401 |
fdctrl->fifo[3] = kt;
|
1402 |
fdctrl->fifo[4] = kh;
|
1403 |
fdctrl->fifo[5] = ks;
|
1404 |
return;
|
1405 |
case 4: |
1406 |
/* No seek enabled */
|
1407 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
1408 |
fdctrl->fifo[3] = kt;
|
1409 |
fdctrl->fifo[4] = kh;
|
1410 |
fdctrl->fifo[5] = ks;
|
1411 |
return;
|
1412 |
case 1: |
1413 |
fdctrl->data_state |= FD_STATE_SEEK; |
1414 |
break;
|
1415 |
default:
|
1416 |
break;
|
1417 |
} |
1418 |
memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
|
1419 |
if (cur_drv->bs == NULL || |
1420 |
bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { |
1421 |
FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
|
1422 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
1423 |
} else {
|
1424 |
if (cur_drv->sect == cur_drv->last_sect) {
|
1425 |
fdctrl->data_state &= ~FD_STATE_FORMAT; |
1426 |
/* Last sector done */
|
1427 |
if (FD_DID_SEEK(fdctrl->data_state))
|
1428 |
fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00); |
1429 |
else
|
1430 |
fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); |
1431 |
} else {
|
1432 |
/* More to do */
|
1433 |
fdctrl->data_pos = 0;
|
1434 |
fdctrl->data_len = 4;
|
1435 |
} |
1436 |
} |
1437 |
} |
1438 |
|
1439 |
static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction) |
1440 |
{ |
1441 |
fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0; |
1442 |
fdctrl->fifo[0] = fdctrl->lock << 4; |
1443 |
fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
|
1444 |
} |
1445 |
|
1446 |
static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction) |
1447 |
{ |
1448 |
fdrive_t *cur_drv = get_cur_drv(fdctrl); |
1449 |
|
1450 |
/* Drives position */
|
1451 |
fdctrl->fifo[0] = drv0(fdctrl)->track;
|
1452 |
fdctrl->fifo[1] = drv1(fdctrl)->track;
|
1453 |
#if MAX_FD == 4 |
1454 |
fdctrl->fifo[2] = drv2(fdctrl)->track;
|
1455 |
fdctrl->fifo[3] = drv3(fdctrl)->track;
|
1456 |
#else
|
1457 |
fdctrl->fifo[2] = 0; |
1458 |
fdctrl->fifo[3] = 0; |
1459 |
#endif
|
1460 |
/* timers */
|
1461 |
fdctrl->fifo[4] = fdctrl->timer0;
|
1462 |
fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0); |
1463 |
fdctrl->fifo[6] = cur_drv->last_sect;
|
1464 |
fdctrl->fifo[7] = (fdctrl->lock << 7) | |
1465 |
(cur_drv->perpendicular << 2);
|
1466 |
fdctrl->fifo[8] = fdctrl->config;
|
1467 |
fdctrl->fifo[9] = fdctrl->precomp_trk;
|
1468 |
fdctrl_set_fifo(fdctrl, 10, 0); |
1469 |
} |
1470 |
|
1471 |
static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction) |
1472 |
{ |
1473 |
/* Controller's version */
|
1474 |
fdctrl->fifo[0] = fdctrl->version;
|
1475 |
fdctrl_set_fifo(fdctrl, 1, 1); |
1476 |
} |
1477 |
|
1478 |
static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction) |
1479 |
{ |
1480 |
fdctrl->fifo[0] = 0x41; /* Stepping 1 */ |
1481 |
fdctrl_set_fifo(fdctrl, 1, 0); |
1482 |
} |
1483 |
|
1484 |
static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction) |
1485 |
{ |
1486 |
fdrive_t *cur_drv = get_cur_drv(fdctrl); |
1487 |
|
1488 |
/* Drives position */
|
1489 |
drv0(fdctrl)->track = fdctrl->fifo[3];
|
1490 |
drv1(fdctrl)->track = fdctrl->fifo[4];
|
1491 |
#if MAX_FD == 4 |
1492 |
drv2(fdctrl)->track = fdctrl->fifo[5];
|
1493 |
drv3(fdctrl)->track = fdctrl->fifo[6];
|
1494 |
#endif
|
1495 |
/* timers */
|
1496 |
fdctrl->timer0 = fdctrl->fifo[7];
|
1497 |
fdctrl->timer1 = fdctrl->fifo[8];
|
1498 |
cur_drv->last_sect = fdctrl->fifo[9];
|
1499 |
fdctrl->lock = fdctrl->fifo[10] >> 7; |
1500 |
cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF; |
1501 |
fdctrl->config = fdctrl->fifo[11];
|
1502 |
fdctrl->precomp_trk = fdctrl->fifo[12];
|
1503 |
fdctrl->pwrd = fdctrl->fifo[13];
|
1504 |
fdctrl_reset_fifo(fdctrl); |
1505 |
} |
1506 |
|
1507 |
static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction) |
1508 |
{ |
1509 |
fdrive_t *cur_drv = get_cur_drv(fdctrl); |
1510 |
|
1511 |
fdctrl->fifo[0] = 0; |
1512 |
fdctrl->fifo[1] = 0; |
1513 |
/* Drives position */
|
1514 |
fdctrl->fifo[2] = drv0(fdctrl)->track;
|
1515 |
fdctrl->fifo[3] = drv1(fdctrl)->track;
|
1516 |
#if MAX_FD == 4 |
1517 |
fdctrl->fifo[4] = drv2(fdctrl)->track;
|
1518 |
fdctrl->fifo[5] = drv3(fdctrl)->track;
|
1519 |
#else
|
1520 |
fdctrl->fifo[4] = 0; |
1521 |
fdctrl->fifo[5] = 0; |
1522 |
#endif
|
1523 |
/* timers */
|
1524 |
fdctrl->fifo[6] = fdctrl->timer0;
|
1525 |
fdctrl->fifo[7] = fdctrl->timer1;
|
1526 |
fdctrl->fifo[8] = cur_drv->last_sect;
|
1527 |
fdctrl->fifo[9] = (fdctrl->lock << 7) | |
1528 |
(cur_drv->perpendicular << 2);
|
1529 |
fdctrl->fifo[10] = fdctrl->config;
|
1530 |
fdctrl->fifo[11] = fdctrl->precomp_trk;
|
1531 |
fdctrl->fifo[12] = fdctrl->pwrd;
|
1532 |
fdctrl->fifo[13] = 0; |
1533 |
fdctrl->fifo[14] = 0; |
1534 |
fdctrl_set_fifo(fdctrl, 15, 1); |
1535 |
} |
1536 |
|
1537 |
static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction) |
1538 |
{ |
1539 |
fdrive_t *cur_drv = get_cur_drv(fdctrl); |
1540 |
|
1541 |
/* XXX: should set main status register to busy */
|
1542 |
cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; |
1543 |
qemu_mod_timer(fdctrl->result_timer, |
1544 |
qemu_get_clock(vm_clock) + (ticks_per_sec / 50));
|
1545 |
} |
1546 |
|
1547 |
static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction) |
1548 |
{ |
1549 |
fdrive_t *cur_drv; |
1550 |
|
1551 |
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1552 |
cur_drv = get_cur_drv(fdctrl); |
1553 |
fdctrl->data_state |= FD_STATE_FORMAT; |
1554 |
if (fdctrl->fifo[0] & 0x80) |
1555 |
fdctrl->data_state |= FD_STATE_MULTI; |
1556 |
else
|
1557 |
fdctrl->data_state &= ~FD_STATE_MULTI; |
1558 |
fdctrl->data_state &= ~FD_STATE_SEEK; |
1559 |
cur_drv->bps = |
1560 |
fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2]; |
1561 |
#if 0
|
1562 |
cur_drv->last_sect =
|
1563 |
cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
|
1564 |
fdctrl->fifo[3] / 2;
|
1565 |
#else
|
1566 |
cur_drv->last_sect = fdctrl->fifo[3];
|
1567 |
#endif
|
1568 |
/* TODO: implement format using DMA expected by the Bochs BIOS
|
1569 |
* and Linux fdformat (read 3 bytes per sector via DMA and fill
|
1570 |
* the sector with the specified fill byte
|
1571 |
*/
|
1572 |
fdctrl->data_state &= ~FD_STATE_FORMAT; |
1573 |
fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); |
1574 |
} |
1575 |
|
1576 |
static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction) |
1577 |
{ |
1578 |
fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF; |
1579 |
fdctrl->timer1 = fdctrl->fifo[2] >> 1; |
1580 |
if (fdctrl->fifo[2] & 1) |
1581 |
fdctrl->dor &= ~FD_DOR_DMAEN; |
1582 |
else
|
1583 |
fdctrl->dor |= FD_DOR_DMAEN; |
1584 |
/* No result back */
|
1585 |
fdctrl_reset_fifo(fdctrl); |
1586 |
} |
1587 |
|
1588 |
static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction) |
1589 |
{ |
1590 |
fdrive_t *cur_drv; |
1591 |
|
1592 |
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1593 |
cur_drv = get_cur_drv(fdctrl); |
1594 |
cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; |
1595 |
/* 1 Byte status back */
|
1596 |
fdctrl->fifo[0] = (cur_drv->ro << 6) | |
1597 |
(cur_drv->track == 0 ? 0x10 : 0x00) | |
1598 |
(cur_drv->head << 2) |
|
1599 |
GET_CUR_DRV(fdctrl) | |
1600 |
0x28;
|
1601 |
fdctrl_set_fifo(fdctrl, 1, 0); |
1602 |
} |
1603 |
|
1604 |
static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction) |
1605 |
{ |
1606 |
fdrive_t *cur_drv; |
1607 |
|
1608 |
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1609 |
cur_drv = get_cur_drv(fdctrl); |
1610 |
fd_recalibrate(cur_drv); |
1611 |
fdctrl_reset_fifo(fdctrl); |
1612 |
/* Raise Interrupt */
|
1613 |
fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); |
1614 |
} |
1615 |
|
1616 |
static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction) |
1617 |
{ |
1618 |
fdrive_t *cur_drv = get_cur_drv(fdctrl); |
1619 |
|
1620 |
if(fdctrl->reset_sensei > 0) { |
1621 |
fdctrl->fifo[0] =
|
1622 |
FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei; |
1623 |
fdctrl->reset_sensei--; |
1624 |
} else {
|
1625 |
/* XXX: status0 handling is broken for read/write
|
1626 |
commands, so we do this hack. It should be suppressed
|
1627 |
ASAP */
|
1628 |
fdctrl->fifo[0] =
|
1629 |
FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
|
1630 |
} |
1631 |
|
1632 |
fdctrl->fifo[1] = cur_drv->track;
|
1633 |
fdctrl_set_fifo(fdctrl, 2, 0); |
1634 |
fdctrl_reset_irq(fdctrl); |
1635 |
fdctrl->status0 = FD_SR0_RDYCHG; |
1636 |
} |
1637 |
|
1638 |
static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction) |
1639 |
{ |
1640 |
fdrive_t *cur_drv; |
1641 |
|
1642 |
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1643 |
cur_drv = get_cur_drv(fdctrl); |
1644 |
fdctrl_reset_fifo(fdctrl); |
1645 |
if (fdctrl->fifo[2] > cur_drv->max_track) { |
1646 |
fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK); |
1647 |
} else {
|
1648 |
cur_drv->track = fdctrl->fifo[2];
|
1649 |
/* Raise Interrupt */
|
1650 |
fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); |
1651 |
} |
1652 |
} |
1653 |
|
1654 |
static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction) |
1655 |
{ |
1656 |
fdrive_t *cur_drv = get_cur_drv(fdctrl); |
1657 |
|
1658 |
if (fdctrl->fifo[1] & 0x80) |
1659 |
cur_drv->perpendicular = fdctrl->fifo[1] & 0x7; |
1660 |
/* No result back */
|
1661 |
fdctrl_reset_fifo(fdctrl); |
1662 |
} |
1663 |
|
1664 |
static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction) |
1665 |
{ |
1666 |
fdctrl->config = fdctrl->fifo[2];
|
1667 |
fdctrl->precomp_trk = fdctrl->fifo[3];
|
1668 |
/* No result back */
|
1669 |
fdctrl_reset_fifo(fdctrl); |
1670 |
} |
1671 |
|
1672 |
static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction) |
1673 |
{ |
1674 |
fdctrl->pwrd = fdctrl->fifo[1];
|
1675 |
fdctrl->fifo[0] = fdctrl->fifo[1]; |
1676 |
fdctrl_set_fifo(fdctrl, 1, 1); |
1677 |
} |
1678 |
|
1679 |
static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction) |
1680 |
{ |
1681 |
/* No result back */
|
1682 |
fdctrl_reset_fifo(fdctrl); |
1683 |
} |
1684 |
|
1685 |
static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction) |
1686 |
{ |
1687 |
fdrive_t *cur_drv = get_cur_drv(fdctrl); |
1688 |
|
1689 |
if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) { |
1690 |
/* Command parameters done */
|
1691 |
if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) { |
1692 |
fdctrl->fifo[0] = fdctrl->fifo[1]; |
1693 |
fdctrl->fifo[2] = 0; |
1694 |
fdctrl->fifo[3] = 0; |
1695 |
fdctrl_set_fifo(fdctrl, 4, 1); |
1696 |
} else {
|
1697 |
fdctrl_reset_fifo(fdctrl); |
1698 |
} |
1699 |
} else if (fdctrl->data_len > 7) { |
1700 |
/* ERROR */
|
1701 |
fdctrl->fifo[0] = 0x80 | |
1702 |
(cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
|
1703 |
fdctrl_set_fifo(fdctrl, 1, 1); |
1704 |
} |
1705 |
} |
1706 |
|
1707 |
static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction) |
1708 |
{ |
1709 |
fdrive_t *cur_drv; |
1710 |
|
1711 |
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1712 |
cur_drv = get_cur_drv(fdctrl); |
1713 |
if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) { |
1714 |
cur_drv->track = cur_drv->max_track - 1;
|
1715 |
} else {
|
1716 |
cur_drv->track += fdctrl->fifo[2];
|
1717 |
} |
1718 |
fdctrl_reset_fifo(fdctrl); |
1719 |
/* Raise Interrupt */
|
1720 |
fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); |
1721 |
} |
1722 |
|
1723 |
static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction) |
1724 |
{ |
1725 |
fdrive_t *cur_drv; |
1726 |
|
1727 |
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
1728 |
cur_drv = get_cur_drv(fdctrl); |
1729 |
if (fdctrl->fifo[2] > cur_drv->track) { |
1730 |
cur_drv->track = 0;
|
1731 |
} else {
|
1732 |
cur_drv->track -= fdctrl->fifo[2];
|
1733 |
} |
1734 |
fdctrl_reset_fifo(fdctrl); |
1735 |
/* Raise Interrupt */
|
1736 |
fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); |
1737 |
} |
1738 |
|
1739 |
static const struct { |
1740 |
uint8_t value; |
1741 |
uint8_t mask; |
1742 |
const char* name; |
1743 |
int parameters;
|
1744 |
void (*handler)(fdctrl_t *fdctrl, int direction); |
1745 |
int direction;
|
1746 |
} handlers[] = { |
1747 |
{ FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ }, |
1748 |
{ FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE }, |
1749 |
{ FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek }, |
1750 |
{ FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status }, |
1751 |
{ FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate }, |
1752 |
{ FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track }, |
1753 |
{ FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ }, |
1754 |
{ FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */ |
1755 |
{ FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */ |
1756 |
{ FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ }, |
1757 |
{ FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE }, |
1758 |
{ FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented }, |
1759 |
{ FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL }, |
1760 |
{ FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH }, |
1761 |
{ FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE }, |
1762 |
{ FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid }, |
1763 |
{ FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify }, |
1764 |
{ FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status }, |
1765 |
{ FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode }, |
1766 |
{ FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure }, |
1767 |
{ FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode }, |
1768 |
{ FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option }, |
1769 |
{ FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command }, |
1770 |
{ FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out }, |
1771 |
{ FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented }, |
1772 |
{ FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in }, |
1773 |
{ FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock }, |
1774 |
{ FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg }, |
1775 |
{ FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version }, |
1776 |
{ FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid }, |
1777 |
{ FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */ |
1778 |
{ 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */ |
1779 |
}; |
1780 |
/* Associate command to an index in the 'handlers' array */
|
1781 |
static uint8_t command_to_handler[256]; |
1782 |
|
1783 |
static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value) |
1784 |
{ |
1785 |
fdrive_t *cur_drv; |
1786 |
int pos;
|
1787 |
|
1788 |
/* Reset mode */
|
1789 |
if (!(fdctrl->dor & FD_DOR_nRESET)) {
|
1790 |
FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
|
1791 |
return;
|
1792 |
} |
1793 |
if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
|
1794 |
FLOPPY_ERROR("controller not ready for writing\n");
|
1795 |
return;
|
1796 |
} |
1797 |
fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
1798 |
/* Is it write command time ? */
|
1799 |
if (fdctrl->msr & FD_MSR_NONDMA) {
|
1800 |
/* FIFO data write */
|
1801 |
pos = fdctrl->data_pos++; |
1802 |
pos %= FD_SECTOR_LEN; |
1803 |
fdctrl->fifo[pos] = value; |
1804 |
if (pos == FD_SECTOR_LEN - 1 || |
1805 |
fdctrl->data_pos == fdctrl->data_len) { |
1806 |
cur_drv = get_cur_drv(fdctrl); |
1807 |
if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { |
1808 |
FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
|
1809 |
return;
|
1810 |
} |
1811 |
if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
|
1812 |
FLOPPY_DPRINTF("error seeking to next sector %d\n",
|
1813 |
fd_sector(cur_drv)); |
1814 |
return;
|
1815 |
} |
1816 |
} |
1817 |
/* Switch from transfer mode to status mode
|
1818 |
* then from status mode to command mode
|
1819 |
*/
|
1820 |
if (fdctrl->data_pos == fdctrl->data_len)
|
1821 |
fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00); |
1822 |
return;
|
1823 |
} |
1824 |
if (fdctrl->data_pos == 0) { |
1825 |
/* Command */
|
1826 |
pos = command_to_handler[value & 0xff];
|
1827 |
FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
|
1828 |
fdctrl->data_len = handlers[pos].parameters + 1;
|
1829 |
} |
1830 |
|
1831 |
FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
|
1832 |
fdctrl->fifo[fdctrl->data_pos++] = value; |
1833 |
if (fdctrl->data_pos == fdctrl->data_len) {
|
1834 |
/* We now have all parameters
|
1835 |
* and will be able to treat the command
|
1836 |
*/
|
1837 |
if (fdctrl->data_state & FD_STATE_FORMAT) {
|
1838 |
fdctrl_format_sector(fdctrl); |
1839 |
return;
|
1840 |
} |
1841 |
|
1842 |
pos = command_to_handler[fdctrl->fifo[0] & 0xff]; |
1843 |
FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
|
1844 |
(*handlers[pos].handler)(fdctrl, handlers[pos].direction); |
1845 |
} |
1846 |
} |
1847 |
|
1848 |
static void fdctrl_result_timer(void *opaque) |
1849 |
{ |
1850 |
fdctrl_t *fdctrl = opaque; |
1851 |
fdrive_t *cur_drv = get_cur_drv(fdctrl); |
1852 |
|
1853 |
/* Pretend we are spinning.
|
1854 |
* This is needed for Coherent, which uses READ ID to check for
|
1855 |
* sector interleaving.
|
1856 |
*/
|
1857 |
if (cur_drv->last_sect != 0) { |
1858 |
cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
|
1859 |
} |
1860 |
fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); |
1861 |
} |
1862 |
|
1863 |
/* Init functions */
|
1864 |
static void fdctrl_connect_drives(fdctrl_t *fdctrl, BlockDriverState **fds) |
1865 |
{ |
1866 |
unsigned int i; |
1867 |
|
1868 |
for (i = 0; i < MAX_FD; i++) { |
1869 |
fd_init(&fdctrl->drives[i], fds[i]); |
1870 |
fd_revalidate(&fdctrl->drives[i]); |
1871 |
} |
1872 |
} |
1873 |
|
1874 |
fdctrl_t *fdctrl_init_isa(int isairq, int dma_chann, |
1875 |
uint32_t io_base, |
1876 |
BlockDriverState **fds) |
1877 |
{ |
1878 |
fdctrl_t *fdctrl; |
1879 |
ISADevice *dev; |
1880 |
|
1881 |
dev = isa_create_simple("isa-fdc", io_base, 0, isairq, -1); |
1882 |
fdctrl = &(DO_UPCAST(fdctrl_isabus_t, busdev, dev)->state); |
1883 |
|
1884 |
fdctrl->dma_chann = dma_chann; |
1885 |
DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl); |
1886 |
|
1887 |
fdctrl_connect_drives(fdctrl, fds); |
1888 |
|
1889 |
return fdctrl;
|
1890 |
} |
1891 |
|
1892 |
fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
|
1893 |
target_phys_addr_t mmio_base, |
1894 |
BlockDriverState **fds) |
1895 |
{ |
1896 |
fdctrl_t *fdctrl; |
1897 |
DeviceState *dev; |
1898 |
fdctrl_sysbus_t *sys; |
1899 |
|
1900 |
dev = qdev_create(NULL, "sysbus-fdc"); |
1901 |
qdev_init(dev); |
1902 |
sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev); |
1903 |
fdctrl = &sys->state; |
1904 |
sysbus_connect_irq(&sys->busdev, 0, irq);
|
1905 |
sysbus_mmio_map(&sys->busdev, 0, mmio_base);
|
1906 |
|
1907 |
fdctrl->dma_chann = dma_chann; |
1908 |
DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl); |
1909 |
fdctrl_connect_drives(fdctrl, fds); |
1910 |
|
1911 |
return fdctrl;
|
1912 |
} |
1913 |
|
1914 |
fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base, |
1915 |
BlockDriverState **fds, qemu_irq *fdc_tc) |
1916 |
{ |
1917 |
DeviceState *dev; |
1918 |
fdctrl_sysbus_t *sys; |
1919 |
fdctrl_t *fdctrl; |
1920 |
|
1921 |
dev = qdev_create(NULL, "SUNW,fdtwo"); |
1922 |
qdev_init(dev); |
1923 |
sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev); |
1924 |
fdctrl = &sys->state; |
1925 |
sysbus_connect_irq(&sys->busdev, 0, irq);
|
1926 |
sysbus_mmio_map(&sys->busdev, 0, io_base);
|
1927 |
*fdc_tc = qdev_get_gpio_in(dev, 0);
|
1928 |
|
1929 |
fdctrl->dma_chann = -1;
|
1930 |
|
1931 |
fdctrl_connect_drives(fdctrl, fds); |
1932 |
|
1933 |
return fdctrl;
|
1934 |
} |
1935 |
|
1936 |
static int fdctrl_init_common(fdctrl_t *fdctrl) |
1937 |
{ |
1938 |
int i, j;
|
1939 |
static int command_tables_inited = 0; |
1940 |
|
1941 |
/* Fill 'command_to_handler' lookup table */
|
1942 |
if (!command_tables_inited) {
|
1943 |
command_tables_inited = 1;
|
1944 |
for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) { |
1945 |
for (j = 0; j < sizeof(command_to_handler); j++) { |
1946 |
if ((j & handlers[i].mask) == handlers[i].value) {
|
1947 |
command_to_handler[j] = i; |
1948 |
} |
1949 |
} |
1950 |
} |
1951 |
} |
1952 |
|
1953 |
FLOPPY_DPRINTF("init controller\n");
|
1954 |
fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
|
1955 |
fdctrl->result_timer = qemu_new_timer(vm_clock, |
1956 |
fdctrl_result_timer, fdctrl); |
1957 |
|
1958 |
fdctrl->version = 0x90; /* Intel 82078 controller */ |
1959 |
fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
|
1960 |
|
1961 |
fdctrl_external_reset(fdctrl); |
1962 |
register_savevm("fdc", -1, 2, fdc_save, fdc_load, fdctrl); |
1963 |
qemu_register_reset(fdctrl_external_reset, fdctrl); |
1964 |
return 0; |
1965 |
} |
1966 |
|
1967 |
static int isabus_fdc_init1(ISADevice *dev) |
1968 |
{ |
1969 |
fdctrl_isabus_t *isa = DO_UPCAST(fdctrl_isabus_t, busdev, dev); |
1970 |
fdctrl_t *fdctrl = &isa->state; |
1971 |
|
1972 |
register_ioport_read(isa->busdev.iobase[0] + 0x01, 5, 1, |
1973 |
&fdctrl_read_port, fdctrl); |
1974 |
register_ioport_read(isa->busdev.iobase[0] + 0x07, 1, 1, |
1975 |
&fdctrl_read_port, fdctrl); |
1976 |
register_ioport_write(isa->busdev.iobase[0] + 0x01, 5, 1, |
1977 |
&fdctrl_write_port, fdctrl); |
1978 |
register_ioport_write(isa->busdev.iobase[0] + 0x07, 1, 1, |
1979 |
&fdctrl_write_port, fdctrl); |
1980 |
isa_init_irq(&isa->busdev, &fdctrl->irq); |
1981 |
|
1982 |
return fdctrl_init_common(fdctrl);
|
1983 |
} |
1984 |
|
1985 |
static int sysbus_fdc_init1(SysBusDevice *dev) |
1986 |
{ |
1987 |
fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state); |
1988 |
int io;
|
1989 |
|
1990 |
io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl); |
1991 |
sysbus_init_mmio(dev, 0x08, io);
|
1992 |
sysbus_init_irq(dev, &fdctrl->irq); |
1993 |
qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
|
1994 |
|
1995 |
return fdctrl_init_common(fdctrl);
|
1996 |
} |
1997 |
|
1998 |
static int sun4m_fdc_init1(SysBusDevice *dev) |
1999 |
{ |
2000 |
fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state); |
2001 |
int io;
|
2002 |
|
2003 |
io = cpu_register_io_memory(fdctrl_mem_read_strict, |
2004 |
fdctrl_mem_write_strict, fdctrl); |
2005 |
sysbus_init_mmio(dev, 0x08, io);
|
2006 |
sysbus_init_irq(dev, &fdctrl->irq); |
2007 |
qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
|
2008 |
|
2009 |
fdctrl->sun4m = 1;
|
2010 |
return fdctrl_init_common(fdctrl);
|
2011 |
} |
2012 |
|
2013 |
static ISADeviceInfo isa_fdc_info = {
|
2014 |
.init = isabus_fdc_init1, |
2015 |
.qdev.name = "isa-fdc",
|
2016 |
.qdev.size = sizeof(fdctrl_isabus_t),
|
2017 |
}; |
2018 |
|
2019 |
static SysBusDeviceInfo sysbus_fdc_info = {
|
2020 |
.init = sysbus_fdc_init1, |
2021 |
.qdev.name = "sysbus-fdc",
|
2022 |
.qdev.size = sizeof(fdctrl_sysbus_t),
|
2023 |
}; |
2024 |
|
2025 |
static SysBusDeviceInfo sun4m_fdc_info = {
|
2026 |
.init = sun4m_fdc_init1, |
2027 |
.qdev.name = "SUNW,fdtwo",
|
2028 |
.qdev.size = sizeof(fdctrl_sysbus_t),
|
2029 |
}; |
2030 |
|
2031 |
static void fdc_register_devices(void) |
2032 |
{ |
2033 |
isa_qdev_register(&isa_fdc_info); |
2034 |
sysbus_register_withprop(&sysbus_fdc_info); |
2035 |
sysbus_register_withprop(&sun4m_fdc_info); |
2036 |
} |
2037 |
|
2038 |
device_init(fdc_register_devices) |