root / hw / r2d.c @ f8b6d672
History | View | Annotate | Download (8.7 kB)
1 | 0d78f544 | ths | /*
|
---|---|---|---|
2 | 0d78f544 | ths | * Renesas SH7751R R2D-PLUS emulation
|
3 | 0d78f544 | ths | *
|
4 | 0d78f544 | ths | * Copyright (c) 2007 Magnus Damm
|
5 | b319feb7 | aurel32 | * Copyright (c) 2008 Paul Mundt
|
6 | 0d78f544 | ths | *
|
7 | 0d78f544 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
8 | 0d78f544 | ths | * of this software and associated documentation files (the "Software"), to deal
|
9 | 0d78f544 | ths | * in the Software without restriction, including without limitation the rights
|
10 | 0d78f544 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
11 | 0d78f544 | ths | * copies of the Software, and to permit persons to whom the Software is
|
12 | 0d78f544 | ths | * furnished to do so, subject to the following conditions:
|
13 | 0d78f544 | ths | *
|
14 | 0d78f544 | ths | * The above copyright notice and this permission notice shall be included in
|
15 | 0d78f544 | ths | * all copies or substantial portions of the Software.
|
16 | 0d78f544 | ths | *
|
17 | 0d78f544 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
18 | 0d78f544 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
19 | 0d78f544 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
20 | 0d78f544 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
21 | 0d78f544 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
22 | 0d78f544 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
23 | 0d78f544 | ths | * THE SOFTWARE.
|
24 | 0d78f544 | ths | */
|
25 | 0d78f544 | ths | |
26 | 87ecb68b | pbrook | #include "hw.h" |
27 | 87ecb68b | pbrook | #include "sh.h" |
28 | ffd39257 | blueswir1 | #include "devices.h" |
29 | 87ecb68b | pbrook | #include "sysemu.h" |
30 | 87ecb68b | pbrook | #include "boards.h" |
31 | c2f01775 | balrog | #include "pci.h" |
32 | 18e08a55 | Michael S. Tsirkin | #include "sh_pci.h" |
33 | c2f01775 | balrog | #include "net.h" |
34 | c2f01775 | balrog | #include "sh7750_regs.h" |
35 | 3d2bf4a1 | Gerd Hoffmann | #include "ide.h" |
36 | ca20cf32 | Blue Swirl | #include "loader.h" |
37 | 9caa3ec1 | Aurelien Jarno | #include "usb.h" |
38 | 56839a19 | Aurelien Jarno | #include "flash.h" |
39 | 2446333c | Blue Swirl | #include "blockdev.h" |
40 | 56839a19 | Aurelien Jarno | |
41 | 56839a19 | Aurelien Jarno | #define FLASH_BASE 0x00000000 |
42 | 56839a19 | Aurelien Jarno | #define FLASH_SIZE 0x02000000 |
43 | 0d78f544 | ths | |
44 | 0d78f544 | ths | #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */ |
45 | 0d78f544 | ths | #define SDRAM_SIZE 0x04000000 |
46 | 0d78f544 | ths | |
47 | ffd39257 | blueswir1 | #define SM501_VRAM_SIZE 0x800000 |
48 | ffd39257 | blueswir1 | |
49 | 73f19035 | Aurelien Jarno | #define BOOT_PARAMS_OFFSET 0x0010000 |
50 | e8afa065 | aurel32 | /* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
|
51 | 73f19035 | Aurelien Jarno | #define LINUX_LOAD_OFFSET 0x0800000 |
52 | 73f19035 | Aurelien Jarno | #define INITRD_LOAD_OFFSET 0x1800000 |
53 | e8afa065 | aurel32 | |
54 | d47ede60 | balrog | #define PA_IRLMSK 0x00 |
55 | b319feb7 | aurel32 | #define PA_POWOFF 0x30 |
56 | b319feb7 | aurel32 | #define PA_VERREG 0x32 |
57 | b319feb7 | aurel32 | #define PA_OUTPORT 0x36 |
58 | b319feb7 | aurel32 | |
59 | b319feb7 | aurel32 | typedef struct { |
60 | b319feb7 | aurel32 | uint16_t bcr; |
61 | d47ede60 | balrog | uint16_t irlmsk; |
62 | b319feb7 | aurel32 | uint16_t irlmon; |
63 | b319feb7 | aurel32 | uint16_t cfctl; |
64 | b319feb7 | aurel32 | uint16_t cfpow; |
65 | b319feb7 | aurel32 | uint16_t dispctl; |
66 | b319feb7 | aurel32 | uint16_t sdmpow; |
67 | b319feb7 | aurel32 | uint16_t rtcce; |
68 | b319feb7 | aurel32 | uint16_t pcicd; |
69 | b319feb7 | aurel32 | uint16_t voyagerrts; |
70 | b319feb7 | aurel32 | uint16_t cfrst; |
71 | b319feb7 | aurel32 | uint16_t admrts; |
72 | b319feb7 | aurel32 | uint16_t extrst; |
73 | b319feb7 | aurel32 | uint16_t cfcdintclr; |
74 | b319feb7 | aurel32 | uint16_t keyctlclr; |
75 | b319feb7 | aurel32 | uint16_t pad0; |
76 | b319feb7 | aurel32 | uint16_t pad1; |
77 | b319feb7 | aurel32 | uint16_t verreg; |
78 | b319feb7 | aurel32 | uint16_t inport; |
79 | b319feb7 | aurel32 | uint16_t outport; |
80 | b319feb7 | aurel32 | uint16_t bverreg; |
81 | d47ede60 | balrog | |
82 | d47ede60 | balrog | /* output pin */
|
83 | d47ede60 | balrog | qemu_irq irl; |
84 | c227f099 | Anthony Liguori | } r2d_fpga_t; |
85 | b319feb7 | aurel32 | |
86 | d47ede60 | balrog | enum r2d_fpga_irq {
|
87 | d47ede60 | balrog | PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T, |
88 | d47ede60 | balrog | SDCARD, PCI_INTA, PCI_INTB, EXT, TP, |
89 | d47ede60 | balrog | NR_IRQS |
90 | d47ede60 | balrog | }; |
91 | d47ede60 | balrog | |
92 | d47ede60 | balrog | static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = { |
93 | d47ede60 | balrog | [CF_IDE] = { 1, 1<<9 }, |
94 | d47ede60 | balrog | [CF_CD] = { 2, 1<<8 }, |
95 | d47ede60 | balrog | [PCI_INTA] = { 9, 1<<14 }, |
96 | d47ede60 | balrog | [PCI_INTB] = { 10, 1<<13 }, |
97 | d47ede60 | balrog | [PCI_INTC] = { 3, 1<<12 }, |
98 | d47ede60 | balrog | [PCI_INTD] = { 0, 1<<11 }, |
99 | d47ede60 | balrog | [SM501] = { 4, 1<<10 }, |
100 | d47ede60 | balrog | [KEY] = { 5, 1<<6 }, |
101 | d47ede60 | balrog | [RTC_A] = { 6, 1<<5 }, |
102 | d47ede60 | balrog | [RTC_T] = { 7, 1<<4 }, |
103 | d47ede60 | balrog | [SDCARD] = { 8, 1<<7 }, |
104 | d47ede60 | balrog | [EXT] = { 11, 1<<0 }, |
105 | d47ede60 | balrog | [TP] = { 12, 1<<15 }, |
106 | d47ede60 | balrog | }; |
107 | d47ede60 | balrog | |
108 | c227f099 | Anthony Liguori | static void update_irl(r2d_fpga_t *fpga) |
109 | d47ede60 | balrog | { |
110 | d47ede60 | balrog | int i, irl = 15; |
111 | d47ede60 | balrog | for (i = 0; i < NR_IRQS; i++) |
112 | d47ede60 | balrog | if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
|
113 | d47ede60 | balrog | if (irqtab[i].irl < irl)
|
114 | d47ede60 | balrog | irl = irqtab[i].irl; |
115 | d47ede60 | balrog | qemu_set_irq(fpga->irl, irl ^ 15);
|
116 | d47ede60 | balrog | } |
117 | d47ede60 | balrog | |
118 | d47ede60 | balrog | static void r2d_fpga_irq_set(void *opaque, int n, int level) |
119 | d47ede60 | balrog | { |
120 | c227f099 | Anthony Liguori | r2d_fpga_t *fpga = opaque; |
121 | d47ede60 | balrog | if (level)
|
122 | d47ede60 | balrog | fpga->irlmon |= irqtab[n].msk; |
123 | d47ede60 | balrog | else
|
124 | d47ede60 | balrog | fpga->irlmon &= ~irqtab[n].msk; |
125 | d47ede60 | balrog | update_irl(fpga); |
126 | d47ede60 | balrog | } |
127 | d47ede60 | balrog | |
128 | c227f099 | Anthony Liguori | static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr) |
129 | b319feb7 | aurel32 | { |
130 | c227f099 | Anthony Liguori | r2d_fpga_t *s = opaque; |
131 | b319feb7 | aurel32 | |
132 | b319feb7 | aurel32 | switch (addr) {
|
133 | d47ede60 | balrog | case PA_IRLMSK:
|
134 | d47ede60 | balrog | return s->irlmsk;
|
135 | b319feb7 | aurel32 | case PA_OUTPORT:
|
136 | b319feb7 | aurel32 | return s->outport;
|
137 | b319feb7 | aurel32 | case PA_POWOFF:
|
138 | 37cc0b44 | Aurelien Jarno | return 0x00; |
139 | b319feb7 | aurel32 | case PA_VERREG:
|
140 | b319feb7 | aurel32 | return 0x10; |
141 | b319feb7 | aurel32 | } |
142 | b319feb7 | aurel32 | |
143 | b319feb7 | aurel32 | return 0; |
144 | b319feb7 | aurel32 | } |
145 | b319feb7 | aurel32 | |
146 | b319feb7 | aurel32 | static void |
147 | c227f099 | Anthony Liguori | r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
|
148 | b319feb7 | aurel32 | { |
149 | c227f099 | Anthony Liguori | r2d_fpga_t *s = opaque; |
150 | b319feb7 | aurel32 | |
151 | b319feb7 | aurel32 | switch (addr) {
|
152 | d47ede60 | balrog | case PA_IRLMSK:
|
153 | d47ede60 | balrog | s->irlmsk = value; |
154 | d47ede60 | balrog | update_irl(s); |
155 | d47ede60 | balrog | break;
|
156 | b319feb7 | aurel32 | case PA_OUTPORT:
|
157 | b319feb7 | aurel32 | s->outport = value; |
158 | b319feb7 | aurel32 | break;
|
159 | b319feb7 | aurel32 | case PA_POWOFF:
|
160 | 37cc0b44 | Aurelien Jarno | if (value & 1) { |
161 | 37cc0b44 | Aurelien Jarno | qemu_system_shutdown_request(); |
162 | 37cc0b44 | Aurelien Jarno | } |
163 | 37cc0b44 | Aurelien Jarno | break;
|
164 | b319feb7 | aurel32 | case PA_VERREG:
|
165 | b319feb7 | aurel32 | /* Discard writes */
|
166 | b319feb7 | aurel32 | break;
|
167 | b319feb7 | aurel32 | } |
168 | b319feb7 | aurel32 | } |
169 | b319feb7 | aurel32 | |
170 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const r2d_fpga_readfn[] = { |
171 | b319feb7 | aurel32 | r2d_fpga_read, |
172 | b319feb7 | aurel32 | r2d_fpga_read, |
173 | b2463a64 | aurel32 | NULL,
|
174 | b319feb7 | aurel32 | }; |
175 | b319feb7 | aurel32 | |
176 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const r2d_fpga_writefn[] = { |
177 | b319feb7 | aurel32 | r2d_fpga_write, |
178 | b319feb7 | aurel32 | r2d_fpga_write, |
179 | b2463a64 | aurel32 | NULL,
|
180 | b319feb7 | aurel32 | }; |
181 | b319feb7 | aurel32 | |
182 | c227f099 | Anthony Liguori | static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
|
183 | b319feb7 | aurel32 | { |
184 | b319feb7 | aurel32 | int iomemtype;
|
185 | c227f099 | Anthony Liguori | r2d_fpga_t *s; |
186 | b319feb7 | aurel32 | |
187 | c227f099 | Anthony Liguori | s = qemu_mallocz(sizeof(r2d_fpga_t));
|
188 | d47ede60 | balrog | |
189 | d47ede60 | balrog | s->irl = irl; |
190 | b319feb7 | aurel32 | |
191 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(r2d_fpga_readfn, |
192 | b319feb7 | aurel32 | r2d_fpga_writefn, s); |
193 | b319feb7 | aurel32 | cpu_register_physical_memory(base, 0x40, iomemtype);
|
194 | d47ede60 | balrog | return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
|
195 | b319feb7 | aurel32 | } |
196 | b319feb7 | aurel32 | |
197 | 5d4e84c8 | Juan Quintela | static void r2d_pci_set_irq(void *opaque, int n, int l) |
198 | c2f01775 | balrog | { |
199 | 5d4e84c8 | Juan Quintela | qemu_irq *p = opaque; |
200 | 5d4e84c8 | Juan Quintela | |
201 | c2f01775 | balrog | qemu_set_irq(p[n], l); |
202 | c2f01775 | balrog | } |
203 | c2f01775 | balrog | |
204 | c2f01775 | balrog | static int r2d_pci_map_irq(PCIDevice *d, int irq_num) |
205 | c2f01775 | balrog | { |
206 | c2f01775 | balrog | const int intx[] = { PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD }; |
207 | c2f01775 | balrog | return intx[d->devfn >> 3]; |
208 | c2f01775 | balrog | } |
209 | c2f01775 | balrog | |
210 | 73f19035 | Aurelien Jarno | static struct __attribute__((__packed__)) |
211 | 73f19035 | Aurelien Jarno | { |
212 | 73f19035 | Aurelien Jarno | int mount_root_rdonly;
|
213 | 73f19035 | Aurelien Jarno | int ramdisk_flags;
|
214 | 73f19035 | Aurelien Jarno | int orig_root_dev;
|
215 | 73f19035 | Aurelien Jarno | int loader_type;
|
216 | 73f19035 | Aurelien Jarno | int initrd_start;
|
217 | 73f19035 | Aurelien Jarno | int initrd_size;
|
218 | 73f19035 | Aurelien Jarno | |
219 | 73f19035 | Aurelien Jarno | char pad[232]; |
220 | 73f19035 | Aurelien Jarno | |
221 | 73f19035 | Aurelien Jarno | char kernel_cmdline[256]; |
222 | 73f19035 | Aurelien Jarno | } boot_params; |
223 | 73f19035 | Aurelien Jarno | |
224 | c227f099 | Anthony Liguori | static void r2d_init(ram_addr_t ram_size, |
225 | 3023f332 | aliguori | const char *boot_device, |
226 | 0d78f544 | ths | const char *kernel_filename, const char *kernel_cmdline, |
227 | 0d78f544 | ths | const char *initrd_filename, const char *cpu_model) |
228 | 0d78f544 | ths | { |
229 | 0d78f544 | ths | CPUState *env; |
230 | 0d78f544 | ths | struct SH7750State *s;
|
231 | c227f099 | Anthony Liguori | ram_addr_t sdram_addr; |
232 | d47ede60 | balrog | qemu_irq *irq; |
233 | 751c6a17 | Gerd Hoffmann | DriveInfo *dinfo; |
234 | c2f01775 | balrog | int i;
|
235 | 0d78f544 | ths | |
236 | aaed909a | bellard | if (!cpu_model)
|
237 | 0fd3ca30 | aurel32 | cpu_model = "SH7751R";
|
238 | aaed909a | bellard | |
239 | aaed909a | bellard | env = cpu_init(cpu_model); |
240 | aaed909a | bellard | if (!env) {
|
241 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
|
242 | aaed909a | bellard | exit(1);
|
243 | aaed909a | bellard | } |
244 | 0d78f544 | ths | |
245 | 0d78f544 | ths | /* Allocate memory space */
|
246 | 1724f049 | Alex Williamson | sdram_addr = qemu_ram_alloc(NULL, "r2d.sdram", SDRAM_SIZE); |
247 | ffd39257 | blueswir1 | cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr); |
248 | 0d78f544 | ths | /* Register peripherals */
|
249 | 0d78f544 | ths | s = sh7750_init(env); |
250 | d47ede60 | balrog | irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
|
251 | a303f9e3 | Blue Swirl | sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4); |
252 | d47ede60 | balrog | |
253 | ac611340 | aurel32 | sm501_init(0x10000000, SM501_VRAM_SIZE, irq[SM501], serial_hds[2]); |
254 | a4a771c0 | balrog | |
255 | a4a771c0 | balrog | /* onboard CF (True IDE mode, Master only). */
|
256 | 612b2bd0 | Aurelien Jarno | dinfo = drive_get(IF_IDE, 0, 0); |
257 | 612b2bd0 | Aurelien Jarno | mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1, |
258 | 612b2bd0 | Aurelien Jarno | dinfo, NULL);
|
259 | a4a771c0 | balrog | |
260 | 56839a19 | Aurelien Jarno | /* onboard flash memory */
|
261 | 45e7e4bc | Aurelien Jarno | dinfo = drive_get(IF_PFLASH, 0, 0); |
262 | 1724f049 | Alex Williamson | pflash_cfi02_register(0x0, qemu_ram_alloc(NULL, "r2d.flash", FLASH_SIZE), |
263 | 612b2bd0 | Aurelien Jarno | dinfo ? dinfo->bdrv : NULL, (16 * 1024), |
264 | 612b2bd0 | Aurelien Jarno | FLASH_SIZE >> 16,
|
265 | 612b2bd0 | Aurelien Jarno | 1, 4, 0x0000, 0x0000, 0x0000, 0x0000, |
266 | 612b2bd0 | Aurelien Jarno | 0x555, 0x2aa, 0); |
267 | 56839a19 | Aurelien Jarno | |
268 | c2f01775 | balrog | /* NIC: rtl8139 on-board, and 2 slots. */
|
269 | ab2da564 | aurel32 | for (i = 0; i < nb_nics; i++) |
270 | 07caea31 | Markus Armbruster | pci_nic_init_nofail(&nd_table[i], "rtl8139", i==0 ? "2" : NULL); |
271 | c2f01775 | balrog | |
272 | 9caa3ec1 | Aurelien Jarno | /* USB keyboard */
|
273 | 9caa3ec1 | Aurelien Jarno | usbdevice_create("keyboard");
|
274 | 9caa3ec1 | Aurelien Jarno | |
275 | 0d78f544 | ths | /* Todo: register on board registers */
|
276 | 73f19035 | Aurelien Jarno | memset(&boot_params, 0, sizeof(boot_params)); |
277 | 73f19035 | Aurelien Jarno | |
278 | e8afa065 | aurel32 | if (kernel_filename) {
|
279 | 73f19035 | Aurelien Jarno | int kernel_size;
|
280 | 73f19035 | Aurelien Jarno | |
281 | 73f19035 | Aurelien Jarno | kernel_size = load_image_targphys(kernel_filename, |
282 | 73f19035 | Aurelien Jarno | SDRAM_BASE + LINUX_LOAD_OFFSET, |
283 | 73f19035 | Aurelien Jarno | INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET); |
284 | 73f19035 | Aurelien Jarno | if (kernel_size < 0) { |
285 | 73f19035 | Aurelien Jarno | fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
|
286 | 73f19035 | Aurelien Jarno | exit(1);
|
287 | 73f19035 | Aurelien Jarno | } |
288 | 73f19035 | Aurelien Jarno | |
289 | 73f19035 | Aurelien Jarno | /* initialization which should be done by firmware */
|
290 | 73f19035 | Aurelien Jarno | stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */ |
291 | 73f19035 | Aurelien Jarno | stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */ |
292 | 73f19035 | Aurelien Jarno | env->pc = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */ |
293 | 0d78f544 | ths | } |
294 | 73f19035 | Aurelien Jarno | |
295 | 73f19035 | Aurelien Jarno | if (initrd_filename) {
|
296 | 73f19035 | Aurelien Jarno | int initrd_size;
|
297 | 73f19035 | Aurelien Jarno | |
298 | 73f19035 | Aurelien Jarno | initrd_size = load_image_targphys(initrd_filename, |
299 | 73f19035 | Aurelien Jarno | SDRAM_BASE + INITRD_LOAD_OFFSET, |
300 | 73f19035 | Aurelien Jarno | SDRAM_SIZE - INITRD_LOAD_OFFSET); |
301 | 73f19035 | Aurelien Jarno | |
302 | 73f19035 | Aurelien Jarno | if (initrd_size < 0) { |
303 | 73f19035 | Aurelien Jarno | fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
|
304 | 73f19035 | Aurelien Jarno | exit(1);
|
305 | 73f19035 | Aurelien Jarno | } |
306 | 73f19035 | Aurelien Jarno | |
307 | 73f19035 | Aurelien Jarno | /* initialization which should be done by firmware */
|
308 | 73f19035 | Aurelien Jarno | boot_params.loader_type = 1;
|
309 | 73f19035 | Aurelien Jarno | boot_params.initrd_start = INITRD_LOAD_OFFSET; |
310 | 73f19035 | Aurelien Jarno | boot_params.initrd_size = initrd_size; |
311 | 73f19035 | Aurelien Jarno | } |
312 | 73f19035 | Aurelien Jarno | |
313 | 73f19035 | Aurelien Jarno | if (kernel_cmdline) {
|
314 | 73f19035 | Aurelien Jarno | strncpy(boot_params.kernel_cmdline, kernel_cmdline, |
315 | 73f19035 | Aurelien Jarno | sizeof(boot_params.kernel_cmdline));
|
316 | 73f19035 | Aurelien Jarno | } |
317 | 73f19035 | Aurelien Jarno | |
318 | 73f19035 | Aurelien Jarno | rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params), |
319 | 73f19035 | Aurelien Jarno | SDRAM_BASE + BOOT_PARAMS_OFFSET); |
320 | 0d78f544 | ths | } |
321 | 0d78f544 | ths | |
322 | f80f9ec9 | Anthony Liguori | static QEMUMachine r2d_machine = {
|
323 | 4b32e168 | aliguori | .name = "r2d",
|
324 | 4b32e168 | aliguori | .desc = "r2d-plus board",
|
325 | 4b32e168 | aliguori | .init = r2d_init, |
326 | 0d78f544 | ths | }; |
327 | f80f9ec9 | Anthony Liguori | |
328 | f80f9ec9 | Anthony Liguori | static void r2d_machine_init(void) |
329 | f80f9ec9 | Anthony Liguori | { |
330 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&r2d_machine); |
331 | f80f9ec9 | Anthony Liguori | } |
332 | f80f9ec9 | Anthony Liguori | |
333 | f80f9ec9 | Anthony Liguori | machine_init(r2d_machine_init); |