Revision f8b9fe24
| b/hw/xilinx_spips.c | ||
|---|---|---|
| 154 | 154 |
hwaddr lqspi_cached_addr; |
| 155 | 155 |
} XilinxSPIPS; |
| 156 | 156 |
|
| 157 |
#define TYPE_XILINX_SPIPS "xilinx,spips" |
|
| 158 |
|
|
| 159 |
#define XILINX_SPIPS(obj) \ |
|
| 160 |
OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS) |
|
| 161 |
|
|
| 157 | 162 |
static inline int num_effective_busses(XilinxSPIPS *s) |
| 158 | 163 |
{
|
| 159 | 164 |
return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && |
| ... | ... | |
| 210 | 215 |
|
| 211 | 216 |
static void xilinx_spips_reset(DeviceState *d) |
| 212 | 217 |
{
|
| 213 |
XilinxSPIPS *s = DO_UPCAST(XilinxSPIPS, busdev.qdev, d);
|
|
| 218 |
XilinxSPIPS *s = XILINX_SPIPS(d);
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|
| 214 | 219 |
|
| 215 | 220 |
int i; |
| 216 | 221 |
for (i = 0; i < R_MAX; i++) {
|
| ... | ... | |
| 500 | 505 |
} |
| 501 | 506 |
}; |
| 502 | 507 |
|
| 503 |
static int xilinx_spips_init(SysBusDevice *dev)
|
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| 508 |
static void xilinx_spips_realize(DeviceState *dev, Error **errp)
|
|
| 504 | 509 |
{
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XilinxSPIPS *s = FROM_SYSBUS(typeof(*s), dev); |
|
| 510 |
XilinxSPIPS *s = XILINX_SPIPS(dev); |
|
| 511 |
SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
|
| 506 | 512 |
int i; |
| 507 | 513 |
|
| 508 | 514 |
DB_PRINT("inited device model\n");
|
| ... | ... | |
| 511 | 517 |
for (i = 0; i < s->num_busses; ++i) {
|
| 512 | 518 |
char bus_name[16]; |
| 513 | 519 |
snprintf(bus_name, 16, "spi%d", i); |
| 514 |
s->spi[i] = ssi_create_bus(&dev->qdev, bus_name);
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s->spi[i] = ssi_create_bus(dev, bus_name); |
|
| 515 | 521 |
} |
| 516 | 522 |
|
| 517 | 523 |
s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); |
| 518 | 524 |
ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[0]); |
| 519 | 525 |
ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[1]); |
| 520 |
sysbus_init_irq(dev, &s->irq);
|
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| 526 |
sysbus_init_irq(sbd, &s->irq);
|
|
| 521 | 527 |
for (i = 0; i < s->num_cs * s->num_busses; ++i) {
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sysbus_init_irq(dev, &s->cs_lines[i]);
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sysbus_init_irq(sbd, &s->cs_lines[i]);
|
|
| 523 | 529 |
} |
| 524 | 530 |
|
| 525 | 531 |
memory_region_init_io(&s->iomem, &spips_ops, s, "spi", R_MAX*4); |
| 526 |
sysbus_init_mmio(dev, &s->iomem);
|
|
| 532 |
sysbus_init_mmio(sbd, &s->iomem);
|
|
| 527 | 533 |
|
| 528 | 534 |
memory_region_init_io(&s->mmlqspi, &lqspi_ops, s, "lqspi", |
| 529 | 535 |
(1 << LQSPI_ADDRESS_BITS) * 2); |
| 530 |
sysbus_init_mmio(dev, &s->mmlqspi);
|
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| 536 |
sysbus_init_mmio(sbd, &s->mmlqspi);
|
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| 531 | 537 |
|
| 532 | 538 |
s->irqline = -1; |
| 533 | 539 |
s->lqspi_cached_addr = ~0ULL; |
| 534 | 540 |
|
| 535 | 541 |
fifo8_create(&s->rx_fifo, RXFF_A); |
| 536 | 542 |
fifo8_create(&s->tx_fifo, TXFF_A); |
| 537 |
|
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return 0; |
|
| 539 | 543 |
} |
| 540 | 544 |
|
| 541 | 545 |
static int xilinx_spips_post_load(void *opaque, int version_id) |
| ... | ... | |
| 569 | 573 |
static void xilinx_spips_class_init(ObjectClass *klass, void *data) |
| 570 | 574 |
{
|
| 571 | 575 |
DeviceClass *dc = DEVICE_CLASS(klass); |
| 572 |
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); |
|
| 573 | 576 |
|
| 574 |
sdc->init = xilinx_spips_init;
|
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| 577 |
dc->realize = xilinx_spips_realize;
|
|
| 575 | 578 |
dc->reset = xilinx_spips_reset; |
| 576 | 579 |
dc->props = xilinx_spips_properties; |
| 577 | 580 |
dc->vmsd = &vmstate_xilinx_spips; |
| 578 | 581 |
} |
| 579 | 582 |
|
| 580 | 583 |
static const TypeInfo xilinx_spips_info = {
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| 581 |
.name = "xilinx,spips",
|
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| 584 |
.name = TYPE_XILINX_SPIPS,
|
|
| 582 | 585 |
.parent = TYPE_SYS_BUS_DEVICE, |
| 583 | 586 |
.instance_size = sizeof(XilinxSPIPS), |
| 584 | 587 |
.class_init = xilinx_spips_class_init, |
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