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1 | f0fc6f8f | ths | /*
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2 | f0fc6f8f | ths | * QEMU/mipssim emulation
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3 | f0fc6f8f | ths | *
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4 | b5e4946f | Stefan Weil | * Emulates a very simple machine model similar to the one used by the
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5 | f0fc6f8f | ths | * proprietary MIPS emulator.
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6 | a79ee211 | ths | *
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7 | a79ee211 | ths | * Copyright (c) 2007 Thiemo Seufer
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8 | a79ee211 | ths | *
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9 | a79ee211 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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10 | a79ee211 | ths | * of this software and associated documentation files (the "Software"), to deal
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11 | a79ee211 | ths | * in the Software without restriction, including without limitation the rights
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12 | a79ee211 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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13 | a79ee211 | ths | * copies of the Software, and to permit persons to whom the Software is
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14 | a79ee211 | ths | * furnished to do so, subject to the following conditions:
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15 | a79ee211 | ths | *
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16 | a79ee211 | ths | * The above copyright notice and this permission notice shall be included in
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17 | a79ee211 | ths | * all copies or substantial portions of the Software.
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18 | a79ee211 | ths | *
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19 | a79ee211 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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20 | a79ee211 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 | a79ee211 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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22 | a79ee211 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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23 | a79ee211 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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24 | a79ee211 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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25 | a79ee211 | ths | * THE SOFTWARE.
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26 | f0fc6f8f | ths | */
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27 | 87ecb68b | pbrook | #include "hw.h" |
28 | 87ecb68b | pbrook | #include "mips.h" |
29 | b970ea8f | Blue Swirl | #include "mips_cpudevs.h" |
30 | 488cb996 | Gerd Hoffmann | #include "serial.h" |
31 | 87ecb68b | pbrook | #include "isa.h" |
32 | 1422e32d | Paolo Bonzini | #include "net/net.h" |
33 | 9c17d615 | Paolo Bonzini | #include "sysemu/sysemu.h" |
34 | 87ecb68b | pbrook | #include "boards.h" |
35 | bba831e8 | Paul Brook | #include "mips-bios.h" |
36 | ca20cf32 | Blue Swirl | #include "loader.h" |
37 | ca20cf32 | Blue Swirl | #include "elf.h" |
38 | d118d64a | Hervé Poussineau | #include "sysbus.h" |
39 | 022c62cb | Paolo Bonzini | #include "exec/address-spaces.h" |
40 | f0fc6f8f | ths | |
41 | 7df526e3 | ths | static struct _loaderparams { |
42 | 7df526e3 | ths | int ram_size;
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43 | 7df526e3 | ths | const char *kernel_filename; |
44 | 7df526e3 | ths | const char *kernel_cmdline; |
45 | 7df526e3 | ths | const char *initrd_filename; |
46 | 7df526e3 | ths | } loaderparams; |
47 | 7df526e3 | ths | |
48 | e16ad5b0 | Aurelien Jarno | typedef struct ResetData { |
49 | 2d44fc8e | Andreas Färber | MIPSCPU *cpu; |
50 | e16ad5b0 | Aurelien Jarno | uint64_t vector; |
51 | e16ad5b0 | Aurelien Jarno | } ResetData; |
52 | e16ad5b0 | Aurelien Jarno | |
53 | e16ad5b0 | Aurelien Jarno | static int64_t load_kernel(void) |
54 | f0fc6f8f | ths | { |
55 | 409dbce5 | Aurelien Jarno | int64_t entry, kernel_high; |
56 | f0fc6f8f | ths | long kernel_size;
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57 | f0fc6f8f | ths | long initrd_size;
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58 | c227f099 | Anthony Liguori | ram_addr_t initrd_offset; |
59 | ca20cf32 | Blue Swirl | int big_endian;
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60 | ca20cf32 | Blue Swirl | |
61 | ca20cf32 | Blue Swirl | #ifdef TARGET_WORDS_BIGENDIAN
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62 | ca20cf32 | Blue Swirl | big_endian = 1;
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63 | ca20cf32 | Blue Swirl | #else
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64 | ca20cf32 | Blue Swirl | big_endian = 0;
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65 | ca20cf32 | Blue Swirl | #endif
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66 | f0fc6f8f | ths | |
67 | 409dbce5 | Aurelien Jarno | kernel_size = load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys, |
68 | 409dbce5 | Aurelien Jarno | NULL, (uint64_t *)&entry, NULL, |
69 | 409dbce5 | Aurelien Jarno | (uint64_t *)&kernel_high, big_endian, |
70 | 409dbce5 | Aurelien Jarno | ELF_MACHINE, 1);
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71 | f0fc6f8f | ths | if (kernel_size >= 0) { |
72 | f0fc6f8f | ths | if ((entry & ~0x7fffffffULL) == 0x80000000) |
73 | f0fc6f8f | ths | entry = (int32_t)entry; |
74 | f0fc6f8f | ths | } else {
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75 | f0fc6f8f | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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76 | 7df526e3 | ths | loaderparams.kernel_filename); |
77 | f0fc6f8f | ths | exit(1);
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78 | f0fc6f8f | ths | } |
79 | f0fc6f8f | ths | |
80 | f0fc6f8f | ths | /* load initrd */
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81 | f0fc6f8f | ths | initrd_size = 0;
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82 | f0fc6f8f | ths | initrd_offset = 0;
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83 | 7df526e3 | ths | if (loaderparams.initrd_filename) {
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84 | 7df526e3 | ths | initrd_size = get_image_size (loaderparams.initrd_filename); |
85 | f0fc6f8f | ths | if (initrd_size > 0) { |
86 | f0fc6f8f | ths | initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; |
87 | 7df526e3 | ths | if (initrd_offset + initrd_size > loaderparams.ram_size) {
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88 | f0fc6f8f | ths | fprintf(stderr, |
89 | f0fc6f8f | ths | "qemu: memory too small for initial ram disk '%s'\n",
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90 | 7df526e3 | ths | loaderparams.initrd_filename); |
91 | f0fc6f8f | ths | exit(1);
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92 | f0fc6f8f | ths | } |
93 | dcac9679 | pbrook | initrd_size = load_image_targphys(loaderparams.initrd_filename, |
94 | dcac9679 | pbrook | initrd_offset, loaderparams.ram_size - initrd_offset); |
95 | f0fc6f8f | ths | } |
96 | f0fc6f8f | ths | if (initrd_size == (target_ulong) -1) { |
97 | f0fc6f8f | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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98 | 7df526e3 | ths | loaderparams.initrd_filename); |
99 | f0fc6f8f | ths | exit(1);
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100 | f0fc6f8f | ths | } |
101 | f0fc6f8f | ths | } |
102 | e16ad5b0 | Aurelien Jarno | return entry;
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103 | f0fc6f8f | ths | } |
104 | f0fc6f8f | ths | |
105 | f0fc6f8f | ths | static void main_cpu_reset(void *opaque) |
106 | f0fc6f8f | ths | { |
107 | e16ad5b0 | Aurelien Jarno | ResetData *s = (ResetData *)opaque; |
108 | 2d44fc8e | Andreas Färber | CPUMIPSState *env = &s->cpu->env; |
109 | f0fc6f8f | ths | |
110 | 2d44fc8e | Andreas Färber | cpu_reset(CPU(s->cpu)); |
111 | aecf1376 | Nathan Froyd | env->active_tc.PC = s->vector & ~(target_ulong)1;
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112 | aecf1376 | Nathan Froyd | if (s->vector & 1) { |
113 | aecf1376 | Nathan Froyd | env->hflags |= MIPS_HFLAG_M16; |
114 | aecf1376 | Nathan Froyd | } |
115 | f0fc6f8f | ths | } |
116 | f0fc6f8f | ths | |
117 | d118d64a | Hervé Poussineau | static void mipsnet_init(int base, qemu_irq irq, NICInfo *nd) |
118 | d118d64a | Hervé Poussineau | { |
119 | d118d64a | Hervé Poussineau | DeviceState *dev; |
120 | d118d64a | Hervé Poussineau | SysBusDevice *s; |
121 | d118d64a | Hervé Poussineau | |
122 | d118d64a | Hervé Poussineau | dev = qdev_create(NULL, "mipsnet"); |
123 | d118d64a | Hervé Poussineau | qdev_set_nic_properties(dev, nd); |
124 | d118d64a | Hervé Poussineau | qdev_init_nofail(dev); |
125 | d118d64a | Hervé Poussineau | |
126 | d118d64a | Hervé Poussineau | s = sysbus_from_qdev(dev); |
127 | d118d64a | Hervé Poussineau | sysbus_connect_irq(s, 0, irq);
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128 | d118d64a | Hervé Poussineau | memory_region_add_subregion(get_system_io(), |
129 | d118d64a | Hervé Poussineau | base, |
130 | d118d64a | Hervé Poussineau | sysbus_mmio_get_region(s, 0));
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131 | d118d64a | Hervé Poussineau | } |
132 | d118d64a | Hervé Poussineau | |
133 | f0fc6f8f | ths | static void |
134 | 5f072e1f | Eduardo Habkost | mips_mipssim_init(QEMUMachineInitArgs *args) |
135 | f0fc6f8f | ths | { |
136 | 5f072e1f | Eduardo Habkost | ram_addr_t ram_size = args->ram_size; |
137 | 5f072e1f | Eduardo Habkost | const char *cpu_model = args->cpu_model; |
138 | 5f072e1f | Eduardo Habkost | const char *kernel_filename = args->kernel_filename; |
139 | 5f072e1f | Eduardo Habkost | const char *kernel_cmdline = args->kernel_cmdline; |
140 | 5f072e1f | Eduardo Habkost | const char *initrd_filename = args->initrd_filename; |
141 | 5cea8590 | Paul Brook | char *filename;
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142 | 23ebf23d | Avi Kivity | MemoryRegion *address_space_mem = get_system_memory(); |
143 | 23ebf23d | Avi Kivity | MemoryRegion *ram = g_new(MemoryRegion, 1);
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144 | 23ebf23d | Avi Kivity | MemoryRegion *bios = g_new(MemoryRegion, 1);
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145 | 7ee274c1 | Andreas Färber | MIPSCPU *cpu; |
146 | 61c56c8c | Andreas Färber | CPUMIPSState *env; |
147 | e16ad5b0 | Aurelien Jarno | ResetData *reset_info; |
148 | b5334159 | ths | int bios_size;
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149 | f0fc6f8f | ths | |
150 | f0fc6f8f | ths | /* Init CPUs. */
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151 | f0fc6f8f | ths | if (cpu_model == NULL) { |
152 | f0fc6f8f | ths | #ifdef TARGET_MIPS64
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153 | f0fc6f8f | ths | cpu_model = "5Kf";
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154 | f0fc6f8f | ths | #else
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155 | f0fc6f8f | ths | cpu_model = "24Kf";
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156 | f0fc6f8f | ths | #endif
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157 | f0fc6f8f | ths | } |
158 | 7ee274c1 | Andreas Färber | cpu = cpu_mips_init(cpu_model); |
159 | 7ee274c1 | Andreas Färber | if (cpu == NULL) { |
160 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
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161 | aaed909a | bellard | exit(1);
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162 | aaed909a | bellard | } |
163 | 7ee274c1 | Andreas Färber | env = &cpu->env; |
164 | 7ee274c1 | Andreas Färber | |
165 | 7267c094 | Anthony Liguori | reset_info = g_malloc0(sizeof(ResetData));
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166 | 2d44fc8e | Andreas Färber | reset_info->cpu = cpu; |
167 | e16ad5b0 | Aurelien Jarno | reset_info->vector = env->active_tc.PC; |
168 | e16ad5b0 | Aurelien Jarno | qemu_register_reset(main_cpu_reset, reset_info); |
169 | f0fc6f8f | ths | |
170 | f0fc6f8f | ths | /* Allocate RAM. */
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171 | c5705a77 | Avi Kivity | memory_region_init_ram(ram, "mips_mipssim.ram", ram_size);
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172 | c5705a77 | Avi Kivity | vmstate_register_ram_global(ram); |
173 | c5705a77 | Avi Kivity | memory_region_init_ram(bios, "mips_mipssim.bios", BIOS_SIZE);
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174 | c5705a77 | Avi Kivity | vmstate_register_ram_global(bios); |
175 | 23ebf23d | Avi Kivity | memory_region_set_readonly(bios, true);
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176 | f0fc6f8f | ths | |
177 | 23ebf23d | Avi Kivity | memory_region_add_subregion(address_space_mem, 0, ram);
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178 | dcac9679 | pbrook | |
179 | dcac9679 | pbrook | /* Map the BIOS / boot exception handler. */
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180 | 23ebf23d | Avi Kivity | memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
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181 | f0fc6f8f | ths | /* Load a BIOS / boot exception handler image. */
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182 | f0fc6f8f | ths | if (bios_name == NULL) |
183 | f0fc6f8f | ths | bios_name = BIOS_FILENAME; |
184 | 5cea8590 | Paul Brook | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
185 | 5cea8590 | Paul Brook | if (filename) {
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186 | 5cea8590 | Paul Brook | bios_size = load_image_targphys(filename, 0x1fc00000LL, BIOS_SIZE);
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187 | 7267c094 | Anthony Liguori | g_free(filename); |
188 | 5cea8590 | Paul Brook | } else {
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189 | 5cea8590 | Paul Brook | bios_size = -1;
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190 | 5cea8590 | Paul Brook | } |
191 | b5334159 | ths | if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) { |
192 | f0fc6f8f | ths | /* Bail out if we have neither a kernel image nor boot vector code. */
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193 | f0fc6f8f | ths | fprintf(stderr, |
194 | f0fc6f8f | ths | "qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
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195 | 5cea8590 | Paul Brook | filename); |
196 | f0fc6f8f | ths | exit(1);
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197 | f0fc6f8f | ths | } else {
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198 | b5334159 | ths | /* We have a boot vector start address. */
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199 | b5dc7732 | ths | env->active_tc.PC = (target_long)(int32_t)0xbfc00000;
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200 | f0fc6f8f | ths | } |
201 | f0fc6f8f | ths | |
202 | f0fc6f8f | ths | if (kernel_filename) {
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203 | 7df526e3 | ths | loaderparams.ram_size = ram_size; |
204 | 7df526e3 | ths | loaderparams.kernel_filename = kernel_filename; |
205 | 7df526e3 | ths | loaderparams.kernel_cmdline = kernel_cmdline; |
206 | 7df526e3 | ths | loaderparams.initrd_filename = initrd_filename; |
207 | e16ad5b0 | Aurelien Jarno | reset_info->vector = load_kernel(); |
208 | f0fc6f8f | ths | } |
209 | f0fc6f8f | ths | |
210 | f0fc6f8f | ths | /* Init CPU internal devices. */
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211 | f0fc6f8f | ths | cpu_mips_irq_init_cpu(env); |
212 | f0fc6f8f | ths | cpu_mips_clock_init(env); |
213 | f0fc6f8f | ths | |
214 | f0fc6f8f | ths | /* Register 64 KB of ISA IO space at 0x1fd00000. */
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215 | 968d683c | Alexander Graf | isa_mmio_init(0x1fd00000, 0x00010000); |
216 | f0fc6f8f | ths | |
217 | f0fc6f8f | ths | /* A single 16450 sits at offset 0x3f8. It is attached to
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218 | f0fc6f8f | ths | MIPS CPU INT2, which is interrupt 4. */
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219 | f0fc6f8f | ths | if (serial_hds[0]) |
220 | 568fd159 | Julien Grall | serial_init(0x3f8, env->irq[4], 115200, serial_hds[0], |
221 | 568fd159 | Julien Grall | get_system_io()); |
222 | f0fc6f8f | ths | |
223 | a005d073 | Stefan Hajnoczi | if (nd_table[0].used) |
224 | 0ae18cee | aliguori | /* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */
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225 | 0ae18cee | aliguori | mipsnet_init(0x4200, env->irq[2], &nd_table[0]); |
226 | f0fc6f8f | ths | } |
227 | f0fc6f8f | ths | |
228 | f80f9ec9 | Anthony Liguori | static QEMUMachine mips_mipssim_machine = {
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229 | eec2743e | ths | .name = "mipssim",
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230 | eec2743e | ths | .desc = "MIPS MIPSsim platform",
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231 | eec2743e | ths | .init = mips_mipssim_init, |
232 | f0fc6f8f | ths | }; |
233 | f80f9ec9 | Anthony Liguori | |
234 | f80f9ec9 | Anthony Liguori | static void mips_mipssim_machine_init(void) |
235 | f80f9ec9 | Anthony Liguori | { |
236 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&mips_mipssim_machine); |
237 | f80f9ec9 | Anthony Liguori | } |
238 | f80f9ec9 | Anthony Liguori | |
239 | f80f9ec9 | Anthony Liguori | machine_init(mips_mipssim_machine_init); |