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1	7a3f1944	bellard	/*
2	7a3f1944	bellard	SPARC translation
3	7a3f1944	bellard
4	7a3f1944	bellard	Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5	3475187d	bellard	Copyright (C) 2003-2005 Fabrice Bellard
6	7a3f1944	bellard
7	7a3f1944	bellard	This library is free software; you can redistribute it and/or
8	7a3f1944	bellard	modify it under the terms of the GNU Lesser General Public
9	7a3f1944	bellard	License as published by the Free Software Foundation; either
10	7a3f1944	bellard	version 2 of the License, or (at your option) any later version.
11	7a3f1944	bellard
12	7a3f1944	bellard	This library is distributed in the hope that it will be useful,
13	7a3f1944	bellard	but WITHOUT ANY WARRANTY; without even the implied warranty of
14	7a3f1944	bellard	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15	7a3f1944	bellard	Lesser General Public License for more details.
16	7a3f1944	bellard
17	7a3f1944	bellard	You should have received a copy of the GNU Lesser General Public
18	7a3f1944	bellard	License along with this library; if not, write to the Free Software
19	7a3f1944	bellard	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20	7a3f1944	bellard	*/
21	7a3f1944	bellard
22	7a3f1944	bellard	#include <stdarg.h>
23	7a3f1944	bellard	#include <stdlib.h>
24	7a3f1944	bellard	#include <stdio.h>
25	7a3f1944	bellard	#include <string.h>
26	7a3f1944	bellard	#include <inttypes.h>
27	7a3f1944	bellard
28	7a3f1944	bellard	#include "cpu.h"
29	7a3f1944	bellard	#include "exec-all.h"
30	7a3f1944	bellard	#include "disas.h"
31	1a2fb1c0	blueswir1	#include "helper.h"
32	57fec1fe	bellard	#include "tcg-op.h"
33	7a3f1944	bellard
34	7a3f1944	bellard	#define DEBUG_DISAS
35	7a3f1944	bellard
36	72cbca10	bellard	#define DYNAMIC_PC 1 /* dynamic pc value */
37	72cbca10	bellard	#define JUMP_PC 2 /* dynamic pc value which takes only two values
38	72cbca10	bellard	according to jump_pc[T2] */
39	72cbca10	bellard
40	1a2fb1c0	blueswir1	/* global register indexes */
41	d987963a	blueswir1	static TCGv cpu_env, cpu_regwptr;
42	77f193da	blueswir1	static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
43	48d5c82b	blueswir1	static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
44	6ae20372	blueswir1	static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
45	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
46	dc99a3f2	blueswir1	static TCGv cpu_xcc;
47	dc99a3f2	blueswir1	#endif
48	1a2fb1c0	blueswir1	/* local register indexes (only used inside old micro ops) */
49	8911f501	blueswir1	static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
50	1a2fb1c0	blueswir1
51	2e70f6ef	pbrook	#include "gen-icount.h"
52	2e70f6ef	pbrook
53	7a3f1944	bellard	typedef struct DisasContext {
54	0f8a249a	blueswir1	target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
55	0f8a249a	blueswir1	target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
56	72cbca10	bellard	target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
57	cf495bcf	bellard	int is_br;
58	e8af50a3	bellard	int mem_idx;
59	a80dde08	bellard	int fpu_enabled;
60	2cade6a3	blueswir1	int address_mask_32bit;
61	cf495bcf	bellard	struct TranslationBlock *tb;
62	5578ceab	blueswir1	sparc_def_t *def;
63	7a3f1944	bellard	} DisasContext;
64	7a3f1944	bellard
65	3475187d	bellard	// This function uses non-native bit order
66	7a3f1944	bellard	#define GET_FIELD(X, FROM, TO) \
67	7a3f1944	bellard	((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
68	7a3f1944	bellard
69	3475187d	bellard	// This function uses the order in the manuals, i.e. bit 0 is 2^0
70	3475187d	bellard	#define GET_FIELD_SP(X, FROM, TO) \
71	3475187d	bellard	GET_FIELD(X, 31 - (TO), 31 - (FROM))
72	3475187d	bellard
73	3475187d	bellard	#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
74	46d38ba8	blueswir1	#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
75	3475187d	bellard
76	3475187d	bellard	#ifdef TARGET_SPARC64
77	19f329ad	blueswir1	#define FFPREG(r) (r)
78	0387d928	blueswir1	#define DFPREG(r) (((r & 1) << 5) \| (r & 0x1e))
79	1f587329	blueswir1	#define QFPREG(r) (((r & 1) << 5) \| (r & 0x1c))
80	3475187d	bellard	#else
81	19f329ad	blueswir1	#define FFPREG(r) (r)
82	c185970a	blueswir1	#define DFPREG(r) (r & 0x1e)
83	1f587329	blueswir1	#define QFPREG(r) (r & 0x1c)
84	3475187d	bellard	#endif
85	3475187d	bellard
86	3475187d	bellard	static int sign_extend(int x, int len)
87	3475187d	bellard	{
88	3475187d	bellard	len = 32 - len;
89	3475187d	bellard	return (x << len) >> len;
90	3475187d	bellard	}
91	3475187d	bellard
92	7a3f1944	bellard	#define IS_IMM (insn & (1<<13))
93	7a3f1944	bellard
94	ff07ec83	blueswir1	/* floating point registers moves */
95	ff07ec83	blueswir1	static void gen_op_load_fpr_FT0(unsigned int src)
96	ff07ec83	blueswir1	{
97	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
98	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
99	3475187d	bellard	}
100	ff07ec83	blueswir1
101	ff07ec83	blueswir1	static void gen_op_load_fpr_FT1(unsigned int src)
102	ff07ec83	blueswir1	{
103	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
104	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
105	e8af50a3	bellard	}
106	e8af50a3	bellard
107	ff07ec83	blueswir1	static void gen_op_store_FT0_fpr(unsigned int dst)
108	ff07ec83	blueswir1	{
109	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
110	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
111	ff07ec83	blueswir1	}
112	ff07ec83	blueswir1
113	ff07ec83	blueswir1	static void gen_op_load_fpr_DT0(unsigned int src)
114	ff07ec83	blueswir1	{
115	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
116	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
117	77f193da	blueswir1	offsetof(CPU_DoubleU, l.upper));
118	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
119	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
120	77f193da	blueswir1	offsetof(CPU_DoubleU, l.lower));
121	ff07ec83	blueswir1	}
122	ff07ec83	blueswir1
123	ff07ec83	blueswir1	static void gen_op_load_fpr_DT1(unsigned int src)
124	ff07ec83	blueswir1	{
125	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
126	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
127	77f193da	blueswir1	offsetof(CPU_DoubleU, l.upper));
128	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
129	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
130	77f193da	blueswir1	offsetof(CPU_DoubleU, l.lower));
131	ff07ec83	blueswir1	}
132	ff07ec83	blueswir1
133	ff07ec83	blueswir1	static void gen_op_store_DT0_fpr(unsigned int dst)
134	ff07ec83	blueswir1	{
135	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
136	77f193da	blueswir1	offsetof(CPU_DoubleU, l.upper));
137	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
138	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
139	77f193da	blueswir1	offsetof(CPU_DoubleU, l.lower));
140	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
141	ff07ec83	blueswir1	}
142	ff07ec83	blueswir1
143	ff07ec83	blueswir1	static void gen_op_load_fpr_QT0(unsigned int src)
144	ff07ec83	blueswir1	{
145	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
146	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
147	77f193da	blueswir1	offsetof(CPU_QuadU, l.upmost));
148	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
149	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
150	77f193da	blueswir1	offsetof(CPU_QuadU, l.upper));
151	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
152	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
153	77f193da	blueswir1	offsetof(CPU_QuadU, l.lower));
154	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
155	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
156	77f193da	blueswir1	offsetof(CPU_QuadU, l.lowest));
157	ff07ec83	blueswir1	}
158	ff07ec83	blueswir1
159	ff07ec83	blueswir1	static void gen_op_load_fpr_QT1(unsigned int src)
160	ff07ec83	blueswir1	{
161	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
162	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
163	77f193da	blueswir1	offsetof(CPU_QuadU, l.upmost));
164	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
165	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
166	77f193da	blueswir1	offsetof(CPU_QuadU, l.upper));
167	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
168	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
169	77f193da	blueswir1	offsetof(CPU_QuadU, l.lower));
170	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
171	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
172	77f193da	blueswir1	offsetof(CPU_QuadU, l.lowest));
173	ff07ec83	blueswir1	}
174	ff07ec83	blueswir1
175	ff07ec83	blueswir1	static void gen_op_store_QT0_fpr(unsigned int dst)
176	ff07ec83	blueswir1	{
177	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
178	77f193da	blueswir1	offsetof(CPU_QuadU, l.upmost));
179	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
180	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
181	77f193da	blueswir1	offsetof(CPU_QuadU, l.upper));
182	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
183	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
184	77f193da	blueswir1	offsetof(CPU_QuadU, l.lower));
185	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
186	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
187	77f193da	blueswir1	offsetof(CPU_QuadU, l.lowest));
188	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
189	ff07ec83	blueswir1	}
190	1f587329	blueswir1
191	81ad8ba2	blueswir1	/* moves */
192	81ad8ba2	blueswir1	#ifdef CONFIG_USER_ONLY
193	3475187d	bellard	#define supervisor(dc) 0
194	81ad8ba2	blueswir1	#ifdef TARGET_SPARC64
195	e9ebed4d	blueswir1	#define hypervisor(dc) 0
196	81ad8ba2	blueswir1	#endif
197	3475187d	bellard	#else
198	6f27aba6	blueswir1	#define supervisor(dc) (dc->mem_idx >= 1)
199	81ad8ba2	blueswir1	#ifdef TARGET_SPARC64
200	81ad8ba2	blueswir1	#define hypervisor(dc) (dc->mem_idx == 2)
201	6f27aba6	blueswir1	#else
202	3475187d	bellard	#endif
203	81ad8ba2	blueswir1	#endif
204	81ad8ba2	blueswir1
205	2cade6a3	blueswir1	#ifdef TARGET_SPARC64
206	2cade6a3	blueswir1	#ifndef TARGET_ABI32
207	2cade6a3	blueswir1	#define AM_CHECK(dc) ((dc)->address_mask_32bit)
208	1a2fb1c0	blueswir1	#else
209	2cade6a3	blueswir1	#define AM_CHECK(dc) (1)
210	2cade6a3	blueswir1	#endif
211	1a2fb1c0	blueswir1	#endif
212	3391c818	blueswir1
213	2cade6a3	blueswir1	static inline void gen_address_mask(DisasContext *dc, TCGv addr)
214	2cade6a3	blueswir1	{
215	2cade6a3	blueswir1	#ifdef TARGET_SPARC64
216	2cade6a3	blueswir1	if (AM_CHECK(dc))
217	2cade6a3	blueswir1	tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
218	2cade6a3	blueswir1	#endif
219	2cade6a3	blueswir1	}
220	2cade6a3	blueswir1
221	1a2fb1c0	blueswir1	static inline void gen_movl_reg_TN(int reg, TCGv tn)
222	81ad8ba2	blueswir1	{
223	1a2fb1c0	blueswir1	if (reg == 0)
224	1a2fb1c0	blueswir1	tcg_gen_movi_tl(tn, 0);
225	1a2fb1c0	blueswir1	else if (reg < 8)
226	f5069b26	blueswir1	tcg_gen_mov_tl(tn, cpu_gregs[reg]);
227	1a2fb1c0	blueswir1	else {
228	1a2fb1c0	blueswir1	tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
229	81ad8ba2	blueswir1	}
230	81ad8ba2	blueswir1	}
231	81ad8ba2	blueswir1
232	1a2fb1c0	blueswir1	static inline void gen_movl_TN_reg(int reg, TCGv tn)
233	81ad8ba2	blueswir1	{
234	1a2fb1c0	blueswir1	if (reg == 0)
235	1a2fb1c0	blueswir1	return;
236	1a2fb1c0	blueswir1	else if (reg < 8)
237	f5069b26	blueswir1	tcg_gen_mov_tl(cpu_gregs[reg], tn);
238	1a2fb1c0	blueswir1	else {
239	1a2fb1c0	blueswir1	tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
240	81ad8ba2	blueswir1	}
241	81ad8ba2	blueswir1	}
242	81ad8ba2	blueswir1
243	5fafdf24	ths	static inline void gen_goto_tb(DisasContext *s, int tb_num,
244	6e256c93	bellard	target_ulong pc, target_ulong npc)
245	6e256c93	bellard	{
246	6e256c93	bellard	TranslationBlock *tb;
247	6e256c93	bellard
248	6e256c93	bellard	tb = s->tb;
249	6e256c93	bellard	if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
250	6e256c93	bellard	(npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
251	6e256c93	bellard	/* jump to same page: we can use a direct jump */
252	57fec1fe	bellard	tcg_gen_goto_tb(tb_num);
253	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_pc, pc);
254	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_npc, npc);
255	57fec1fe	bellard	tcg_gen_exit_tb((long)tb + tb_num);
256	6e256c93	bellard	} else {
257	6e256c93	bellard	/* jump to another page: currently not optimized */
258	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_pc, pc);
259	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_npc, npc);
260	57fec1fe	bellard	tcg_gen_exit_tb(0);
261	6e256c93	bellard	}
262	6e256c93	bellard	}
263	6e256c93	bellard
264	19f329ad	blueswir1	// XXX suboptimal
265	19f329ad	blueswir1	static inline void gen_mov_reg_N(TCGv reg, TCGv src)
266	19f329ad	blueswir1	{
267	8911f501	blueswir1	tcg_gen_extu_i32_tl(reg, src);
268	4b8b8b76	blueswir1	tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
269	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
270	19f329ad	blueswir1	}
271	19f329ad	blueswir1
272	19f329ad	blueswir1	static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
273	19f329ad	blueswir1	{
274	8911f501	blueswir1	tcg_gen_extu_i32_tl(reg, src);
275	4b8b8b76	blueswir1	tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
276	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
277	19f329ad	blueswir1	}
278	19f329ad	blueswir1
279	19f329ad	blueswir1	static inline void gen_mov_reg_V(TCGv reg, TCGv src)
280	19f329ad	blueswir1	{
281	8911f501	blueswir1	tcg_gen_extu_i32_tl(reg, src);
282	4b8b8b76	blueswir1	tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
283	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
284	19f329ad	blueswir1	}
285	19f329ad	blueswir1
286	19f329ad	blueswir1	static inline void gen_mov_reg_C(TCGv reg, TCGv src)
287	19f329ad	blueswir1	{
288	8911f501	blueswir1	tcg_gen_extu_i32_tl(reg, src);
289	4b8b8b76	blueswir1	tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
290	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
291	19f329ad	blueswir1	}
292	19f329ad	blueswir1
293	ce5b3c3d	blueswir1	static inline void gen_cc_clear_icc(void)
294	dc99a3f2	blueswir1	{
295	dc99a3f2	blueswir1	tcg_gen_movi_i32(cpu_psr, 0);
296	ce5b3c3d	blueswir1	}
297	ce5b3c3d	blueswir1
298	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
299	ce5b3c3d	blueswir1	static inline void gen_cc_clear_xcc(void)
300	ce5b3c3d	blueswir1	{
301	dc99a3f2	blueswir1	tcg_gen_movi_i32(cpu_xcc, 0);
302	dc99a3f2	blueswir1	}
303	ce5b3c3d	blueswir1	#endif
304	dc99a3f2	blueswir1
305	dc99a3f2	blueswir1	/* old op:
306	dc99a3f2	blueswir1	if (!T0)
307	dc99a3f2	blueswir1	env->psr \|= PSR_ZERO;
308	dc99a3f2	blueswir1	if ((int32_t) T0 < 0)
309	dc99a3f2	blueswir1	env->psr \|= PSR_NEG;
310	dc99a3f2	blueswir1	*/
311	ce5b3c3d	blueswir1	static inline void gen_cc_NZ_icc(TCGv dst)
312	dc99a3f2	blueswir1	{
313	8911f501	blueswir1	TCGv r_temp;
314	dc99a3f2	blueswir1	int l1, l2;
315	dc99a3f2	blueswir1
316	dc99a3f2	blueswir1	l1 = gen_new_label();
317	dc99a3f2	blueswir1	l2 = gen_new_label();
318	8911f501	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
319	8911f501	blueswir1	tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
320	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
321	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
322	dc99a3f2	blueswir1	gen_set_label(l1);
323	bdf46ea2	blueswir1	tcg_gen_ext_i32_tl(r_temp, dst);
324	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
325	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
326	dc99a3f2	blueswir1	gen_set_label(l2);
327	2ea815ca	blueswir1	tcg_temp_free(r_temp);
328	ce5b3c3d	blueswir1	}
329	ce5b3c3d	blueswir1
330	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
331	ce5b3c3d	blueswir1	static inline void gen_cc_NZ_xcc(TCGv dst)
332	ce5b3c3d	blueswir1	{
333	ce5b3c3d	blueswir1	int l1, l2;
334	ce5b3c3d	blueswir1
335	ce5b3c3d	blueswir1	l1 = gen_new_label();
336	ce5b3c3d	blueswir1	l2 = gen_new_label();
337	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
338	ce5b3c3d	blueswir1	tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
339	ce5b3c3d	blueswir1	gen_set_label(l1);
340	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
341	ce5b3c3d	blueswir1	tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
342	ce5b3c3d	blueswir1	gen_set_label(l2);
343	dc99a3f2	blueswir1	}
344	ce5b3c3d	blueswir1	#endif
345	dc99a3f2	blueswir1
346	dc99a3f2	blueswir1	/* old op:
347	dc99a3f2	blueswir1	if (T0 < src1)
348	dc99a3f2	blueswir1	env->psr \|= PSR_CARRY;
349	dc99a3f2	blueswir1	*/
350	ce5b3c3d	blueswir1	static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
351	dc99a3f2	blueswir1	{
352	2ae72bce	blueswir1	TCGv r_temp1, r_temp2;
353	dc99a3f2	blueswir1	int l1;
354	dc99a3f2	blueswir1
355	dc99a3f2	blueswir1	l1 = gen_new_label();
356	2ae72bce	blueswir1	r_temp1 = tcg_temp_new(TCG_TYPE_TL);
357	2ae72bce	blueswir1	r_temp2 = tcg_temp_new(TCG_TYPE_TL);
358	2ae72bce	blueswir1	tcg_gen_andi_tl(r_temp1, dst, 0xffffffffULL);
359	2ae72bce	blueswir1	tcg_gen_andi_tl(r_temp2, src1, 0xffffffffULL);
360	2ae72bce	blueswir1	tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
361	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
362	dc99a3f2	blueswir1	gen_set_label(l1);
363	2ae72bce	blueswir1	tcg_temp_free(r_temp1);
364	2ae72bce	blueswir1	tcg_temp_free(r_temp2);
365	ce5b3c3d	blueswir1	}
366	ce5b3c3d	blueswir1
367	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
368	ce5b3c3d	blueswir1	static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
369	ce5b3c3d	blueswir1	{
370	ce5b3c3d	blueswir1	int l1;
371	dc99a3f2	blueswir1
372	ce5b3c3d	blueswir1	l1 = gen_new_label();
373	ce5b3c3d	blueswir1	tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
374	ce5b3c3d	blueswir1	tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
375	ce5b3c3d	blueswir1	gen_set_label(l1);
376	dc99a3f2	blueswir1	}
377	ce5b3c3d	blueswir1	#endif
378	dc99a3f2	blueswir1
379	dc99a3f2	blueswir1	/* old op:
380	dc99a3f2	blueswir1	if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
381	dc99a3f2	blueswir1	env->psr \|= PSR_OVF;
382	dc99a3f2	blueswir1	*/
383	ce5b3c3d	blueswir1	static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
384	dc99a3f2	blueswir1	{
385	0425bee5	blueswir1	TCGv r_temp;
386	dc99a3f2	blueswir1
387	dc99a3f2	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
388	dc99a3f2	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
389	dc99a3f2	blueswir1	tcg_gen_xori_tl(r_temp, r_temp, -1);
390	0425bee5	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
391	0425bee5	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
392	dd5e6304	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
393	653ccb80	blueswir1	tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
394	653ccb80	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
395	2ea815ca	blueswir1	tcg_temp_free(r_temp);
396	653ccb80	blueswir1	tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
397	ce5b3c3d	blueswir1	}
398	ce5b3c3d	blueswir1
399	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
400	ce5b3c3d	blueswir1	static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
401	ce5b3c3d	blueswir1	{
402	ce5b3c3d	blueswir1	TCGv r_temp;
403	ce5b3c3d	blueswir1
404	ce5b3c3d	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
405	ce5b3c3d	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
406	ce5b3c3d	blueswir1	tcg_gen_xori_tl(r_temp, r_temp, -1);
407	ce5b3c3d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
408	ce5b3c3d	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
409	ce5b3c3d	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
410	653ccb80	blueswir1	tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
411	653ccb80	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
412	2ea815ca	blueswir1	tcg_temp_free(r_temp);
413	653ccb80	blueswir1	tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
414	dc99a3f2	blueswir1	}
415	ce5b3c3d	blueswir1	#endif
416	dc99a3f2	blueswir1
417	dc99a3f2	blueswir1	static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
418	dc99a3f2	blueswir1	{
419	2ea815ca	blueswir1	TCGv r_temp, r_const;
420	dc99a3f2	blueswir1	int l1;
421	dc99a3f2	blueswir1
422	dc99a3f2	blueswir1	l1 = gen_new_label();
423	dc99a3f2	blueswir1
424	dc99a3f2	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
425	dc99a3f2	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
426	dc99a3f2	blueswir1	tcg_gen_xori_tl(r_temp, r_temp, -1);
427	0425bee5	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
428	0425bee5	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
429	dd5e6304	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
430	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
431	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_TOVF);
432	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
433	2ea815ca	blueswir1	tcg_temp_free(r_const);
434	dc99a3f2	blueswir1	gen_set_label(l1);
435	2ea815ca	blueswir1	tcg_temp_free(r_temp);
436	dc99a3f2	blueswir1	}
437	dc99a3f2	blueswir1
438	dc99a3f2	blueswir1	static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
439	dc99a3f2	blueswir1	{
440	dc99a3f2	blueswir1	int l1;
441	dc99a3f2	blueswir1
442	dc99a3f2	blueswir1	l1 = gen_new_label();
443	0425bee5	blueswir1	tcg_gen_or_tl(cpu_tmp0, src1, src2);
444	0425bee5	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
445	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
446	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
447	dc99a3f2	blueswir1	gen_set_label(l1);
448	dc99a3f2	blueswir1	}
449	dc99a3f2	blueswir1
450	dc99a3f2	blueswir1	static inline void gen_tag_tv(TCGv src1, TCGv src2)
451	dc99a3f2	blueswir1	{
452	dc99a3f2	blueswir1	int l1;
453	2ea815ca	blueswir1	TCGv r_const;
454	dc99a3f2	blueswir1
455	dc99a3f2	blueswir1	l1 = gen_new_label();
456	0425bee5	blueswir1	tcg_gen_or_tl(cpu_tmp0, src1, src2);
457	0425bee5	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
458	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
459	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_TOVF);
460	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
461	2ea815ca	blueswir1	tcg_temp_free(r_const);
462	dc99a3f2	blueswir1	gen_set_label(l1);
463	dc99a3f2	blueswir1	}
464	dc99a3f2	blueswir1
465	4af984a7	blueswir1	static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
466	dc99a3f2	blueswir1	{
467	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
468	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
469	5c6a0628	blueswir1	tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
470	ce5b3c3d	blueswir1	gen_cc_clear_icc();
471	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
472	ba28189b	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
473	ba28189b	blueswir1	gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
474	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
475	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
476	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
477	ba28189b	blueswir1	gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
478	ba28189b	blueswir1	gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
479	ce5b3c3d	blueswir1	#endif
480	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
481	dc99a3f2	blueswir1	}
482	dc99a3f2	blueswir1
483	4af984a7	blueswir1	static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
484	dc99a3f2	blueswir1	{
485	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
486	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
487	dc99a3f2	blueswir1	gen_mov_reg_C(cpu_tmp0, cpu_psr);
488	5c6a0628	blueswir1	tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
489	ce5b3c3d	blueswir1	gen_cc_clear_icc();
490	5c6a0628	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
491	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
492	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
493	5c6a0628	blueswir1	gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
494	ce5b3c3d	blueswir1	#endif
495	5c6a0628	blueswir1	tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
496	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
497	ba28189b	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
498	ba28189b	blueswir1	gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
499	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
500	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
501	ba28189b	blueswir1	gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
502	ba28189b	blueswir1	gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
503	ce5b3c3d	blueswir1	#endif
504	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
505	dc99a3f2	blueswir1	}
506	dc99a3f2	blueswir1
507	4af984a7	blueswir1	static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
508	dc99a3f2	blueswir1	{
509	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
510	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
511	5c6a0628	blueswir1	tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
512	ce5b3c3d	blueswir1	gen_cc_clear_icc();
513	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
514	ba28189b	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
515	ba28189b	blueswir1	gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
516	6f551262	blueswir1	gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
517	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
518	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
519	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
520	ba28189b	blueswir1	gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
521	ba28189b	blueswir1	gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
522	ce5b3c3d	blueswir1	#endif
523	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
524	dc99a3f2	blueswir1	}
525	dc99a3f2	blueswir1
526	4af984a7	blueswir1	static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
527	dc99a3f2	blueswir1	{
528	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
529	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
530	6f551262	blueswir1	gen_tag_tv(cpu_cc_src, cpu_cc_src2);
531	5c6a0628	blueswir1	tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
532	5c6a0628	blueswir1	gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
533	ce5b3c3d	blueswir1	gen_cc_clear_icc();
534	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
535	ba28189b	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
536	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
537	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
538	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
539	ba28189b	blueswir1	gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
540	ba28189b	blueswir1	gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
541	ce5b3c3d	blueswir1	#endif
542	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
543	dc99a3f2	blueswir1	}
544	dc99a3f2	blueswir1
545	dc99a3f2	blueswir1	/* old op:
546	dc99a3f2	blueswir1	if (src1 < T1)
547	dc99a3f2	blueswir1	env->psr \|= PSR_CARRY;
548	dc99a3f2	blueswir1	*/
549	ce5b3c3d	blueswir1	static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
550	dc99a3f2	blueswir1	{
551	8911f501	blueswir1	TCGv r_temp1, r_temp2;
552	dc99a3f2	blueswir1	int l1;
553	dc99a3f2	blueswir1
554	dc99a3f2	blueswir1	l1 = gen_new_label();
555	8911f501	blueswir1	r_temp1 = tcg_temp_new(TCG_TYPE_TL);
556	8911f501	blueswir1	r_temp2 = tcg_temp_new(TCG_TYPE_TL);
557	8911f501	blueswir1	tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
558	8911f501	blueswir1	tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
559	8911f501	blueswir1	tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
560	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
561	dc99a3f2	blueswir1	gen_set_label(l1);
562	2ea815ca	blueswir1	tcg_temp_free(r_temp1);
563	2ea815ca	blueswir1	tcg_temp_free(r_temp2);
564	ce5b3c3d	blueswir1	}
565	ce5b3c3d	blueswir1
566	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
567	ce5b3c3d	blueswir1	static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
568	ce5b3c3d	blueswir1	{
569	ce5b3c3d	blueswir1	int l1;
570	dc99a3f2	blueswir1
571	ce5b3c3d	blueswir1	l1 = gen_new_label();
572	ce5b3c3d	blueswir1	tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
573	ce5b3c3d	blueswir1	tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
574	ce5b3c3d	blueswir1	gen_set_label(l1);
575	dc99a3f2	blueswir1	}
576	ce5b3c3d	blueswir1	#endif
577	dc99a3f2	blueswir1
578	dc99a3f2	blueswir1	/* old op:
579	dc99a3f2	blueswir1	if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
580	dc99a3f2	blueswir1	env->psr \|= PSR_OVF;
581	dc99a3f2	blueswir1	*/
582	ce5b3c3d	blueswir1	static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
583	dc99a3f2	blueswir1	{
584	0425bee5	blueswir1	TCGv r_temp;
585	dc99a3f2	blueswir1
586	dc99a3f2	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
587	dc99a3f2	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
588	0425bee5	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
589	0425bee5	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
590	dd5e6304	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
591	653ccb80	blueswir1	tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
592	653ccb80	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
593	653ccb80	blueswir1	tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
594	2ea815ca	blueswir1	tcg_temp_free(r_temp);
595	ce5b3c3d	blueswir1	}
596	ce5b3c3d	blueswir1
597	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
598	ce5b3c3d	blueswir1	static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
599	ce5b3c3d	blueswir1	{
600	ce5b3c3d	blueswir1	TCGv r_temp;
601	ce5b3c3d	blueswir1
602	ce5b3c3d	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
603	ce5b3c3d	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
604	ce5b3c3d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
605	ce5b3c3d	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
606	ce5b3c3d	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
607	653ccb80	blueswir1	tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
608	653ccb80	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
609	653ccb80	blueswir1	tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
610	2ea815ca	blueswir1	tcg_temp_free(r_temp);
611	dc99a3f2	blueswir1	}
612	ce5b3c3d	blueswir1	#endif
613	dc99a3f2	blueswir1
614	dc99a3f2	blueswir1	static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
615	dc99a3f2	blueswir1	{
616	2ea815ca	blueswir1	TCGv r_temp, r_const;
617	dc99a3f2	blueswir1	int l1;
618	dc99a3f2	blueswir1
619	dc99a3f2	blueswir1	l1 = gen_new_label();
620	dc99a3f2	blueswir1
621	dc99a3f2	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
622	dc99a3f2	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
623	0425bee5	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
624	0425bee5	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
625	dd5e6304	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
626	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
627	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_TOVF);
628	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
629	2ea815ca	blueswir1	tcg_temp_free(r_const);
630	dc99a3f2	blueswir1	gen_set_label(l1);
631	2ea815ca	blueswir1	tcg_temp_free(r_temp);
632	dc99a3f2	blueswir1	}
633	dc99a3f2	blueswir1
634	4af984a7	blueswir1	static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
635	dc99a3f2	blueswir1	{
636	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
637	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
638	5c6a0628	blueswir1	tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
639	ce5b3c3d	blueswir1	gen_cc_clear_icc();
640	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
641	6f551262	blueswir1	gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
642	ba28189b	blueswir1	gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
643	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
644	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
645	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
646	6f551262	blueswir1	gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
647	ba28189b	blueswir1	gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
648	ce5b3c3d	blueswir1	#endif
649	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
650	dc99a3f2	blueswir1	}
651	dc99a3f2	blueswir1
652	4af984a7	blueswir1	static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
653	dc99a3f2	blueswir1	{
654	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
655	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
656	dc99a3f2	blueswir1	gen_mov_reg_C(cpu_tmp0, cpu_psr);
657	5c6a0628	blueswir1	tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
658	ce5b3c3d	blueswir1	gen_cc_clear_icc();
659	5c6a0628	blueswir1	gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
660	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
661	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
662	5c6a0628	blueswir1	gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
663	ce5b3c3d	blueswir1	#endif
664	5c6a0628	blueswir1	tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
665	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
666	ba28189b	blueswir1	gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
667	ba28189b	blueswir1	gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
668	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
669	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
670	ba28189b	blueswir1	gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
671	ba28189b	blueswir1	gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
672	ce5b3c3d	blueswir1	#endif
673	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
674	dc99a3f2	blueswir1	}
675	dc99a3f2	blueswir1
676	4af984a7	blueswir1	static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
677	dc99a3f2	blueswir1	{
678	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
679	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
680	5c6a0628	blueswir1	tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
681	ce5b3c3d	blueswir1	gen_cc_clear_icc();
682	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
683	6f551262	blueswir1	gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
684	ba28189b	blueswir1	gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
685	6f551262	blueswir1	gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
686	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
687	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
688	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
689	6f551262	blueswir1	gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
690	ba28189b	blueswir1	gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
691	ce5b3c3d	blueswir1	#endif
692	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
693	dc99a3f2	blueswir1	}
694	dc99a3f2	blueswir1
695	4af984a7	blueswir1	static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
696	dc99a3f2	blueswir1	{
697	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
698	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
699	6f551262	blueswir1	gen_tag_tv(cpu_cc_src, cpu_cc_src2);
700	5c6a0628	blueswir1	tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
701	5c6a0628	blueswir1	gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
702	ce5b3c3d	blueswir1	gen_cc_clear_icc();
703	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
704	6f551262	blueswir1	gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
705	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
706	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
707	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
708	6f551262	blueswir1	gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
709	ba28189b	blueswir1	gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
710	ce5b3c3d	blueswir1	#endif
711	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
712	dc99a3f2	blueswir1	}
713	dc99a3f2	blueswir1
714	4af984a7	blueswir1	static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
715	d9bdab86	blueswir1	{
716	7127fe84	blueswir1	TCGv r_temp, r_temp2;
717	6f551262	blueswir1	int l1;
718	d9bdab86	blueswir1
719	d9bdab86	blueswir1	l1 = gen_new_label();
720	d9bdab86	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
721	7127fe84	blueswir1	r_temp2 = tcg_temp_new(TCG_TYPE_I32);
722	d9bdab86	blueswir1
723	d9bdab86	blueswir1	/* old op:
724	d9bdab86	blueswir1	if (!(env->y & 1))
725	d9bdab86	blueswir1	T1 = 0;
726	d9bdab86	blueswir1	*/
727	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
728	7127fe84	blueswir1	tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
729	7127fe84	blueswir1	tcg_gen_trunc_tl_i32(r_temp2, r_temp);
730	7127fe84	blueswir1	tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
731	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
732	cb63669a	pbrook	tcg_gen_brcondi_i32(TCG_COND_NE, r_temp2, 0, l1);
733	d9bdab86	blueswir1	tcg_gen_movi_tl(cpu_cc_src2, 0);
734	6f551262	blueswir1	gen_set_label(l1);
735	d9bdab86	blueswir1
736	d9bdab86	blueswir1	// b2 = T0 & 1;
737	d9bdab86	blueswir1	// env->y = (b2 << 31) \| (env->y >> 1);
738	6f551262	blueswir1	tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src);
739	7127fe84	blueswir1	tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
740	7127fe84	blueswir1	tcg_gen_shli_i32(r_temp2, r_temp2, 31);
741	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
742	8911f501	blueswir1	tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
743	7127fe84	blueswir1	tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
744	2ea815ca	blueswir1	tcg_temp_free(r_temp2);
745	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
746	d9bdab86	blueswir1
747	d9bdab86	blueswir1	// b1 = N ^ V;
748	d9bdab86	blueswir1	gen_mov_reg_N(cpu_tmp0, cpu_psr);
749	d9bdab86	blueswir1	gen_mov_reg_V(r_temp, cpu_psr);
750	d9bdab86	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
751	2ea815ca	blueswir1	tcg_temp_free(r_temp);
752	d9bdab86	blueswir1
753	d9bdab86	blueswir1	// T0 = (b1 << 31) \| (T0 >> 1);
754	d9bdab86	blueswir1	// src1 = T0;
755	d9bdab86	blueswir1	tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
756	6f551262	blueswir1	tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
757	d9bdab86	blueswir1	tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
758	d9bdab86	blueswir1
759	d9bdab86	blueswir1	/* do addition and update flags */
760	5c6a0628	blueswir1	tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
761	d9bdab86	blueswir1
762	ce5b3c3d	blueswir1	gen_cc_clear_icc();
763	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
764	ba28189b	blueswir1	gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
765	ba28189b	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
766	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
767	d9bdab86	blueswir1	}
768	d9bdab86	blueswir1
769	4af984a7	blueswir1	static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
770	8879d139	blueswir1	{
771	8879d139	blueswir1	TCGv r_temp, r_temp2;
772	8879d139	blueswir1
773	8879d139	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_I64);
774	8879d139	blueswir1	r_temp2 = tcg_temp_new(TCG_TYPE_I64);
775	8879d139	blueswir1
776	4af984a7	blueswir1	tcg_gen_extu_tl_i64(r_temp, src2);
777	4af984a7	blueswir1	tcg_gen_extu_tl_i64(r_temp2, src1);
778	8879d139	blueswir1	tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
779	8879d139	blueswir1
780	8879d139	blueswir1	tcg_gen_shri_i64(r_temp, r_temp2, 32);
781	8879d139	blueswir1	tcg_gen_trunc_i64_i32(r_temp, r_temp);
782	8879d139	blueswir1	tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
783	2ea815ca	blueswir1	tcg_temp_free(r_temp);
784	8879d139	blueswir1	#ifdef TARGET_SPARC64
785	4af984a7	blueswir1	tcg_gen_mov_i64(dst, r_temp2);
786	8879d139	blueswir1	#else
787	4af984a7	blueswir1	tcg_gen_trunc_i64_tl(dst, r_temp2);
788	8879d139	blueswir1	#endif
789	2ea815ca	blueswir1	tcg_temp_free(r_temp2);
790	8879d139	blueswir1	}
791	8879d139	blueswir1
792	4af984a7	blueswir1	static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
793	8879d139	blueswir1	{
794	8879d139	blueswir1	TCGv r_temp, r_temp2;
795	8879d139	blueswir1
796	8879d139	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_I64);
797	8879d139	blueswir1	r_temp2 = tcg_temp_new(TCG_TYPE_I64);
798	8879d139	blueswir1
799	4af984a7	blueswir1	tcg_gen_ext_tl_i64(r_temp, src2);
800	4af984a7	blueswir1	tcg_gen_ext_tl_i64(r_temp2, src1);
801	8879d139	blueswir1	tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
802	8879d139	blueswir1
803	8879d139	blueswir1	tcg_gen_shri_i64(r_temp, r_temp2, 32);
804	8879d139	blueswir1	tcg_gen_trunc_i64_i32(r_temp, r_temp);
805	8879d139	blueswir1	tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
806	2ea815ca	blueswir1	tcg_temp_free(r_temp);
807	8879d139	blueswir1	#ifdef TARGET_SPARC64
808	4af984a7	blueswir1	tcg_gen_mov_i64(dst, r_temp2);
809	8879d139	blueswir1	#else
810	4af984a7	blueswir1	tcg_gen_trunc_i64_tl(dst, r_temp2);
811	8879d139	blueswir1	#endif
812	2ea815ca	blueswir1	tcg_temp_free(r_temp2);
813	8879d139	blueswir1	}
814	8879d139	blueswir1
815	1a7b60e7	blueswir1	#ifdef TARGET_SPARC64
816	8911f501	blueswir1	static inline void gen_trap_ifdivzero_tl(TCGv divisor)
817	1a7b60e7	blueswir1	{
818	2ea815ca	blueswir1	TCGv r_const;
819	1a7b60e7	blueswir1	int l1;
820	1a7b60e7	blueswir1
821	1a7b60e7	blueswir1	l1 = gen_new_label();
822	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
823	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_DIV_ZERO);
824	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
825	2ea815ca	blueswir1	tcg_temp_free(r_const);
826	1a7b60e7	blueswir1	gen_set_label(l1);
827	1a7b60e7	blueswir1	}
828	1a7b60e7	blueswir1
829	4af984a7	blueswir1	static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
830	1a7b60e7	blueswir1	{
831	1a7b60e7	blueswir1	int l1, l2;
832	1a7b60e7	blueswir1
833	1a7b60e7	blueswir1	l1 = gen_new_label();
834	1a7b60e7	blueswir1	l2 = gen_new_label();
835	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
836	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
837	5c6a0628	blueswir1	gen_trap_ifdivzero_tl(cpu_cc_src2);
838	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1);
839	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
840	4af984a7	blueswir1	tcg_gen_movi_i64(dst, INT64_MIN);
841	06b3e1b3	blueswir1	tcg_gen_br(l2);
842	1a7b60e7	blueswir1	gen_set_label(l1);
843	6f551262	blueswir1	tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
844	1a7b60e7	blueswir1	gen_set_label(l2);
845	1a7b60e7	blueswir1	}
846	1a7b60e7	blueswir1	#endif
847	1a7b60e7	blueswir1
848	4af984a7	blueswir1	static inline void gen_op_div_cc(TCGv dst)
849	dc99a3f2	blueswir1	{
850	dc99a3f2	blueswir1	int l1;
851	dc99a3f2	blueswir1
852	ba28189b	blueswir1	tcg_gen_mov_tl(cpu_cc_dst, dst);
853	ce5b3c3d	blueswir1	gen_cc_clear_icc();
854	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
855	dc99a3f2	blueswir1	l1 = gen_new_label();
856	5c6a0628	blueswir1	tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1);
857	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
858	dc99a3f2	blueswir1	gen_set_label(l1);
859	dc99a3f2	blueswir1	}
860	dc99a3f2	blueswir1
861	4af984a7	blueswir1	static inline void gen_op_logic_cc(TCGv dst)
862	dc99a3f2	blueswir1	{
863	ba28189b	blueswir1	tcg_gen_mov_tl(cpu_cc_dst, dst);
864	ba28189b	blueswir1
865	ce5b3c3d	blueswir1	gen_cc_clear_icc();
866	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
867	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
868	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
869	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
870	ce5b3c3d	blueswir1	#endif
871	dc99a3f2	blueswir1	}
872	dc99a3f2	blueswir1
873	19f329ad	blueswir1	// 1
874	19f329ad	blueswir1	static inline void gen_op_eval_ba(TCGv dst)
875	19f329ad	blueswir1	{
876	19f329ad	blueswir1	tcg_gen_movi_tl(dst, 1);
877	19f329ad	blueswir1	}
878	19f329ad	blueswir1
879	19f329ad	blueswir1	// Z
880	19f329ad	blueswir1	static inline void gen_op_eval_be(TCGv dst, TCGv src)
881	19f329ad	blueswir1	{
882	19f329ad	blueswir1	gen_mov_reg_Z(dst, src);
883	19f329ad	blueswir1	}
884	19f329ad	blueswir1
885	19f329ad	blueswir1	// Z \| (N ^ V)
886	19f329ad	blueswir1	static inline void gen_op_eval_ble(TCGv dst, TCGv src)
887	19f329ad	blueswir1	{
888	0425bee5	blueswir1	gen_mov_reg_N(cpu_tmp0, src);
889	19f329ad	blueswir1	gen_mov_reg_V(dst, src);
890	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
891	0425bee5	blueswir1	gen_mov_reg_Z(cpu_tmp0, src);
892	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
893	19f329ad	blueswir1	}
894	19f329ad	blueswir1
895	19f329ad	blueswir1	// N ^ V
896	19f329ad	blueswir1	static inline void gen_op_eval_bl(TCGv dst, TCGv src)
897	19f329ad	blueswir1	{
898	0425bee5	blueswir1	gen_mov_reg_V(cpu_tmp0, src);
899	19f329ad	blueswir1	gen_mov_reg_N(dst, src);
900	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
901	19f329ad	blueswir1	}
902	19f329ad	blueswir1
903	19f329ad	blueswir1	// C \| Z
904	19f329ad	blueswir1	static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
905	19f329ad	blueswir1	{
906	0425bee5	blueswir1	gen_mov_reg_Z(cpu_tmp0, src);
907	19f329ad	blueswir1	gen_mov_reg_C(dst, src);
908	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
909	19f329ad	blueswir1	}
910	19f329ad	blueswir1
911	19f329ad	blueswir1	// C
912	19f329ad	blueswir1	static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
913	19f329ad	blueswir1	{
914	19f329ad	blueswir1	gen_mov_reg_C(dst, src);
915	19f329ad	blueswir1	}
916	19f329ad	blueswir1
917	19f329ad	blueswir1	// V
918	19f329ad	blueswir1	static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
919	19f329ad	blueswir1	{
920	19f329ad	blueswir1	gen_mov_reg_V(dst, src);
921	19f329ad	blueswir1	}
922	19f329ad	blueswir1
923	19f329ad	blueswir1	// 0
924	19f329ad	blueswir1	static inline void gen_op_eval_bn(TCGv dst)
925	19f329ad	blueswir1	{
926	19f329ad	blueswir1	tcg_gen_movi_tl(dst, 0);
927	19f329ad	blueswir1	}
928	19f329ad	blueswir1
929	19f329ad	blueswir1	// N
930	19f329ad	blueswir1	static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
931	19f329ad	blueswir1	{
932	19f329ad	blueswir1	gen_mov_reg_N(dst, src);
933	19f329ad	blueswir1	}
934	19f329ad	blueswir1
935	19f329ad	blueswir1	// !Z
936	19f329ad	blueswir1	static inline void gen_op_eval_bne(TCGv dst, TCGv src)
937	19f329ad	blueswir1	{
938	19f329ad	blueswir1	gen_mov_reg_Z(dst, src);
939	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
940	19f329ad	blueswir1	}
941	19f329ad	blueswir1
942	19f329ad	blueswir1	// !(Z \| (N ^ V))
943	19f329ad	blueswir1	static inline void gen_op_eval_bg(TCGv dst, TCGv src)
944	19f329ad	blueswir1	{
945	0425bee5	blueswir1	gen_mov_reg_N(cpu_tmp0, src);
946	19f329ad	blueswir1	gen_mov_reg_V(dst, src);
947	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
948	0425bee5	blueswir1	gen_mov_reg_Z(cpu_tmp0, src);
949	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
950	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
951	19f329ad	blueswir1	}
952	19f329ad	blueswir1
953	19f329ad	blueswir1	// !(N ^ V)
954	19f329ad	blueswir1	static inline void gen_op_eval_bge(TCGv dst, TCGv src)
955	19f329ad	blueswir1	{
956	0425bee5	blueswir1	gen_mov_reg_V(cpu_tmp0, src);
957	19f329ad	blueswir1	gen_mov_reg_N(dst, src);
958	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
959	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
960	19f329ad	blueswir1	}
961	19f329ad	blueswir1
962	19f329ad	blueswir1	// !(C \| Z)
963	19f329ad	blueswir1	static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
964	19f329ad	blueswir1	{
965	0425bee5	blueswir1	gen_mov_reg_Z(cpu_tmp0, src);
966	19f329ad	blueswir1	gen_mov_reg_C(dst, src);
967	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
968	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
969	19f329ad	blueswir1	}
970	19f329ad	blueswir1
971	19f329ad	blueswir1	// !C
972	19f329ad	blueswir1	static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
973	19f329ad	blueswir1	{
974	19f329ad	blueswir1	gen_mov_reg_C(dst, src);
975	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
976	19f329ad	blueswir1	}
977	19f329ad	blueswir1
978	19f329ad	blueswir1	// !N
979	19f329ad	blueswir1	static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
980	19f329ad	blueswir1	{
981	19f329ad	blueswir1	gen_mov_reg_N(dst, src);
982	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
983	19f329ad	blueswir1	}
984	19f329ad	blueswir1
985	19f329ad	blueswir1	// !V
986	19f329ad	blueswir1	static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
987	19f329ad	blueswir1	{
988	19f329ad	blueswir1	gen_mov_reg_V(dst, src);
989	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
990	19f329ad	blueswir1	}
991	19f329ad	blueswir1
992	19f329ad	blueswir1	/*
993	19f329ad	blueswir1	FPSR bit field FCC1 \| FCC0:
994	19f329ad	blueswir1	0 =
995	19f329ad	blueswir1	1 <
996	19f329ad	blueswir1	2 >
997	19f329ad	blueswir1	3 unordered
998	19f329ad	blueswir1	*/
999	19f329ad	blueswir1	static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
1000	19f329ad	blueswir1	unsigned int fcc_offset)
1001	19f329ad	blueswir1	{
1002	8911f501	blueswir1	tcg_gen_extu_i32_tl(reg, src);
1003	4b8b8b76	blueswir1	tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);
1004	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
1005	19f329ad	blueswir1	}
1006	19f329ad	blueswir1
1007	19f329ad	blueswir1	static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
1008	19f329ad	blueswir1	unsigned int fcc_offset)
1009	19f329ad	blueswir1	{
1010	8911f501	blueswir1	tcg_gen_extu_i32_tl(reg, src);
1011	4b8b8b76	blueswir1	tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);
1012	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
1013	19f329ad	blueswir1	}
1014	19f329ad	blueswir1
1015	19f329ad	blueswir1	// !0: FCC0 \| FCC1
1016	19f329ad	blueswir1	static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
1017	19f329ad	blueswir1	unsigned int fcc_offset)
1018	19f329ad	blueswir1	{
1019	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1020	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1021	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
1022	19f329ad	blueswir1	}
1023	19f329ad	blueswir1
1024	19f329ad	blueswir1	// 1 or 2: FCC0 ^ FCC1
1025	19f329ad	blueswir1	static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
1026	19f329ad	blueswir1	unsigned int fcc_offset)
1027	19f329ad	blueswir1	{
1028	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1029	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1030	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1031	19f329ad	blueswir1	}
1032	19f329ad	blueswir1
1033	19f329ad	blueswir1	// 1 or 3: FCC0
1034	19f329ad	blueswir1	static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1035	19f329ad	blueswir1	unsigned int fcc_offset)
1036	19f329ad	blueswir1	{
1037	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1038	19f329ad	blueswir1	}
1039	19f329ad	blueswir1
1040	19f329ad	blueswir1	// 1: FCC0 & !FCC1
1041	19f329ad	blueswir1	static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1042	19f329ad	blueswir1	unsigned int fcc_offset)
1043	19f329ad	blueswir1	{
1044	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1045	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1046	0425bee5	blueswir1	tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1047	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1048	19f329ad	blueswir1	}
1049	19f329ad	blueswir1
1050	19f329ad	blueswir1	// 2 or 3: FCC1
1051	19f329ad	blueswir1	static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1052	19f329ad	blueswir1	unsigned int fcc_offset)
1053	19f329ad	blueswir1	{
1054	19f329ad	blueswir1	gen_mov_reg_FCC1(dst, src, fcc_offset);
1055	19f329ad	blueswir1	}
1056	19f329ad	blueswir1
1057	19f329ad	blueswir1	// 2: !FCC0 & FCC1
1058	19f329ad	blueswir1	static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1059	19f329ad	blueswir1	unsigned int fcc_offset)
1060	19f329ad	blueswir1	{
1061	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1062	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1063	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1064	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1065	19f329ad	blueswir1	}
1066	19f329ad	blueswir1
1067	19f329ad	blueswir1	// 3: FCC0 & FCC1
1068	19f329ad	blueswir1	static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1069	19f329ad	blueswir1	unsigned int fcc_offset)
1070	19f329ad	blueswir1	{
1071	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1072	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1073	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1074	19f329ad	blueswir1	}
1075	19f329ad	blueswir1
1076	19f329ad	blueswir1	// 0: !(FCC0 \| FCC1)
1077	19f329ad	blueswir1	static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1078	19f329ad	blueswir1	unsigned int fcc_offset)
1079	19f329ad	blueswir1	{
1080	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1081	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1082	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
1083	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1084	19f329ad	blueswir1	}
1085	19f329ad	blueswir1
1086	19f329ad	blueswir1	// 0 or 3: !(FCC0 ^ FCC1)
1087	19f329ad	blueswir1	static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1088	19f329ad	blueswir1	unsigned int fcc_offset)
1089	19f329ad	blueswir1	{
1090	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1091	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1092	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1093	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1094	19f329ad	blueswir1	}
1095	19f329ad	blueswir1
1096	19f329ad	blueswir1	// 0 or 2: !FCC0
1097	19f329ad	blueswir1	static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1098	19f329ad	blueswir1	unsigned int fcc_offset)
1099	19f329ad	blueswir1	{
1100	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1101	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1102	19f329ad	blueswir1	}
1103	19f329ad	blueswir1
1104	19f329ad	blueswir1	// !1: !(FCC0 & !FCC1)
1105	19f329ad	blueswir1	static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1106	19f329ad	blueswir1	unsigned int fcc_offset)
1107	19f329ad	blueswir1	{
1108	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1109	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1110	0425bee5	blueswir1	tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1111	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1112	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1113	19f329ad	blueswir1	}
1114	19f329ad	blueswir1
1115	19f329ad	blueswir1	// 0 or 1: !FCC1
1116	19f329ad	blueswir1	static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1117	19f329ad	blueswir1	unsigned int fcc_offset)
1118	19f329ad	blueswir1	{
1119	19f329ad	blueswir1	gen_mov_reg_FCC1(dst, src, fcc_offset);
1120	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1121	19f329ad	blueswir1	}
1122	19f329ad	blueswir1
1123	19f329ad	blueswir1	// !2: !(!FCC0 & FCC1)
1124	19f329ad	blueswir1	static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1125	19f329ad	blueswir1	unsigned int fcc_offset)
1126	19f329ad	blueswir1	{
1127	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1128	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1129	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1130	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1131	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1132	19f329ad	blueswir1	}
1133	19f329ad	blueswir1
1134	19f329ad	blueswir1	// !3: !(FCC0 & FCC1)
1135	19f329ad	blueswir1	static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1136	19f329ad	blueswir1	unsigned int fcc_offset)
1137	19f329ad	blueswir1	{
1138	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1139	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1140	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1141	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1142	19f329ad	blueswir1	}
1143	19f329ad	blueswir1
1144	46525e1f	blueswir1	static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1145	19f329ad	blueswir1	target_ulong pc2, TCGv r_cond)
1146	83469015	bellard	{
1147	83469015	bellard	int l1;
1148	83469015	bellard
1149	83469015	bellard	l1 = gen_new_label();
1150	83469015	bellard
1151	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1152	83469015	bellard
1153	6e256c93	bellard	gen_goto_tb(dc, 0, pc1, pc1 + 4);
1154	83469015	bellard
1155	83469015	bellard	gen_set_label(l1);
1156	6e256c93	bellard	gen_goto_tb(dc, 1, pc2, pc2 + 4);
1157	83469015	bellard	}
1158	83469015	bellard
1159	46525e1f	blueswir1	static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1160	19f329ad	blueswir1	target_ulong pc2, TCGv r_cond)
1161	83469015	bellard	{
1162	83469015	bellard	int l1;
1163	83469015	bellard
1164	83469015	bellard	l1 = gen_new_label();
1165	83469015	bellard
1166	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1167	83469015	bellard
1168	6e256c93	bellard	gen_goto_tb(dc, 0, pc2, pc1);
1169	83469015	bellard
1170	83469015	bellard	gen_set_label(l1);
1171	6e256c93	bellard	gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1172	83469015	bellard	}
1173	83469015	bellard
1174	19f329ad	blueswir1	static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1175	19f329ad	blueswir1	TCGv r_cond)
1176	83469015	bellard	{
1177	83469015	bellard	int l1, l2;
1178	83469015	bellard
1179	83469015	bellard	l1 = gen_new_label();
1180	83469015	bellard	l2 = gen_new_label();
1181	19f329ad	blueswir1
1182	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1183	83469015	bellard
1184	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_npc, npc1);
1185	06b3e1b3	blueswir1	tcg_gen_br(l2);
1186	83469015	bellard
1187	83469015	bellard	gen_set_label(l1);
1188	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_npc, npc2);
1189	83469015	bellard	gen_set_label(l2);
1190	83469015	bellard	}
1191	83469015	bellard
1192	4af984a7	blueswir1	/* call this function before using the condition register as it may
1193	4af984a7	blueswir1	have been set for a jump */
1194	4af984a7	blueswir1	static inline void flush_cond(DisasContext *dc, TCGv cond)
1195	83469015	bellard	{
1196	83469015	bellard	if (dc->npc == JUMP_PC) {
1197	4af984a7	blueswir1	gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1198	83469015	bellard	dc->npc = DYNAMIC_PC;
1199	83469015	bellard	}
1200	83469015	bellard	}
1201	83469015	bellard
1202	4af984a7	blueswir1	static inline void save_npc(DisasContext *dc, TCGv cond)
1203	72cbca10	bellard	{
1204	72cbca10	bellard	if (dc->npc == JUMP_PC) {
1205	4af984a7	blueswir1	gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1206	72cbca10	bellard	dc->npc = DYNAMIC_PC;
1207	72cbca10	bellard	} else if (dc->npc != DYNAMIC_PC) {
1208	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_npc, dc->npc);
1209	72cbca10	bellard	}
1210	72cbca10	bellard	}
1211	72cbca10	bellard
1212	4af984a7	blueswir1	static inline void save_state(DisasContext *dc, TCGv cond)
1213	72cbca10	bellard	{
1214	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_pc, dc->pc);
1215	4af984a7	blueswir1	save_npc(dc, cond);
1216	72cbca10	bellard	}
1217	72cbca10	bellard
1218	4af984a7	blueswir1	static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1219	0bee699e	bellard	{
1220	0bee699e	bellard	if (dc->npc == JUMP_PC) {
1221	4af984a7	blueswir1	gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1222	48d5c82b	blueswir1	tcg_gen_mov_tl(cpu_pc, cpu_npc);
1223	0bee699e	bellard	dc->pc = DYNAMIC_PC;
1224	0bee699e	bellard	} else if (dc->npc == DYNAMIC_PC) {
1225	48d5c82b	blueswir1	tcg_gen_mov_tl(cpu_pc, cpu_npc);
1226	0bee699e	bellard	dc->pc = DYNAMIC_PC;
1227	0bee699e	bellard	} else {
1228	0bee699e	bellard	dc->pc = dc->npc;
1229	0bee699e	bellard	}
1230	0bee699e	bellard	}
1231	0bee699e	bellard
1232	38bc628b	blueswir1	static inline void gen_op_next_insn(void)
1233	38bc628b	blueswir1	{
1234	48d5c82b	blueswir1	tcg_gen_mov_tl(cpu_pc, cpu_npc);
1235	48d5c82b	blueswir1	tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1236	38bc628b	blueswir1	}
1237	38bc628b	blueswir1
1238	19f329ad	blueswir1	static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1239	19f329ad	blueswir1	{
1240	19f329ad	blueswir1	TCGv r_src;
1241	3475187d	bellard
1242	3475187d	bellard	#ifdef TARGET_SPARC64
1243	19f329ad	blueswir1	if (cc)
1244	dc99a3f2	blueswir1	r_src = cpu_xcc;
1245	19f329ad	blueswir1	else
1246	dc99a3f2	blueswir1	r_src = cpu_psr;
1247	3475187d	bellard	#else
1248	dc99a3f2	blueswir1	r_src = cpu_psr;
1249	3475187d	bellard	#endif
1250	19f329ad	blueswir1	switch (cond) {
1251	19f329ad	blueswir1	case 0x0:
1252	19f329ad	blueswir1	gen_op_eval_bn(r_dst);
1253	19f329ad	blueswir1	break;
1254	19f329ad	blueswir1	case 0x1:
1255	19f329ad	blueswir1	gen_op_eval_be(r_dst, r_src);
1256	19f329ad	blueswir1	break;
1257	19f329ad	blueswir1	case 0x2:
1258	19f329ad	blueswir1	gen_op_eval_ble(r_dst, r_src);
1259	19f329ad	blueswir1	break;
1260	19f329ad	blueswir1	case 0x3:
1261	19f329ad	blueswir1	gen_op_eval_bl(r_dst, r_src);
1262	19f329ad	blueswir1	break;
1263	19f329ad	blueswir1	case 0x4:
1264	19f329ad	blueswir1	gen_op_eval_bleu(r_dst, r_src);
1265	19f329ad	blueswir1	break;
1266	19f329ad	blueswir1	case 0x5:
1267	19f329ad	blueswir1	gen_op_eval_bcs(r_dst, r_src);
1268	19f329ad	blueswir1	break;
1269	19f329ad	blueswir1	case 0x6:
1270	19f329ad	blueswir1	gen_op_eval_bneg(r_dst, r_src);
1271	19f329ad	blueswir1	break;
1272	19f329ad	blueswir1	case 0x7:
1273	19f329ad	blueswir1	gen_op_eval_bvs(r_dst, r_src);
1274	19f329ad	blueswir1	break;
1275	19f329ad	blueswir1	case 0x8:
1276	19f329ad	blueswir1	gen_op_eval_ba(r_dst);
1277	19f329ad	blueswir1	break;
1278	19f329ad	blueswir1	case 0x9:
1279	19f329ad	blueswir1	gen_op_eval_bne(r_dst, r_src);
1280	19f329ad	blueswir1	break;
1281	19f329ad	blueswir1	case 0xa:
1282	19f329ad	blueswir1	gen_op_eval_bg(r_dst, r_src);
1283	19f329ad	blueswir1	break;
1284	19f329ad	blueswir1	case 0xb:
1285	19f329ad	blueswir1	gen_op_eval_bge(r_dst, r_src);
1286	19f329ad	blueswir1	break;
1287	19f329ad	blueswir1	case 0xc:
1288	19f329ad	blueswir1	gen_op_eval_bgu(r_dst, r_src);
1289	19f329ad	blueswir1	break;
1290	19f329ad	blueswir1	case 0xd:
1291	19f329ad	blueswir1	gen_op_eval_bcc(r_dst, r_src);
1292	19f329ad	blueswir1	break;
1293	19f329ad	blueswir1	case 0xe:
1294	19f329ad	blueswir1	gen_op_eval_bpos(r_dst, r_src);
1295	19f329ad	blueswir1	break;
1296	19f329ad	blueswir1	case 0xf:
1297	19f329ad	blueswir1	gen_op_eval_bvc(r_dst, r_src);
1298	19f329ad	blueswir1	break;
1299	19f329ad	blueswir1	}
1300	19f329ad	blueswir1	}
1301	7a3f1944	bellard
1302	19f329ad	blueswir1	static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1303	e8af50a3	bellard	{
1304	19f329ad	blueswir1	unsigned int offset;
1305	19f329ad	blueswir1
1306	19f329ad	blueswir1	switch (cc) {
1307	19f329ad	blueswir1	default:
1308	19f329ad	blueswir1	case 0x0:
1309	19f329ad	blueswir1	offset = 0;
1310	19f329ad	blueswir1	break;
1311	19f329ad	blueswir1	case 0x1:
1312	19f329ad	blueswir1	offset = 32 - 10;
1313	19f329ad	blueswir1	break;
1314	19f329ad	blueswir1	case 0x2:
1315	19f329ad	blueswir1	offset = 34 - 10;
1316	19f329ad	blueswir1	break;
1317	19f329ad	blueswir1	case 0x3:
1318	19f329ad	blueswir1	offset = 36 - 10;
1319	19f329ad	blueswir1	break;
1320	19f329ad	blueswir1	}
1321	19f329ad	blueswir1
1322	19f329ad	blueswir1	switch (cond) {
1323	19f329ad	blueswir1	case 0x0:
1324	19f329ad	blueswir1	gen_op_eval_bn(r_dst);
1325	19f329ad	blueswir1	break;
1326	19f329ad	blueswir1	case 0x1:
1327	87e92502	blueswir1	gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1328	19f329ad	blueswir1	break;
1329	19f329ad	blueswir1	case 0x2:
1330	87e92502	blueswir1	gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1331	19f329ad	blueswir1	break;
1332	19f329ad	blueswir1	case 0x3:
1333	87e92502	blueswir1	gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1334	19f329ad	blueswir1	break;
1335	19f329ad	blueswir1	case 0x4:
1336	87e92502	blueswir1	gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1337	19f329ad	blueswir1	break;
1338	19f329ad	blueswir1	case 0x5:
1339	87e92502	blueswir1	gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1340	19f329ad	blueswir1	break;
1341	19f329ad	blueswir1	case 0x6:
1342	87e92502	blueswir1	gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1343	19f329ad	blueswir1	break;
1344	19f329ad	blueswir1	case 0x7:
1345	87e92502	blueswir1	gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1346	19f329ad	blueswir1	break;
1347	19f329ad	blueswir1	case 0x8:
1348	19f329ad	blueswir1	gen_op_eval_ba(r_dst);
1349	19f329ad	blueswir1	break;
1350	19f329ad	blueswir1	case 0x9:
1351	87e92502	blueswir1	gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1352	19f329ad	blueswir1	break;
1353	19f329ad	blueswir1	case 0xa:
1354	87e92502	blueswir1	gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1355	19f329ad	blueswir1	break;
1356	19f329ad	blueswir1	case 0xb:
1357	87e92502	blueswir1	gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1358	19f329ad	blueswir1	break;
1359	19f329ad	blueswir1	case 0xc:
1360	87e92502	blueswir1	gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1361	19f329ad	blueswir1	break;
1362	19f329ad	blueswir1	case 0xd:
1363	87e92502	blueswir1	gen_op_eval_fble(r_dst, cpu_fsr, offset);
1364	19f329ad	blueswir1	break;
1365	19f329ad	blueswir1	case 0xe:
1366	87e92502	blueswir1	gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1367	19f329ad	blueswir1	break;
1368	19f329ad	blueswir1	case 0xf:
1369	87e92502	blueswir1	gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1370	19f329ad	blueswir1	break;
1371	19f329ad	blueswir1	}
1372	e8af50a3	bellard	}
1373	00f219bf	blueswir1
1374	19f329ad	blueswir1	#ifdef TARGET_SPARC64
1375	00f219bf	blueswir1	// Inverted logic
1376	00f219bf	blueswir1	static const int gen_tcg_cond_reg[8] = {
1377	00f219bf	blueswir1	-1,
1378	00f219bf	blueswir1	TCG_COND_NE,
1379	00f219bf	blueswir1	TCG_COND_GT,
1380	00f219bf	blueswir1	TCG_COND_GE,
1381	00f219bf	blueswir1	-1,
1382	00f219bf	blueswir1	TCG_COND_EQ,
1383	00f219bf	blueswir1	TCG_COND_LE,
1384	00f219bf	blueswir1	TCG_COND_LT,
1385	00f219bf	blueswir1	};
1386	19f329ad	blueswir1
1387	4af984a7	blueswir1	static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1388	19f329ad	blueswir1	{
1389	19f329ad	blueswir1	int l1;
1390	19f329ad	blueswir1
1391	19f329ad	blueswir1	l1 = gen_new_label();
1392	0425bee5	blueswir1	tcg_gen_movi_tl(r_dst, 0);
1393	cb63669a	pbrook	tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
1394	19f329ad	blueswir1	tcg_gen_movi_tl(r_dst, 1);
1395	19f329ad	blueswir1	gen_set_label(l1);
1396	19f329ad	blueswir1	}
1397	3475187d	bellard	#endif
1398	cf495bcf	bellard
1399	0bee699e	bellard	/* XXX: potentially incorrect if dynamic npc */
1400	4af984a7	blueswir1	static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1401	4af984a7	blueswir1	TCGv r_cond)
1402	7a3f1944	bellard	{
1403	cf495bcf	bellard	unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1404	af7bf89b	bellard	target_ulong target = dc->pc + offset;
1405	5fafdf24	ths
1406	cf495bcf	bellard	if (cond == 0x0) {
1407	0f8a249a	blueswir1	/* unconditional not taken */
1408	0f8a249a	blueswir1	if (a) {
1409	0f8a249a	blueswir1	dc->pc = dc->npc + 4;
1410	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1411	0f8a249a	blueswir1	} else {
1412	0f8a249a	blueswir1	dc->pc = dc->npc;
1413	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1414	0f8a249a	blueswir1	}
1415	cf495bcf	bellard	} else if (cond == 0x8) {
1416	0f8a249a	blueswir1	/* unconditional taken */
1417	0f8a249a	blueswir1	if (a) {
1418	0f8a249a	blueswir1	dc->pc = target;
1419	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1420	0f8a249a	blueswir1	} else {
1421	0f8a249a	blueswir1	dc->pc = dc->npc;
1422	0f8a249a	blueswir1	dc->npc = target;
1423	0f8a249a	blueswir1	}
1424	cf495bcf	bellard	} else {
1425	4af984a7	blueswir1	flush_cond(dc, r_cond);
1426	4af984a7	blueswir1	gen_cond(r_cond, cc, cond);
1427	0f8a249a	blueswir1	if (a) {
1428	4af984a7	blueswir1	gen_branch_a(dc, target, dc->npc, r_cond);
1429	cf495bcf	bellard	dc->is_br = 1;
1430	0f8a249a	blueswir1	} else {
1431	cf495bcf	bellard	dc->pc = dc->npc;
1432	72cbca10	bellard	dc->jump_pc[0] = target;
1433	72cbca10	bellard	dc->jump_pc[1] = dc->npc + 4;
1434	72cbca10	bellard	dc->npc = JUMP_PC;
1435	0f8a249a	blueswir1	}
1436	cf495bcf	bellard	}
1437	7a3f1944	bellard	}
1438	7a3f1944	bellard
1439	0bee699e	bellard	/* XXX: potentially incorrect if dynamic npc */
1440	4af984a7	blueswir1	static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1441	4af984a7	blueswir1	TCGv r_cond)
1442	e8af50a3	bellard	{
1443	e8af50a3	bellard	unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1444	af7bf89b	bellard	target_ulong target = dc->pc + offset;
1445	af7bf89b	bellard
1446	e8af50a3	bellard	if (cond == 0x0) {
1447	0f8a249a	blueswir1	/* unconditional not taken */
1448	0f8a249a	blueswir1	if (a) {
1449	0f8a249a	blueswir1	dc->pc = dc->npc + 4;
1450	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1451	0f8a249a	blueswir1	} else {
1452	0f8a249a	blueswir1	dc->pc = dc->npc;
1453	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1454	0f8a249a	blueswir1	}
1455	e8af50a3	bellard	} else if (cond == 0x8) {
1456	0f8a249a	blueswir1	/* unconditional taken */
1457	0f8a249a	blueswir1	if (a) {
1458	0f8a249a	blueswir1	dc->pc = target;
1459	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1460	0f8a249a	blueswir1	} else {
1461	0f8a249a	blueswir1	dc->pc = dc->npc;
1462	0f8a249a	blueswir1	dc->npc = target;
1463	0f8a249a	blueswir1	}
1464	e8af50a3	bellard	} else {
1465	4af984a7	blueswir1	flush_cond(dc, r_cond);
1466	4af984a7	blueswir1	gen_fcond(r_cond, cc, cond);
1467	0f8a249a	blueswir1	if (a) {
1468	4af984a7	blueswir1	gen_branch_a(dc, target, dc->npc, r_cond);
1469	e8af50a3	bellard	dc->is_br = 1;
1470	0f8a249a	blueswir1	} else {
1471	e8af50a3	bellard	dc->pc = dc->npc;
1472	e8af50a3	bellard	dc->jump_pc[0] = target;
1473	e8af50a3	bellard	dc->jump_pc[1] = dc->npc + 4;
1474	e8af50a3	bellard	dc->npc = JUMP_PC;
1475	0f8a249a	blueswir1	}
1476	e8af50a3	bellard	}
1477	e8af50a3	bellard	}
1478	e8af50a3	bellard
1479	3475187d	bellard	#ifdef TARGET_SPARC64
1480	3475187d	bellard	/* XXX: potentially incorrect if dynamic npc */
1481	4af984a7	blueswir1	static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1482	4af984a7	blueswir1	TCGv r_cond, TCGv r_reg)
1483	7a3f1944	bellard	{
1484	3475187d	bellard	unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1485	3475187d	bellard	target_ulong target = dc->pc + offset;
1486	3475187d	bellard
1487	4af984a7	blueswir1	flush_cond(dc, r_cond);
1488	4af984a7	blueswir1	gen_cond_reg(r_cond, cond, r_reg);
1489	3475187d	bellard	if (a) {
1490	4af984a7	blueswir1	gen_branch_a(dc, target, dc->npc, r_cond);
1491	0f8a249a	blueswir1	dc->is_br = 1;
1492	3475187d	bellard	} else {
1493	0f8a249a	blueswir1	dc->pc = dc->npc;
1494	0f8a249a	blueswir1	dc->jump_pc[0] = target;
1495	0f8a249a	blueswir1	dc->jump_pc[1] = dc->npc + 4;
1496	0f8a249a	blueswir1	dc->npc = JUMP_PC;
1497	3475187d	bellard	}
1498	7a3f1944	bellard	}
1499	7a3f1944	bellard
1500	3475187d	bellard	static GenOpFunc * const gen_fcmps[4] = {
1501	7e8c2b6c	blueswir1	helper_fcmps,
1502	7e8c2b6c	blueswir1	helper_fcmps_fcc1,
1503	7e8c2b6c	blueswir1	helper_fcmps_fcc2,
1504	7e8c2b6c	blueswir1	helper_fcmps_fcc3,
1505	3475187d	bellard	};
1506	3475187d	bellard
1507	3475187d	bellard	static GenOpFunc * const gen_fcmpd[4] = {
1508	7e8c2b6c	blueswir1	helper_fcmpd,
1509	7e8c2b6c	blueswir1	helper_fcmpd_fcc1,
1510	7e8c2b6c	blueswir1	helper_fcmpd_fcc2,
1511	7e8c2b6c	blueswir1	helper_fcmpd_fcc3,
1512	3475187d	bellard	};
1513	417454b0	blueswir1
1514	1f587329	blueswir1	static GenOpFunc * const gen_fcmpq[4] = {
1515	7e8c2b6c	blueswir1	helper_fcmpq,
1516	7e8c2b6c	blueswir1	helper_fcmpq_fcc1,
1517	7e8c2b6c	blueswir1	helper_fcmpq_fcc2,
1518	7e8c2b6c	blueswir1	helper_fcmpq_fcc3,
1519	1f587329	blueswir1	};
1520	1f587329	blueswir1
1521	417454b0	blueswir1	static GenOpFunc * const gen_fcmpes[4] = {
1522	7e8c2b6c	blueswir1	helper_fcmpes,
1523	7e8c2b6c	blueswir1	helper_fcmpes_fcc1,
1524	7e8c2b6c	blueswir1	helper_fcmpes_fcc2,
1525	7e8c2b6c	blueswir1	helper_fcmpes_fcc3,
1526	417454b0	blueswir1	};
1527	417454b0	blueswir1
1528	417454b0	blueswir1	static GenOpFunc * const gen_fcmped[4] = {
1529	7e8c2b6c	blueswir1	helper_fcmped,
1530	7e8c2b6c	blueswir1	helper_fcmped_fcc1,
1531	7e8c2b6c	blueswir1	helper_fcmped_fcc2,
1532	7e8c2b6c	blueswir1	helper_fcmped_fcc3,
1533	417454b0	blueswir1	};
1534	417454b0	blueswir1
1535	1f587329	blueswir1	static GenOpFunc * const gen_fcmpeq[4] = {
1536	7e8c2b6c	blueswir1	helper_fcmpeq,
1537	7e8c2b6c	blueswir1	helper_fcmpeq_fcc1,
1538	7e8c2b6c	blueswir1	helper_fcmpeq_fcc2,
1539	7e8c2b6c	blueswir1	helper_fcmpeq_fcc3,
1540	1f587329	blueswir1	};
1541	7e8c2b6c	blueswir1
1542	7e8c2b6c	blueswir1	static inline void gen_op_fcmps(int fccno)
1543	7e8c2b6c	blueswir1	{
1544	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmps[fccno]);
1545	7e8c2b6c	blueswir1	}
1546	7e8c2b6c	blueswir1
1547	7e8c2b6c	blueswir1	static inline void gen_op_fcmpd(int fccno)
1548	7e8c2b6c	blueswir1	{
1549	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1550	7e8c2b6c	blueswir1	}
1551	7e8c2b6c	blueswir1
1552	7e8c2b6c	blueswir1	static inline void gen_op_fcmpq(int fccno)
1553	7e8c2b6c	blueswir1	{
1554	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1555	7e8c2b6c	blueswir1	}
1556	7e8c2b6c	blueswir1
1557	7e8c2b6c	blueswir1	static inline void gen_op_fcmpes(int fccno)
1558	7e8c2b6c	blueswir1	{
1559	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1560	7e8c2b6c	blueswir1	}
1561	7e8c2b6c	blueswir1
1562	7e8c2b6c	blueswir1	static inline void gen_op_fcmped(int fccno)
1563	7e8c2b6c	blueswir1	{
1564	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmped[fccno]);
1565	7e8c2b6c	blueswir1	}
1566	7e8c2b6c	blueswir1
1567	7e8c2b6c	blueswir1	static inline void gen_op_fcmpeq(int fccno)
1568	7e8c2b6c	blueswir1	{
1569	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1570	7e8c2b6c	blueswir1	}
1571	7e8c2b6c	blueswir1
1572	7e8c2b6c	blueswir1	#else
1573	7e8c2b6c	blueswir1
1574	7e8c2b6c	blueswir1	static inline void gen_op_fcmps(int fccno)
1575	7e8c2b6c	blueswir1	{
1576	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmps);
1577	7e8c2b6c	blueswir1	}
1578	7e8c2b6c	blueswir1
1579	7e8c2b6c	blueswir1	static inline void gen_op_fcmpd(int fccno)
1580	7e8c2b6c	blueswir1	{
1581	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmpd);
1582	7e8c2b6c	blueswir1	}
1583	7e8c2b6c	blueswir1
1584	7e8c2b6c	blueswir1	static inline void gen_op_fcmpq(int fccno)
1585	7e8c2b6c	blueswir1	{
1586	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmpq);
1587	7e8c2b6c	blueswir1	}
1588	7e8c2b6c	blueswir1
1589	7e8c2b6c	blueswir1	static inline void gen_op_fcmpes(int fccno)
1590	7e8c2b6c	blueswir1	{
1591	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmpes);
1592	7e8c2b6c	blueswir1	}
1593	7e8c2b6c	blueswir1
1594	7e8c2b6c	blueswir1	static inline void gen_op_fcmped(int fccno)
1595	7e8c2b6c	blueswir1	{
1596	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmped);
1597	7e8c2b6c	blueswir1	}
1598	7e8c2b6c	blueswir1
1599	7e8c2b6c	blueswir1	static inline void gen_op_fcmpeq(int fccno)
1600	7e8c2b6c	blueswir1	{
1601	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmpeq);
1602	7e8c2b6c	blueswir1	}
1603	7e8c2b6c	blueswir1	#endif
1604	7e8c2b6c	blueswir1
1605	134d77a1	blueswir1	static inline void gen_op_fpexception_im(int fsr_flags)
1606	134d77a1	blueswir1	{
1607	2ea815ca	blueswir1	TCGv r_const;
1608	2ea815ca	blueswir1
1609	87e92502	blueswir1	tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1610	87e92502	blueswir1	tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1611	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_FP_EXCP);
1612	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
1613	2ea815ca	blueswir1	tcg_temp_free(r_const);
1614	134d77a1	blueswir1	}
1615	134d77a1	blueswir1
1616	4af984a7	blueswir1	static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1617	a80dde08	bellard	{
1618	a80dde08	bellard	#if !defined(CONFIG_USER_ONLY)
1619	a80dde08	bellard	if (!dc->fpu_enabled) {
1620	2ea815ca	blueswir1	TCGv r_const;
1621	2ea815ca	blueswir1
1622	4af984a7	blueswir1	save_state(dc, r_cond);
1623	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_NFPU_INSN);
1624	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
1625	2ea815ca	blueswir1	tcg_temp_free(r_const);
1626	a80dde08	bellard	dc->is_br = 1;
1627	a80dde08	bellard	return 1;
1628	a80dde08	bellard	}
1629	a80dde08	bellard	#endif
1630	a80dde08	bellard	return 0;
1631	a80dde08	bellard	}
1632	a80dde08	bellard
1633	7e8c2b6c	blueswir1	static inline void gen_op_clear_ieee_excp_and_FTT(void)
1634	7e8c2b6c	blueswir1	{
1635	87e92502	blueswir1	tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK \| FSR_CEXC_MASK));
1636	7e8c2b6c	blueswir1	}
1637	7e8c2b6c	blueswir1
1638	7e8c2b6c	blueswir1	static inline void gen_clear_float_exceptions(void)
1639	7e8c2b6c	blueswir1	{
1640	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_clear_float_exceptions);
1641	7e8c2b6c	blueswir1	}
1642	7e8c2b6c	blueswir1
1643	1a2fb1c0	blueswir1	/* asi moves */
1644	1a2fb1c0	blueswir1	#ifdef TARGET_SPARC64
1645	0425bee5	blueswir1	static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1646	1a2fb1c0	blueswir1	{
1647	95f9397c	blueswir1	int asi;
1648	0425bee5	blueswir1	TCGv r_asi;
1649	1a2fb1c0	blueswir1
1650	1a2fb1c0	blueswir1	if (IS_IMM) {
1651	0425bee5	blueswir1	r_asi = tcg_temp_new(TCG_TYPE_I32);
1652	0425bee5	blueswir1	tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1653	1a2fb1c0	blueswir1	} else {
1654	1a2fb1c0	blueswir1	asi = GET_FIELD(insn, 19, 26);
1655	0425bee5	blueswir1	r_asi = tcg_const_i32(asi);
1656	1a2fb1c0	blueswir1	}
1657	0425bee5	blueswir1	return r_asi;
1658	0425bee5	blueswir1	}
1659	0425bee5	blueswir1
1660	77f193da	blueswir1	static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1661	77f193da	blueswir1	int sign)
1662	0425bee5	blueswir1	{
1663	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1664	0425bee5	blueswir1
1665	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1666	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1667	2ea815ca	blueswir1	r_sign = tcg_const_i32(sign);
1668	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign);
1669	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1670	2ea815ca	blueswir1	tcg_temp_free(r_size);
1671	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1672	1a2fb1c0	blueswir1	}
1673	1a2fb1c0	blueswir1
1674	4af984a7	blueswir1	static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1675	1a2fb1c0	blueswir1	{
1676	2ea815ca	blueswir1	TCGv r_asi, r_size;
1677	1a2fb1c0	blueswir1
1678	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1679	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1680	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size);
1681	2ea815ca	blueswir1	tcg_temp_free(r_size);
1682	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1683	1a2fb1c0	blueswir1	}
1684	1a2fb1c0	blueswir1
1685	4af984a7	blueswir1	static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1686	1a2fb1c0	blueswir1	{
1687	2ea815ca	blueswir1	TCGv r_asi, r_size, r_rd;
1688	1a2fb1c0	blueswir1
1689	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1690	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1691	2ea815ca	blueswir1	r_rd = tcg_const_i32(rd);
1692	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd);
1693	2ea815ca	blueswir1	tcg_temp_free(r_rd);
1694	2ea815ca	blueswir1	tcg_temp_free(r_size);
1695	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1696	1a2fb1c0	blueswir1	}
1697	1a2fb1c0	blueswir1
1698	4af984a7	blueswir1	static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1699	1a2fb1c0	blueswir1	{
1700	2ea815ca	blueswir1	TCGv r_asi, r_size, r_rd;
1701	1a2fb1c0	blueswir1
1702	31741a27	blueswir1	r_asi = gen_get_asi(insn, addr);
1703	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1704	2ea815ca	blueswir1	r_rd = tcg_const_i32(rd);
1705	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd);
1706	2ea815ca	blueswir1	tcg_temp_free(r_rd);
1707	2ea815ca	blueswir1	tcg_temp_free(r_size);
1708	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1709	1a2fb1c0	blueswir1	}
1710	1a2fb1c0	blueswir1
1711	4af984a7	blueswir1	static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1712	1a2fb1c0	blueswir1	{
1713	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1714	1a2fb1c0	blueswir1
1715	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1716	2ea815ca	blueswir1	r_size = tcg_const_i32(4);
1717	2ea815ca	blueswir1	r_sign = tcg_const_i32(0);
1718	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1719	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1720	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1721	2ea815ca	blueswir1	tcg_temp_free(r_size);
1722	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1723	8d96d209	blueswir1	tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1724	1a2fb1c0	blueswir1	}
1725	1a2fb1c0	blueswir1
1726	db166940	blueswir1	static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1727	1a2fb1c0	blueswir1	{
1728	db166940	blueswir1	TCGv r_asi, r_rd;
1729	1a2fb1c0	blueswir1
1730	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1731	db166940	blueswir1	r_rd = tcg_const_i32(rd);
1732	db166940	blueswir1	tcg_gen_helper_0_3(helper_ldda_asi, addr, r_asi, r_rd);
1733	db166940	blueswir1	tcg_temp_free(r_rd);
1734	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1735	0425bee5	blueswir1	}
1736	0425bee5	blueswir1
1737	4af984a7	blueswir1	static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1738	0425bee5	blueswir1	{
1739	2ea815ca	blueswir1	TCGv r_temp, r_asi, r_size;
1740	0425bee5	blueswir1
1741	8d96d209	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
1742	0425bee5	blueswir1	gen_movl_reg_TN(rd + 1, r_temp);
1743	4af984a7	blueswir1	tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1744	0425bee5	blueswir1	r_temp);
1745	2ea815ca	blueswir1	tcg_temp_free(r_temp);
1746	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1747	2ea815ca	blueswir1	r_size = tcg_const_i32(8);
1748	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1749	2ea815ca	blueswir1	tcg_temp_free(r_size);
1750	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1751	1a2fb1c0	blueswir1	}
1752	1a2fb1c0	blueswir1
1753	77f193da	blueswir1	static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1754	77f193da	blueswir1	int rd)
1755	1a2fb1c0	blueswir1	{
1756	1a2fb1c0	blueswir1	TCGv r_val1, r_asi;
1757	1a2fb1c0	blueswir1
1758	ef28fd86	blueswir1	r_val1 = tcg_temp_new(TCG_TYPE_TL);
1759	1a2fb1c0	blueswir1	gen_movl_reg_TN(rd, r_val1);
1760	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1761	4af984a7	blueswir1	tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1762	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1763	2ea815ca	blueswir1	tcg_temp_free(r_val1);
1764	1a2fb1c0	blueswir1	}
1765	1a2fb1c0	blueswir1
1766	77f193da	blueswir1	static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1767	77f193da	blueswir1	int rd)
1768	1a2fb1c0	blueswir1	{
1769	8911f501	blueswir1	TCGv r_asi;
1770	1a2fb1c0	blueswir1
1771	8911f501	blueswir1	gen_movl_reg_TN(rd, cpu_tmp64);
1772	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1773	4af984a7	blueswir1	tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1774	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1775	1a2fb1c0	blueswir1	}
1776	1a2fb1c0	blueswir1
1777	1a2fb1c0	blueswir1	#elif !defined(CONFIG_USER_ONLY)
1778	1a2fb1c0	blueswir1
1779	77f193da	blueswir1	static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1780	77f193da	blueswir1	int sign)
1781	1a2fb1c0	blueswir1	{
1782	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1783	1a2fb1c0	blueswir1
1784	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1785	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1786	2ea815ca	blueswir1	r_sign = tcg_const_i32(sign);
1787	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1788	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1789	2ea815ca	blueswir1	tcg_temp_free(r_size);
1790	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1791	4af984a7	blueswir1	tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1792	1a2fb1c0	blueswir1	}
1793	1a2fb1c0	blueswir1
1794	4af984a7	blueswir1	static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1795	1a2fb1c0	blueswir1	{
1796	2ea815ca	blueswir1	TCGv r_asi, r_size;
1797	1a2fb1c0	blueswir1
1798	4af984a7	blueswir1	tcg_gen_extu_tl_i64(cpu_tmp64, src);
1799	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1800	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1801	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1802	2ea815ca	blueswir1	tcg_temp_free(r_size);
1803	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1804	1a2fb1c0	blueswir1	}
1805	1a2fb1c0	blueswir1
1806	4af984a7	blueswir1	static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1807	1a2fb1c0	blueswir1	{
1808	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1809	1a2fb1c0	blueswir1
1810	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1811	2ea815ca	blueswir1	r_size = tcg_const_i32(4);
1812	2ea815ca	blueswir1	r_sign = tcg_const_i32(0);
1813	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1814	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1815	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1816	2ea815ca	blueswir1	tcg_temp_free(r_size);
1817	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1818	8d96d209	blueswir1	tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1819	1a2fb1c0	blueswir1	}
1820	1a2fb1c0	blueswir1
1821	db166940	blueswir1	static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1822	1a2fb1c0	blueswir1	{
1823	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1824	1a2fb1c0	blueswir1
1825	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1826	2ea815ca	blueswir1	r_size = tcg_const_i32(8);
1827	2ea815ca	blueswir1	r_sign = tcg_const_i32(0);
1828	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1829	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1830	2ea815ca	blueswir1	tcg_temp_free(r_size);
1831	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1832	db166940	blueswir1	tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
1833	db166940	blueswir1	gen_movl_TN_reg(rd + 1, cpu_tmp0);
1834	8911f501	blueswir1	tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1835	4af984a7	blueswir1	tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1836	db166940	blueswir1	gen_movl_TN_reg(rd, hi);
1837	0425bee5	blueswir1	}
1838	0425bee5	blueswir1
1839	4af984a7	blueswir1	static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1840	0425bee5	blueswir1	{
1841	2ea815ca	blueswir1	TCGv r_temp, r_asi, r_size;
1842	0425bee5	blueswir1
1843	8d96d209	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
1844	0425bee5	blueswir1	gen_movl_reg_TN(rd + 1, r_temp);
1845	4af984a7	blueswir1	tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1846	2ea815ca	blueswir1	tcg_temp_free(r_temp);
1847	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1848	2ea815ca	blueswir1	r_size = tcg_const_i32(8);
1849	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1850	2ea815ca	blueswir1	tcg_temp_free(r_size);
1851	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1852	1a2fb1c0	blueswir1	}
1853	1a2fb1c0	blueswir1	#endif
1854	1a2fb1c0	blueswir1
1855	1a2fb1c0	blueswir1	#if !defined(CONFIG_USER_ONLY) \|\| defined(TARGET_SPARC64)
1856	4af984a7	blueswir1	static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1857	1a2fb1c0	blueswir1	{
1858	2ea815ca	blueswir1	TCGv r_val, r_asi, r_size;
1859	1a2fb1c0	blueswir1
1860	4af984a7	blueswir1	gen_ld_asi(dst, addr, insn, 1, 0);
1861	1a2fb1c0	blueswir1
1862	2ea815ca	blueswir1	r_val = tcg_const_i64(0xffULL);
1863	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1864	2ea815ca	blueswir1	r_size = tcg_const_i32(1);
1865	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size);
1866	2ea815ca	blueswir1	tcg_temp_free(r_size);
1867	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1868	2ea815ca	blueswir1	tcg_temp_free(r_val);
1869	1a2fb1c0	blueswir1	}
1870	1a2fb1c0	blueswir1	#endif
1871	1a2fb1c0	blueswir1
1872	9322a4bf	blueswir1	static inline TCGv get_src1(unsigned int insn, TCGv def)
1873	9322a4bf	blueswir1	{
1874	9322a4bf	blueswir1	TCGv r_rs1 = def;
1875	9322a4bf	blueswir1	unsigned int rs1;
1876	9322a4bf	blueswir1
1877	9322a4bf	blueswir1	rs1 = GET_FIELD(insn, 13, 17);
1878	9322a4bf	blueswir1	if (rs1 == 0)
1879	5c6a0628	blueswir1	r_rs1 = tcg_const_tl(0); // XXX how to free?
1880	9322a4bf	blueswir1	else if (rs1 < 8)
1881	5c6a0628	blueswir1	r_rs1 = cpu_gregs[rs1];
1882	9322a4bf	blueswir1	else
1883	9322a4bf	blueswir1	tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1884	9322a4bf	blueswir1	return r_rs1;
1885	9322a4bf	blueswir1	}
1886	9322a4bf	blueswir1
1887	a49d9390	blueswir1	static inline TCGv get_src2(unsigned int insn, TCGv def)
1888	a49d9390	blueswir1	{
1889	a49d9390	blueswir1	TCGv r_rs2 = def;
1890	a49d9390	blueswir1	unsigned int rs2;
1891	a49d9390	blueswir1
1892	a49d9390	blueswir1	if (IS_IMM) { /* immediate */
1893	a49d9390	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
1894	2ea815ca	blueswir1	r_rs2 = tcg_const_tl((int)rs2); // XXX how to free?
1895	a49d9390	blueswir1	} else { /* register */
1896	a49d9390	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
1897	a49d9390	blueswir1	if (rs2 == 0)
1898	2ea815ca	blueswir1	r_rs2 = tcg_const_tl(0); // XXX how to free?
1899	a49d9390	blueswir1	else if (rs2 < 8)
1900	a49d9390	blueswir1	r_rs2 = cpu_gregs[rs2];
1901	a49d9390	blueswir1	else
1902	a49d9390	blueswir1	tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1903	a49d9390	blueswir1	}
1904	a49d9390	blueswir1	return r_rs2;
1905	a49d9390	blueswir1	}
1906	a49d9390	blueswir1
1907	64a88d5d	blueswir1	#define CHECK_IU_FEATURE(dc, FEATURE) \
1908	5578ceab	blueswir1	if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
1909	64a88d5d	blueswir1	goto illegal_insn;
1910	64a88d5d	blueswir1	#define CHECK_FPU_FEATURE(dc, FEATURE) \
1911	5578ceab	blueswir1	if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
1912	64a88d5d	blueswir1	goto nfpu_insn;
1913	64a88d5d	blueswir1
1914	0bee699e	bellard	/* before an instruction, dc->pc must be static */
1915	cf495bcf	bellard	static void disas_sparc_insn(DisasContext * dc)
1916	cf495bcf	bellard	{
1917	cf495bcf	bellard	unsigned int insn, opc, rs1, rs2, rd;
1918	7a3f1944	bellard
1919	a8c768c0	blueswir1	if (unlikely(loglevel & CPU_LOG_TB_OP))
1920	a8c768c0	blueswir1	tcg_gen_debug_insn_start(dc->pc);
1921	0fa85d43	bellard	insn = ldl_code(dc->pc);
1922	cf495bcf	bellard	opc = GET_FIELD(insn, 0, 1);
1923	7a3f1944	bellard
1924	cf495bcf	bellard	rd = GET_FIELD(insn, 2, 6);
1925	6ae20372	blueswir1
1926	5c6a0628	blueswir1	cpu_src1 = tcg_temp_new(TCG_TYPE_TL); // const
1927	5c6a0628	blueswir1	cpu_src2 = tcg_temp_new(TCG_TYPE_TL); // const
1928	6ae20372	blueswir1
1929	cf495bcf	bellard	switch (opc) {
1930	0f8a249a	blueswir1	case 0: /* branches/sethi */
1931	0f8a249a	blueswir1	{
1932	0f8a249a	blueswir1	unsigned int xop = GET_FIELD(insn, 7, 9);
1933	0f8a249a	blueswir1	int32_t target;
1934	0f8a249a	blueswir1	switch (xop) {
1935	3475187d	bellard	#ifdef TARGET_SPARC64
1936	0f8a249a	blueswir1	case 0x1: /* V9 BPcc */
1937	0f8a249a	blueswir1	{
1938	0f8a249a	blueswir1	int cc;
1939	0f8a249a	blueswir1
1940	0f8a249a	blueswir1	target = GET_FIELD_SP(insn, 0, 18);
1941	0f8a249a	blueswir1	target = sign_extend(target, 18);
1942	0f8a249a	blueswir1	target <<= 2;
1943	0f8a249a	blueswir1	cc = GET_FIELD_SP(insn, 20, 21);
1944	0f8a249a	blueswir1	if (cc == 0)
1945	6ae20372	blueswir1	do_branch(dc, target, insn, 0, cpu_cond);
1946	0f8a249a	blueswir1	else if (cc == 2)
1947	6ae20372	blueswir1	do_branch(dc, target, insn, 1, cpu_cond);
1948	0f8a249a	blueswir1	else
1949	0f8a249a	blueswir1	goto illegal_insn;
1950	0f8a249a	blueswir1	goto jmp_insn;
1951	0f8a249a	blueswir1	}
1952	0f8a249a	blueswir1	case 0x3: /* V9 BPr */
1953	0f8a249a	blueswir1	{
1954	0f8a249a	blueswir1	target = GET_FIELD_SP(insn, 0, 13) \|
1955	13846e70	bellard	(GET_FIELD_SP(insn, 20, 21) << 14);
1956	0f8a249a	blueswir1	target = sign_extend(target, 16);
1957	0f8a249a	blueswir1	target <<= 2;
1958	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
1959	6ae20372	blueswir1	do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1960	0f8a249a	blueswir1	goto jmp_insn;
1961	0f8a249a	blueswir1	}
1962	0f8a249a	blueswir1	case 0x5: /* V9 FBPcc */
1963	0f8a249a	blueswir1	{
1964	0f8a249a	blueswir1	int cc = GET_FIELD_SP(insn, 20, 21);
1965	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
1966	a80dde08	bellard	goto jmp_insn;
1967	0f8a249a	blueswir1	target = GET_FIELD_SP(insn, 0, 18);
1968	0f8a249a	blueswir1	target = sign_extend(target, 19);
1969	0f8a249a	blueswir1	target <<= 2;
1970	6ae20372	blueswir1	do_fbranch(dc, target, insn, cc, cpu_cond);
1971	0f8a249a	blueswir1	goto jmp_insn;
1972	0f8a249a	blueswir1	}
1973	a4d17f19	blueswir1	#else
1974	0f8a249a	blueswir1	case 0x7: /* CBN+x */
1975	0f8a249a	blueswir1	{
1976	0f8a249a	blueswir1	goto ncp_insn;
1977	0f8a249a	blueswir1	}
1978	0f8a249a	blueswir1	#endif
1979	0f8a249a	blueswir1	case 0x2: /* BN+x */
1980	0f8a249a	blueswir1	{
1981	0f8a249a	blueswir1	target = GET_FIELD(insn, 10, 31);
1982	0f8a249a	blueswir1	target = sign_extend(target, 22);
1983	0f8a249a	blueswir1	target <<= 2;
1984	6ae20372	blueswir1	do_branch(dc, target, insn, 0, cpu_cond);
1985	0f8a249a	blueswir1	goto jmp_insn;
1986	0f8a249a	blueswir1	}
1987	0f8a249a	blueswir1	case 0x6: /* FBN+x */
1988	0f8a249a	blueswir1	{
1989	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
1990	a80dde08	bellard	goto jmp_insn;
1991	0f8a249a	blueswir1	target = GET_FIELD(insn, 10, 31);
1992	0f8a249a	blueswir1	target = sign_extend(target, 22);
1993	0f8a249a	blueswir1	target <<= 2;
1994	6ae20372	blueswir1	do_fbranch(dc, target, insn, 0, cpu_cond);
1995	0f8a249a	blueswir1	goto jmp_insn;
1996	0f8a249a	blueswir1	}
1997	0f8a249a	blueswir1	case 0x4: /* SETHI */
1998	0f8a249a	blueswir1	if (rd) { // nop
1999	0f8a249a	blueswir1	uint32_t value = GET_FIELD(insn, 10, 31);
2000	2ea815ca	blueswir1	TCGv r_const;
2001	2ea815ca	blueswir1
2002	2ea815ca	blueswir1	r_const = tcg_const_tl(value << 10);
2003	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
2004	2ea815ca	blueswir1	tcg_temp_free(r_const);
2005	0f8a249a	blueswir1	}
2006	0f8a249a	blueswir1	break;
2007	0f8a249a	blueswir1	case 0x0: /* UNIMPL */
2008	0f8a249a	blueswir1	default:
2009	3475187d	bellard	goto illegal_insn;
2010	0f8a249a	blueswir1	}
2011	0f8a249a	blueswir1	break;
2012	0f8a249a	blueswir1	}
2013	0f8a249a	blueswir1	break;
2014	cf495bcf	bellard	case 1:
2015	0f8a249a	blueswir1	/CALL/ {
2016	0f8a249a	blueswir1	target_long target = GET_FIELDs(insn, 2, 31) << 2;
2017	2ea815ca	blueswir1	TCGv r_const;
2018	cf495bcf	bellard
2019	2ea815ca	blueswir1	r_const = tcg_const_tl(dc->pc);
2020	2ea815ca	blueswir1	gen_movl_TN_reg(15, r_const);
2021	2ea815ca	blueswir1	tcg_temp_free(r_const);
2022	0f8a249a	blueswir1	target += dc->pc;
2023	6ae20372	blueswir1	gen_mov_pc_npc(dc, cpu_cond);
2024	0f8a249a	blueswir1	dc->npc = target;
2025	0f8a249a	blueswir1	}
2026	0f8a249a	blueswir1	goto jmp_insn;
2027	0f8a249a	blueswir1	case 2: /* FPU & Logical Operations */
2028	0f8a249a	blueswir1	{
2029	0f8a249a	blueswir1	unsigned int xop = GET_FIELD(insn, 7, 12);
2030	0f8a249a	blueswir1	if (xop == 0x3a) { /* generate trap */
2031	cf495bcf	bellard	int cond;
2032	3475187d	bellard
2033	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2034	0f8a249a	blueswir1	if (IS_IMM) {
2035	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 25, 31);
2036	6ae20372	blueswir1	tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
2037	cf495bcf	bellard	} else {
2038	cf495bcf	bellard	rs2 = GET_FIELD(insn, 27, 31);
2039	0f8a249a	blueswir1	if (rs2 != 0) {
2040	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
2041	6ae20372	blueswir1	tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2042	6f551262	blueswir1	} else
2043	6f551262	blueswir1	tcg_gen_mov_tl(cpu_dst, cpu_src1);
2044	cf495bcf	bellard	}
2045	cf495bcf	bellard	cond = GET_FIELD(insn, 3, 6);
2046	cf495bcf	bellard	if (cond == 0x8) {
2047	6ae20372	blueswir1	save_state(dc, cpu_cond);
2048	6ae20372	blueswir1	tcg_gen_helper_0_1(helper_trap, cpu_dst);
2049	af7bf89b	bellard	} else if (cond != 0) {
2050	748b9d8e	blueswir1	TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
2051	3475187d	bellard	#ifdef TARGET_SPARC64
2052	0f8a249a	blueswir1	/* V9 icc/xcc */
2053	0f8a249a	blueswir1	int cc = GET_FIELD_SP(insn, 11, 12);
2054	748b9d8e	blueswir1
2055	6ae20372	blueswir1	save_state(dc, cpu_cond);
2056	0f8a249a	blueswir1	if (cc == 0)
2057	748b9d8e	blueswir1	gen_cond(r_cond, 0, cond);
2058	0f8a249a	blueswir1	else if (cc == 2)
2059	748b9d8e	blueswir1	gen_cond(r_cond, 1, cond);
2060	0f8a249a	blueswir1	else
2061	0f8a249a	blueswir1	goto illegal_insn;
2062	3475187d	bellard	#else
2063	6ae20372	blueswir1	save_state(dc, cpu_cond);
2064	748b9d8e	blueswir1	gen_cond(r_cond, 0, cond);
2065	3475187d	bellard	#endif
2066	6ae20372	blueswir1	tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
2067	2ea815ca	blueswir1	tcg_temp_free(r_cond);
2068	cf495bcf	bellard	}
2069	a80dde08	bellard	gen_op_next_insn();
2070	57fec1fe	bellard	tcg_gen_exit_tb(0);
2071	a80dde08	bellard	dc->is_br = 1;
2072	a80dde08	bellard	goto jmp_insn;
2073	cf495bcf	bellard	} else if (xop == 0x28) {
2074	cf495bcf	bellard	rs1 = GET_FIELD(insn, 13, 17);
2075	cf495bcf	bellard	switch(rs1) {
2076	cf495bcf	bellard	case 0: /* rdy */
2077	65fe7b09	blueswir1	#ifndef TARGET_SPARC64
2078	65fe7b09	blueswir1	case 0x01 ... 0x0e: /* undefined in the SPARCv8
2079	65fe7b09	blueswir1	manual, rdy on the microSPARC
2080	65fe7b09	blueswir1	II */
2081	65fe7b09	blueswir1	case 0x0f: /* stbar in the SPARCv8 manual,
2082	65fe7b09	blueswir1	rdy on the microSPARC II */
2083	65fe7b09	blueswir1	case 0x10 ... 0x1f: /* implementation-dependent in the
2084	65fe7b09	blueswir1	SPARCv8 manual, rdy on the
2085	65fe7b09	blueswir1	microSPARC II */
2086	65fe7b09	blueswir1	#endif
2087	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2088	77f193da	blueswir1	offsetof(CPUSPARCState, y));
2089	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2090	cf495bcf	bellard	break;
2091	3475187d	bellard	#ifdef TARGET_SPARC64
2092	0f8a249a	blueswir1	case 0x2: /* V9 rdccr */
2093	6ae20372	blueswir1	tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2094	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2095	3475187d	bellard	break;
2096	0f8a249a	blueswir1	case 0x3: /* V9 rdasi */
2097	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2098	77f193da	blueswir1	offsetof(CPUSPARCState, asi));
2099	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2100	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2101	3475187d	bellard	break;
2102	0f8a249a	blueswir1	case 0x4: /* V9 rdtick */
2103	ccd4a219	blueswir1	{
2104	ccd4a219	blueswir1	TCGv r_tickptr;
2105	ccd4a219	blueswir1
2106	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2107	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
2108	ccd4a219	blueswir1	offsetof(CPUState, tick));
2109	6ae20372	blueswir1	tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2110	ccd4a219	blueswir1	r_tickptr);
2111	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
2112	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2113	ccd4a219	blueswir1	}
2114	3475187d	bellard	break;
2115	0f8a249a	blueswir1	case 0x5: /* V9 rdpc */
2116	2ea815ca	blueswir1	{
2117	2ea815ca	blueswir1	TCGv r_const;
2118	2ea815ca	blueswir1
2119	2ea815ca	blueswir1	r_const = tcg_const_tl(dc->pc);
2120	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
2121	2ea815ca	blueswir1	tcg_temp_free(r_const);
2122	2ea815ca	blueswir1	}
2123	0f8a249a	blueswir1	break;
2124	0f8a249a	blueswir1	case 0x6: /* V9 rdfprs */
2125	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2126	77f193da	blueswir1	offsetof(CPUSPARCState, fprs));
2127	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2128	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2129	3475187d	bellard	break;
2130	65fe7b09	blueswir1	case 0xf: /* V9 membar */
2131	65fe7b09	blueswir1	break; /* no effect */
2132	0f8a249a	blueswir1	case 0x13: /* Graphics Status */
2133	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
2134	725cb90b	bellard	goto jmp_insn;
2135	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2136	77f193da	blueswir1	offsetof(CPUSPARCState, gsr));
2137	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2138	725cb90b	bellard	break;
2139	0f8a249a	blueswir1	case 0x17: /* Tick compare */
2140	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2141	77f193da	blueswir1	offsetof(CPUSPARCState, tick_cmpr));
2142	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2143	83469015	bellard	break;
2144	0f8a249a	blueswir1	case 0x18: /* System tick */
2145	ccd4a219	blueswir1	{
2146	ccd4a219	blueswir1	TCGv r_tickptr;
2147	ccd4a219	blueswir1
2148	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2149	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
2150	ccd4a219	blueswir1	offsetof(CPUState, stick));
2151	6ae20372	blueswir1	tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2152	ccd4a219	blueswir1	r_tickptr);
2153	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
2154	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2155	ccd4a219	blueswir1	}
2156	83469015	bellard	break;
2157	0f8a249a	blueswir1	case 0x19: /* System tick compare */
2158	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2159	77f193da	blueswir1	offsetof(CPUSPARCState, stick_cmpr));
2160	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2161	83469015	bellard	break;
2162	0f8a249a	blueswir1	case 0x10: /* Performance Control */
2163	0f8a249a	blueswir1	case 0x11: /* Performance Instrumentation Counter */
2164	0f8a249a	blueswir1	case 0x12: /* Dispatch Control */
2165	0f8a249a	blueswir1	case 0x14: /* Softint set, WO */
2166	0f8a249a	blueswir1	case 0x15: /* Softint clear, WO */
2167	0f8a249a	blueswir1	case 0x16: /* Softint write */
2168	3475187d	bellard	#endif
2169	3475187d	bellard	default:
2170	cf495bcf	bellard	goto illegal_insn;
2171	cf495bcf	bellard	}
2172	e8af50a3	bellard	#if !defined(CONFIG_USER_ONLY)
2173	e9ebed4d	blueswir1	} else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2174	3475187d	bellard	#ifndef TARGET_SPARC64
2175	0f8a249a	blueswir1	if (!supervisor(dc))
2176	0f8a249a	blueswir1	goto priv_insn;
2177	6ae20372	blueswir1	tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2178	e9ebed4d	blueswir1	#else
2179	fb79ceb9	blueswir1	CHECK_IU_FEATURE(dc, HYPV);
2180	e9ebed4d	blueswir1	if (!hypervisor(dc))
2181	e9ebed4d	blueswir1	goto priv_insn;
2182	e9ebed4d	blueswir1	rs1 = GET_FIELD(insn, 13, 17);
2183	e9ebed4d	blueswir1	switch (rs1) {
2184	e9ebed4d	blueswir1	case 0: // hpstate
2185	e9ebed4d	blueswir1	// gen_op_rdhpstate();
2186	e9ebed4d	blueswir1	break;
2187	e9ebed4d	blueswir1	case 1: // htstate
2188	e9ebed4d	blueswir1	// gen_op_rdhtstate();
2189	e9ebed4d	blueswir1	break;
2190	e9ebed4d	blueswir1	case 3: // hintp
2191	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2192	77f193da	blueswir1	offsetof(CPUSPARCState, hintp));
2193	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2194	e9ebed4d	blueswir1	break;
2195	e9ebed4d	blueswir1	case 5: // htba
2196	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2197	77f193da	blueswir1	offsetof(CPUSPARCState, htba));
2198	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2199	e9ebed4d	blueswir1	break;
2200	e9ebed4d	blueswir1	case 6: // hver
2201	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2202	77f193da	blueswir1	offsetof(CPUSPARCState, hver));
2203	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2204	e9ebed4d	blueswir1	break;
2205	e9ebed4d	blueswir1	case 31: // hstick_cmpr
2206	8d7d8c4b	blueswir1	tcg_gen_ld_tl(cpu_dst, cpu_env,
2207	8d7d8c4b	blueswir1	offsetof(CPUSPARCState, hstick_cmpr));
2208	e9ebed4d	blueswir1	break;
2209	e9ebed4d	blueswir1	default:
2210	e9ebed4d	blueswir1	goto illegal_insn;
2211	e9ebed4d	blueswir1	}
2212	e9ebed4d	blueswir1	#endif
2213	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2214	e8af50a3	bellard	break;
2215	3475187d	bellard	} else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2216	0f8a249a	blueswir1	if (!supervisor(dc))
2217	0f8a249a	blueswir1	goto priv_insn;
2218	3475187d	bellard	#ifdef TARGET_SPARC64
2219	3475187d	bellard	rs1 = GET_FIELD(insn, 13, 17);
2220	0f8a249a	blueswir1	switch (rs1) {
2221	0f8a249a	blueswir1	case 0: // tpc
2222	375ee38b	blueswir1	{
2223	375ee38b	blueswir1	TCGv r_tsptr;
2224	375ee38b	blueswir1
2225	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2226	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
2227	375ee38b	blueswir1	offsetof(CPUState, tsptr));
2228	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2229	375ee38b	blueswir1	offsetof(trap_state, tpc));
2230	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
2231	375ee38b	blueswir1	}
2232	0f8a249a	blueswir1	break;
2233	0f8a249a	blueswir1	case 1: // tnpc
2234	375ee38b	blueswir1	{
2235	375ee38b	blueswir1	TCGv r_tsptr;
2236	375ee38b	blueswir1
2237	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2238	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
2239	375ee38b	blueswir1	offsetof(CPUState, tsptr));
2240	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2241	375ee38b	blueswir1	offsetof(trap_state, tnpc));
2242	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
2243	375ee38b	blueswir1	}
2244	0f8a249a	blueswir1	break;
2245	0f8a249a	blueswir1	case 2: // tstate
2246	375ee38b	blueswir1	{
2247	375ee38b	blueswir1	TCGv r_tsptr;
2248	375ee38b	blueswir1
2249	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2250	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
2251	375ee38b	blueswir1	offsetof(CPUState, tsptr));
2252	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2253	375ee38b	blueswir1	offsetof(trap_state, tstate));
2254	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
2255	375ee38b	blueswir1	}
2256	0f8a249a	blueswir1	break;
2257	0f8a249a	blueswir1	case 3: // tt
2258	375ee38b	blueswir1	{
2259	375ee38b	blueswir1	TCGv r_tsptr;
2260	375ee38b	blueswir1
2261	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2262	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
2263	375ee38b	blueswir1	offsetof(CPUState, tsptr));
2264	ece43b8d	blueswir1	tcg_gen_ld_i32(cpu_tmp0, r_tsptr,
2265	375ee38b	blueswir1	offsetof(trap_state, tt));
2266	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
2267	375ee38b	blueswir1	}
2268	0f8a249a	blueswir1	break;
2269	0f8a249a	blueswir1	case 4: // tick
2270	ccd4a219	blueswir1	{
2271	ccd4a219	blueswir1	TCGv r_tickptr;
2272	ccd4a219	blueswir1
2273	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2274	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
2275	ccd4a219	blueswir1	offsetof(CPUState, tick));
2276	ece43b8d	blueswir1	tcg_gen_helper_1_1(helper_tick_get_count, cpu_tmp0,
2277	ccd4a219	blueswir1	r_tickptr);
2278	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2279	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
2280	ccd4a219	blueswir1	}
2281	0f8a249a	blueswir1	break;
2282	0f8a249a	blueswir1	case 5: // tba
2283	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2284	77f193da	blueswir1	offsetof(CPUSPARCState, tbr));
2285	0f8a249a	blueswir1	break;
2286	0f8a249a	blueswir1	case 6: // pstate
2287	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2288	77f193da	blueswir1	offsetof(CPUSPARCState, pstate));
2289	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2290	0f8a249a	blueswir1	break;
2291	0f8a249a	blueswir1	case 7: // tl
2292	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2293	77f193da	blueswir1	offsetof(CPUSPARCState, tl));
2294	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2295	0f8a249a	blueswir1	break;
2296	0f8a249a	blueswir1	case 8: // pil
2297	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2298	77f193da	blueswir1	offsetof(CPUSPARCState, psrpil));
2299	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2300	0f8a249a	blueswir1	break;
2301	0f8a249a	blueswir1	case 9: // cwp
2302	ece43b8d	blueswir1	tcg_gen_helper_1_0(helper_rdcwp, cpu_tmp0);
2303	0f8a249a	blueswir1	break;
2304	0f8a249a	blueswir1	case 10: // cansave
2305	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2306	77f193da	blueswir1	offsetof(CPUSPARCState, cansave));
2307	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2308	0f8a249a	blueswir1	break;
2309	0f8a249a	blueswir1	case 11: // canrestore
2310	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2311	77f193da	blueswir1	offsetof(CPUSPARCState, canrestore));
2312	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2313	0f8a249a	blueswir1	break;
2314	0f8a249a	blueswir1	case 12: // cleanwin
2315	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2316	77f193da	blueswir1	offsetof(CPUSPARCState, cleanwin));
2317	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2318	0f8a249a	blueswir1	break;
2319	0f8a249a	blueswir1	case 13: // otherwin
2320	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2321	77f193da	blueswir1	offsetof(CPUSPARCState, otherwin));
2322	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2323	0f8a249a	blueswir1	break;
2324	0f8a249a	blueswir1	case 14: // wstate
2325	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2326	77f193da	blueswir1	offsetof(CPUSPARCState, wstate));
2327	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2328	0f8a249a	blueswir1	break;
2329	e9ebed4d	blueswir1	case 16: // UA2005 gl
2330	fb79ceb9	blueswir1	CHECK_IU_FEATURE(dc, GL);
2331	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2332	77f193da	blueswir1	offsetof(CPUSPARCState, gl));
2333	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2334	e9ebed4d	blueswir1	break;
2335	e9ebed4d	blueswir1	case 26: // UA2005 strand status
2336	fb79ceb9	blueswir1	CHECK_IU_FEATURE(dc, HYPV);
2337	e9ebed4d	blueswir1	if (!hypervisor(dc))
2338	e9ebed4d	blueswir1	goto priv_insn;
2339	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2340	77f193da	blueswir1	offsetof(CPUSPARCState, ssr));
2341	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2342	e9ebed4d	blueswir1	break;
2343	0f8a249a	blueswir1	case 31: // ver
2344	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2345	77f193da	blueswir1	offsetof(CPUSPARCState, version));
2346	0f8a249a	blueswir1	break;
2347	0f8a249a	blueswir1	case 15: // fq
2348	0f8a249a	blueswir1	default:
2349	0f8a249a	blueswir1	goto illegal_insn;
2350	0f8a249a	blueswir1	}
2351	3475187d	bellard	#else
2352	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2353	77f193da	blueswir1	offsetof(CPUSPARCState, wim));
2354	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2355	3475187d	bellard	#endif
2356	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2357	e8af50a3	bellard	break;
2358	3475187d	bellard	} else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2359	3475187d	bellard	#ifdef TARGET_SPARC64
2360	c5f2f668	blueswir1	save_state(dc, cpu_cond);
2361	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_flushw);
2362	3475187d	bellard	#else
2363	0f8a249a	blueswir1	if (!supervisor(dc))
2364	0f8a249a	blueswir1	goto priv_insn;
2365	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, tbr));
2366	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2367	3475187d	bellard	#endif
2368	e8af50a3	bellard	break;
2369	e8af50a3	bellard	#endif
2370	0f8a249a	blueswir1	} else if (xop == 0x34) { /* FPU Operations */
2371	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
2372	a80dde08	bellard	goto jmp_insn;
2373	0f8a249a	blueswir1	gen_op_clear_ieee_excp_and_FTT();
2374	e8af50a3	bellard	rs1 = GET_FIELD(insn, 13, 17);
2375	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
2376	0f8a249a	blueswir1	xop = GET_FIELD(insn, 18, 26);
2377	0f8a249a	blueswir1	switch (xop) {
2378	0f8a249a	blueswir1	case 0x1: /* fmovs */
2379	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs2);
2380	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2381	0f8a249a	blueswir1	break;
2382	0f8a249a	blueswir1	case 0x5: /* fnegs */
2383	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2384	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnegs);
2385	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2386	0f8a249a	blueswir1	break;
2387	0f8a249a	blueswir1	case 0x9: /* fabss */
2388	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2389	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fabss);
2390	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2391	0f8a249a	blueswir1	break;
2392	0f8a249a	blueswir1	case 0x29: /* fsqrts */
2393	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FSQRT);
2394	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2395	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2396	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fsqrts);
2397	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2398	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2399	0f8a249a	blueswir1	break;
2400	0f8a249a	blueswir1	case 0x2a: /* fsqrtd */
2401	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FSQRT);
2402	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2403	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2404	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fsqrtd);
2405	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2406	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2407	0f8a249a	blueswir1	break;
2408	0f8a249a	blueswir1	case 0x2b: /* fsqrtq */
2409	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2410	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2411	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2412	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fsqrtq);
2413	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2414	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2415	1f587329	blueswir1	break;
2416	0f8a249a	blueswir1	case 0x41:
2417	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2418	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2419	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2420	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fadds);
2421	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2422	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2423	0f8a249a	blueswir1	break;
2424	0f8a249a	blueswir1	case 0x42:
2425	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2426	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2427	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2428	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_faddd);
2429	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2430	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2431	0f8a249a	blueswir1	break;
2432	0f8a249a	blueswir1	case 0x43: /* faddq */
2433	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2434	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2435	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2436	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2437	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_faddq);
2438	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2439	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2440	1f587329	blueswir1	break;
2441	0f8a249a	blueswir1	case 0x45:
2442	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2443	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2444	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2445	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fsubs);
2446	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2447	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2448	0f8a249a	blueswir1	break;
2449	0f8a249a	blueswir1	case 0x46:
2450	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2451	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2452	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2453	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fsubd);
2454	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2455	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2456	0f8a249a	blueswir1	break;
2457	0f8a249a	blueswir1	case 0x47: /* fsubq */
2458	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2459	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2460	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2461	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2462	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fsubq);
2463	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2464	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2465	1f587329	blueswir1	break;
2466	64a88d5d	blueswir1	case 0x49: /* fmuls */
2467	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FMUL);
2468	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2469	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2470	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2471	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmuls);
2472	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2473	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2474	0f8a249a	blueswir1	break;
2475	64a88d5d	blueswir1	case 0x4a: /* fmuld */
2476	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FMUL);
2477	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2478	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2479	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2480	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmuld);
2481	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2482	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2483	0f8a249a	blueswir1	break;
2484	0f8a249a	blueswir1	case 0x4b: /* fmulq */
2485	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2486	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FMUL);
2487	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2488	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2489	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2490	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmulq);
2491	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2492	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2493	1f587329	blueswir1	break;
2494	0f8a249a	blueswir1	case 0x4d:
2495	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2496	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2497	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2498	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdivs);
2499	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2500	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2501	0f8a249a	blueswir1	break;
2502	0f8a249a	blueswir1	case 0x4e:
2503	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2504	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2505	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2506	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdivd);
2507	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2508	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2509	0f8a249a	blueswir1	break;
2510	0f8a249a	blueswir1	case 0x4f: /* fdivq */
2511	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2512	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2513	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2514	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2515	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdivq);
2516	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2517	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2518	1f587329	blueswir1	break;
2519	0f8a249a	blueswir1	case 0x69:
2520	e30b4678	blueswir1	CHECK_FPU_FEATURE(dc, FSMULD);
2521	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2522	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2523	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2524	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fsmuld);
2525	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2526	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2527	0f8a249a	blueswir1	break;
2528	0f8a249a	blueswir1	case 0x6e: /* fdmulq */
2529	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2530	1f587329	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2531	1f587329	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2532	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2533	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdmulq);
2534	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2535	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2536	1f587329	blueswir1	break;
2537	0f8a249a	blueswir1	case 0xc4:
2538	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2539	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2540	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fitos);
2541	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2542	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2543	0f8a249a	blueswir1	break;
2544	0f8a249a	blueswir1	case 0xc6:
2545	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2546	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2547	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdtos);
2548	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2549	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2550	0f8a249a	blueswir1	break;
2551	0f8a249a	blueswir1	case 0xc7: /* fqtos */
2552	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2553	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2554	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2555	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fqtos);
2556	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2557	1f587329	blueswir1	gen_op_store_FT0_fpr(rd);
2558	1f587329	blueswir1	break;
2559	0f8a249a	blueswir1	case 0xc8:
2560	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2561	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fitod);
2562	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2563	0f8a249a	blueswir1	break;
2564	0f8a249a	blueswir1	case 0xc9:
2565	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2566	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fstod);
2567	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2568	0f8a249a	blueswir1	break;
2569	0f8a249a	blueswir1	case 0xcb: /* fqtod */
2570	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2571	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2572	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2573	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fqtod);
2574	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2575	1f587329	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2576	1f587329	blueswir1	break;
2577	0f8a249a	blueswir1	case 0xcc: /* fitoq */
2578	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2579	1f587329	blueswir1	gen_op_load_fpr_FT1(rs2);
2580	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fitoq);
2581	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2582	1f587329	blueswir1	break;
2583	0f8a249a	blueswir1	case 0xcd: /* fstoq */
2584	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2585	1f587329	blueswir1	gen_op_load_fpr_FT1(rs2);
2586	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fstoq);
2587	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2588	1f587329	blueswir1	break;
2589	0f8a249a	blueswir1	case 0xce: /* fdtoq */
2590	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2591	1f587329	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2592	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdtoq);
2593	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2594	1f587329	blueswir1	break;
2595	0f8a249a	blueswir1	case 0xd1:
2596	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2597	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2598	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fstoi);
2599	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2600	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2601	0f8a249a	blueswir1	break;
2602	0f8a249a	blueswir1	case 0xd2:
2603	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2604	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2605	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdtoi);
2606	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2607	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2608	0f8a249a	blueswir1	break;
2609	0f8a249a	blueswir1	case 0xd3: /* fqtoi */
2610	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2611	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2612	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2613	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fqtoi);
2614	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2615	1f587329	blueswir1	gen_op_store_FT0_fpr(rd);
2616	1f587329	blueswir1	break;
2617	3475187d	bellard	#ifdef TARGET_SPARC64
2618	0f8a249a	blueswir1	case 0x2: /* V9 fmovd */
2619	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs2));
2620	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2621	0f8a249a	blueswir1	break;
2622	1f587329	blueswir1	case 0x3: /* V9 fmovq */
2623	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2624	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs2));
2625	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2626	1f587329	blueswir1	break;
2627	0f8a249a	blueswir1	case 0x6: /* V9 fnegd */
2628	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2629	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnegd);
2630	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2631	0f8a249a	blueswir1	break;
2632	1f587329	blueswir1	case 0x7: /* V9 fnegq */
2633	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2634	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2635	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnegq);
2636	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2637	1f587329	blueswir1	break;
2638	0f8a249a	blueswir1	case 0xa: /* V9 fabsd */
2639	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2640	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fabsd);
2641	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2642	0f8a249a	blueswir1	break;
2643	1f587329	blueswir1	case 0xb: /* V9 fabsq */
2644	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2645	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2646	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fabsq);
2647	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2648	1f587329	blueswir1	break;
2649	0f8a249a	blueswir1	case 0x81: /* V9 fstox */
2650	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2651	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2652	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fstox);
2653	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2654	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2655	0f8a249a	blueswir1	break;
2656	0f8a249a	blueswir1	case 0x82: /* V9 fdtox */
2657	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2658	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2659	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdtox);
2660	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2661	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2662	0f8a249a	blueswir1	break;
2663	1f587329	blueswir1	case 0x83: /* V9 fqtox */
2664	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2665	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2666	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2667	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fqtox);
2668	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2669	1f587329	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2670	1f587329	blueswir1	break;
2671	0f8a249a	blueswir1	case 0x84: /* V9 fxtos */
2672	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2673	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2674	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxtos);
2675	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2676	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2677	0f8a249a	blueswir1	break;
2678	0f8a249a	blueswir1	case 0x88: /* V9 fxtod */
2679	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2680	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2681	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxtod);
2682	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2683	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2684	0f8a249a	blueswir1	break;
2685	0f8a249a	blueswir1	case 0x8c: /* V9 fxtoq */
2686	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2687	1f587329	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2688	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2689	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxtoq);
2690	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2691	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2692	1f587329	blueswir1	break;
2693	1f587329	blueswir1	#endif
2694	0f8a249a	blueswir1	default:
2695	0f8a249a	blueswir1	goto illegal_insn;
2696	0f8a249a	blueswir1	}
2697	0f8a249a	blueswir1	} else if (xop == 0x35) { /* FPU Operations */
2698	3475187d	bellard	#ifdef TARGET_SPARC64
2699	0f8a249a	blueswir1	int cond;
2700	3475187d	bellard	#endif
2701	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
2702	a80dde08	bellard	goto jmp_insn;
2703	0f8a249a	blueswir1	gen_op_clear_ieee_excp_and_FTT();
2704	cf495bcf	bellard	rs1 = GET_FIELD(insn, 13, 17);
2705	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
2706	0f8a249a	blueswir1	xop = GET_FIELD(insn, 18, 26);
2707	3475187d	bellard	#ifdef TARGET_SPARC64
2708	0f8a249a	blueswir1	if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2709	dcf24905	blueswir1	int l1;
2710	dcf24905	blueswir1
2711	dcf24905	blueswir1	l1 = gen_new_label();
2712	0f8a249a	blueswir1	cond = GET_FIELD_SP(insn, 14, 17);
2713	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2714	cb63669a	pbrook	tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2715	cb63669a	pbrook	0, l1);
2716	19f329ad	blueswir1	gen_op_load_fpr_FT0(rs2);
2717	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2718	dcf24905	blueswir1	gen_set_label(l1);
2719	0f8a249a	blueswir1	break;
2720	0f8a249a	blueswir1	} else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2721	dcf24905	blueswir1	int l1;
2722	dcf24905	blueswir1
2723	dcf24905	blueswir1	l1 = gen_new_label();
2724	0f8a249a	blueswir1	cond = GET_FIELD_SP(insn, 14, 17);
2725	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2726	cb63669a	pbrook	tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2727	cb63669a	pbrook	0, l1);
2728	19f329ad	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs2));
2729	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2730	dcf24905	blueswir1	gen_set_label(l1);
2731	0f8a249a	blueswir1	break;
2732	0f8a249a	blueswir1	} else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2733	dcf24905	blueswir1	int l1;
2734	dcf24905	blueswir1
2735	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2736	dcf24905	blueswir1	l1 = gen_new_label();
2737	1f587329	blueswir1	cond = GET_FIELD_SP(insn, 14, 17);
2738	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2739	cb63669a	pbrook	tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2740	cb63669a	pbrook	0, l1);
2741	19f329ad	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs2));
2742	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2743	dcf24905	blueswir1	gen_set_label(l1);
2744	1f587329	blueswir1	break;
2745	0f8a249a	blueswir1	}
2746	0f8a249a	blueswir1	#endif
2747	0f8a249a	blueswir1	switch (xop) {
2748	3475187d	bellard	#ifdef TARGET_SPARC64
2749	19f329ad	blueswir1	#define FMOVCC(size_FDQ, fcc) \
2750	19f329ad	blueswir1	{ \
2751	0425bee5	blueswir1	TCGv r_cond; \
2752	19f329ad	blueswir1	int l1; \
2753	19f329ad	blueswir1	\
2754	19f329ad	blueswir1	l1 = gen_new_label(); \
2755	19f329ad	blueswir1	r_cond = tcg_temp_new(TCG_TYPE_TL); \
2756	19f329ad	blueswir1	cond = GET_FIELD_SP(insn, 14, 17); \
2757	19f329ad	blueswir1	gen_fcond(r_cond, fcc, cond); \
2758	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2759	cb63669a	pbrook	0, l1); \
2760	77f193da	blueswir1	glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
2761	77f193da	blueswir1	(glue(size_FDQ, FPREG(rs2))); \
2762	77f193da	blueswir1	glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
2763	77f193da	blueswir1	(glue(size_FDQ, FPREG(rd))); \
2764	19f329ad	blueswir1	gen_set_label(l1); \
2765	2ea815ca	blueswir1	tcg_temp_free(r_cond); \
2766	19f329ad	blueswir1	}
2767	0f8a249a	blueswir1	case 0x001: /* V9 fmovscc %fcc0 */
2768	19f329ad	blueswir1	FMOVCC(F, 0);
2769	0f8a249a	blueswir1	break;
2770	0f8a249a	blueswir1	case 0x002: /* V9 fmovdcc %fcc0 */
2771	19f329ad	blueswir1	FMOVCC(D, 0);
2772	0f8a249a	blueswir1	break;
2773	0f8a249a	blueswir1	case 0x003: /* V9 fmovqcc %fcc0 */
2774	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2775	19f329ad	blueswir1	FMOVCC(Q, 0);
2776	1f587329	blueswir1	break;
2777	0f8a249a	blueswir1	case 0x041: /* V9 fmovscc %fcc1 */
2778	19f329ad	blueswir1	FMOVCC(F, 1);
2779	0f8a249a	blueswir1	break;
2780	0f8a249a	blueswir1	case 0x042: /* V9 fmovdcc %fcc1 */
2781	19f329ad	blueswir1	FMOVCC(D, 1);
2782	0f8a249a	blueswir1	break;
2783	0f8a249a	blueswir1	case 0x043: /* V9 fmovqcc %fcc1 */
2784	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2785	19f329ad	blueswir1	FMOVCC(Q, 1);
2786	1f587329	blueswir1	break;
2787	0f8a249a	blueswir1	case 0x081: /* V9 fmovscc %fcc2 */
2788	19f329ad	blueswir1	FMOVCC(F, 2);
2789	0f8a249a	blueswir1	break;
2790	0f8a249a	blueswir1	case 0x082: /* V9 fmovdcc %fcc2 */
2791	19f329ad	blueswir1	FMOVCC(D, 2);
2792	0f8a249a	blueswir1	break;
2793	0f8a249a	blueswir1	case 0x083: /* V9 fmovqcc %fcc2 */
2794	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2795	19f329ad	blueswir1	FMOVCC(Q, 2);
2796	1f587329	blueswir1	break;
2797	0f8a249a	blueswir1	case 0x0c1: /* V9 fmovscc %fcc3 */
2798	19f329ad	blueswir1	FMOVCC(F, 3);
2799	0f8a249a	blueswir1	break;
2800	0f8a249a	blueswir1	case 0x0c2: /* V9 fmovdcc %fcc3 */
2801	19f329ad	blueswir1	FMOVCC(D, 3);
2802	0f8a249a	blueswir1	break;
2803	0f8a249a	blueswir1	case 0x0c3: /* V9 fmovqcc %fcc3 */
2804	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2805	19f329ad	blueswir1	FMOVCC(Q, 3);
2806	1f587329	blueswir1	break;
2807	19f329ad	blueswir1	#undef FMOVCC
2808	19f329ad	blueswir1	#define FMOVCC(size_FDQ, icc) \
2809	19f329ad	blueswir1	{ \
2810	0425bee5	blueswir1	TCGv r_cond; \
2811	19f329ad	blueswir1	int l1; \
2812	19f329ad	blueswir1	\
2813	19f329ad	blueswir1	l1 = gen_new_label(); \
2814	19f329ad	blueswir1	r_cond = tcg_temp_new(TCG_TYPE_TL); \
2815	19f329ad	blueswir1	cond = GET_FIELD_SP(insn, 14, 17); \
2816	19f329ad	blueswir1	gen_cond(r_cond, icc, cond); \
2817	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2818	cb63669a	pbrook	0, l1); \
2819	77f193da	blueswir1	glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
2820	77f193da	blueswir1	(glue(size_FDQ, FPREG(rs2))); \
2821	77f193da	blueswir1	glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
2822	77f193da	blueswir1	(glue(size_FDQ, FPREG(rd))); \
2823	19f329ad	blueswir1	gen_set_label(l1); \
2824	2ea815ca	blueswir1	tcg_temp_free(r_cond); \
2825	19f329ad	blueswir1	}
2826	19f329ad	blueswir1
2827	0f8a249a	blueswir1	case 0x101: /* V9 fmovscc %icc */
2828	19f329ad	blueswir1	FMOVCC(F, 0);
2829	0f8a249a	blueswir1	break;
2830	0f8a249a	blueswir1	case 0x102: /* V9 fmovdcc %icc */
2831	19f329ad	blueswir1	FMOVCC(D, 0);
2832	0f8a249a	blueswir1	case 0x103: /* V9 fmovqcc %icc */
2833	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2834	64a88d5d	blueswir1	FMOVCC(Q, 0);
2835	1f587329	blueswir1	break;
2836	0f8a249a	blueswir1	case 0x181: /* V9 fmovscc %xcc */
2837	19f329ad	blueswir1	FMOVCC(F, 1);
2838	0f8a249a	blueswir1	break;
2839	0f8a249a	blueswir1	case 0x182: /* V9 fmovdcc %xcc */
2840	19f329ad	blueswir1	FMOVCC(D, 1);
2841	0f8a249a	blueswir1	break;
2842	0f8a249a	blueswir1	case 0x183: /* V9 fmovqcc %xcc */
2843	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2844	19f329ad	blueswir1	FMOVCC(Q, 1);
2845	1f587329	blueswir1	break;
2846	19f329ad	blueswir1	#undef FMOVCC
2847	1f587329	blueswir1	#endif
2848	1f587329	blueswir1	case 0x51: /* fcmps, V9 %fcc */
2849	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2850	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2851	7e8c2b6c	blueswir1	gen_op_fcmps(rd & 3);
2852	0f8a249a	blueswir1	break;
2853	1f587329	blueswir1	case 0x52: /* fcmpd, V9 %fcc */
2854	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2855	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2856	7e8c2b6c	blueswir1	gen_op_fcmpd(rd & 3);
2857	0f8a249a	blueswir1	break;
2858	1f587329	blueswir1	case 0x53: /* fcmpq, V9 %fcc */
2859	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2860	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2861	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2862	7e8c2b6c	blueswir1	gen_op_fcmpq(rd & 3);
2863	1f587329	blueswir1	break;
2864	0f8a249a	blueswir1	case 0x55: /* fcmpes, V9 %fcc */
2865	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2866	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2867	7e8c2b6c	blueswir1	gen_op_fcmpes(rd & 3);
2868	0f8a249a	blueswir1	break;
2869	0f8a249a	blueswir1	case 0x56: /* fcmped, V9 %fcc */
2870	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2871	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2872	7e8c2b6c	blueswir1	gen_op_fcmped(rd & 3);
2873	0f8a249a	blueswir1	break;
2874	1f587329	blueswir1	case 0x57: /* fcmpeq, V9 %fcc */
2875	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2876	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2877	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2878	7e8c2b6c	blueswir1	gen_op_fcmpeq(rd & 3);
2879	1f587329	blueswir1	break;
2880	0f8a249a	blueswir1	default:
2881	0f8a249a	blueswir1	goto illegal_insn;
2882	0f8a249a	blueswir1	}
2883	0f8a249a	blueswir1	} else if (xop == 0x2) {
2884	0f8a249a	blueswir1	// clr/mov shortcut
2885	e80cfcfc	bellard
2886	e80cfcfc	bellard	rs1 = GET_FIELD(insn, 13, 17);
2887	0f8a249a	blueswir1	if (rs1 == 0) {
2888	1a2fb1c0	blueswir1	// or %g0, x, y -> mov T0, x; mov y, T0
2889	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
2890	2ea815ca	blueswir1	TCGv r_const;
2891	2ea815ca	blueswir1
2892	0f8a249a	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
2893	2ea815ca	blueswir1	r_const = tcg_const_tl((int)rs2);
2894	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
2895	2ea815ca	blueswir1	tcg_temp_free(r_const);
2896	0f8a249a	blueswir1	} else { /* register */
2897	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
2898	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_dst);
2899	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2900	0f8a249a	blueswir1	}
2901	0f8a249a	blueswir1	} else {
2902	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2903	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
2904	0f8a249a	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
2905	6ae20372	blueswir1	tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2906	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2907	0f8a249a	blueswir1	} else { /* register */
2908	0f8a249a	blueswir1	// or x, %g0, y -> mov T1, x; mov y, T1
2909	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
2910	0f8a249a	blueswir1	if (rs2 != 0) {
2911	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
2912	6ae20372	blueswir1	tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2913	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2914	6f551262	blueswir1	} else
2915	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_src1);
2916	0f8a249a	blueswir1	}
2917	0f8a249a	blueswir1	}
2918	83469015	bellard	#ifdef TARGET_SPARC64
2919	0f8a249a	blueswir1	} else if (xop == 0x25) { /* sll, V9 sllx */
2920	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2921	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
2922	83469015	bellard	rs2 = GET_FIELDs(insn, 20, 31);
2923	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2924	6ae20372	blueswir1	tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2925	1a2fb1c0	blueswir1	} else {
2926	01b1fa6d	blueswir1	tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x1f);
2927	1a2fb1c0	blueswir1	}
2928	0f8a249a	blueswir1	} else { /* register */
2929	83469015	bellard	rs2 = GET_FIELD(insn, 27, 31);
2930	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
2931	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2932	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2933	1a2fb1c0	blueswir1	} else {
2934	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2935	1a2fb1c0	blueswir1	}
2936	01b1fa6d	blueswir1	tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2937	83469015	bellard	}
2938	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2939	0f8a249a	blueswir1	} else if (xop == 0x26) { /* srl, V9 srlx */
2940	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2941	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
2942	83469015	bellard	rs2 = GET_FIELDs(insn, 20, 31);
2943	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2944	6ae20372	blueswir1	tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2945	1a2fb1c0	blueswir1	} else {
2946	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2947	6ae20372	blueswir1	tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2948	1a2fb1c0	blueswir1	}
2949	0f8a249a	blueswir1	} else { /* register */
2950	83469015	bellard	rs2 = GET_FIELD(insn, 27, 31);
2951	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
2952	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2953	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2954	6ae20372	blueswir1	tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2955	1a2fb1c0	blueswir1	} else {
2956	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2957	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2958	6ae20372	blueswir1	tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2959	1a2fb1c0	blueswir1	}
2960	83469015	bellard	}
2961	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2962	0f8a249a	blueswir1	} else if (xop == 0x27) { /* sra, V9 srax */
2963	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2964	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
2965	83469015	bellard	rs2 = GET_FIELDs(insn, 20, 31);
2966	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2967	6ae20372	blueswir1	tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2968	1a2fb1c0	blueswir1	} else {
2969	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2970	6ae20372	blueswir1	tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2971	6ae20372	blueswir1	tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2972	1a2fb1c0	blueswir1	}
2973	0f8a249a	blueswir1	} else { /* register */
2974	83469015	bellard	rs2 = GET_FIELD(insn, 27, 31);
2975	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
2976	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2977	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2978	6ae20372	blueswir1	tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
2979	1a2fb1c0	blueswir1	} else {
2980	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2981	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2982	01b1fa6d	blueswir1	tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2983	6ae20372	blueswir1	tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2984	1a2fb1c0	blueswir1	}
2985	83469015	bellard	}
2986	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2987	83469015	bellard	#endif
2988	fcc72045	blueswir1	} else if (xop < 0x36) {
2989	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2990	a49d9390	blueswir1	cpu_src2 = get_src2(insn, cpu_src2);
2991	cf495bcf	bellard	if (xop < 0x20) {
2992	cf495bcf	bellard	switch (xop & ~0x10) {
2993	cf495bcf	bellard	case 0x0:
2994	cf495bcf	bellard	if (xop & 0x10)
2995	6ae20372	blueswir1	gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2996	cf495bcf	bellard	else
2997	6ae20372	blueswir1	tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2998	cf495bcf	bellard	break;
2999	cf495bcf	bellard	case 0x1:
3000	6ae20372	blueswir1	tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
3001	cf495bcf	bellard	if (xop & 0x10)
3002	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3003	cf495bcf	bellard	break;
3004	cf495bcf	bellard	case 0x2:
3005	6ae20372	blueswir1	tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
3006	0f8a249a	blueswir1	if (xop & 0x10)
3007	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3008	0f8a249a	blueswir1	break;
3009	cf495bcf	bellard	case 0x3:
3010	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3011	cf495bcf	bellard	if (xop & 0x10)
3012	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3013	cf495bcf	bellard	break;
3014	cf495bcf	bellard	case 0x4:
3015	cf495bcf	bellard	if (xop & 0x10)
3016	6ae20372	blueswir1	gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3017	cf495bcf	bellard	else
3018	6ae20372	blueswir1	tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
3019	cf495bcf	bellard	break;
3020	cf495bcf	bellard	case 0x5:
3021	6ae20372	blueswir1	tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3022	6ae20372	blueswir1	tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
3023	cf495bcf	bellard	if (xop & 0x10)
3024	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3025	cf495bcf	bellard	break;
3026	cf495bcf	bellard	case 0x6:
3027	6ae20372	blueswir1	tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3028	6ae20372	blueswir1	tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
3029	cf495bcf	bellard	if (xop & 0x10)
3030	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3031	cf495bcf	bellard	break;
3032	cf495bcf	bellard	case 0x7:
3033	6ae20372	blueswir1	tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3034	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3035	cf495bcf	bellard	if (xop & 0x10)
3036	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3037	cf495bcf	bellard	break;
3038	cf495bcf	bellard	case 0x8:
3039	cf495bcf	bellard	if (xop & 0x10)
3040	6ae20372	blueswir1	gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
3041	38bc628b	blueswir1	else {
3042	dc99a3f2	blueswir1	gen_mov_reg_C(cpu_tmp0, cpu_psr);
3043	6ae20372	blueswir1	tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3044	6ae20372	blueswir1	tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
3045	38bc628b	blueswir1	}
3046	cf495bcf	bellard	break;
3047	ded3ab80	pbrook	#ifdef TARGET_SPARC64
3048	0f8a249a	blueswir1	case 0x9: /* V9 mulx */
3049	6ae20372	blueswir1	tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3050	ded3ab80	pbrook	break;
3051	ded3ab80	pbrook	#endif
3052	cf495bcf	bellard	case 0xa:
3053	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, MUL);
3054	6ae20372	blueswir1	gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3055	cf495bcf	bellard	if (xop & 0x10)
3056	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3057	cf495bcf	bellard	break;
3058	cf495bcf	bellard	case 0xb:
3059	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, MUL);
3060	6ae20372	blueswir1	gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3061	cf495bcf	bellard	if (xop & 0x10)
3062	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3063	cf495bcf	bellard	break;
3064	cf495bcf	bellard	case 0xc:
3065	cf495bcf	bellard	if (xop & 0x10)
3066	6ae20372	blueswir1	gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3067	38bc628b	blueswir1	else {
3068	dc99a3f2	blueswir1	gen_mov_reg_C(cpu_tmp0, cpu_psr);
3069	6ae20372	blueswir1	tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3070	6ae20372	blueswir1	tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
3071	38bc628b	blueswir1	}
3072	cf495bcf	bellard	break;
3073	ded3ab80	pbrook	#ifdef TARGET_SPARC64
3074	0f8a249a	blueswir1	case 0xd: /* V9 udivx */
3075	07bf2857	blueswir1	tcg_gen_mov_tl(cpu_cc_src, cpu_src1);
3076	07bf2857	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, cpu_src2);
3077	07bf2857	blueswir1	gen_trap_ifdivzero_tl(cpu_cc_src2);
3078	07bf2857	blueswir1	tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2);
3079	ded3ab80	pbrook	break;
3080	ded3ab80	pbrook	#endif
3081	cf495bcf	bellard	case 0xe:
3082	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, DIV);
3083	77f193da	blueswir1	tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
3084	77f193da	blueswir1	cpu_src2);
3085	cf495bcf	bellard	if (xop & 0x10)
3086	6ae20372	blueswir1	gen_op_div_cc(cpu_dst);
3087	cf495bcf	bellard	break;
3088	cf495bcf	bellard	case 0xf:
3089	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, DIV);
3090	77f193da	blueswir1	tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
3091	77f193da	blueswir1	cpu_src2);
3092	cf495bcf	bellard	if (xop & 0x10)
3093	6ae20372	blueswir1	gen_op_div_cc(cpu_dst);
3094	cf495bcf	bellard	break;
3095	cf495bcf	bellard	default:
3096	cf495bcf	bellard	goto illegal_insn;
3097	cf495bcf	bellard	}
3098	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3099	cf495bcf	bellard	} else {
3100	cf495bcf	bellard	switch (xop) {
3101	0f8a249a	blueswir1	case 0x20: /* taddcc */
3102	6ae20372	blueswir1	gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3103	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3104	0f8a249a	blueswir1	break;
3105	0f8a249a	blueswir1	case 0x21: /* tsubcc */
3106	6ae20372	blueswir1	gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3107	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3108	0f8a249a	blueswir1	break;
3109	0f8a249a	blueswir1	case 0x22: /* taddcctv */
3110	6ae20372	blueswir1	save_state(dc, cpu_cond);
3111	6ae20372	blueswir1	gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3112	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3113	0f8a249a	blueswir1	break;
3114	0f8a249a	blueswir1	case 0x23: /* tsubcctv */
3115	6ae20372	blueswir1	save_state(dc, cpu_cond);
3116	6ae20372	blueswir1	gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3117	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3118	0f8a249a	blueswir1	break;
3119	cf495bcf	bellard	case 0x24: /* mulscc */
3120	6ae20372	blueswir1	gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3121	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3122	cf495bcf	bellard	break;
3123	83469015	bellard	#ifndef TARGET_SPARC64
3124	0f8a249a	blueswir1	case 0x25: /* sll */
3125	e35298cd	blueswir1	if (IS_IMM) { /* immediate */
3126	e35298cd	blueswir1	rs2 = GET_FIELDs(insn, 20, 31);
3127	e35298cd	blueswir1	tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3128	e35298cd	blueswir1	} else { /* register */
3129	e35298cd	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3130	e35298cd	blueswir1	tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3131	e35298cd	blueswir1	}
3132	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3133	cf495bcf	bellard	break;
3134	83469015	bellard	case 0x26: /* srl */
3135	e35298cd	blueswir1	if (IS_IMM) { /* immediate */
3136	e35298cd	blueswir1	rs2 = GET_FIELDs(insn, 20, 31);
3137	e35298cd	blueswir1	tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3138	e35298cd	blueswir1	} else { /* register */
3139	e35298cd	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3140	e35298cd	blueswir1	tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3141	e35298cd	blueswir1	}
3142	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3143	cf495bcf	bellard	break;
3144	83469015	bellard	case 0x27: /* sra */
3145	e35298cd	blueswir1	if (IS_IMM) { /* immediate */
3146	e35298cd	blueswir1	rs2 = GET_FIELDs(insn, 20, 31);
3147	e35298cd	blueswir1	tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3148	e35298cd	blueswir1	} else { /* register */
3149	e35298cd	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3150	e35298cd	blueswir1	tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3151	e35298cd	blueswir1	}
3152	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3153	cf495bcf	bellard	break;
3154	83469015	bellard	#endif
3155	cf495bcf	bellard	case 0x30:
3156	cf495bcf	bellard	{
3157	cf495bcf	bellard	switch(rd) {
3158	3475187d	bellard	case 0: /* wry */
3159	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3160	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3161	77f193da	blueswir1	offsetof(CPUSPARCState, y));
3162	cf495bcf	bellard	break;
3163	65fe7b09	blueswir1	#ifndef TARGET_SPARC64
3164	65fe7b09	blueswir1	case 0x01 ... 0x0f: /* undefined in the
3165	65fe7b09	blueswir1	SPARCv8 manual, nop
3166	65fe7b09	blueswir1	on the microSPARC
3167	65fe7b09	blueswir1	II */
3168	65fe7b09	blueswir1	case 0x10 ... 0x1f: /* implementation-dependent
3169	65fe7b09	blueswir1	in the SPARCv8
3170	65fe7b09	blueswir1	manual, nop on the
3171	65fe7b09	blueswir1	microSPARC II */
3172	65fe7b09	blueswir1	break;
3173	65fe7b09	blueswir1	#else
3174	0f8a249a	blueswir1	case 0x2: /* V9 wrccr */
3175	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3176	6ae20372	blueswir1	tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3177	0f8a249a	blueswir1	break;
3178	0f8a249a	blueswir1	case 0x3: /* V9 wrasi */
3179	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3180	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3181	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3182	77f193da	blueswir1	offsetof(CPUSPARCState, asi));
3183	0f8a249a	blueswir1	break;
3184	0f8a249a	blueswir1	case 0x6: /* V9 wrfprs */
3185	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3186	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3187	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3188	77f193da	blueswir1	offsetof(CPUSPARCState, fprs));
3189	6ae20372	blueswir1	save_state(dc, cpu_cond);
3190	3299908c	blueswir1	gen_op_next_insn();
3191	57fec1fe	bellard	tcg_gen_exit_tb(0);
3192	3299908c	blueswir1	dc->is_br = 1;
3193	0f8a249a	blueswir1	break;
3194	0f8a249a	blueswir1	case 0xf: /* V9 sir, nop if user */
3195	3475187d	bellard	#if !defined(CONFIG_USER_ONLY)
3196	0f8a249a	blueswir1	if (supervisor(dc))
3197	1a2fb1c0	blueswir1	; // XXX
3198	3475187d	bellard	#endif
3199	0f8a249a	blueswir1	break;
3200	0f8a249a	blueswir1	case 0x13: /* Graphics Status */
3201	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
3202	725cb90b	bellard	goto jmp_insn;
3203	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3204	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3205	77f193da	blueswir1	offsetof(CPUSPARCState, gsr));
3206	0f8a249a	blueswir1	break;
3207	0f8a249a	blueswir1	case 0x17: /* Tick compare */
3208	83469015	bellard	#if !defined(CONFIG_USER_ONLY)
3209	0f8a249a	blueswir1	if (!supervisor(dc))
3210	0f8a249a	blueswir1	goto illegal_insn;
3211	83469015	bellard	#endif
3212	ccd4a219	blueswir1	{
3213	ccd4a219	blueswir1	TCGv r_tickptr;
3214	ccd4a219	blueswir1
3215	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3216	6ae20372	blueswir1	cpu_src2);
3217	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3218	77f193da	blueswir1	offsetof(CPUSPARCState,
3219	77f193da	blueswir1	tick_cmpr));
3220	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3221	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
3222	ccd4a219	blueswir1	offsetof(CPUState, tick));
3223	ccd4a219	blueswir1	tcg_gen_helper_0_2(helper_tick_set_limit,
3224	ece43b8d	blueswir1	r_tickptr, cpu_tmp0);
3225	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
3226	ccd4a219	blueswir1	}
3227	0f8a249a	blueswir1	break;
3228	0f8a249a	blueswir1	case 0x18: /* System tick */
3229	83469015	bellard	#if !defined(CONFIG_USER_ONLY)
3230	0f8a249a	blueswir1	if (!supervisor(dc))
3231	0f8a249a	blueswir1	goto illegal_insn;
3232	83469015	bellard	#endif
3233	ccd4a219	blueswir1	{
3234	ccd4a219	blueswir1	TCGv r_tickptr;
3235	ccd4a219	blueswir1
3236	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1,
3237	6ae20372	blueswir1	cpu_src2);
3238	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3239	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
3240	ccd4a219	blueswir1	offsetof(CPUState, stick));
3241	ccd4a219	blueswir1	tcg_gen_helper_0_2(helper_tick_set_count,
3242	6ae20372	blueswir1	r_tickptr, cpu_dst);
3243	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
3244	ccd4a219	blueswir1	}
3245	0f8a249a	blueswir1	break;
3246	0f8a249a	blueswir1	case 0x19: /* System tick compare */
3247	83469015	bellard	#if !defined(CONFIG_USER_ONLY)
3248	0f8a249a	blueswir1	if (!supervisor(dc))
3249	0f8a249a	blueswir1	goto illegal_insn;
3250	3475187d	bellard	#endif
3251	ccd4a219	blueswir1	{
3252	ccd4a219	blueswir1	TCGv r_tickptr;
3253	ccd4a219	blueswir1
3254	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3255	6ae20372	blueswir1	cpu_src2);
3256	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3257	77f193da	blueswir1	offsetof(CPUSPARCState,
3258	77f193da	blueswir1	stick_cmpr));
3259	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3260	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
3261	ccd4a219	blueswir1	offsetof(CPUState, stick));
3262	ccd4a219	blueswir1	tcg_gen_helper_0_2(helper_tick_set_limit,
3263	ece43b8d	blueswir1	r_tickptr, cpu_tmp0);
3264	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
3265	ccd4a219	blueswir1	}
3266	0f8a249a	blueswir1	break;
3267	83469015	bellard
3268	0f8a249a	blueswir1	case 0x10: /* Performance Control */
3269	77f193da	blueswir1	case 0x11: /* Performance Instrumentation
3270	77f193da	blueswir1	Counter */
3271	0f8a249a	blueswir1	case 0x12: /* Dispatch Control */
3272	0f8a249a	blueswir1	case 0x14: /* Softint set */
3273	0f8a249a	blueswir1	case 0x15: /* Softint clear */
3274	0f8a249a	blueswir1	case 0x16: /* Softint write */
3275	83469015	bellard	#endif
3276	3475187d	bellard	default:
3277	cf495bcf	bellard	goto illegal_insn;
3278	cf495bcf	bellard	}
3279	cf495bcf	bellard	}
3280	cf495bcf	bellard	break;
3281	e8af50a3	bellard	#if !defined(CONFIG_USER_ONLY)
3282	af7bf89b	bellard	case 0x31: /* wrpsr, V9 saved, restored */
3283	e8af50a3	bellard	{
3284	0f8a249a	blueswir1	if (!supervisor(dc))
3285	0f8a249a	blueswir1	goto priv_insn;
3286	3475187d	bellard	#ifdef TARGET_SPARC64
3287	0f8a249a	blueswir1	switch (rd) {
3288	0f8a249a	blueswir1	case 0:
3289	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_saved);
3290	0f8a249a	blueswir1	break;
3291	0f8a249a	blueswir1	case 1:
3292	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_restored);
3293	0f8a249a	blueswir1	break;
3294	e9ebed4d	blueswir1	case 2: /* UA2005 allclean */
3295	e9ebed4d	blueswir1	case 3: /* UA2005 otherw */
3296	e9ebed4d	blueswir1	case 4: /* UA2005 normalw */
3297	e9ebed4d	blueswir1	case 5: /* UA2005 invalw */
3298	e9ebed4d	blueswir1	// XXX
3299	0f8a249a	blueswir1	default:
3300	3475187d	bellard	goto illegal_insn;
3301	3475187d	bellard	}
3302	3475187d	bellard	#else
3303	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3304	6ae20372	blueswir1	tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3305	6ae20372	blueswir1	save_state(dc, cpu_cond);
3306	9e61bde5	bellard	gen_op_next_insn();
3307	57fec1fe	bellard	tcg_gen_exit_tb(0);
3308	0f8a249a	blueswir1	dc->is_br = 1;
3309	3475187d	bellard	#endif
3310	e8af50a3	bellard	}
3311	e8af50a3	bellard	break;
3312	af7bf89b	bellard	case 0x32: /* wrwim, V9 wrpr */
3313	e8af50a3	bellard	{
3314	0f8a249a	blueswir1	if (!supervisor(dc))
3315	0f8a249a	blueswir1	goto priv_insn;
3316	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3317	3475187d	bellard	#ifdef TARGET_SPARC64
3318	0f8a249a	blueswir1	switch (rd) {
3319	0f8a249a	blueswir1	case 0: // tpc
3320	375ee38b	blueswir1	{
3321	375ee38b	blueswir1	TCGv r_tsptr;
3322	375ee38b	blueswir1
3323	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3324	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
3325	375ee38b	blueswir1	offsetof(CPUState, tsptr));
3326	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3327	375ee38b	blueswir1	offsetof(trap_state, tpc));
3328	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
3329	375ee38b	blueswir1	}
3330	0f8a249a	blueswir1	break;
3331	0f8a249a	blueswir1	case 1: // tnpc
3332	375ee38b	blueswir1	{
3333	375ee38b	blueswir1	TCGv r_tsptr;
3334	375ee38b	blueswir1
3335	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3336	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
3337	375ee38b	blueswir1	offsetof(CPUState, tsptr));
3338	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3339	375ee38b	blueswir1	offsetof(trap_state, tnpc));
3340	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
3341	375ee38b	blueswir1	}
3342	0f8a249a	blueswir1	break;
3343	0f8a249a	blueswir1	case 2: // tstate
3344	375ee38b	blueswir1	{
3345	375ee38b	blueswir1	TCGv r_tsptr;
3346	375ee38b	blueswir1
3347	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3348	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
3349	375ee38b	blueswir1	offsetof(CPUState, tsptr));
3350	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3351	77f193da	blueswir1	offsetof(trap_state,
3352	77f193da	blueswir1	tstate));
3353	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
3354	375ee38b	blueswir1	}
3355	0f8a249a	blueswir1	break;
3356	0f8a249a	blueswir1	case 3: // tt
3357	375ee38b	blueswir1	{
3358	375ee38b	blueswir1	TCGv r_tsptr;
3359	375ee38b	blueswir1
3360	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3361	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
3362	375ee38b	blueswir1	offsetof(CPUState, tsptr));
3363	ece43b8d	blueswir1	tcg_gen_st_i32(cpu_tmp0, r_tsptr,
3364	375ee38b	blueswir1	offsetof(trap_state, tt));
3365	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
3366	375ee38b	blueswir1	}
3367	0f8a249a	blueswir1	break;
3368	0f8a249a	blueswir1	case 4: // tick
3369	ccd4a219	blueswir1	{
3370	ccd4a219	blueswir1	TCGv r_tickptr;
3371	ccd4a219	blueswir1
3372	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3373	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
3374	ccd4a219	blueswir1	offsetof(CPUState, tick));
3375	ccd4a219	blueswir1	tcg_gen_helper_0_2(helper_tick_set_count,
3376	ece43b8d	blueswir1	r_tickptr, cpu_tmp0);
3377	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
3378	ccd4a219	blueswir1	}
3379	0f8a249a	blueswir1	break;
3380	0f8a249a	blueswir1	case 5: // tba
3381	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3382	77f193da	blueswir1	offsetof(CPUSPARCState, tbr));
3383	0f8a249a	blueswir1	break;
3384	0f8a249a	blueswir1	case 6: // pstate
3385	6ae20372	blueswir1	save_state(dc, cpu_cond);
3386	ece43b8d	blueswir1	tcg_gen_helper_0_1(helper_wrpstate, cpu_tmp0);
3387	ded3ab80	pbrook	gen_op_next_insn();
3388	57fec1fe	bellard	tcg_gen_exit_tb(0);
3389	ded3ab80	pbrook	dc->is_br = 1;
3390	0f8a249a	blueswir1	break;
3391	0f8a249a	blueswir1	case 7: // tl
3392	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3393	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3394	77f193da	blueswir1	offsetof(CPUSPARCState, tl));
3395	0f8a249a	blueswir1	break;
3396	0f8a249a	blueswir1	case 8: // pil
3397	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3398	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3399	77f193da	blueswir1	offsetof(CPUSPARCState,
3400	77f193da	blueswir1	psrpil));
3401	0f8a249a	blueswir1	break;
3402	0f8a249a	blueswir1	case 9: // cwp
3403	ece43b8d	blueswir1	tcg_gen_helper_0_1(helper_wrcwp, cpu_tmp0);
3404	0f8a249a	blueswir1	break;
3405	0f8a249a	blueswir1	case 10: // cansave
3406	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3407	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3408	77f193da	blueswir1	offsetof(CPUSPARCState,
3409	77f193da	blueswir1	cansave));
3410	0f8a249a	blueswir1	break;
3411	0f8a249a	blueswir1	case 11: // canrestore
3412	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3413	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3414	77f193da	blueswir1	offsetof(CPUSPARCState,
3415	77f193da	blueswir1	canrestore));
3416	0f8a249a	blueswir1	break;
3417	0f8a249a	blueswir1	case 12: // cleanwin
3418	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3419	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3420	77f193da	blueswir1	offsetof(CPUSPARCState,
3421	77f193da	blueswir1	cleanwin));
3422	0f8a249a	blueswir1	break;
3423	0f8a249a	blueswir1	case 13: // otherwin
3424	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3425	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3426	77f193da	blueswir1	offsetof(CPUSPARCState,
3427	77f193da	blueswir1	otherwin));
3428	0f8a249a	blueswir1	break;
3429	0f8a249a	blueswir1	case 14: // wstate
3430	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3431	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3432	77f193da	blueswir1	offsetof(CPUSPARCState,
3433	77f193da	blueswir1	wstate));
3434	0f8a249a	blueswir1	break;
3435	e9ebed4d	blueswir1	case 16: // UA2005 gl
3436	fb79ceb9	blueswir1	CHECK_IU_FEATURE(dc, GL);
3437	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3438	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3439	77f193da	blueswir1	offsetof(CPUSPARCState, gl));
3440	e9ebed4d	blueswir1	break;
3441	e9ebed4d	blueswir1	case 26: // UA2005 strand status
3442	fb79ceb9	blueswir1	CHECK_IU_FEATURE(dc, HYPV);
3443	e9ebed4d	blueswir1	if (!hypervisor(dc))
3444	e9ebed4d	blueswir1	goto priv_insn;
3445	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3446	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3447	77f193da	blueswir1	offsetof(CPUSPARCState, ssr));
3448	e9ebed4d	blueswir1	break;
3449	0f8a249a	blueswir1	default:
3450	0f8a249a	blueswir1	goto illegal_insn;
3451	0f8a249a	blueswir1	}
3452	3475187d	bellard	#else
3453	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3454	c93e7817	blueswir1	if (dc->def->nwindows != 32)
3455	c93e7817	blueswir1	tcg_gen_andi_tl(cpu_tmp32, cpu_tmp32,
3456	c93e7817	blueswir1	(1 << dc->def->nwindows) - 1);
3457	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3458	77f193da	blueswir1	offsetof(CPUSPARCState, wim));
3459	3475187d	bellard	#endif
3460	e8af50a3	bellard	}
3461	e8af50a3	bellard	break;
3462	e9ebed4d	blueswir1	case 0x33: /* wrtbr, UA2005 wrhpr */
3463	e8af50a3	bellard	{
3464	e9ebed4d	blueswir1	#ifndef TARGET_SPARC64
3465	0f8a249a	blueswir1	if (!supervisor(dc))
3466	0f8a249a	blueswir1	goto priv_insn;
3467	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3468	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3469	77f193da	blueswir1	offsetof(CPUSPARCState, tbr));
3470	e9ebed4d	blueswir1	#else
3471	fb79ceb9	blueswir1	CHECK_IU_FEATURE(dc, HYPV);
3472	e9ebed4d	blueswir1	if (!hypervisor(dc))
3473	e9ebed4d	blueswir1	goto priv_insn;
3474	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3475	e9ebed4d	blueswir1	switch (rd) {
3476	e9ebed4d	blueswir1	case 0: // hpstate
3477	e9ebed4d	blueswir1	// XXX gen_op_wrhpstate();
3478	6ae20372	blueswir1	save_state(dc, cpu_cond);
3479	e9ebed4d	blueswir1	gen_op_next_insn();
3480	57fec1fe	bellard	tcg_gen_exit_tb(0);
3481	e9ebed4d	blueswir1	dc->is_br = 1;
3482	e9ebed4d	blueswir1	break;
3483	e9ebed4d	blueswir1	case 1: // htstate
3484	e9ebed4d	blueswir1	// XXX gen_op_wrhtstate();
3485	e9ebed4d	blueswir1	break;
3486	e9ebed4d	blueswir1	case 3: // hintp
3487	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3488	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3489	77f193da	blueswir1	offsetof(CPUSPARCState, hintp));
3490	e9ebed4d	blueswir1	break;
3491	e9ebed4d	blueswir1	case 5: // htba
3492	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3493	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3494	77f193da	blueswir1	offsetof(CPUSPARCState, htba));
3495	e9ebed4d	blueswir1	break;
3496	e9ebed4d	blueswir1	case 31: // hstick_cmpr
3497	ccd4a219	blueswir1	{
3498	ccd4a219	blueswir1	TCGv r_tickptr;
3499	ccd4a219	blueswir1
3500	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3501	77f193da	blueswir1	offsetof(CPUSPARCState,
3502	77f193da	blueswir1	hstick_cmpr));
3503	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3504	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
3505	ccd4a219	blueswir1	offsetof(CPUState, hstick));
3506	ccd4a219	blueswir1	tcg_gen_helper_0_2(helper_tick_set_limit,
3507	ece43b8d	blueswir1	r_tickptr, cpu_tmp0);
3508	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
3509	ccd4a219	blueswir1	}
3510	e9ebed4d	blueswir1	break;
3511	e9ebed4d	blueswir1	case 6: // hver readonly
3512	e9ebed4d	blueswir1	default:
3513	e9ebed4d	blueswir1	goto illegal_insn;
3514	e9ebed4d	blueswir1	}
3515	e9ebed4d	blueswir1	#endif
3516	e8af50a3	bellard	}
3517	e8af50a3	bellard	break;
3518	e8af50a3	bellard	#endif
3519	3475187d	bellard	#ifdef TARGET_SPARC64
3520	0f8a249a	blueswir1	case 0x2c: /* V9 movcc */
3521	0f8a249a	blueswir1	{
3522	0f8a249a	blueswir1	int cc = GET_FIELD_SP(insn, 11, 12);
3523	0f8a249a	blueswir1	int cond = GET_FIELD_SP(insn, 14, 17);
3524	748b9d8e	blueswir1	TCGv r_cond;
3525	00f219bf	blueswir1	int l1;
3526	00f219bf	blueswir1
3527	748b9d8e	blueswir1	r_cond = tcg_temp_new(TCG_TYPE_TL);
3528	0f8a249a	blueswir1	if (insn & (1 << 18)) {
3529	0f8a249a	blueswir1	if (cc == 0)
3530	748b9d8e	blueswir1	gen_cond(r_cond, 0, cond);
3531	0f8a249a	blueswir1	else if (cc == 2)
3532	748b9d8e	blueswir1	gen_cond(r_cond, 1, cond);
3533	0f8a249a	blueswir1	else
3534	0f8a249a	blueswir1	goto illegal_insn;
3535	0f8a249a	blueswir1	} else {
3536	748b9d8e	blueswir1	gen_fcond(r_cond, cc, cond);
3537	0f8a249a	blueswir1	}
3538	00f219bf	blueswir1
3539	00f219bf	blueswir1	l1 = gen_new_label();
3540	00f219bf	blueswir1
3541	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
3542	00f219bf	blueswir1	if (IS_IMM) { /* immediate */
3543	2ea815ca	blueswir1	TCGv r_const;
3544	2ea815ca	blueswir1
3545	00f219bf	blueswir1	rs2 = GET_FIELD_SPs(insn, 0, 10);
3546	2ea815ca	blueswir1	r_const = tcg_const_tl((int)rs2);
3547	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
3548	2ea815ca	blueswir1	tcg_temp_free(r_const);
3549	00f219bf	blueswir1	} else {
3550	00f219bf	blueswir1	rs2 = GET_FIELD_SP(insn, 0, 4);
3551	9c6c6662	blueswir1	gen_movl_reg_TN(rs2, cpu_tmp0);
3552	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
3553	00f219bf	blueswir1	}
3554	00f219bf	blueswir1	gen_set_label(l1);
3555	2ea815ca	blueswir1	tcg_temp_free(r_cond);
3556	0f8a249a	blueswir1	break;
3557	0f8a249a	blueswir1	}
3558	0f8a249a	blueswir1	case 0x2d: /* V9 sdivx */
3559	6ae20372	blueswir1	gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3560	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3561	0f8a249a	blueswir1	break;
3562	0f8a249a	blueswir1	case 0x2e: /* V9 popc */
3563	0f8a249a	blueswir1	{
3564	a49d9390	blueswir1	cpu_src2 = get_src2(insn, cpu_src2);
3565	6ae20372	blueswir1	tcg_gen_helper_1_1(helper_popc, cpu_dst,
3566	6ae20372	blueswir1	cpu_src2);
3567	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3568	0f8a249a	blueswir1	}
3569	0f8a249a	blueswir1	case 0x2f: /* V9 movr */
3570	0f8a249a	blueswir1	{
3571	0f8a249a	blueswir1	int cond = GET_FIELD_SP(insn, 10, 12);
3572	00f219bf	blueswir1	int l1;
3573	00f219bf	blueswir1
3574	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
3575	00f219bf	blueswir1
3576	00f219bf	blueswir1	l1 = gen_new_label();
3577	00f219bf	blueswir1
3578	cb63669a	pbrook	tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
3579	cb63669a	pbrook	cpu_src1, 0, l1);
3580	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
3581	2ea815ca	blueswir1	TCGv r_const;
3582	2ea815ca	blueswir1
3583	0f8a249a	blueswir1	rs2 = GET_FIELD_SPs(insn, 0, 9);
3584	2ea815ca	blueswir1	r_const = tcg_const_tl((int)rs2);
3585	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
3586	2ea815ca	blueswir1	tcg_temp_free(r_const);
3587	00f219bf	blueswir1	} else {
3588	0f8a249a	blueswir1	rs2 = GET_FIELD_SP(insn, 0, 4);
3589	9c6c6662	blueswir1	gen_movl_reg_TN(rs2, cpu_tmp0);
3590	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
3591	0f8a249a	blueswir1	}
3592	00f219bf	blueswir1	gen_set_label(l1);
3593	0f8a249a	blueswir1	break;
3594	0f8a249a	blueswir1	}
3595	0f8a249a	blueswir1	#endif
3596	0f8a249a	blueswir1	default:
3597	0f8a249a	blueswir1	goto illegal_insn;
3598	0f8a249a	blueswir1	}
3599	0f8a249a	blueswir1	}
3600	3299908c	blueswir1	} else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3601	3299908c	blueswir1	#ifdef TARGET_SPARC64
3602	3299908c	blueswir1	int opf = GET_FIELD_SP(insn, 5, 13);
3603	3299908c	blueswir1	rs1 = GET_FIELD(insn, 13, 17);
3604	3299908c	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
3605	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
3606	e9ebed4d	blueswir1	goto jmp_insn;
3607	3299908c	blueswir1
3608	3299908c	blueswir1	switch (opf) {
3609	e9ebed4d	blueswir1	case 0x000: /* VIS I edge8cc */
3610	e9ebed4d	blueswir1	case 0x001: /* VIS II edge8n */
3611	e9ebed4d	blueswir1	case 0x002: /* VIS I edge8lcc */
3612	e9ebed4d	blueswir1	case 0x003: /* VIS II edge8ln */
3613	e9ebed4d	blueswir1	case 0x004: /* VIS I edge16cc */
3614	e9ebed4d	blueswir1	case 0x005: /* VIS II edge16n */
3615	e9ebed4d	blueswir1	case 0x006: /* VIS I edge16lcc */
3616	e9ebed4d	blueswir1	case 0x007: /* VIS II edge16ln */
3617	e9ebed4d	blueswir1	case 0x008: /* VIS I edge32cc */
3618	e9ebed4d	blueswir1	case 0x009: /* VIS II edge32n */
3619	e9ebed4d	blueswir1	case 0x00a: /* VIS I edge32lcc */
3620	e9ebed4d	blueswir1	case 0x00b: /* VIS II edge32ln */
3621	e9ebed4d	blueswir1	// XXX
3622	e9ebed4d	blueswir1	goto illegal_insn;
3623	e9ebed4d	blueswir1	case 0x010: /* VIS I array8 */
3624	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3625	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
3626	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
3627	6ae20372	blueswir1	tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3628	6ae20372	blueswir1	cpu_src2);
3629	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3630	e9ebed4d	blueswir1	break;
3631	e9ebed4d	blueswir1	case 0x012: /* VIS I array16 */
3632	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3633	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
3634	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
3635	6ae20372	blueswir1	tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3636	6ae20372	blueswir1	cpu_src2);
3637	6ae20372	blueswir1	tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3638	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3639	e9ebed4d	blueswir1	break;
3640	e9ebed4d	blueswir1	case 0x014: /* VIS I array32 */
3641	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3642	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
3643	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
3644	6ae20372	blueswir1	tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3645	6ae20372	blueswir1	cpu_src2);
3646	6ae20372	blueswir1	tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3647	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3648	e9ebed4d	blueswir1	break;
3649	3299908c	blueswir1	case 0x018: /* VIS I alignaddr */
3650	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3651	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
3652	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
3653	6ae20372	blueswir1	tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3654	6ae20372	blueswir1	cpu_src2);
3655	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3656	3299908c	blueswir1	break;
3657	e9ebed4d	blueswir1	case 0x019: /* VIS II bmask */
3658	3299908c	blueswir1	case 0x01a: /* VIS I alignaddrl */
3659	3299908c	blueswir1	// XXX
3660	e9ebed4d	blueswir1	goto illegal_insn;
3661	e9ebed4d	blueswir1	case 0x020: /* VIS I fcmple16 */
3662	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3663	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3664	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3665	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmple16);
3666	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3667	e9ebed4d	blueswir1	break;
3668	e9ebed4d	blueswir1	case 0x022: /* VIS I fcmpne16 */
3669	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3670	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3671	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3672	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpne16);
3673	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3674	3299908c	blueswir1	break;
3675	e9ebed4d	blueswir1	case 0x024: /* VIS I fcmple32 */
3676	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3677	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3678	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3679	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmple32);
3680	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3681	e9ebed4d	blueswir1	break;
3682	e9ebed4d	blueswir1	case 0x026: /* VIS I fcmpne32 */
3683	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3684	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3685	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3686	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpne32);
3687	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3688	e9ebed4d	blueswir1	break;
3689	e9ebed4d	blueswir1	case 0x028: /* VIS I fcmpgt16 */
3690	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3691	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3692	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3693	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpgt16);
3694	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3695	e9ebed4d	blueswir1	break;
3696	e9ebed4d	blueswir1	case 0x02a: /* VIS I fcmpeq16 */
3697	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3698	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3699	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3700	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpeq16);
3701	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3702	e9ebed4d	blueswir1	break;
3703	e9ebed4d	blueswir1	case 0x02c: /* VIS I fcmpgt32 */
3704	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3705	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3706	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3707	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpgt32);
3708	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3709	e9ebed4d	blueswir1	break;
3710	e9ebed4d	blueswir1	case 0x02e: /* VIS I fcmpeq32 */
3711	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3712	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3713	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3714	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpeq32);
3715	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3716	e9ebed4d	blueswir1	break;
3717	e9ebed4d	blueswir1	case 0x031: /* VIS I fmul8x16 */
3718	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3719	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3720	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3721	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmul8x16);
3722	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3723	e9ebed4d	blueswir1	break;
3724	e9ebed4d	blueswir1	case 0x033: /* VIS I fmul8x16au */
3725	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3726	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3727	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3728	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmul8x16au);
3729	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3730	e9ebed4d	blueswir1	break;
3731	e9ebed4d	blueswir1	case 0x035: /* VIS I fmul8x16al */
3732	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3733	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3734	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3735	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmul8x16al);
3736	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3737	e9ebed4d	blueswir1	break;
3738	e9ebed4d	blueswir1	case 0x036: /* VIS I fmul8sux16 */
3739	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3740	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3741	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3742	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmul8sux16);
3743	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3744	e9ebed4d	blueswir1	break;
3745	e9ebed4d	blueswir1	case 0x037: /* VIS I fmul8ulx16 */
3746	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3747	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3748	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3749	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmul8ulx16);
3750	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3751	e9ebed4d	blueswir1	break;
3752	e9ebed4d	blueswir1	case 0x038: /* VIS I fmuld8sux16 */
3753	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3754	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3755	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3756	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmuld8sux16);
3757	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3758	e9ebed4d	blueswir1	break;
3759	e9ebed4d	blueswir1	case 0x039: /* VIS I fmuld8ulx16 */
3760	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3761	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3762	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3763	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmuld8ulx16);
3764	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3765	e9ebed4d	blueswir1	break;
3766	e9ebed4d	blueswir1	case 0x03a: /* VIS I fpack32 */
3767	e9ebed4d	blueswir1	case 0x03b: /* VIS I fpack16 */
3768	e9ebed4d	blueswir1	case 0x03d: /* VIS I fpackfix */
3769	e9ebed4d	blueswir1	case 0x03e: /* VIS I pdist */
3770	e9ebed4d	blueswir1	// XXX
3771	e9ebed4d	blueswir1	goto illegal_insn;
3772	3299908c	blueswir1	case 0x048: /* VIS I faligndata */
3773	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3774	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3775	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3776	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_faligndata);
3777	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3778	3299908c	blueswir1	break;
3779	e9ebed4d	blueswir1	case 0x04b: /* VIS I fpmerge */
3780	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3781	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3782	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3783	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpmerge);
3784	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3785	e9ebed4d	blueswir1	break;
3786	e9ebed4d	blueswir1	case 0x04c: /* VIS II bshuffle */
3787	e9ebed4d	blueswir1	// XXX
3788	e9ebed4d	blueswir1	goto illegal_insn;
3789	e9ebed4d	blueswir1	case 0x04d: /* VIS I fexpand */
3790	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3791	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3792	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3793	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fexpand);
3794	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3795	e9ebed4d	blueswir1	break;
3796	e9ebed4d	blueswir1	case 0x050: /* VIS I fpadd16 */
3797	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3798	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3799	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3800	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpadd16);
3801	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3802	e9ebed4d	blueswir1	break;
3803	e9ebed4d	blueswir1	case 0x051: /* VIS I fpadd16s */
3804	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3805	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3806	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3807	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpadd16s);
3808	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3809	e9ebed4d	blueswir1	break;
3810	e9ebed4d	blueswir1	case 0x052: /* VIS I fpadd32 */
3811	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3812	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3813	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3814	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpadd32);
3815	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3816	e9ebed4d	blueswir1	break;
3817	e9ebed4d	blueswir1	case 0x053: /* VIS I fpadd32s */
3818	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3819	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3820	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3821	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpadd32s);
3822	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3823	e9ebed4d	blueswir1	break;
3824	e9ebed4d	blueswir1	case 0x054: /* VIS I fpsub16 */
3825	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3826	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3827	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3828	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpsub16);
3829	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3830	e9ebed4d	blueswir1	break;
3831	e9ebed4d	blueswir1	case 0x055: /* VIS I fpsub16s */
3832	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3833	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3834	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3835	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpsub16s);
3836	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3837	e9ebed4d	blueswir1	break;
3838	e9ebed4d	blueswir1	case 0x056: /* VIS I fpsub32 */
3839	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3840	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3841	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3842	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpadd32);
3843	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3844	e9ebed4d	blueswir1	break;
3845	e9ebed4d	blueswir1	case 0x057: /* VIS I fpsub32s */
3846	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3847	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3848	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3849	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpsub32s);
3850	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3851	e9ebed4d	blueswir1	break;
3852	3299908c	blueswir1	case 0x060: /* VIS I fzero */
3853	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3854	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_movl_DT0_0);
3855	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3856	3299908c	blueswir1	break;
3857	3299908c	blueswir1	case 0x061: /* VIS I fzeros */
3858	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3859	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_movl_FT0_0);
3860	3299908c	blueswir1	gen_op_store_FT0_fpr(rd);
3861	3299908c	blueswir1	break;
3862	e9ebed4d	blueswir1	case 0x062: /* VIS I fnor */
3863	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3864	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3865	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3866	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnor);
3867	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3868	e9ebed4d	blueswir1	break;
3869	e9ebed4d	blueswir1	case 0x063: /* VIS I fnors */
3870	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3871	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3872	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3873	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnors);
3874	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3875	e9ebed4d	blueswir1	break;
3876	e9ebed4d	blueswir1	case 0x064: /* VIS I fandnot2 */
3877	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3878	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs1));
3879	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs2));
3880	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fandnot);
3881	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3882	e9ebed4d	blueswir1	break;
3883	e9ebed4d	blueswir1	case 0x065: /* VIS I fandnot2s */
3884	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3885	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs1);
3886	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs2);
3887	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fandnots);
3888	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3889	e9ebed4d	blueswir1	break;
3890	e9ebed4d	blueswir1	case 0x066: /* VIS I fnot2 */
3891	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3892	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3893	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnot);
3894	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3895	e9ebed4d	blueswir1	break;
3896	e9ebed4d	blueswir1	case 0x067: /* VIS I fnot2s */
3897	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3898	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3899	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnot);
3900	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3901	e9ebed4d	blueswir1	break;
3902	e9ebed4d	blueswir1	case 0x068: /* VIS I fandnot1 */
3903	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3904	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3905	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3906	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fandnot);
3907	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3908	e9ebed4d	blueswir1	break;
3909	e9ebed4d	blueswir1	case 0x069: /* VIS I fandnot1s */
3910	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3911	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3912	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3913	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fandnots);
3914	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3915	e9ebed4d	blueswir1	break;
3916	e9ebed4d	blueswir1	case 0x06a: /* VIS I fnot1 */
3917	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3918	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs1));
3919	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnot);
3920	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3921	e9ebed4d	blueswir1	break;
3922	e9ebed4d	blueswir1	case 0x06b: /* VIS I fnot1s */
3923	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3924	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs1);
3925	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnot);
3926	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3927	e9ebed4d	blueswir1	break;
3928	e9ebed4d	blueswir1	case 0x06c: /* VIS I fxor */
3929	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3930	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3931	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3932	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxor);
3933	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3934	e9ebed4d	blueswir1	break;
3935	e9ebed4d	blueswir1	case 0x06d: /* VIS I fxors */
3936	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3937	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3938	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3939	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxors);
3940	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3941	e9ebed4d	blueswir1	break;
3942	e9ebed4d	blueswir1	case 0x06e: /* VIS I fnand */
3943	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3944	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3945	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3946	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnand);
3947	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3948	e9ebed4d	blueswir1	break;
3949	e9ebed4d	blueswir1	case 0x06f: /* VIS I fnands */
3950	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3951	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3952	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3953	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnands);
3954	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3955	e9ebed4d	blueswir1	break;
3956	e9ebed4d	blueswir1	case 0x070: /* VIS I fand */
3957	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3958	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3959	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3960	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fand);
3961	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3962	e9ebed4d	blueswir1	break;
3963	e9ebed4d	blueswir1	case 0x071: /* VIS I fands */
3964	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3965	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3966	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3967	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fands);
3968	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3969	e9ebed4d	blueswir1	break;
3970	e9ebed4d	blueswir1	case 0x072: /* VIS I fxnor */
3971	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3972	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3973	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3974	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxnor);
3975	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3976	e9ebed4d	blueswir1	break;
3977	e9ebed4d	blueswir1	case 0x073: /* VIS I fxnors */
3978	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3979	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3980	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3981	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxnors);
3982	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3983	e9ebed4d	blueswir1	break;
3984	3299908c	blueswir1	case 0x074: /* VIS I fsrc1 */
3985	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3986	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3987	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3988	3299908c	blueswir1	break;
3989	3299908c	blueswir1	case 0x075: /* VIS I fsrc1s */
3990	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3991	3299908c	blueswir1	gen_op_load_fpr_FT0(rs1);
3992	3299908c	blueswir1	gen_op_store_FT0_fpr(rd);
3993	3299908c	blueswir1	break;
3994	e9ebed4d	blueswir1	case 0x076: /* VIS I fornot2 */
3995	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3996	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs1));
3997	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs2));
3998	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fornot);
3999	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4000	e9ebed4d	blueswir1	break;
4001	e9ebed4d	blueswir1	case 0x077: /* VIS I fornot2s */
4002	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4003	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs1);
4004	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs2);
4005	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fornots);
4006	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
4007	e9ebed4d	blueswir1	break;
4008	3299908c	blueswir1	case 0x078: /* VIS I fsrc2 */
4009	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4010	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs2));
4011	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4012	3299908c	blueswir1	break;
4013	3299908c	blueswir1	case 0x079: /* VIS I fsrc2s */
4014	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4015	3299908c	blueswir1	gen_op_load_fpr_FT0(rs2);
4016	3299908c	blueswir1	gen_op_store_FT0_fpr(rd);
4017	3299908c	blueswir1	break;
4018	e9ebed4d	blueswir1	case 0x07a: /* VIS I fornot1 */
4019	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4020	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
4021	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
4022	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fornot);
4023	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4024	e9ebed4d	blueswir1	break;
4025	e9ebed4d	blueswir1	case 0x07b: /* VIS I fornot1s */
4026	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4027	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
4028	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
4029	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fornots);
4030	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
4031	e9ebed4d	blueswir1	break;
4032	e9ebed4d	blueswir1	case 0x07c: /* VIS I for */
4033	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4034	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
4035	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
4036	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_for);
4037	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4038	e9ebed4d	blueswir1	break;
4039	e9ebed4d	blueswir1	case 0x07d: /* VIS I fors */
4040	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4041	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
4042	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
4043	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fors);
4044	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
4045	e9ebed4d	blueswir1	break;
4046	3299908c	blueswir1	case 0x07e: /* VIS I fone */
4047	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4048	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_movl_DT0_1);
4049	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4050	3299908c	blueswir1	break;
4051	3299908c	blueswir1	case 0x07f: /* VIS I fones */
4052	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4053	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_movl_FT0_1);
4054	3299908c	blueswir1	gen_op_store_FT0_fpr(rd);
4055	3299908c	blueswir1	break;
4056	e9ebed4d	blueswir1	case 0x080: /* VIS I shutdown */
4057	e9ebed4d	blueswir1	case 0x081: /* VIS II siam */
4058	e9ebed4d	blueswir1	// XXX
4059	e9ebed4d	blueswir1	goto illegal_insn;
4060	3299908c	blueswir1	default:
4061	3299908c	blueswir1	goto illegal_insn;
4062	3299908c	blueswir1	}
4063	3299908c	blueswir1	#else
4064	0f8a249a	blueswir1	goto ncp_insn;
4065	3299908c	blueswir1	#endif
4066	3299908c	blueswir1	} else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
4067	fcc72045	blueswir1	#ifdef TARGET_SPARC64
4068	0f8a249a	blueswir1	goto illegal_insn;
4069	fcc72045	blueswir1	#else
4070	0f8a249a	blueswir1	goto ncp_insn;
4071	fcc72045	blueswir1	#endif
4072	3475187d	bellard	#ifdef TARGET_SPARC64
4073	0f8a249a	blueswir1	} else if (xop == 0x39) { /* V9 return */
4074	2ea815ca	blueswir1	TCGv r_const;
4075	2ea815ca	blueswir1
4076	6ae20372	blueswir1	save_state(dc, cpu_cond);
4077	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
4078	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
4079	0f8a249a	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
4080	6ae20372	blueswir1	tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4081	0f8a249a	blueswir1	} else { /* register */
4082	3475187d	bellard	rs2 = GET_FIELD(insn, 27, 31);
4083	0f8a249a	blueswir1	if (rs2) {
4084	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
4085	6ae20372	blueswir1	tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4086	6f551262	blueswir1	} else
4087	6f551262	blueswir1	tcg_gen_mov_tl(cpu_dst, cpu_src1);
4088	3475187d	bellard	}
4089	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_restore);
4090	6ae20372	blueswir1	gen_mov_pc_npc(dc, cpu_cond);
4091	2ea815ca	blueswir1	r_const = tcg_const_i32(3);
4092	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const);
4093	2ea815ca	blueswir1	tcg_temp_free(r_const);
4094	6ae20372	blueswir1	tcg_gen_mov_tl(cpu_npc, cpu_dst);
4095	0f8a249a	blueswir1	dc->npc = DYNAMIC_PC;
4096	0f8a249a	blueswir1	goto jmp_insn;
4097	3475187d	bellard	#endif
4098	0f8a249a	blueswir1	} else {
4099	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
4100	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
4101	0f8a249a	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
4102	6ae20372	blueswir1	tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4103	0f8a249a	blueswir1	} else { /* register */
4104	e80cfcfc	bellard	rs2 = GET_FIELD(insn, 27, 31);
4105	0f8a249a	blueswir1	if (rs2) {
4106	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
4107	6ae20372	blueswir1	tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4108	6f551262	blueswir1	} else
4109	6f551262	blueswir1	tcg_gen_mov_tl(cpu_dst, cpu_src1);
4110	cf495bcf	bellard	}
4111	0f8a249a	blueswir1	switch (xop) {
4112	0f8a249a	blueswir1	case 0x38: /* jmpl */
4113	0f8a249a	blueswir1	{
4114	2ea815ca	blueswir1	TCGv r_const;
4115	2ea815ca	blueswir1
4116	2ea815ca	blueswir1	r_const = tcg_const_tl(dc->pc);
4117	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
4118	2ea815ca	blueswir1	tcg_temp_free(r_const);
4119	6ae20372	blueswir1	gen_mov_pc_npc(dc, cpu_cond);
4120	2ea815ca	blueswir1	r_const = tcg_const_i32(3);
4121	77f193da	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4122	2ea815ca	blueswir1	r_const);
4123	2ea815ca	blueswir1	tcg_temp_free(r_const);
4124	6ae20372	blueswir1	tcg_gen_mov_tl(cpu_npc, cpu_dst);
4125	0f8a249a	blueswir1	dc->npc = DYNAMIC_PC;
4126	0f8a249a	blueswir1	}
4127	0f8a249a	blueswir1	goto jmp_insn;
4128	3475187d	bellard	#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4129	0f8a249a	blueswir1	case 0x39: /* rett, V9 return */
4130	0f8a249a	blueswir1	{
4131	2ea815ca	blueswir1	TCGv r_const;
4132	2ea815ca	blueswir1
4133	0f8a249a	blueswir1	if (!supervisor(dc))
4134	0f8a249a	blueswir1	goto priv_insn;
4135	6ae20372	blueswir1	gen_mov_pc_npc(dc, cpu_cond);
4136	2ea815ca	blueswir1	r_const = tcg_const_i32(3);
4137	77f193da	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4138	2ea815ca	blueswir1	r_const);
4139	2ea815ca	blueswir1	tcg_temp_free(r_const);
4140	6ae20372	blueswir1	tcg_gen_mov_tl(cpu_npc, cpu_dst);
4141	0f8a249a	blueswir1	dc->npc = DYNAMIC_PC;
4142	1a2fb1c0	blueswir1	tcg_gen_helper_0_0(helper_rett);
4143	0f8a249a	blueswir1	}
4144	0f8a249a	blueswir1	goto jmp_insn;
4145	0f8a249a	blueswir1	#endif
4146	0f8a249a	blueswir1	case 0x3b: /* flush */
4147	5578ceab	blueswir1	if (!((dc)->def->features & CPU_FEATURE_FLUSH))
4148	64a88d5d	blueswir1	goto unimp_flush;
4149	6ae20372	blueswir1	tcg_gen_helper_0_1(helper_flush, cpu_dst);
4150	0f8a249a	blueswir1	break;
4151	0f8a249a	blueswir1	case 0x3c: /* save */
4152	6ae20372	blueswir1	save_state(dc, cpu_cond);
4153	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_save);
4154	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
4155	0f8a249a	blueswir1	break;
4156	0f8a249a	blueswir1	case 0x3d: /* restore */
4157	6ae20372	blueswir1	save_state(dc, cpu_cond);
4158	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_restore);
4159	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
4160	0f8a249a	blueswir1	break;
4161	3475187d	bellard	#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4162	0f8a249a	blueswir1	case 0x3e: /* V9 done/retry */
4163	0f8a249a	blueswir1	{
4164	0f8a249a	blueswir1	switch (rd) {
4165	0f8a249a	blueswir1	case 0:
4166	0f8a249a	blueswir1	if (!supervisor(dc))
4167	0f8a249a	blueswir1	goto priv_insn;
4168	0f8a249a	blueswir1	dc->npc = DYNAMIC_PC;
4169	0f8a249a	blueswir1	dc->pc = DYNAMIC_PC;
4170	1a2fb1c0	blueswir1	tcg_gen_helper_0_0(helper_done);
4171	0f8a249a	blueswir1	goto jmp_insn;
4172	0f8a249a	blueswir1	case 1:
4173	0f8a249a	blueswir1	if (!supervisor(dc))
4174	0f8a249a	blueswir1	goto priv_insn;
4175	0f8a249a	blueswir1	dc->npc = DYNAMIC_PC;
4176	0f8a249a	blueswir1	dc->pc = DYNAMIC_PC;
4177	1a2fb1c0	blueswir1	tcg_gen_helper_0_0(helper_retry);
4178	0f8a249a	blueswir1	goto jmp_insn;
4179	0f8a249a	blueswir1	default:
4180	0f8a249a	blueswir1	goto illegal_insn;
4181	0f8a249a	blueswir1	}
4182	0f8a249a	blueswir1	}
4183	0f8a249a	blueswir1	break;
4184	0f8a249a	blueswir1	#endif
4185	0f8a249a	blueswir1	default:
4186	0f8a249a	blueswir1	goto illegal_insn;
4187	0f8a249a	blueswir1	}
4188	cf495bcf	bellard	}
4189	0f8a249a	blueswir1	break;
4190	0f8a249a	blueswir1	}
4191	0f8a249a	blueswir1	break;
4192	0f8a249a	blueswir1	case 3: /* load/store instructions */
4193	0f8a249a	blueswir1	{
4194	0f8a249a	blueswir1	unsigned int xop = GET_FIELD(insn, 7, 12);
4195	9322a4bf	blueswir1
4196	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
4197	71817e48	blueswir1	if (xop == 0x3c \|\| xop == 0x3e) { // V9 casa/casxa
4198	81ad8ba2	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
4199	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
4200	71817e48	blueswir1	tcg_gen_mov_tl(cpu_addr, cpu_src1);
4201	71817e48	blueswir1	} else if (IS_IMM) { /* immediate */
4202	0f8a249a	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
4203	6ae20372	blueswir1	tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
4204	0f8a249a	blueswir1	} else { /* register */
4205	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
4206	0f8a249a	blueswir1	if (rs2 != 0) {
4207	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
4208	6ae20372	blueswir1	tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4209	6f551262	blueswir1	} else
4210	6f551262	blueswir1	tcg_gen_mov_tl(cpu_addr, cpu_src1);
4211	0f8a249a	blueswir1	}
4212	2f2ecb83	blueswir1	if (xop < 4 \|\| (xop > 7 && xop < 0x14 && xop != 0x0e) \|\|
4213	2f2ecb83	blueswir1	(xop > 0x17 && xop <= 0x1d ) \|\|
4214	2f2ecb83	blueswir1	(xop > 0x2c && xop <= 0x33) \|\| xop == 0x1f \|\| xop == 0x3d) {
4215	0f8a249a	blueswir1	switch (xop) {
4216	1a2fb1c0	blueswir1	case 0x0: /* load unsigned word */
4217	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4218	6ae20372	blueswir1	tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4219	0f8a249a	blueswir1	break;
4220	0f8a249a	blueswir1	case 0x1: /* load unsigned byte */
4221	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4222	6ae20372	blueswir1	tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4223	0f8a249a	blueswir1	break;
4224	0f8a249a	blueswir1	case 0x2: /* load unsigned halfword */
4225	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4226	6ae20372	blueswir1	tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4227	0f8a249a	blueswir1	break;
4228	0f8a249a	blueswir1	case 0x3: /* load double word */
4229	0f8a249a	blueswir1	if (rd & 1)
4230	d4218d99	blueswir1	goto illegal_insn;
4231	1a2fb1c0	blueswir1	else {
4232	2ea815ca	blueswir1	TCGv r_const;
4233	2ea815ca	blueswir1
4234	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4235	2ea815ca	blueswir1	r_const = tcg_const_i32(7);
4236	d987963a	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4237	2ea815ca	blueswir1	r_const); // XXX remove
4238	2ea815ca	blueswir1	tcg_temp_free(r_const);
4239	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4240	6ae20372	blueswir1	tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4241	32b6c812	blueswir1	tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4242	32b6c812	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4243	32b6c812	blueswir1	gen_movl_TN_reg(rd + 1, cpu_tmp0);
4244	8911f501	blueswir1	tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4245	6ae20372	blueswir1	tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4246	6ae20372	blueswir1	tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4247	1a2fb1c0	blueswir1	}
4248	0f8a249a	blueswir1	break;
4249	0f8a249a	blueswir1	case 0x9: /* load signed byte */
4250	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4251	6ae20372	blueswir1	tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4252	0f8a249a	blueswir1	break;
4253	0f8a249a	blueswir1	case 0xa: /* load signed halfword */
4254	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4255	6ae20372	blueswir1	tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4256	0f8a249a	blueswir1	break;
4257	0f8a249a	blueswir1	case 0xd: /* ldstub -- XXX: should be atomically */
4258	2ea815ca	blueswir1	{
4259	2ea815ca	blueswir1	TCGv r_const;
4260	2ea815ca	blueswir1
4261	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4262	2ea815ca	blueswir1	tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4263	2ea815ca	blueswir1	r_const = tcg_const_tl(0xff);
4264	2ea815ca	blueswir1	tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4265	2ea815ca	blueswir1	tcg_temp_free(r_const);
4266	2ea815ca	blueswir1	}
4267	0f8a249a	blueswir1	break;
4268	77f193da	blueswir1	case 0x0f: /* swap register with memory. Also
4269	77f193da	blueswir1	atomically */
4270	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, SWAP);
4271	6ae20372	blueswir1	gen_movl_reg_TN(rd, cpu_val);
4272	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4273	6ae20372	blueswir1	tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4274	6ae20372	blueswir1	tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4275	6ae20372	blueswir1	tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
4276	0f8a249a	blueswir1	break;
4277	3475187d	bellard	#if !defined(CONFIG_USER_ONLY) \|\| defined(TARGET_SPARC64)
4278	0f8a249a	blueswir1	case 0x10: /* load word alternate */
4279	3475187d	bellard	#ifndef TARGET_SPARC64
4280	0f8a249a	blueswir1	if (IS_IMM)
4281	0f8a249a	blueswir1	goto illegal_insn;
4282	0f8a249a	blueswir1	if (!supervisor(dc))
4283	0f8a249a	blueswir1	goto priv_insn;
4284	6ea4a6c8	blueswir1	#endif
4285	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4286	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4287	0f8a249a	blueswir1	break;
4288	0f8a249a	blueswir1	case 0x11: /* load unsigned byte alternate */
4289	3475187d	bellard	#ifndef TARGET_SPARC64
4290	0f8a249a	blueswir1	if (IS_IMM)
4291	0f8a249a	blueswir1	goto illegal_insn;
4292	0f8a249a	blueswir1	if (!supervisor(dc))
4293	0f8a249a	blueswir1	goto priv_insn;
4294	0f8a249a	blueswir1	#endif
4295	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4296	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4297	0f8a249a	blueswir1	break;
4298	0f8a249a	blueswir1	case 0x12: /* load unsigned halfword alternate */
4299	3475187d	bellard	#ifndef TARGET_SPARC64
4300	0f8a249a	blueswir1	if (IS_IMM)
4301	0f8a249a	blueswir1	goto illegal_insn;
4302	0f8a249a	blueswir1	if (!supervisor(dc))
4303	0f8a249a	blueswir1	goto priv_insn;
4304	6ea4a6c8	blueswir1	#endif
4305	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4306	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4307	0f8a249a	blueswir1	break;
4308	0f8a249a	blueswir1	case 0x13: /* load double word alternate */
4309	3475187d	bellard	#ifndef TARGET_SPARC64
4310	0f8a249a	blueswir1	if (IS_IMM)
4311	0f8a249a	blueswir1	goto illegal_insn;
4312	0f8a249a	blueswir1	if (!supervisor(dc))
4313	0f8a249a	blueswir1	goto priv_insn;
4314	3475187d	bellard	#endif
4315	0f8a249a	blueswir1	if (rd & 1)
4316	d4218d99	blueswir1	goto illegal_insn;
4317	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4318	db166940	blueswir1	gen_ldda_asi(cpu_val, cpu_addr, insn, rd);
4319	db166940	blueswir1	goto skip_move;
4320	0f8a249a	blueswir1	case 0x19: /* load signed byte alternate */
4321	3475187d	bellard	#ifndef TARGET_SPARC64
4322	0f8a249a	blueswir1	if (IS_IMM)
4323	0f8a249a	blueswir1	goto illegal_insn;
4324	0f8a249a	blueswir1	if (!supervisor(dc))
4325	0f8a249a	blueswir1	goto priv_insn;
4326	0f8a249a	blueswir1	#endif
4327	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4328	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4329	0f8a249a	blueswir1	break;
4330	0f8a249a	blueswir1	case 0x1a: /* load signed halfword alternate */
4331	3475187d	bellard	#ifndef TARGET_SPARC64
4332	0f8a249a	blueswir1	if (IS_IMM)
4333	0f8a249a	blueswir1	goto illegal_insn;
4334	0f8a249a	blueswir1	if (!supervisor(dc))
4335	0f8a249a	blueswir1	goto priv_insn;
4336	6ea4a6c8	blueswir1	#endif
4337	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4338	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4339	0f8a249a	blueswir1	break;
4340	0f8a249a	blueswir1	case 0x1d: /* ldstuba -- XXX: should be atomically */
4341	3475187d	bellard	#ifndef TARGET_SPARC64
4342	0f8a249a	blueswir1	if (IS_IMM)
4343	0f8a249a	blueswir1	goto illegal_insn;
4344	0f8a249a	blueswir1	if (!supervisor(dc))
4345	0f8a249a	blueswir1	goto priv_insn;
4346	0f8a249a	blueswir1	#endif
4347	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4348	6ae20372	blueswir1	gen_ldstub_asi(cpu_val, cpu_addr, insn);
4349	0f8a249a	blueswir1	break;
4350	77f193da	blueswir1	case 0x1f: /* swap reg with alt. memory. Also
4351	77f193da	blueswir1	atomically */
4352	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, SWAP);
4353	3475187d	bellard	#ifndef TARGET_SPARC64
4354	0f8a249a	blueswir1	if (IS_IMM)
4355	0f8a249a	blueswir1	goto illegal_insn;
4356	0f8a249a	blueswir1	if (!supervisor(dc))
4357	0f8a249a	blueswir1	goto priv_insn;
4358	6ea4a6c8	blueswir1	#endif
4359	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4360	6ae20372	blueswir1	gen_movl_reg_TN(rd, cpu_val);
4361	6ae20372	blueswir1	gen_swap_asi(cpu_val, cpu_addr, insn);
4362	0f8a249a	blueswir1	break;
4363	3475187d	bellard
4364	3475187d	bellard	#ifndef TARGET_SPARC64
4365	0f8a249a	blueswir1	case 0x30: /* ldc */
4366	0f8a249a	blueswir1	case 0x31: /* ldcsr */
4367	0f8a249a	blueswir1	case 0x33: /* lddc */
4368	0f8a249a	blueswir1	goto ncp_insn;
4369	3475187d	bellard	#endif
4370	3475187d	bellard	#endif
4371	3475187d	bellard	#ifdef TARGET_SPARC64
4372	0f8a249a	blueswir1	case 0x08: /* V9 ldsw */
4373	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4374	6ae20372	blueswir1	tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4375	0f8a249a	blueswir1	break;
4376	0f8a249a	blueswir1	case 0x0b: /* V9 ldx */
4377	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4378	6ae20372	blueswir1	tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4379	0f8a249a	blueswir1	break;
4380	0f8a249a	blueswir1	case 0x18: /* V9 ldswa */
4381	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4382	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4383	0f8a249a	blueswir1	break;
4384	0f8a249a	blueswir1	case 0x1b: /* V9 ldxa */
4385	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4386	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4387	0f8a249a	blueswir1	break;
4388	0f8a249a	blueswir1	case 0x2d: /* V9 prefetch, no effect */
4389	0f8a249a	blueswir1	goto skip_move;
4390	0f8a249a	blueswir1	case 0x30: /* V9 ldfa */
4391	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4392	6ae20372	blueswir1	gen_ldf_asi(cpu_addr, insn, 4, rd);
4393	81ad8ba2	blueswir1	goto skip_move;
4394	0f8a249a	blueswir1	case 0x33: /* V9 lddfa */
4395	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4396	6ae20372	blueswir1	gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4397	81ad8ba2	blueswir1	goto skip_move;
4398	0f8a249a	blueswir1	case 0x3d: /* V9 prefetcha, no effect */
4399	0f8a249a	blueswir1	goto skip_move;
4400	0f8a249a	blueswir1	case 0x32: /* V9 ldqfa */
4401	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
4402	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4403	6ae20372	blueswir1	gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4404	1f587329	blueswir1	goto skip_move;
4405	1f587329	blueswir1	#endif
4406	0f8a249a	blueswir1	default:
4407	0f8a249a	blueswir1	goto illegal_insn;
4408	0f8a249a	blueswir1	}
4409	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_val);
4410	db166940	blueswir1	#if !defined(CONFIG_USER_ONLY) \|\| defined(TARGET_SPARC64)
4411	0f8a249a	blueswir1	skip_move: ;
4412	3475187d	bellard	#endif
4413	0f8a249a	blueswir1	} else if (xop >= 0x20 && xop < 0x24) {
4414	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
4415	a80dde08	bellard	goto jmp_insn;
4416	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4417	0f8a249a	blueswir1	switch (xop) {
4418	0f8a249a	blueswir1	case 0x20: /* load fpreg */
4419	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4420	6ae20372	blueswir1	tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4421	ce8536e2	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
4422	ce8536e2	blueswir1	offsetof(CPUState, fpr[rd]));
4423	0f8a249a	blueswir1	break;
4424	0f8a249a	blueswir1	case 0x21: /* load fsr */
4425	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4426	6ae20372	blueswir1	tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4427	ce8536e2	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
4428	ce8536e2	blueswir1	offsetof(CPUState, ft0));
4429	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_ldfsr);
4430	0f8a249a	blueswir1	break;
4431	0f8a249a	blueswir1	case 0x22: /* load quad fpreg */
4432	2ea815ca	blueswir1	{
4433	2ea815ca	blueswir1	TCGv r_const;
4434	2ea815ca	blueswir1
4435	2ea815ca	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
4436	2ea815ca	blueswir1	r_const = tcg_const_i32(dc->mem_idx);
4437	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const);
4438	2ea815ca	blueswir1	tcg_temp_free(r_const);
4439	2ea815ca	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
4440	2ea815ca	blueswir1	}
4441	1f587329	blueswir1	break;
4442	0f8a249a	blueswir1	case 0x23: /* load double fpreg */
4443	2ea815ca	blueswir1	{
4444	2ea815ca	blueswir1	TCGv r_const;
4445	2ea815ca	blueswir1
4446	2ea815ca	blueswir1	r_const = tcg_const_i32(dc->mem_idx);
4447	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const);
4448	2ea815ca	blueswir1	tcg_temp_free(r_const);
4449	2ea815ca	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4450	2ea815ca	blueswir1	}
4451	0f8a249a	blueswir1	break;
4452	0f8a249a	blueswir1	default:
4453	0f8a249a	blueswir1	goto illegal_insn;
4454	0f8a249a	blueswir1	}
4455	0f8a249a	blueswir1	} else if (xop < 8 \|\| (xop >= 0x14 && xop < 0x18) \|\| \
4456	0f8a249a	blueswir1	xop == 0xe \|\| xop == 0x1e) {
4457	6ae20372	blueswir1	gen_movl_reg_TN(rd, cpu_val);
4458	0f8a249a	blueswir1	switch (xop) {
4459	1a2fb1c0	blueswir1	case 0x4: /* store word */
4460	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4461	6ae20372	blueswir1	tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4462	0f8a249a	blueswir1	break;
4463	1a2fb1c0	blueswir1	case 0x5: /* store byte */
4464	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4465	6ae20372	blueswir1	tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4466	0f8a249a	blueswir1	break;
4467	1a2fb1c0	blueswir1	case 0x6: /* store halfword */
4468	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4469	6ae20372	blueswir1	tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4470	0f8a249a	blueswir1	break;
4471	1a2fb1c0	blueswir1	case 0x7: /* store double word */
4472	0f8a249a	blueswir1	if (rd & 1)
4473	d4218d99	blueswir1	goto illegal_insn;
4474	1a2fb1c0	blueswir1	else {
4475	2ea815ca	blueswir1	TCGv r_low, r_const;
4476	1a2fb1c0	blueswir1
4477	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4478	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4479	2ea815ca	blueswir1	r_const = tcg_const_i32(7);
4480	c2bc0e38	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4481	2ea815ca	blueswir1	r_const); // XXX remove
4482	2ea815ca	blueswir1	tcg_temp_free(r_const);
4483	8d96d209	blueswir1	r_low = tcg_temp_new(TCG_TYPE_TL);
4484	1a2fb1c0	blueswir1	gen_movl_reg_TN(rd + 1, r_low);
4485	6ae20372	blueswir1	tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4486	1a2fb1c0	blueswir1	r_low);
4487	2ea815ca	blueswir1	tcg_temp_free(r_low);
4488	6ae20372	blueswir1	tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4489	7fa76c0b	blueswir1	}
4490	0f8a249a	blueswir1	break;
4491	3475187d	bellard	#if !defined(CONFIG_USER_ONLY) \|\| defined(TARGET_SPARC64)
4492	1a2fb1c0	blueswir1	case 0x14: /* store word alternate */
4493	3475187d	bellard	#ifndef TARGET_SPARC64
4494	0f8a249a	blueswir1	if (IS_IMM)
4495	0f8a249a	blueswir1	goto illegal_insn;
4496	0f8a249a	blueswir1	if (!supervisor(dc))
4497	0f8a249a	blueswir1	goto priv_insn;
4498	3475187d	bellard	#endif
4499	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4500	6ae20372	blueswir1	gen_st_asi(cpu_val, cpu_addr, insn, 4);
4501	d39c0b99	bellard	break;
4502	1a2fb1c0	blueswir1	case 0x15: /* store byte alternate */
4503	3475187d	bellard	#ifndef TARGET_SPARC64
4504	0f8a249a	blueswir1	if (IS_IMM)
4505	0f8a249a	blueswir1	goto illegal_insn;
4506	0f8a249a	blueswir1	if (!supervisor(dc))
4507	0f8a249a	blueswir1	goto priv_insn;
4508	3475187d	bellard	#endif
4509	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4510	6ae20372	blueswir1	gen_st_asi(cpu_val, cpu_addr, insn, 1);
4511	d39c0b99	bellard	break;
4512	1a2fb1c0	blueswir1	case 0x16: /* store halfword alternate */
4513	3475187d	bellard	#ifndef TARGET_SPARC64
4514	0f8a249a	blueswir1	if (IS_IMM)
4515	0f8a249a	blueswir1	goto illegal_insn;
4516	0f8a249a	blueswir1	if (!supervisor(dc))
4517	0f8a249a	blueswir1	goto priv_insn;
4518	3475187d	bellard	#endif
4519	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4520	6ae20372	blueswir1	gen_st_asi(cpu_val, cpu_addr, insn, 2);
4521	d39c0b99	bellard	break;
4522	1a2fb1c0	blueswir1	case 0x17: /* store double word alternate */
4523	3475187d	bellard	#ifndef TARGET_SPARC64
4524	0f8a249a	blueswir1	if (IS_IMM)
4525	0f8a249a	blueswir1	goto illegal_insn;
4526	0f8a249a	blueswir1	if (!supervisor(dc))
4527	0f8a249a	blueswir1	goto priv_insn;
4528	3475187d	bellard	#endif
4529	0f8a249a	blueswir1	if (rd & 1)
4530	d4218d99	blueswir1	goto illegal_insn;
4531	1a2fb1c0	blueswir1	else {
4532	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4533	6ae20372	blueswir1	gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4534	1a2fb1c0	blueswir1	}
4535	d39c0b99	bellard	break;
4536	e80cfcfc	bellard	#endif
4537	3475187d	bellard	#ifdef TARGET_SPARC64
4538	0f8a249a	blueswir1	case 0x0e: /* V9 stx */
4539	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4540	6ae20372	blueswir1	tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4541	0f8a249a	blueswir1	break;
4542	0f8a249a	blueswir1	case 0x1e: /* V9 stxa */
4543	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4544	6ae20372	blueswir1	gen_st_asi(cpu_val, cpu_addr, insn, 8);
4545	0f8a249a	blueswir1	break;
4546	3475187d	bellard	#endif
4547	0f8a249a	blueswir1	default:
4548	0f8a249a	blueswir1	goto illegal_insn;
4549	0f8a249a	blueswir1	}
4550	0f8a249a	blueswir1	} else if (xop > 0x23 && xop < 0x28) {
4551	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
4552	a80dde08	bellard	goto jmp_insn;
4553	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4554	0f8a249a	blueswir1	switch (xop) {
4555	ce8536e2	blueswir1	case 0x24: /* store fpreg */
4556	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4557	ce8536e2	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4558	ce8536e2	blueswir1	offsetof(CPUState, fpr[rd]));
4559	6ae20372	blueswir1	tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4560	0f8a249a	blueswir1	break;
4561	0f8a249a	blueswir1	case 0x25: /* stfsr, V9 stxfsr */
4562	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4563	bb5529bb	blueswir1	tcg_gen_helper_0_0(helper_stfsr);
4564	ce8536e2	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4565	ce8536e2	blueswir1	offsetof(CPUState, ft0));
4566	6ae20372	blueswir1	tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4567	0f8a249a	blueswir1	break;
4568	1f587329	blueswir1	case 0x26:
4569	1f587329	blueswir1	#ifdef TARGET_SPARC64
4570	1f587329	blueswir1	/* V9 stqf, store quad fpreg */
4571	2ea815ca	blueswir1	{
4572	2ea815ca	blueswir1	TCGv r_const;
4573	2ea815ca	blueswir1
4574	2ea815ca	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
4575	2ea815ca	blueswir1	gen_op_load_fpr_QT0(QFPREG(rd));
4576	2ea815ca	blueswir1	r_const = tcg_const_i32(dc->mem_idx);
4577	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const);
4578	2ea815ca	blueswir1	tcg_temp_free(r_const);
4579	2ea815ca	blueswir1	}
4580	1f587329	blueswir1	break;
4581	1f587329	blueswir1	#else /* !TARGET_SPARC64 */
4582	1f587329	blueswir1	/* stdfq, store floating point queue */
4583	1f587329	blueswir1	#if defined(CONFIG_USER_ONLY)
4584	1f587329	blueswir1	goto illegal_insn;
4585	1f587329	blueswir1	#else
4586	0f8a249a	blueswir1	if (!supervisor(dc))
4587	0f8a249a	blueswir1	goto priv_insn;
4588	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
4589	0f8a249a	blueswir1	goto jmp_insn;
4590	0f8a249a	blueswir1	goto nfq_insn;
4591	0f8a249a	blueswir1	#endif
4592	1f587329	blueswir1	#endif
4593	7fa76c0b	blueswir1	case 0x27: /* store double fpreg */
4594	2ea815ca	blueswir1	{
4595	2ea815ca	blueswir1	TCGv r_const;
4596	2ea815ca	blueswir1
4597	2ea815ca	blueswir1	gen_op_load_fpr_DT0(DFPREG(rd));
4598	2ea815ca	blueswir1	r_const = tcg_const_i32(dc->mem_idx);
4599	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const);
4600	2ea815ca	blueswir1	tcg_temp_free(r_const);
4601	2ea815ca	blueswir1	}
4602	0f8a249a	blueswir1	break;
4603	0f8a249a	blueswir1	default:
4604	0f8a249a	blueswir1	goto illegal_insn;
4605	0f8a249a	blueswir1	}
4606	0f8a249a	blueswir1	} else if (xop > 0x33 && xop < 0x3f) {
4607	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4608	0f8a249a	blueswir1	switch (xop) {
4609	a4d17f19	blueswir1	#ifdef TARGET_SPARC64
4610	0f8a249a	blueswir1	case 0x34: /* V9 stfa */
4611	3391c818	blueswir1	gen_op_load_fpr_FT0(rd);
4612	6ae20372	blueswir1	gen_stf_asi(cpu_addr, insn, 4, rd);
4613	0f8a249a	blueswir1	break;
4614	1f587329	blueswir1	case 0x36: /* V9 stqfa */
4615	2ea815ca	blueswir1	{
4616	2ea815ca	blueswir1	TCGv r_const;
4617	2ea815ca	blueswir1
4618	2ea815ca	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
4619	2ea815ca	blueswir1	r_const = tcg_const_i32(7);
4620	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4621	2ea815ca	blueswir1	r_const);
4622	2ea815ca	blueswir1	tcg_temp_free(r_const);
4623	2ea815ca	blueswir1	gen_op_load_fpr_QT0(QFPREG(rd));
4624	2ea815ca	blueswir1	gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4625	2ea815ca	blueswir1	}
4626	1f587329	blueswir1	break;
4627	0f8a249a	blueswir1	case 0x37: /* V9 stdfa */
4628	3391c818	blueswir1	gen_op_load_fpr_DT0(DFPREG(rd));
4629	6ae20372	blueswir1	gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4630	0f8a249a	blueswir1	break;
4631	0f8a249a	blueswir1	case 0x3c: /* V9 casa */
4632	71817e48	blueswir1	gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4633	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_val);
4634	0f8a249a	blueswir1	break;
4635	0f8a249a	blueswir1	case 0x3e: /* V9 casxa */
4636	71817e48	blueswir1	gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4637	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_val);
4638	0f8a249a	blueswir1	break;
4639	a4d17f19	blueswir1	#else
4640	0f8a249a	blueswir1	case 0x34: /* stc */
4641	0f8a249a	blueswir1	case 0x35: /* stcsr */
4642	0f8a249a	blueswir1	case 0x36: /* stdcq */
4643	0f8a249a	blueswir1	case 0x37: /* stdc */
4644	0f8a249a	blueswir1	goto ncp_insn;
4645	0f8a249a	blueswir1	#endif
4646	0f8a249a	blueswir1	default:
4647	0f8a249a	blueswir1	goto illegal_insn;
4648	0f8a249a	blueswir1	}
4649	e8af50a3	bellard	}
4650	0f8a249a	blueswir1	else
4651	0f8a249a	blueswir1	goto illegal_insn;
4652	0f8a249a	blueswir1	}
4653	0f8a249a	blueswir1	break;
4654	cf495bcf	bellard	}
4655	cf495bcf	bellard	/* default case for non jump instructions */
4656	72cbca10	bellard	if (dc->npc == DYNAMIC_PC) {
4657	0f8a249a	blueswir1	dc->pc = DYNAMIC_PC;
4658	0f8a249a	blueswir1	gen_op_next_insn();
4659	72cbca10	bellard	} else if (dc->npc == JUMP_PC) {
4660	72cbca10	bellard	/* we can do a static jump */
4661	6ae20372	blueswir1	gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4662	72cbca10	bellard	dc->is_br = 1;
4663	72cbca10	bellard	} else {
4664	0f8a249a	blueswir1	dc->pc = dc->npc;
4665	0f8a249a	blueswir1	dc->npc = dc->npc + 4;
4666	cf495bcf	bellard	}
4667	e80cfcfc	bellard	jmp_insn:
4668	cf495bcf	bellard	return;
4669	cf495bcf	bellard	illegal_insn:
4670	2ea815ca	blueswir1	{
4671	2ea815ca	blueswir1	TCGv r_const;
4672	2ea815ca	blueswir1
4673	2ea815ca	blueswir1	save_state(dc, cpu_cond);
4674	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_ILL_INSN);
4675	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
4676	2ea815ca	blueswir1	tcg_temp_free(r_const);
4677	2ea815ca	blueswir1	dc->is_br = 1;
4678	2ea815ca	blueswir1	}
4679	e8af50a3	bellard	return;
4680	64a88d5d	blueswir1	unimp_flush:
4681	2ea815ca	blueswir1	{
4682	2ea815ca	blueswir1	TCGv r_const;
4683	2ea815ca	blueswir1
4684	2ea815ca	blueswir1	save_state(dc, cpu_cond);
4685	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_UNIMP_FLUSH);
4686	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
4687	2ea815ca	blueswir1	tcg_temp_free(r_const);
4688	2ea815ca	blueswir1	dc->is_br = 1;
4689	2ea815ca	blueswir1	}
4690	64a88d5d	blueswir1	return;
4691	e80cfcfc	bellard	#if !defined(CONFIG_USER_ONLY)
4692	e8af50a3	bellard	priv_insn:
4693	2ea815ca	blueswir1	{
4694	2ea815ca	blueswir1	TCGv r_const;
4695	2ea815ca	blueswir1
4696	2ea815ca	blueswir1	save_state(dc, cpu_cond);
4697	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_PRIV_INSN);
4698	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
4699	2ea815ca	blueswir1	tcg_temp_free(r_const);
4700	2ea815ca	blueswir1	dc->is_br = 1;
4701	2ea815ca	blueswir1	}
4702	e80cfcfc	bellard	return;
4703	64a88d5d	blueswir1	#endif
4704	e80cfcfc	bellard	nfpu_insn:
4705	6ae20372	blueswir1	save_state(dc, cpu_cond);
4706	e80cfcfc	bellard	gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4707	e80cfcfc	bellard	dc->is_br = 1;
4708	fcc72045	blueswir1	return;
4709	64a88d5d	blueswir1	#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4710	9143e598	blueswir1	nfq_insn:
4711	6ae20372	blueswir1	save_state(dc, cpu_cond);
4712	9143e598	blueswir1	gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4713	9143e598	blueswir1	dc->is_br = 1;
4714	9143e598	blueswir1	return;
4715	9143e598	blueswir1	#endif
4716	fcc72045	blueswir1	#ifndef TARGET_SPARC64
4717	fcc72045	blueswir1	ncp_insn:
4718	2ea815ca	blueswir1	{
4719	2ea815ca	blueswir1	TCGv r_const;
4720	2ea815ca	blueswir1
4721	2ea815ca	blueswir1	save_state(dc, cpu_cond);
4722	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_NCP_INSN);
4723	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
4724	2ea815ca	blueswir1	tcg_temp_free(r_const);
4725	2ea815ca	blueswir1	dc->is_br = 1;
4726	2ea815ca	blueswir1	}
4727	fcc72045	blueswir1	return;
4728	fcc72045	blueswir1	#endif
4729	7a3f1944	bellard	}
4730	7a3f1944	bellard
4731	2cfc5f17	ths	static inline void gen_intermediate_code_internal(TranslationBlock * tb,
4732	2cfc5f17	ths	int spc, CPUSPARCState *env)
4733	7a3f1944	bellard	{
4734	72cbca10	bellard	target_ulong pc_start, last_pc;
4735	cf495bcf	bellard	uint16_t *gen_opc_end;
4736	cf495bcf	bellard	DisasContext dc1, *dc = &dc1;
4737	e8af50a3	bellard	int j, lj = -1;
4738	2e70f6ef	pbrook	int num_insns;
4739	2e70f6ef	pbrook	int max_insns;
4740	cf495bcf	bellard
4741	cf495bcf	bellard	memset(dc, 0, sizeof(DisasContext));
4742	cf495bcf	bellard	dc->tb = tb;
4743	72cbca10	bellard	pc_start = tb->pc;
4744	cf495bcf	bellard	dc->pc = pc_start;
4745	e80cfcfc	bellard	last_pc = dc->pc;
4746	72cbca10	bellard	dc->npc = (target_ulong) tb->cs_base;
4747	6f27aba6	blueswir1	dc->mem_idx = cpu_mmu_index(env);
4748	5578ceab	blueswir1	dc->def = env->def;
4749	5578ceab	blueswir1	if ((dc->def->features & CPU_FEATURE_FLOAT))
4750	64a88d5d	blueswir1	dc->fpu_enabled = cpu_fpu_enabled(env);
4751	5578ceab	blueswir1	else
4752	64a88d5d	blueswir1	dc->fpu_enabled = 0;
4753	2cade6a3	blueswir1	#ifdef TARGET_SPARC64
4754	2cade6a3	blueswir1	dc->address_mask_32bit = env->pstate & PS_AM;
4755	2cade6a3	blueswir1	#endif
4756	cf495bcf	bellard	gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4757	cf495bcf	bellard
4758	1a2fb1c0	blueswir1	cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4759	8911f501	blueswir1	cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4760	8911f501	blueswir1	cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4761	d987963a	blueswir1
4762	d987963a	blueswir1	cpu_dst = tcg_temp_local_new(TCG_TYPE_TL);
4763	d987963a	blueswir1
4764	d987963a	blueswir1	// loads and stores
4765	3f0436fe	blueswir1	cpu_val = tcg_temp_local_new(TCG_TYPE_TL);
4766	d987963a	blueswir1	cpu_addr = tcg_temp_local_new(TCG_TYPE_TL);
4767	1a2fb1c0	blueswir1
4768	2e70f6ef	pbrook	num_insns = 0;
4769	2e70f6ef	pbrook	max_insns = tb->cflags & CF_COUNT_MASK;
4770	2e70f6ef	pbrook	if (max_insns == 0)
4771	2e70f6ef	pbrook	max_insns = CF_COUNT_MASK;
4772	2e70f6ef	pbrook	gen_icount_start();
4773	cf495bcf	bellard	do {
4774	e8af50a3	bellard	if (env->nb_breakpoints > 0) {
4775	e8af50a3	bellard	for(j = 0; j < env->nb_breakpoints; j++) {
4776	e8af50a3	bellard	if (env->breakpoints[j] == dc->pc) {
4777	0f8a249a	blueswir1	if (dc->pc != pc_start)
4778	6ae20372	blueswir1	save_state(dc, cpu_cond);
4779	1a2fb1c0	blueswir1	tcg_gen_helper_0_0(helper_debug);
4780	57fec1fe	bellard	tcg_gen_exit_tb(0);
4781	0f8a249a	blueswir1	dc->is_br = 1;
4782	e80cfcfc	bellard	goto exit_gen_loop;
4783	e8af50a3	bellard	}
4784	e8af50a3	bellard	}
4785	e8af50a3	bellard	}
4786	e8af50a3	bellard	if (spc) {
4787	e8af50a3	bellard	if (loglevel > 0)
4788	e8af50a3	bellard	fprintf(logfile, "Search PC...\n");
4789	e8af50a3	bellard	j = gen_opc_ptr - gen_opc_buf;
4790	e8af50a3	bellard	if (lj < j) {
4791	e8af50a3	bellard	lj++;
4792	e8af50a3	bellard	while (lj < j)
4793	e8af50a3	bellard	gen_opc_instr_start[lj++] = 0;
4794	e8af50a3	bellard	gen_opc_pc[lj] = dc->pc;
4795	e8af50a3	bellard	gen_opc_npc[lj] = dc->npc;
4796	e8af50a3	bellard	gen_opc_instr_start[lj] = 1;
4797	2e70f6ef	pbrook	gen_opc_icount[lj] = num_insns;
4798	e8af50a3	bellard	}
4799	e8af50a3	bellard	}
4800	2e70f6ef	pbrook	if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
4801	2e70f6ef	pbrook	gen_io_start();
4802	0f8a249a	blueswir1	last_pc = dc->pc;
4803	0f8a249a	blueswir1	disas_sparc_insn(dc);
4804	2e70f6ef	pbrook	num_insns++;
4805	0f8a249a	blueswir1
4806	0f8a249a	blueswir1	if (dc->is_br)
4807	0f8a249a	blueswir1	break;
4808	0f8a249a	blueswir1	/* if the next PC is different, we abort now */
4809	0f8a249a	blueswir1	if (dc->pc != (last_pc + 4))
4810	0f8a249a	blueswir1	break;
4811	d39c0b99	bellard	/* if we reach a page boundary, we stop generation so that the
4812	d39c0b99	bellard	PC of a TT_TFAULT exception is always in the right page */
4813	d39c0b99	bellard	if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4814	d39c0b99	bellard	break;
4815	e80cfcfc	bellard	/* if single step mode, we generate only one instruction and
4816	e80cfcfc	bellard	generate an exception */
4817	e80cfcfc	bellard	if (env->singlestep_enabled) {
4818	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_pc, dc->pc);
4819	57fec1fe	bellard	tcg_gen_exit_tb(0);
4820	e80cfcfc	bellard	break;
4821	e80cfcfc	bellard	}
4822	cf495bcf	bellard	} while ((gen_opc_ptr < gen_opc_end) &&
4823	2e70f6ef	pbrook	(dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
4824	2e70f6ef	pbrook	num_insns < max_insns);
4825	e80cfcfc	bellard
4826	e80cfcfc	bellard	exit_gen_loop:
4827	d987963a	blueswir1	tcg_temp_free(cpu_addr);
4828	3f0436fe	blueswir1	tcg_temp_free(cpu_val);
4829	d987963a	blueswir1	tcg_temp_free(cpu_dst);
4830	2ea815ca	blueswir1	tcg_temp_free(cpu_tmp64);
4831	2ea815ca	blueswir1	tcg_temp_free(cpu_tmp32);
4832	2ea815ca	blueswir1	tcg_temp_free(cpu_tmp0);
4833	2e70f6ef	pbrook	if (tb->cflags & CF_LAST_IO)
4834	2e70f6ef	pbrook	gen_io_end();
4835	72cbca10	bellard	if (!dc->is_br) {
4836	5fafdf24	ths	if (dc->pc != DYNAMIC_PC &&
4837	72cbca10	bellard	(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4838	72cbca10	bellard	/* static PC and NPC: we can use direct chaining */
4839	2f5680ee	blueswir1	gen_goto_tb(dc, 0, dc->pc, dc->npc);
4840	72cbca10	bellard	} else {
4841	72cbca10	bellard	if (dc->pc != DYNAMIC_PC)
4842	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_pc, dc->pc);
4843	6ae20372	blueswir1	save_npc(dc, cpu_cond);
4844	57fec1fe	bellard	tcg_gen_exit_tb(0);
4845	72cbca10	bellard	}
4846	72cbca10	bellard	}
4847	2e70f6ef	pbrook	gen_icount_end(tb, num_insns);
4848	cf495bcf	bellard	*gen_opc_ptr = INDEX_op_end;
4849	e8af50a3	bellard	if (spc) {
4850	e8af50a3	bellard	j = gen_opc_ptr - gen_opc_buf;
4851	e8af50a3	bellard	lj++;
4852	e8af50a3	bellard	while (lj <= j)
4853	e8af50a3	bellard	gen_opc_instr_start[lj++] = 0;
4854	e8af50a3	bellard	#if 0
4855	e8af50a3	bellard	if (loglevel > 0) {
4856	e8af50a3	bellard	page_dump(logfile);
4857	e8af50a3	bellard	}
4858	e8af50a3	bellard	#endif
4859	c3278b7b	bellard	gen_opc_jump_pc[0] = dc->jump_pc[0];
4860	c3278b7b	bellard	gen_opc_jump_pc[1] = dc->jump_pc[1];
4861	e8af50a3	bellard	} else {
4862	e80cfcfc	bellard	tb->size = last_pc + 4 - pc_start;
4863	2e70f6ef	pbrook	tb->icount = num_insns;
4864	e8af50a3	bellard	}
4865	7a3f1944	bellard	#ifdef DEBUG_DISAS
4866	e19e89a5	bellard	if (loglevel & CPU_LOG_TB_IN_ASM) {
4867	0f8a249a	blueswir1	fprintf(logfile, "--------------\n");
4868	0f8a249a	blueswir1	fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4869	0f8a249a	blueswir1	target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4870	0f8a249a	blueswir1	fprintf(logfile, "\n");
4871	cf495bcf	bellard	}
4872	7a3f1944	bellard	#endif
4873	7a3f1944	bellard	}
4874	7a3f1944	bellard
4875	2cfc5f17	ths	void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4876	7a3f1944	bellard	{
4877	2cfc5f17	ths	gen_intermediate_code_internal(tb, 0, env);
4878	7a3f1944	bellard	}
4879	7a3f1944	bellard
4880	2cfc5f17	ths	void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4881	7a3f1944	bellard	{
4882	2cfc5f17	ths	gen_intermediate_code_internal(tb, 1, env);
4883	7a3f1944	bellard	}
4884	7a3f1944	bellard
4885	c48fcb47	blueswir1	void gen_intermediate_code_init(CPUSPARCState *env)
4886	e80cfcfc	bellard	{
4887	f5069b26	blueswir1	unsigned int i;
4888	c48fcb47	blueswir1	static int inited;
4889	f5069b26	blueswir1	static const char * const gregnames[8] = {
4890	f5069b26	blueswir1	NULL, // g0 not used
4891	f5069b26	blueswir1	"g1",
4892	f5069b26	blueswir1	"g2",
4893	f5069b26	blueswir1	"g3",
4894	f5069b26	blueswir1	"g4",
4895	f5069b26	blueswir1	"g5",
4896	f5069b26	blueswir1	"g6",
4897	f5069b26	blueswir1	"g7",
4898	f5069b26	blueswir1	};
4899	aaed909a	bellard
4900	1a2fb1c0	blueswir1	/* init various static tables */
4901	1a2fb1c0	blueswir1	if (!inited) {
4902	1a2fb1c0	blueswir1	inited = 1;
4903	1a2fb1c0	blueswir1
4904	1a2fb1c0	blueswir1	cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4905	db4a4ea4	blueswir1	cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4906	db4a4ea4	blueswir1	offsetof(CPUState, regwptr),
4907	db4a4ea4	blueswir1	"regwptr");
4908	1a2fb1c0	blueswir1	#ifdef TARGET_SPARC64
4909	dc99a3f2	blueswir1	cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4910	dc99a3f2	blueswir1	TCG_AREG0, offsetof(CPUState, xcc),
4911	dc99a3f2	blueswir1	"xcc");
4912	1a2fb1c0	blueswir1	#endif
4913	7c60cc4b	bellard	cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
4914	77f193da	blueswir1	TCG_AREG0, offsetof(CPUState, cond),
4915	77f193da	blueswir1	"cond");
4916	dc99a3f2	blueswir1	cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4917	dc99a3f2	blueswir1	TCG_AREG0, offsetof(CPUState, cc_src),
4918	dc99a3f2	blueswir1	"cc_src");
4919	d9bdab86	blueswir1	cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4920	d9bdab86	blueswir1	offsetof(CPUState, cc_src2),
4921	d9bdab86	blueswir1	"cc_src2");
4922	dc99a3f2	blueswir1	cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4923	dc99a3f2	blueswir1	TCG_AREG0, offsetof(CPUState, cc_dst),
4924	dc99a3f2	blueswir1	"cc_dst");
4925	dc99a3f2	blueswir1	cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4926	dc99a3f2	blueswir1	TCG_AREG0, offsetof(CPUState, psr),
4927	dc99a3f2	blueswir1	"psr");
4928	87e92502	blueswir1	cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4929	87e92502	blueswir1	TCG_AREG0, offsetof(CPUState, fsr),
4930	87e92502	blueswir1	"fsr");
4931	48d5c82b	blueswir1	cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
4932	48d5c82b	blueswir1	TCG_AREG0, offsetof(CPUState, pc),
4933	48d5c82b	blueswir1	"pc");
4934	48d5c82b	blueswir1	cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
4935	48d5c82b	blueswir1	TCG_AREG0, offsetof(CPUState, npc),
4936	48d5c82b	blueswir1	"npc");
4937	f5069b26	blueswir1	for (i = 1; i < 8; i++)
4938	f5069b26	blueswir1	cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4939	f5069b26	blueswir1	offsetof(CPUState, gregs[i]),
4940	f5069b26	blueswir1	gregnames[i]);
4941	c9e03d8f	blueswir1	/* register helpers */
4942	c9e03d8f	blueswir1
4943	c9e03d8f	blueswir1	#undef DEF_HELPER
4944	c9e03d8f	blueswir1	#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
4945	c9e03d8f	blueswir1	#include "helper.h"
4946	1a2fb1c0	blueswir1	}
4947	658138bc	bellard	}
4948	d2856f1a	aurel32
4949	d2856f1a	aurel32	void gen_pc_load(CPUState env, TranslationBlock tb,
4950	d2856f1a	aurel32	unsigned long searched_pc, int pc_pos, void *puc)
4951	d2856f1a	aurel32	{
4952	d2856f1a	aurel32	target_ulong npc;
4953	d2856f1a	aurel32	env->pc = gen_opc_pc[pc_pos];
4954	d2856f1a	aurel32	npc = gen_opc_npc[pc_pos];
4955	d2856f1a	aurel32	if (npc == 1) {
4956	d2856f1a	aurel32	/* dynamic NPC: already stored */
4957	d2856f1a	aurel32	} else if (npc == 2) {
4958	d2856f1a	aurel32	target_ulong t2 = (target_ulong)(unsigned long)puc;
4959	d2856f1a	aurel32	/* jump PC: use T2 and the jump targets of the translation */
4960	d2856f1a	aurel32	if (t2)
4961	d2856f1a	aurel32	env->npc = gen_opc_jump_pc[0];
4962	d2856f1a	aurel32	else
4963	d2856f1a	aurel32	env->npc = gen_opc_jump_pc[1];
4964	d2856f1a	aurel32	} else {
4965	d2856f1a	aurel32	env->npc = npc;
4966	d2856f1a	aurel32	}
4967	d2856f1a	aurel32	}

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root / target-sparc / translate.c @ f97572e5