Revision f9bf77dd hw/pci.h

b/hw/pci.h
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#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
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#define  PCI_COMMAND_MASTER	0x4	/* Enable bus master */
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#define PCI_STATUS              0x06    /* 16 bits */
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#define  PCI_STATUS_INTERRUPT   0x08
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#define PCI_REVISION_ID         0x08    /* 8 bits  */
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#define PCI_CLASS_PROG		0x09	/* Reg. Level Programming Interface */
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#define PCI_CLASS_DEVICE        0x0a    /* Device class */

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