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1 | d4e8164f | bellard | /*
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2 | d4e8164f | bellard | * internal execution defines for qemu
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3 | 5fafdf24 | ths | *
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4 | d4e8164f | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | d4e8164f | bellard | *
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6 | d4e8164f | bellard | * This library is free software; you can redistribute it and/or
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7 | d4e8164f | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | d4e8164f | bellard | * License as published by the Free Software Foundation; either
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9 | d4e8164f | bellard | * version 2 of the License, or (at your option) any later version.
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10 | d4e8164f | bellard | *
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11 | d4e8164f | bellard | * This library is distributed in the hope that it will be useful,
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12 | d4e8164f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | d4e8164f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | d4e8164f | bellard | * Lesser General Public License for more details.
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15 | d4e8164f | bellard | *
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16 | d4e8164f | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | d4e8164f | bellard | * License along with this library; if not, write to the Free Software
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18 | d4e8164f | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | d4e8164f | bellard | */
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20 | d4e8164f | bellard | |
21 | b346ff46 | bellard | /* allow to see translation results - the slowdown should be negligible, so we leave it */
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22 | b346ff46 | bellard | #define DEBUG_DISAS
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23 | b346ff46 | bellard | |
24 | b346ff46 | bellard | /* is_jmp field values */
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25 | b346ff46 | bellard | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
26 | b346ff46 | bellard | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
27 | b346ff46 | bellard | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
28 | b346ff46 | bellard | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
29 | b346ff46 | bellard | |
30 | b346ff46 | bellard | struct TranslationBlock;
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31 | b346ff46 | bellard | |
32 | b346ff46 | bellard | /* XXX: make safe guess about sizes */
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33 | b346ff46 | bellard | #define MAX_OP_PER_INSTR 32 |
34 | b346ff46 | bellard | #define OPC_BUF_SIZE 512 |
35 | b346ff46 | bellard | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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36 | b346ff46 | bellard | |
37 | b346ff46 | bellard | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3) |
38 | b346ff46 | bellard | |
39 | b346ff46 | bellard | extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
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40 | b346ff46 | bellard | extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
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41 | c27004ec | bellard | extern long gen_labels[OPC_BUF_SIZE]; |
42 | c27004ec | bellard | extern int nb_gen_labels; |
43 | c27004ec | bellard | extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
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44 | c27004ec | bellard | extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
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45 | 66e85a21 | bellard | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
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46 | b346ff46 | bellard | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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47 | c3278b7b | bellard | extern target_ulong gen_opc_jump_pc[2]; |
48 | 30d6cb84 | bellard | extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
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49 | b346ff46 | bellard | |
50 | 9886cc16 | bellard | typedef void (GenOpFunc)(void); |
51 | 9886cc16 | bellard | typedef void (GenOpFunc1)(long); |
52 | 9886cc16 | bellard | typedef void (GenOpFunc2)(long, long); |
53 | 9886cc16 | bellard | typedef void (GenOpFunc3)(long, long, long); |
54 | 3b46e624 | ths | |
55 | b346ff46 | bellard | #if defined(TARGET_I386)
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56 | b346ff46 | bellard | |
57 | 33417e70 | bellard | void optimize_flags_init(void); |
58 | d4e8164f | bellard | |
59 | b346ff46 | bellard | #endif
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60 | b346ff46 | bellard | |
61 | b346ff46 | bellard | extern FILE *logfile;
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62 | b346ff46 | bellard | extern int loglevel; |
63 | b346ff46 | bellard | |
64 | 4c3a88a2 | bellard | int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
65 | 4c3a88a2 | bellard | int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
66 | b346ff46 | bellard | void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf); |
67 | 4c3a88a2 | bellard | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
68 | b346ff46 | bellard | int max_code_size, int *gen_code_size_ptr); |
69 | 5fafdf24 | ths | int cpu_restore_state(struct TranslationBlock *tb, |
70 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
71 | 58fe2f10 | bellard | void *puc);
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72 | 58fe2f10 | bellard | int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb, |
73 | 58fe2f10 | bellard | int max_code_size, int *gen_code_size_ptr); |
74 | 5fafdf24 | ths | int cpu_restore_state_copy(struct TranslationBlock *tb, |
75 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
76 | 58fe2f10 | bellard | void *puc);
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77 | 2e12669a | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc); |
78 | 6a00d601 | bellard | void cpu_exec_init(CPUState *env);
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79 | 53a5960a | pbrook | int page_unprotect(target_ulong address, unsigned long pc, void *puc); |
80 | 5fafdf24 | ths | void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
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81 | 2e12669a | bellard | int is_cpu_write_access);
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82 | 4390df51 | bellard | void tb_invalidate_page_range(target_ulong start, target_ulong end);
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83 | 2e12669a | bellard | void tlb_flush_page(CPUState *env, target_ulong addr);
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84 | ee8b7021 | bellard | void tlb_flush(CPUState *env, int flush_global); |
85 | 5fafdf24 | ths | int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
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86 | 5fafdf24 | ths | target_phys_addr_t paddr, int prot,
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87 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu); |
88 | 5fafdf24 | ths | static inline int tlb_set_page(CPUState *env, target_ulong vaddr, |
89 | 5fafdf24 | ths | target_phys_addr_t paddr, int prot,
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90 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
91 | 84b7b8e7 | bellard | { |
92 | 84b7b8e7 | bellard | if (prot & PAGE_READ)
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93 | 84b7b8e7 | bellard | prot |= PAGE_EXEC; |
94 | 6ebbf390 | j_mayer | return tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
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95 | 84b7b8e7 | bellard | } |
96 | d4e8164f | bellard | |
97 | d4e8164f | bellard | #define CODE_GEN_MAX_SIZE 65536 |
98 | d4e8164f | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
99 | d4e8164f | bellard | |
100 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_BITS 15 |
101 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
102 | 4390df51 | bellard | |
103 | d4e8164f | bellard | /* maximum total translate dcode allocated */
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104 | 4390df51 | bellard | |
105 | 4390df51 | bellard | /* NOTE: the translated code area cannot be too big because on some
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106 | c4c7e3e6 | bellard | archs the range of "fast" function calls is limited. Here is a
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107 | 4390df51 | bellard | summary of the ranges:
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108 | 4390df51 | bellard | |
109 | 4390df51 | bellard | i386 : signed 32 bits
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110 | 4390df51 | bellard | arm : signed 26 bits
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111 | 4390df51 | bellard | ppc : signed 24 bits
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112 | 4390df51 | bellard | sparc : signed 32 bits
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113 | 4390df51 | bellard | alpha : signed 23 bits
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114 | 4390df51 | bellard | */
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115 | 4390df51 | bellard | |
116 | 4390df51 | bellard | #if defined(__alpha__)
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117 | 4390df51 | bellard | #define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024) |
118 | b8076a74 | bellard | #elif defined(__ia64)
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119 | b8076a74 | bellard | #define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */ |
120 | 4390df51 | bellard | #elif defined(__powerpc__)
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121 | c4c7e3e6 | bellard | #define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024) |
122 | 4390df51 | bellard | #else
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123 | c98baaac | bellard | #define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024) |
124 | 4390df51 | bellard | #endif
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125 | 4390df51 | bellard | |
126 | d4e8164f | bellard | //#define CODE_GEN_BUFFER_SIZE (128 * 1024)
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127 | d4e8164f | bellard | |
128 | 4390df51 | bellard | /* estimated block size for TB allocation */
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129 | 4390df51 | bellard | /* XXX: use a per code average code fragment size and modulate it
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130 | 4390df51 | bellard | according to the host CPU */
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131 | 4390df51 | bellard | #if defined(CONFIG_SOFTMMU)
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132 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
133 | 4390df51 | bellard | #else
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134 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
135 | 4390df51 | bellard | #endif
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136 | 4390df51 | bellard | |
137 | 4390df51 | bellard | #define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
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138 | 4390df51 | bellard | |
139 | 5fafdf24 | ths | #if defined(__powerpc__)
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140 | 4390df51 | bellard | #define USE_DIRECT_JUMP
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141 | 4390df51 | bellard | #endif
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142 | 67b915a5 | bellard | #if defined(__i386__) && !defined(_WIN32)
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143 | d4e8164f | bellard | #define USE_DIRECT_JUMP
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144 | d4e8164f | bellard | #endif
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145 | d4e8164f | bellard | |
146 | d4e8164f | bellard | typedef struct TranslationBlock { |
147 | 2e12669a | bellard | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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148 | 2e12669a | bellard | target_ulong cs_base; /* CS base for this block */
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149 | c068688b | j_mayer | uint64_t flags; /* flags defining in which context the code was generated */
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150 | d4e8164f | bellard | uint16_t size; /* size of target code for this block (1 <=
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151 | d4e8164f | bellard | size <= TARGET_PAGE_SIZE) */
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152 | 58fe2f10 | bellard | uint16_t cflags; /* compile flags */
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153 | bf088061 | bellard | #define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */ |
154 | bf088061 | bellard | #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */ |
155 | bf088061 | bellard | #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */ |
156 | 2e12669a | bellard | #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */ |
157 | 58fe2f10 | bellard | |
158 | d4e8164f | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
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159 | 4390df51 | bellard | /* next matching tb for physical address. */
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160 | 5fafdf24 | ths | struct TranslationBlock *phys_hash_next;
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161 | 4390df51 | bellard | /* first and second physical page containing code. The lower bit
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162 | 4390df51 | bellard | of the pointer tells the index in page_next[] */
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163 | 5fafdf24 | ths | struct TranslationBlock *page_next[2]; |
164 | 5fafdf24 | ths | target_ulong page_addr[2];
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165 | 4390df51 | bellard | |
166 | d4e8164f | bellard | /* the following data are used to directly call another TB from
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167 | d4e8164f | bellard | the code of this one. */
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168 | d4e8164f | bellard | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
169 | d4e8164f | bellard | #ifdef USE_DIRECT_JUMP
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170 | 4cbb86e1 | bellard | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
171 | d4e8164f | bellard | #else
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172 | 95f7652d | bellard | uint32_t tb_next[2]; /* address of jump generated code */ |
173 | d4e8164f | bellard | #endif
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174 | d4e8164f | bellard | /* list of TBs jumping to this one. This is a circular list using
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175 | d4e8164f | bellard | the two least significant bits of the pointers to tell what is
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176 | d4e8164f | bellard | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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177 | d4e8164f | bellard | jmp_first */
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178 | 5fafdf24 | ths | struct TranslationBlock *jmp_next[2]; |
179 | d4e8164f | bellard | struct TranslationBlock *jmp_first;
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180 | d4e8164f | bellard | } TranslationBlock; |
181 | d4e8164f | bellard | |
182 | b362e5e0 | pbrook | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
183 | b362e5e0 | pbrook | { |
184 | b362e5e0 | pbrook | target_ulong tmp; |
185 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
186 | b362e5e0 | pbrook | return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
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187 | b362e5e0 | pbrook | } |
188 | b362e5e0 | pbrook | |
189 | 8a40a180 | bellard | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
190 | d4e8164f | bellard | { |
191 | b362e5e0 | pbrook | target_ulong tmp; |
192 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
193 | b362e5e0 | pbrook | return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) |
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194 | b362e5e0 | pbrook | (tmp & TB_JMP_ADDR_MASK)); |
195 | d4e8164f | bellard | } |
196 | d4e8164f | bellard | |
197 | 4390df51 | bellard | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
198 | 4390df51 | bellard | { |
199 | 4390df51 | bellard | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); |
200 | 4390df51 | bellard | } |
201 | 4390df51 | bellard | |
202 | c27004ec | bellard | TranslationBlock *tb_alloc(target_ulong pc); |
203 | 0124311e | bellard | void tb_flush(CPUState *env);
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204 | 5fafdf24 | ths | void tb_link_phys(TranslationBlock *tb,
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205 | 4390df51 | bellard | target_ulong phys_pc, target_ulong phys_page2); |
206 | d4e8164f | bellard | |
207 | 4390df51 | bellard | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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208 | d4e8164f | bellard | |
209 | d4e8164f | bellard | extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
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210 | d4e8164f | bellard | extern uint8_t *code_gen_ptr;
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211 | d4e8164f | bellard | |
212 | 4390df51 | bellard | #if defined(USE_DIRECT_JUMP)
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213 | 4390df51 | bellard | |
214 | 4390df51 | bellard | #if defined(__powerpc__)
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215 | 4cbb86e1 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
216 | d4e8164f | bellard | { |
217 | d4e8164f | bellard | uint32_t val, *ptr; |
218 | d4e8164f | bellard | |
219 | d4e8164f | bellard | /* patch the branch destination */
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220 | 4cbb86e1 | bellard | ptr = (uint32_t *)jmp_addr; |
221 | d4e8164f | bellard | val = *ptr; |
222 | 4cbb86e1 | bellard | val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc); |
223 | d4e8164f | bellard | *ptr = val; |
224 | d4e8164f | bellard | /* flush icache */
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225 | d4e8164f | bellard | asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory"); |
226 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
227 | d4e8164f | bellard | asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory"); |
228 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
229 | d4e8164f | bellard | asm volatile ("isync" : : : "memory"); |
230 | d4e8164f | bellard | } |
231 | 4390df51 | bellard | #elif defined(__i386__)
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232 | 4390df51 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
233 | 4390df51 | bellard | { |
234 | 4390df51 | bellard | /* patch the branch destination */
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235 | 4390df51 | bellard | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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236 | 4390df51 | bellard | /* no need to flush icache explicitely */
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237 | 4390df51 | bellard | } |
238 | 4390df51 | bellard | #endif
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239 | d4e8164f | bellard | |
240 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
241 | 4cbb86e1 | bellard | int n, unsigned long addr) |
242 | 4cbb86e1 | bellard | { |
243 | 4cbb86e1 | bellard | unsigned long offset; |
244 | 4cbb86e1 | bellard | |
245 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n]; |
246 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
247 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n + 2];
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248 | 4cbb86e1 | bellard | if (offset != 0xffff) |
249 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
250 | 4cbb86e1 | bellard | } |
251 | 4cbb86e1 | bellard | |
252 | d4e8164f | bellard | #else
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253 | d4e8164f | bellard | |
254 | d4e8164f | bellard | /* set the jump target */
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255 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
256 | d4e8164f | bellard | int n, unsigned long addr) |
257 | d4e8164f | bellard | { |
258 | 95f7652d | bellard | tb->tb_next[n] = addr; |
259 | d4e8164f | bellard | } |
260 | d4e8164f | bellard | |
261 | d4e8164f | bellard | #endif
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262 | d4e8164f | bellard | |
263 | 5fafdf24 | ths | static inline void tb_add_jump(TranslationBlock *tb, int n, |
264 | d4e8164f | bellard | TranslationBlock *tb_next) |
265 | d4e8164f | bellard | { |
266 | cf25629d | bellard | /* NOTE: this test is only needed for thread safety */
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267 | cf25629d | bellard | if (!tb->jmp_next[n]) {
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268 | cf25629d | bellard | /* patch the native jump address */
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269 | cf25629d | bellard | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
270 | 3b46e624 | ths | |
271 | cf25629d | bellard | /* add in TB jmp circular list */
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272 | cf25629d | bellard | tb->jmp_next[n] = tb_next->jmp_first; |
273 | cf25629d | bellard | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
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274 | cf25629d | bellard | } |
275 | d4e8164f | bellard | } |
276 | d4e8164f | bellard | |
277 | a513fe19 | bellard | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
278 | a513fe19 | bellard | |
279 | d4e8164f | bellard | #ifndef offsetof
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280 | d4e8164f | bellard | #define offsetof(type, field) ((size_t) &((type *)0)->field) |
281 | d4e8164f | bellard | #endif
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282 | d4e8164f | bellard | |
283 | d549f7d9 | bellard | #if defined(_WIN32)
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284 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
285 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".section .text\n" |
286 | d549f7d9 | bellard | #elif defined(__APPLE__)
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287 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".data\n" |
288 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".text\n" |
289 | d549f7d9 | bellard | #else
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290 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
291 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".previous\n" |
292 | d549f7d9 | bellard | #endif
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293 | d549f7d9 | bellard | |
294 | 75913b72 | bellard | #define ASM_OP_LABEL_NAME(n, opname) \
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295 | 75913b72 | bellard | ASM_NAME(__op_label) #n "." ASM_NAME(opname) |
296 | 75913b72 | bellard | |
297 | b346ff46 | bellard | #if defined(__powerpc__)
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298 | b346ff46 | bellard | |
299 | 4390df51 | bellard | /* we patch the jump instruction directly */
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300 | ae063a68 | bellard | #define GOTO_TB(opname, tbparam, n)\
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301 | b346ff46 | bellard | do {\
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302 | d549f7d9 | bellard | asm volatile (ASM_DATA_SECTION\ |
303 | 75913b72 | bellard | ASM_OP_LABEL_NAME(n, opname) ":\n"\
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304 | 9257a9e4 | bellard | ".long 1f\n"\
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305 | d549f7d9 | bellard | ASM_PREVIOUS_SECTION \ |
306 | d549f7d9 | bellard | "b " ASM_NAME(__op_jmp) #n "\n"\ |
307 | 9257a9e4 | bellard | "1:\n");\
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308 | 4390df51 | bellard | } while (0) |
309 | 4390df51 | bellard | |
310 | 4390df51 | bellard | #elif defined(__i386__) && defined(USE_DIRECT_JUMP)
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311 | 4390df51 | bellard | |
312 | 4390df51 | bellard | /* we patch the jump instruction directly */
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313 | ae063a68 | bellard | #define GOTO_TB(opname, tbparam, n)\
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314 | c27004ec | bellard | do {\
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315 | c27004ec | bellard | asm volatile (".section .data\n"\ |
316 | 75913b72 | bellard | ASM_OP_LABEL_NAME(n, opname) ":\n"\
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317 | c27004ec | bellard | ".long 1f\n"\
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318 | c27004ec | bellard | ASM_PREVIOUS_SECTION \ |
319 | c27004ec | bellard | "jmp " ASM_NAME(__op_jmp) #n "\n"\ |
320 | c27004ec | bellard | "1:\n");\
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321 | c27004ec | bellard | } while (0) |
322 | c27004ec | bellard | |
323 | b346ff46 | bellard | #else
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324 | b346ff46 | bellard | |
325 | b346ff46 | bellard | /* jump to next block operations (more portable code, does not need
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326 | b346ff46 | bellard | cache flushing, but slower because of indirect jump) */
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327 | ae063a68 | bellard | #define GOTO_TB(opname, tbparam, n)\
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328 | b346ff46 | bellard | do {\
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329 | 6d8aa3bf | balrog | static void __attribute__((used)) *dummy ## n = &&dummy_label ## n;\ |
330 | 6d8aa3bf | balrog | static void __attribute__((used)) *__op_label ## n \ |
331 | 75913b72 | bellard | __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\ |
332 | b346ff46 | bellard | goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\ |
333 | ae063a68 | bellard | label ## n: ;\ |
334 | ae063a68 | bellard | dummy_label ## n: ;\ |
335 | b346ff46 | bellard | } while (0) |
336 | b346ff46 | bellard | |
337 | ae063a68 | bellard | #endif
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338 | ae063a68 | bellard | |
339 | 33417e70 | bellard | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
340 | 33417e70 | bellard | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
341 | a4193c8a | bellard | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
342 | 33417e70 | bellard | |
343 | 204a1b8d | ths | #if defined(__powerpc__)
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344 | d4e8164f | bellard | static inline int testandset (int *p) |
345 | d4e8164f | bellard | { |
346 | d4e8164f | bellard | int ret;
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347 | d4e8164f | bellard | __asm__ __volatile__ ( |
348 | 02e1ec9b | bellard | "0: lwarx %0,0,%1\n"
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349 | 02e1ec9b | bellard | " xor. %0,%3,%0\n"
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350 | 02e1ec9b | bellard | " bne 1f\n"
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351 | 02e1ec9b | bellard | " stwcx. %2,0,%1\n"
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352 | 02e1ec9b | bellard | " bne- 0b\n"
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353 | d4e8164f | bellard | "1: "
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354 | d4e8164f | bellard | : "=&r" (ret)
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355 | d4e8164f | bellard | : "r" (p), "r" (1), "r" (0) |
356 | d4e8164f | bellard | : "cr0", "memory"); |
357 | d4e8164f | bellard | return ret;
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358 | d4e8164f | bellard | } |
359 | 204a1b8d | ths | #elif defined(__i386__)
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360 | d4e8164f | bellard | static inline int testandset (int *p) |
361 | d4e8164f | bellard | { |
362 | 4955a2cd | bellard | long int readval = 0; |
363 | 3b46e624 | ths | |
364 | 4955a2cd | bellard | __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
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365 | 4955a2cd | bellard | : "+m" (*p), "+a" (readval) |
366 | 4955a2cd | bellard | : "r" (1) |
367 | 4955a2cd | bellard | : "cc");
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368 | 4955a2cd | bellard | return readval;
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369 | d4e8164f | bellard | } |
370 | 204a1b8d | ths | #elif defined(__x86_64__)
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371 | bc51c5c9 | bellard | static inline int testandset (int *p) |
372 | bc51c5c9 | bellard | { |
373 | 4955a2cd | bellard | long int readval = 0; |
374 | 3b46e624 | ths | |
375 | 4955a2cd | bellard | __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
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376 | 4955a2cd | bellard | : "+m" (*p), "+a" (readval) |
377 | 4955a2cd | bellard | : "r" (1) |
378 | 4955a2cd | bellard | : "cc");
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379 | 4955a2cd | bellard | return readval;
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380 | bc51c5c9 | bellard | } |
381 | 204a1b8d | ths | #elif defined(__s390__)
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382 | d4e8164f | bellard | static inline int testandset (int *p) |
383 | d4e8164f | bellard | { |
384 | d4e8164f | bellard | int ret;
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385 | d4e8164f | bellard | |
386 | d4e8164f | bellard | __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
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387 | d4e8164f | bellard | " jl 0b"
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388 | d4e8164f | bellard | : "=&d" (ret)
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389 | 5fafdf24 | ths | : "r" (1), "a" (p), "0" (*p) |
390 | d4e8164f | bellard | : "cc", "memory" ); |
391 | d4e8164f | bellard | return ret;
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392 | d4e8164f | bellard | } |
393 | 204a1b8d | ths | #elif defined(__alpha__)
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394 | 2f87c607 | bellard | static inline int testandset (int *p) |
395 | d4e8164f | bellard | { |
396 | d4e8164f | bellard | int ret;
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397 | d4e8164f | bellard | unsigned long one; |
398 | d4e8164f | bellard | |
399 | d4e8164f | bellard | __asm__ __volatile__ ("0: mov 1,%2\n"
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400 | d4e8164f | bellard | " ldl_l %0,%1\n"
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401 | d4e8164f | bellard | " stl_c %2,%1\n"
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402 | d4e8164f | bellard | " beq %2,1f\n"
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403 | d4e8164f | bellard | ".subsection 2\n"
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404 | d4e8164f | bellard | "1: br 0b\n"
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405 | d4e8164f | bellard | ".previous"
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406 | d4e8164f | bellard | : "=r" (ret), "=m" (*p), "=r" (one) |
407 | d4e8164f | bellard | : "m" (*p));
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408 | d4e8164f | bellard | return ret;
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409 | d4e8164f | bellard | } |
410 | 204a1b8d | ths | #elif defined(__sparc__)
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411 | d4e8164f | bellard | static inline int testandset (int *p) |
412 | d4e8164f | bellard | { |
413 | d4e8164f | bellard | int ret;
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414 | d4e8164f | bellard | |
415 | d4e8164f | bellard | __asm__ __volatile__("ldstub [%1], %0"
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416 | d4e8164f | bellard | : "=r" (ret)
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417 | d4e8164f | bellard | : "r" (p)
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418 | d4e8164f | bellard | : "memory");
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419 | d4e8164f | bellard | |
420 | d4e8164f | bellard | return (ret ? 1 : 0); |
421 | d4e8164f | bellard | } |
422 | 204a1b8d | ths | #elif defined(__arm__)
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423 | a95c6790 | bellard | static inline int testandset (int *spinlock) |
424 | a95c6790 | bellard | { |
425 | a95c6790 | bellard | register unsigned int ret; |
426 | a95c6790 | bellard | __asm__ __volatile__("swp %0, %1, [%2]"
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427 | a95c6790 | bellard | : "=r"(ret)
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428 | a95c6790 | bellard | : "0"(1), "r"(spinlock)); |
429 | 3b46e624 | ths | |
430 | a95c6790 | bellard | return ret;
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431 | a95c6790 | bellard | } |
432 | 204a1b8d | ths | #elif defined(__mc68000)
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433 | 38e584a0 | bellard | static inline int testandset (int *p) |
434 | 38e584a0 | bellard | { |
435 | 38e584a0 | bellard | char ret;
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436 | 38e584a0 | bellard | __asm__ __volatile__("tas %1; sne %0"
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437 | 38e584a0 | bellard | : "=r" (ret)
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438 | 38e584a0 | bellard | : "m" (p)
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439 | 38e584a0 | bellard | : "cc","memory"); |
440 | 4955a2cd | bellard | return ret;
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441 | 38e584a0 | bellard | } |
442 | 204a1b8d | ths | #elif defined(__ia64)
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443 | 38e584a0 | bellard | |
444 | b8076a74 | bellard | #include <ia64intrin.h> |
445 | b8076a74 | bellard | |
446 | b8076a74 | bellard | static inline int testandset (int *p) |
447 | b8076a74 | bellard | { |
448 | b8076a74 | bellard | return __sync_lock_test_and_set (p, 1); |
449 | b8076a74 | bellard | } |
450 | 204a1b8d | ths | #elif defined(__mips__)
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451 | c4b89d18 | ths | static inline int testandset (int *p) |
452 | c4b89d18 | ths | { |
453 | c4b89d18 | ths | int ret;
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454 | c4b89d18 | ths | |
455 | c4b89d18 | ths | __asm__ __volatile__ ( |
456 | c4b89d18 | ths | " .set push \n"
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457 | c4b89d18 | ths | " .set noat \n"
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458 | c4b89d18 | ths | " .set mips2 \n"
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459 | c4b89d18 | ths | "1: li $1, 1 \n"
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460 | c4b89d18 | ths | " ll %0, %1 \n"
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461 | c4b89d18 | ths | " sc $1, %1 \n"
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462 | 976a0d0d | ths | " beqz $1, 1b \n"
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463 | c4b89d18 | ths | " .set pop "
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464 | c4b89d18 | ths | : "=r" (ret), "+R" (*p) |
465 | c4b89d18 | ths | : |
466 | c4b89d18 | ths | : "memory");
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467 | c4b89d18 | ths | |
468 | c4b89d18 | ths | return ret;
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469 | c4b89d18 | ths | } |
470 | 204a1b8d | ths | #else
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471 | 204a1b8d | ths | #error unimplemented CPU support
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472 | c4b89d18 | ths | #endif
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473 | c4b89d18 | ths | |
474 | d4e8164f | bellard | typedef int spinlock_t; |
475 | d4e8164f | bellard | |
476 | d4e8164f | bellard | #define SPIN_LOCK_UNLOCKED 0 |
477 | d4e8164f | bellard | |
478 | aebcb60e | bellard | #if defined(CONFIG_USER_ONLY)
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479 | d4e8164f | bellard | static inline void spin_lock(spinlock_t *lock) |
480 | d4e8164f | bellard | { |
481 | d4e8164f | bellard | while (testandset(lock));
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482 | d4e8164f | bellard | } |
483 | d4e8164f | bellard | |
484 | d4e8164f | bellard | static inline void spin_unlock(spinlock_t *lock) |
485 | d4e8164f | bellard | { |
486 | d4e8164f | bellard | *lock = 0;
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487 | d4e8164f | bellard | } |
488 | d4e8164f | bellard | |
489 | d4e8164f | bellard | static inline int spin_trylock(spinlock_t *lock) |
490 | d4e8164f | bellard | { |
491 | d4e8164f | bellard | return !testandset(lock);
|
492 | d4e8164f | bellard | } |
493 | 3c1cf9fa | bellard | #else
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494 | 3c1cf9fa | bellard | static inline void spin_lock(spinlock_t *lock) |
495 | 3c1cf9fa | bellard | { |
496 | 3c1cf9fa | bellard | } |
497 | 3c1cf9fa | bellard | |
498 | 3c1cf9fa | bellard | static inline void spin_unlock(spinlock_t *lock) |
499 | 3c1cf9fa | bellard | { |
500 | 3c1cf9fa | bellard | } |
501 | 3c1cf9fa | bellard | |
502 | 3c1cf9fa | bellard | static inline int spin_trylock(spinlock_t *lock) |
503 | 3c1cf9fa | bellard | { |
504 | 3c1cf9fa | bellard | return 1; |
505 | 3c1cf9fa | bellard | } |
506 | 3c1cf9fa | bellard | #endif
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507 | d4e8164f | bellard | |
508 | d4e8164f | bellard | extern spinlock_t tb_lock;
|
509 | d4e8164f | bellard | |
510 | 36bdbe54 | bellard | extern int tb_invalidated_flag; |
511 | 6e59c1db | bellard | |
512 | e95c8d51 | bellard | #if !defined(CONFIG_USER_ONLY)
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513 | 6e59c1db | bellard | |
514 | 6ebbf390 | j_mayer | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, |
515 | 6e59c1db | bellard | void *retaddr);
|
516 | 6e59c1db | bellard | |
517 | 6ebbf390 | j_mayer | #define ACCESS_TYPE (NB_MMU_MODES + 1) |
518 | 6e59c1db | bellard | #define MEMSUFFIX _code
|
519 | 6e59c1db | bellard | #define env cpu_single_env
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520 | 6e59c1db | bellard | |
521 | 6e59c1db | bellard | #define DATA_SIZE 1 |
522 | 6e59c1db | bellard | #include "softmmu_header.h" |
523 | 6e59c1db | bellard | |
524 | 6e59c1db | bellard | #define DATA_SIZE 2 |
525 | 6e59c1db | bellard | #include "softmmu_header.h" |
526 | 6e59c1db | bellard | |
527 | 6e59c1db | bellard | #define DATA_SIZE 4 |
528 | 6e59c1db | bellard | #include "softmmu_header.h" |
529 | 6e59c1db | bellard | |
530 | c27004ec | bellard | #define DATA_SIZE 8 |
531 | c27004ec | bellard | #include "softmmu_header.h" |
532 | c27004ec | bellard | |
533 | 6e59c1db | bellard | #undef ACCESS_TYPE
|
534 | 6e59c1db | bellard | #undef MEMSUFFIX
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535 | 6e59c1db | bellard | #undef env
|
536 | 6e59c1db | bellard | |
537 | 6e59c1db | bellard | #endif
|
538 | 4390df51 | bellard | |
539 | 4390df51 | bellard | #if defined(CONFIG_USER_ONLY)
|
540 | 4390df51 | bellard | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
541 | 4390df51 | bellard | { |
542 | 4390df51 | bellard | return addr;
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543 | 4390df51 | bellard | } |
544 | 4390df51 | bellard | #else
|
545 | 4390df51 | bellard | /* NOTE: this function can trigger an exception */
|
546 | 1ccde1cb | bellard | /* NOTE2: the returned address is not exactly the physical address: it
|
547 | 1ccde1cb | bellard | is the offset relative to phys_ram_base */
|
548 | 4390df51 | bellard | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
549 | 4390df51 | bellard | { |
550 | 6ebbf390 | j_mayer | int mmu_idx, index, pd;
|
551 | 4390df51 | bellard | |
552 | 4390df51 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
553 | 6ebbf390 | j_mayer | mmu_idx = cpu_mmu_index(env); |
554 | 6ebbf390 | j_mayer | if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_code !=
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555 | 4390df51 | bellard | (addr & TARGET_PAGE_MASK), 0)) {
|
556 | c27004ec | bellard | ldub_code(addr); |
557 | c27004ec | bellard | } |
558 | 6ebbf390 | j_mayer | pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK; |
559 | 2a4188a3 | bellard | if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
|
560 | 647de6ca | ths | #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
|
561 | 6c36d3fa | blueswir1 | do_unassigned_access(addr, 0, 1, 0); |
562 | 6c36d3fa | blueswir1 | #else
|
563 | 36d23958 | ths | cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); |
564 | 6c36d3fa | blueswir1 | #endif
|
565 | 4390df51 | bellard | } |
566 | 6ebbf390 | j_mayer | return addr + env->tlb_table[mmu_idx][index].addend - (unsigned long)phys_ram_base; |
567 | 4390df51 | bellard | } |
568 | 4390df51 | bellard | #endif
|
569 | 9df217a3 | bellard | |
570 | 9df217a3 | bellard | #ifdef USE_KQEMU
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571 | f32fc648 | bellard | #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG)) |
572 | f32fc648 | bellard | |
573 | 9df217a3 | bellard | int kqemu_init(CPUState *env);
|
574 | 9df217a3 | bellard | int kqemu_cpu_exec(CPUState *env);
|
575 | 9df217a3 | bellard | void kqemu_flush_page(CPUState *env, target_ulong addr);
|
576 | 9df217a3 | bellard | void kqemu_flush(CPUState *env, int global); |
577 | 4b7df22f | bellard | void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
|
578 | f32fc648 | bellard | void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
|
579 | a332e112 | bellard | void kqemu_cpu_interrupt(CPUState *env);
|
580 | f32fc648 | bellard | void kqemu_record_dump(void); |
581 | 9df217a3 | bellard | |
582 | 9df217a3 | bellard | static inline int kqemu_is_ok(CPUState *env) |
583 | 9df217a3 | bellard | { |
584 | 9df217a3 | bellard | return(env->kqemu_enabled &&
|
585 | 5fafdf24 | ths | (env->cr[0] & CR0_PE_MASK) &&
|
586 | f32fc648 | bellard | !(env->hflags & HF_INHIBIT_IRQ_MASK) && |
587 | 9df217a3 | bellard | (env->eflags & IF_MASK) && |
588 | f32fc648 | bellard | !(env->eflags & VM_MASK) && |
589 | 5fafdf24 | ths | (env->kqemu_enabled == 2 ||
|
590 | f32fc648 | bellard | ((env->hflags & HF_CPL_MASK) == 3 &&
|
591 | f32fc648 | bellard | (env->eflags & IOPL_MASK) != IOPL_MASK))); |
592 | 9df217a3 | bellard | } |
593 | 9df217a3 | bellard | |
594 | 9df217a3 | bellard | #endif |