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/*
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 * QEMU System Emulator header
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 *
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 * Copyright (c) 2003 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#ifndef VL_H
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#define VL_H
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/* we put basic includes here to avoid repeating them in device drivers */
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <inttypes.h>
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#include <limits.h>
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#include <time.h>
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#include <ctype.h>
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#include <errno.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <sys/stat.h>
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#ifndef O_LARGEFILE
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#define O_LARGEFILE 0
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#endif
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#ifndef O_BINARY
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#define O_BINARY 0
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#endif
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#ifndef ENOMEDIUM
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#define ENOMEDIUM ENODEV
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#endif
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#ifdef _WIN32
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#include <windows.h>
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#define fsync _commit
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#define lseek _lseeki64
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#define ENOTSUP 4096
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extern int qemu_ftruncate64(int, int64_t);
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#define ftruncate qemu_ftruncate64
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static inline char *realpath(const char *path, char *resolved_path)
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{
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    _fullpath(resolved_path, path, _MAX_PATH);
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    return resolved_path;
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}
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#define PRId64 "I64d"
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#define PRIx64 "I64x"
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#define PRIu64 "I64u"
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#define PRIo64 "I64o"
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#endif
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#ifdef QEMU_TOOL
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/* we use QEMU_TOOL in the command line tools which do not depend on
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   the target CPU type */
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#include "config-host.h"
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#include <setjmp.h>
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#include "osdep.h"
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#include "bswap.h"
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#else
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#include "audio/audio.h"
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#include "cpu.h"
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#endif /* !defined(QEMU_TOOL) */
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#ifndef glue
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#define xglue(x, y) x ## y
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#define glue(x, y) xglue(x, y)
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#define stringify(s)        tostring(s)
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#define tostring(s)        #s
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#endif
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#ifndef likely
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#if __GNUC__ < 3
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#define __builtin_expect(x, n) (x)
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#endif
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#define likely(x)   __builtin_expect(!!(x), 1)
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#define unlikely(x)   __builtin_expect(!!(x), 0)
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#endif
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#ifndef MIN
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#define MIN(a, b) (((a) < (b)) ? (a) : (b))
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#endif
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#ifndef MAX
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#define MAX(a, b) (((a) > (b)) ? (a) : (b))
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#endif
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#ifndef always_inline
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#if (__GNUC__ < 3) || defined(__APPLE__)
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#define always_inline inline
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#else
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#define always_inline __attribute__ (( always_inline )) inline
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#endif
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#endif
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/* cutils.c */
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void pstrcpy(char *buf, int buf_size, const char *str);
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char *pstrcat(char *buf, int buf_size, const char *s);
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int strstart(const char *str, const char *val, const char **ptr);
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int stristart(const char *str, const char *val, const char **ptr);
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/* vl.c */
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uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
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void hw_error(const char *fmt, ...);
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extern const char *bios_dir;
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extern const char *bios_name;
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extern int vm_running;
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extern const char *qemu_name;
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typedef struct vm_change_state_entry VMChangeStateEntry;
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typedef void VMChangeStateHandler(void *opaque, int running);
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typedef void VMStopHandler(void *opaque, int reason);
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VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
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                                                     void *opaque);
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void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
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int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
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void vm_start(void);
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void vm_stop(int reason);
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typedef void QEMUResetHandler(void *opaque);
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void qemu_register_reset(QEMUResetHandler *func, void *opaque);
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void qemu_system_reset_request(void);
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void qemu_system_shutdown_request(void);
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void qemu_system_powerdown_request(void);
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#if !defined(TARGET_SPARC)
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// Please implement a power failure function to signal the OS
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#define qemu_system_powerdown() do{}while(0)
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#else
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void qemu_system_powerdown(void);
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#endif
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void main_loop_wait(int timeout);
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extern int ram_size;
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extern int bios_size;
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extern int rtc_utc;
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extern int cirrus_vga_enabled;
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extern int vmsvga_enabled;
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extern int graphic_width;
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extern int graphic_height;
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extern int graphic_depth;
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extern const char *keyboard_layout;
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extern int kqemu_allowed;
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extern int win2k_install_hack;
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extern int alt_grab;
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extern int usb_enabled;
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extern int smp_cpus;
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extern int cursor_hide;
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extern int graphic_rotate;
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extern int no_quit;
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extern int semihosting_enabled;
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extern int autostart;
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extern int old_param;
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extern const char *bootp_filename;
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#define MAX_OPTION_ROMS 16
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extern const char *option_rom[MAX_OPTION_ROMS];
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extern int nb_option_roms;
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#ifdef TARGET_SPARC
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#define MAX_PROM_ENVS 128
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extern const char *prom_envs[MAX_PROM_ENVS];
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extern unsigned int nb_prom_envs;
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#endif
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/* XXX: make it dynamic */
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#define MAX_BIOS_SIZE (4 * 1024 * 1024)
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#if defined (TARGET_PPC) || defined (TARGET_SPARC64)
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#define BIOS_SIZE ((512 + 32) * 1024)
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#elif defined(TARGET_MIPS)
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#define BIOS_SIZE (4 * 1024 * 1024)
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#endif
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/* keyboard/mouse support */
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#define MOUSE_EVENT_LBUTTON 0x01
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#define MOUSE_EVENT_RBUTTON 0x02
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#define MOUSE_EVENT_MBUTTON 0x04
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typedef void QEMUPutKBDEvent(void *opaque, int keycode);
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typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
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typedef struct QEMUPutMouseEntry {
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    QEMUPutMouseEvent *qemu_put_mouse_event;
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    void *qemu_put_mouse_event_opaque;
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    int qemu_put_mouse_event_absolute;
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    char *qemu_put_mouse_event_name;
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    /* used internally by qemu for handling mice */
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    struct QEMUPutMouseEntry *next;
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} QEMUPutMouseEntry;
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void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
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QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
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                                                void *opaque, int absolute,
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                                                const char *name);
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void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
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void kbd_put_keycode(int keycode);
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void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
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int kbd_mouse_is_absolute(void);
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void do_info_mice(void);
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void do_mouse_set(int index);
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/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
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   constants) */
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#define QEMU_KEY_ESC1(c) ((c) | 0xe100)
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#define QEMU_KEY_BACKSPACE  0x007f
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#define QEMU_KEY_UP         QEMU_KEY_ESC1('A')
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#define QEMU_KEY_DOWN       QEMU_KEY_ESC1('B')
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#define QEMU_KEY_RIGHT      QEMU_KEY_ESC1('C')
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#define QEMU_KEY_LEFT       QEMU_KEY_ESC1('D')
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#define QEMU_KEY_HOME       QEMU_KEY_ESC1(1)
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#define QEMU_KEY_END        QEMU_KEY_ESC1(4)
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#define QEMU_KEY_PAGEUP     QEMU_KEY_ESC1(5)
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#define QEMU_KEY_PAGEDOWN   QEMU_KEY_ESC1(6)
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#define QEMU_KEY_DELETE     QEMU_KEY_ESC1(3)
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#define QEMU_KEY_CTRL_UP         0xe400
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#define QEMU_KEY_CTRL_DOWN       0xe401
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#define QEMU_KEY_CTRL_LEFT       0xe402
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#define QEMU_KEY_CTRL_RIGHT      0xe403
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#define QEMU_KEY_CTRL_HOME       0xe404
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#define QEMU_KEY_CTRL_END        0xe405
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#define QEMU_KEY_CTRL_PAGEUP     0xe406
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#define QEMU_KEY_CTRL_PAGEDOWN   0xe407
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void kbd_put_keysym(int keysym);
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/* async I/O support */
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typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
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typedef int IOCanRWHandler(void *opaque);
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typedef void IOHandler(void *opaque);
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int qemu_set_fd_handler2(int fd,
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                         IOCanRWHandler *fd_read_poll,
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                         IOHandler *fd_read,
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                         IOHandler *fd_write,
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                         void *opaque);
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int qemu_set_fd_handler(int fd,
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                        IOHandler *fd_read,
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                        IOHandler *fd_write,
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                        void *opaque);
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/* Polling handling */
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/* return TRUE if no sleep should be done afterwards */
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typedef int PollingFunc(void *opaque);
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int qemu_add_polling_cb(PollingFunc *func, void *opaque);
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void qemu_del_polling_cb(PollingFunc *func, void *opaque);
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#ifdef _WIN32
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/* Wait objects handling */
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typedef void WaitObjectFunc(void *opaque);
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int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
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#endif
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typedef struct QEMUBH QEMUBH;
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/* character device */
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#define CHR_EVENT_BREAK 0 /* serial break char */
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#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
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#define CHR_EVENT_RESET 2 /* new connection established */
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#define CHR_IOCTL_SERIAL_SET_PARAMS   1
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typedef struct {
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    int speed;
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    int parity;
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    int data_bits;
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    int stop_bits;
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} QEMUSerialSetParams;
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#define CHR_IOCTL_SERIAL_SET_BREAK    2
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#define CHR_IOCTL_PP_READ_DATA        3
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#define CHR_IOCTL_PP_WRITE_DATA       4
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#define CHR_IOCTL_PP_READ_CONTROL     5
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#define CHR_IOCTL_PP_WRITE_CONTROL    6
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#define CHR_IOCTL_PP_READ_STATUS      7
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#define CHR_IOCTL_PP_EPP_READ_ADDR    8
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#define CHR_IOCTL_PP_EPP_READ         9
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#define CHR_IOCTL_PP_EPP_WRITE_ADDR  10
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#define CHR_IOCTL_PP_EPP_WRITE       11
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typedef void IOEventHandler(void *opaque, int event);
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typedef struct CharDriverState {
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    int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
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    void (*chr_update_read_handler)(struct CharDriverState *s);
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    int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
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    IOEventHandler *chr_event;
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    IOCanRWHandler *chr_can_read;
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    IOReadHandler *chr_read;
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    void *handler_opaque;
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    void (*chr_send_event)(struct CharDriverState *chr, int event);
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    void (*chr_close)(struct CharDriverState *chr);
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    void *opaque;
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    int focus;
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    QEMUBH *bh;
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} CharDriverState;
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CharDriverState *qemu_chr_open(const char *filename);
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void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
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int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
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void qemu_chr_send_event(CharDriverState *s, int event);
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void qemu_chr_add_handlers(CharDriverState *s,
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                           IOCanRWHandler *fd_can_read,
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                           IOReadHandler *fd_read,
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                           IOEventHandler *fd_event,
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                           void *opaque);
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int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
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void qemu_chr_reset(CharDriverState *s);
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int qemu_chr_can_read(CharDriverState *s);
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void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
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/* consoles */
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typedef struct DisplayState DisplayState;
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typedef struct TextConsole TextConsole;
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typedef void (*vga_hw_update_ptr)(void *);
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typedef void (*vga_hw_invalidate_ptr)(void *);
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typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
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TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
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                                  vga_hw_invalidate_ptr invalidate,
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                                  vga_hw_screen_dump_ptr screen_dump,
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                                  void *opaque);
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void vga_hw_update(void);
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void vga_hw_invalidate(void);
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void vga_hw_screen_dump(const char *filename);
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int is_graphic_console(void);
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CharDriverState *text_console_init(DisplayState *ds, const char *p);
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void console_select(unsigned int index);
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/* serial ports */
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#define MAX_SERIAL_PORTS 4
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extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
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/* parallel ports */
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#define MAX_PARALLEL_PORTS 3
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extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
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388 5867c88a ths
struct ParallelIOArg {
389 5867c88a ths
    void *buffer;
390 5867c88a ths
    int count;
391 5867c88a ths
};
392 5867c88a ths
393 7c9d8e07 bellard
/* VLANs support */
394 7c9d8e07 bellard
395 7c9d8e07 bellard
typedef struct VLANClientState VLANClientState;
396 7c9d8e07 bellard
397 7c9d8e07 bellard
struct VLANClientState {
398 7c9d8e07 bellard
    IOReadHandler *fd_read;
399 d861b05e pbrook
    /* Packets may still be sent if this returns zero.  It's used to
400 d861b05e pbrook
       rate-limit the slirp code.  */
401 d861b05e pbrook
    IOCanRWHandler *fd_can_read;
402 7c9d8e07 bellard
    void *opaque;
403 7c9d8e07 bellard
    struct VLANClientState *next;
404 7c9d8e07 bellard
    struct VLANState *vlan;
405 7c9d8e07 bellard
    char info_str[256];
406 7c9d8e07 bellard
};
407 7c9d8e07 bellard
408 7c9d8e07 bellard
typedef struct VLANState {
409 7c9d8e07 bellard
    int id;
410 7c9d8e07 bellard
    VLANClientState *first_client;
411 7c9d8e07 bellard
    struct VLANState *next;
412 833c7174 blueswir1
    unsigned int nb_guest_devs, nb_host_devs;
413 7c9d8e07 bellard
} VLANState;
414 7c9d8e07 bellard
415 7c9d8e07 bellard
VLANState *qemu_find_vlan(int id);
416 7c9d8e07 bellard
VLANClientState *qemu_new_vlan_client(VLANState *vlan,
417 d861b05e pbrook
                                      IOReadHandler *fd_read,
418 d861b05e pbrook
                                      IOCanRWHandler *fd_can_read,
419 d861b05e pbrook
                                      void *opaque);
420 d861b05e pbrook
int qemu_can_send_packet(VLANClientState *vc);
421 7c9d8e07 bellard
void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
422 d861b05e pbrook
void qemu_handler_true(void *opaque);
423 7c9d8e07 bellard
424 7c9d8e07 bellard
void do_info_network(void);
425 7c9d8e07 bellard
426 7fb843f8 bellard
/* TAP win32 */
427 7fb843f8 bellard
int tap_win32_init(VLANState *vlan, const char *ifname);
428 7fb843f8 bellard
429 7c9d8e07 bellard
/* NIC info */
430 c4b1fcc0 bellard
431 c4b1fcc0 bellard
#define MAX_NICS 8
432 c4b1fcc0 bellard
433 7c9d8e07 bellard
typedef struct NICInfo {
434 c4b1fcc0 bellard
    uint8_t macaddr[6];
435 a41b2ff2 pbrook
    const char *model;
436 7c9d8e07 bellard
    VLANState *vlan;
437 7c9d8e07 bellard
} NICInfo;
438 c4b1fcc0 bellard
439 c4b1fcc0 bellard
extern int nb_nics;
440 7c9d8e07 bellard
extern NICInfo nd_table[MAX_NICS];
441 8a7ddc38 bellard
442 8a7ddc38 bellard
/* timers */
443 8a7ddc38 bellard
444 8a7ddc38 bellard
typedef struct QEMUClock QEMUClock;
445 8a7ddc38 bellard
typedef struct QEMUTimer QEMUTimer;
446 8a7ddc38 bellard
typedef void QEMUTimerCB(void *opaque);
447 8a7ddc38 bellard
448 8a7ddc38 bellard
/* The real time clock should be used only for stuff which does not
449 8a7ddc38 bellard
   change the virtual machine state, as it is run even if the virtual
450 69b91039 bellard
   machine is stopped. The real time clock has a frequency of 1000
451 8a7ddc38 bellard
   Hz. */
452 8a7ddc38 bellard
extern QEMUClock *rt_clock;
453 8a7ddc38 bellard
454 e80cfcfc bellard
/* The virtual clock is only run during the emulation. It is stopped
455 8a7ddc38 bellard
   when the virtual machine is stopped. Virtual timers use a high
456 8a7ddc38 bellard
   precision clock, usually cpu cycles (use ticks_per_sec). */
457 8a7ddc38 bellard
extern QEMUClock *vm_clock;
458 8a7ddc38 bellard
459 8a7ddc38 bellard
int64_t qemu_get_clock(QEMUClock *clock);
460 8a7ddc38 bellard
461 8a7ddc38 bellard
QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
462 8a7ddc38 bellard
void qemu_free_timer(QEMUTimer *ts);
463 8a7ddc38 bellard
void qemu_del_timer(QEMUTimer *ts);
464 8a7ddc38 bellard
void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
465 8a7ddc38 bellard
int qemu_timer_pending(QEMUTimer *ts);
466 8a7ddc38 bellard
467 8a7ddc38 bellard
extern int64_t ticks_per_sec;
468 8a7ddc38 bellard
469 1dce7c3c bellard
int64_t cpu_get_ticks(void);
470 8a7ddc38 bellard
void cpu_enable_ticks(void);
471 8a7ddc38 bellard
void cpu_disable_ticks(void);
472 8a7ddc38 bellard
473 8a7ddc38 bellard
/* VM Load/Save */
474 8a7ddc38 bellard
475 faea38e7 bellard
typedef struct QEMUFile QEMUFile;
476 8a7ddc38 bellard
477 faea38e7 bellard
QEMUFile *qemu_fopen(const char *filename, const char *mode);
478 faea38e7 bellard
void qemu_fflush(QEMUFile *f);
479 faea38e7 bellard
void qemu_fclose(QEMUFile *f);
480 8a7ddc38 bellard
void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
481 8a7ddc38 bellard
void qemu_put_byte(QEMUFile *f, int v);
482 8a7ddc38 bellard
void qemu_put_be16(QEMUFile *f, unsigned int v);
483 8a7ddc38 bellard
void qemu_put_be32(QEMUFile *f, unsigned int v);
484 8a7ddc38 bellard
void qemu_put_be64(QEMUFile *f, uint64_t v);
485 8a7ddc38 bellard
int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
486 8a7ddc38 bellard
int qemu_get_byte(QEMUFile *f);
487 8a7ddc38 bellard
unsigned int qemu_get_be16(QEMUFile *f);
488 8a7ddc38 bellard
unsigned int qemu_get_be32(QEMUFile *f);
489 8a7ddc38 bellard
uint64_t qemu_get_be64(QEMUFile *f);
490 8a7ddc38 bellard
491 8a7ddc38 bellard
static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
492 8a7ddc38 bellard
{
493 8a7ddc38 bellard
    qemu_put_be64(f, *pv);
494 8a7ddc38 bellard
}
495 8a7ddc38 bellard
496 8a7ddc38 bellard
static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
497 8a7ddc38 bellard
{
498 8a7ddc38 bellard
    qemu_put_be32(f, *pv);
499 8a7ddc38 bellard
}
500 8a7ddc38 bellard
501 8a7ddc38 bellard
static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
502 8a7ddc38 bellard
{
503 8a7ddc38 bellard
    qemu_put_be16(f, *pv);
504 8a7ddc38 bellard
}
505 8a7ddc38 bellard
506 8a7ddc38 bellard
static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
507 8a7ddc38 bellard
{
508 8a7ddc38 bellard
    qemu_put_byte(f, *pv);
509 8a7ddc38 bellard
}
510 8a7ddc38 bellard
511 8a7ddc38 bellard
static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
512 8a7ddc38 bellard
{
513 8a7ddc38 bellard
    *pv = qemu_get_be64(f);
514 8a7ddc38 bellard
}
515 8a7ddc38 bellard
516 8a7ddc38 bellard
static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
517 8a7ddc38 bellard
{
518 8a7ddc38 bellard
    *pv = qemu_get_be32(f);
519 8a7ddc38 bellard
}
520 8a7ddc38 bellard
521 8a7ddc38 bellard
static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
522 8a7ddc38 bellard
{
523 8a7ddc38 bellard
    *pv = qemu_get_be16(f);
524 8a7ddc38 bellard
}
525 8a7ddc38 bellard
526 8a7ddc38 bellard
static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
527 8a7ddc38 bellard
{
528 8a7ddc38 bellard
    *pv = qemu_get_byte(f);
529 8a7ddc38 bellard
}
530 8a7ddc38 bellard
531 c27004ec bellard
#if TARGET_LONG_BITS == 64
532 c27004ec bellard
#define qemu_put_betl qemu_put_be64
533 c27004ec bellard
#define qemu_get_betl qemu_get_be64
534 c27004ec bellard
#define qemu_put_betls qemu_put_be64s
535 c27004ec bellard
#define qemu_get_betls qemu_get_be64s
536 c27004ec bellard
#else
537 c27004ec bellard
#define qemu_put_betl qemu_put_be32
538 c27004ec bellard
#define qemu_get_betl qemu_get_be32
539 c27004ec bellard
#define qemu_put_betls qemu_put_be32s
540 c27004ec bellard
#define qemu_get_betls qemu_get_be32s
541 c27004ec bellard
#endif
542 c27004ec bellard
543 8a7ddc38 bellard
int64_t qemu_ftell(QEMUFile *f);
544 8a7ddc38 bellard
int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
545 8a7ddc38 bellard
546 8a7ddc38 bellard
typedef void SaveStateHandler(QEMUFile *f, void *opaque);
547 8a7ddc38 bellard
typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
548 8a7ddc38 bellard
549 5fafdf24 ths
int register_savevm(const char *idstr,
550 5fafdf24 ths
                    int instance_id,
551 8a7ddc38 bellard
                    int version_id,
552 8a7ddc38 bellard
                    SaveStateHandler *save_state,
553 8a7ddc38 bellard
                    LoadStateHandler *load_state,
554 8a7ddc38 bellard
                    void *opaque);
555 8a7ddc38 bellard
void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
556 8a7ddc38 bellard
void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
557 c4b1fcc0 bellard
558 6a00d601 bellard
void cpu_save(QEMUFile *f, void *opaque);
559 6a00d601 bellard
int cpu_load(QEMUFile *f, void *opaque, int version_id);
560 6a00d601 bellard
561 faea38e7 bellard
void do_savevm(const char *name);
562 faea38e7 bellard
void do_loadvm(const char *name);
563 faea38e7 bellard
void do_delvm(const char *name);
564 faea38e7 bellard
void do_info_snapshots(void);
565 faea38e7 bellard
566 83f64091 bellard
/* bottom halves */
567 83f64091 bellard
typedef void QEMUBHFunc(void *opaque);
568 83f64091 bellard
569 83f64091 bellard
QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
570 83f64091 bellard
void qemu_bh_schedule(QEMUBH *bh);
571 83f64091 bellard
void qemu_bh_cancel(QEMUBH *bh);
572 83f64091 bellard
void qemu_bh_delete(QEMUBH *bh);
573 6eb5733a bellard
int qemu_bh_poll(void);
574 83f64091 bellard
575 fc01f7e7 bellard
/* block.c */
576 fc01f7e7 bellard
typedef struct BlockDriverState BlockDriverState;
577 ea2384d3 bellard
typedef struct BlockDriver BlockDriver;
578 ea2384d3 bellard
579 ea2384d3 bellard
extern BlockDriver bdrv_raw;
580 19cb3738 bellard
extern BlockDriver bdrv_host_device;
581 ea2384d3 bellard
extern BlockDriver bdrv_cow;
582 ea2384d3 bellard
extern BlockDriver bdrv_qcow;
583 ea2384d3 bellard
extern BlockDriver bdrv_vmdk;
584 3c56521b bellard
extern BlockDriver bdrv_cloop;
585 585d0ed9 bellard
extern BlockDriver bdrv_dmg;
586 a8753c34 bellard
extern BlockDriver bdrv_bochs;
587 6a0f9e82 bellard
extern BlockDriver bdrv_vpc;
588 de167e41 bellard
extern BlockDriver bdrv_vvfat;
589 faea38e7 bellard
extern BlockDriver bdrv_qcow2;
590 6ada7453 ths
extern BlockDriver bdrv_parallels;
591 faea38e7 bellard
592 faea38e7 bellard
typedef struct BlockDriverInfo {
593 faea38e7 bellard
    /* in bytes, 0 if irrelevant */
594 5fafdf24 ths
    int cluster_size;
595 faea38e7 bellard
    /* offset at which the VM state can be saved (0 if not possible) */
596 5fafdf24 ths
    int64_t vm_state_offset;
597 faea38e7 bellard
} BlockDriverInfo;
598 faea38e7 bellard
599 faea38e7 bellard
typedef struct QEMUSnapshotInfo {
600 faea38e7 bellard
    char id_str[128]; /* unique snapshot id */
601 faea38e7 bellard
    /* the following fields are informative. They are not needed for
602 faea38e7 bellard
       the consistency of the snapshot */
603 faea38e7 bellard
    char name[256]; /* user choosen name */
604 faea38e7 bellard
    uint32_t vm_state_size; /* VM state info size */
605 faea38e7 bellard
    uint32_t date_sec; /* UTC date of the snapshot */
606 faea38e7 bellard
    uint32_t date_nsec;
607 faea38e7 bellard
    uint64_t vm_clock_nsec; /* VM clock relative to boot */
608 faea38e7 bellard
} QEMUSnapshotInfo;
609 ea2384d3 bellard
610 83f64091 bellard
#define BDRV_O_RDONLY      0x0000
611 83f64091 bellard
#define BDRV_O_RDWR        0x0002
612 83f64091 bellard
#define BDRV_O_ACCESS      0x0003
613 83f64091 bellard
#define BDRV_O_CREAT       0x0004 /* create an empty file */
614 83f64091 bellard
#define BDRV_O_SNAPSHOT    0x0008 /* open the file read only and save writes in a snapshot */
615 83f64091 bellard
#define BDRV_O_FILE        0x0010 /* open as a raw file (do not try to
616 83f64091 bellard
                                     use a disk image format on top of
617 83f64091 bellard
                                     it (default for
618 83f64091 bellard
                                     bdrv_file_open()) */
619 83f64091 bellard
620 ea2384d3 bellard
void bdrv_init(void);
621 ea2384d3 bellard
BlockDriver *bdrv_find_format(const char *format_name);
622 5fafdf24 ths
int bdrv_create(BlockDriver *drv,
623 ea2384d3 bellard
                const char *filename, int64_t size_in_sectors,
624 ea2384d3 bellard
                const char *backing_file, int flags);
625 c4b1fcc0 bellard
BlockDriverState *bdrv_new(const char *device_name);
626 c4b1fcc0 bellard
void bdrv_delete(BlockDriverState *bs);
627 83f64091 bellard
int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
628 83f64091 bellard
int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
629 83f64091 bellard
int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
630 ea2384d3 bellard
               BlockDriver *drv);
631 fc01f7e7 bellard
void bdrv_close(BlockDriverState *bs);
632 5fafdf24 ths
int bdrv_read(BlockDriverState *bs, int64_t sector_num,
633 fc01f7e7 bellard
              uint8_t *buf, int nb_sectors);
634 5fafdf24 ths
int bdrv_write(BlockDriverState *bs, int64_t sector_num,
635 fc01f7e7 bellard
               const uint8_t *buf, int nb_sectors);
636 5fafdf24 ths
int bdrv_pread(BlockDriverState *bs, int64_t offset,
637 83f64091 bellard
               void *buf, int count);
638 5fafdf24 ths
int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
639 83f64091 bellard
                const void *buf, int count);
640 83f64091 bellard
int bdrv_truncate(BlockDriverState *bs, int64_t offset);
641 83f64091 bellard
int64_t bdrv_getlength(BlockDriverState *bs);
642 fc01f7e7 bellard
void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
643 33e3963e bellard
int bdrv_commit(BlockDriverState *bs);
644 77fef8c1 bellard
void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
645 83f64091 bellard
/* async block I/O */
646 83f64091 bellard
typedef struct BlockDriverAIOCB BlockDriverAIOCB;
647 83f64091 bellard
typedef void BlockDriverCompletionFunc(void *opaque, int ret);
648 83f64091 bellard
649 ce1a14dc pbrook
BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
650 ce1a14dc pbrook
                                uint8_t *buf, int nb_sectors,
651 ce1a14dc pbrook
                                BlockDriverCompletionFunc *cb, void *opaque);
652 ce1a14dc pbrook
BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
653 ce1a14dc pbrook
                                 const uint8_t *buf, int nb_sectors,
654 ce1a14dc pbrook
                                 BlockDriverCompletionFunc *cb, void *opaque);
655 83f64091 bellard
void bdrv_aio_cancel(BlockDriverAIOCB *acb);
656 83f64091 bellard
657 83f64091 bellard
void qemu_aio_init(void);
658 83f64091 bellard
void qemu_aio_poll(void);
659 6192bc37 pbrook
void qemu_aio_flush(void);
660 83f64091 bellard
void qemu_aio_wait_start(void);
661 83f64091 bellard
void qemu_aio_wait(void);
662 83f64091 bellard
void qemu_aio_wait_end(void);
663 83f64091 bellard
664 2bac6019 balrog
int qemu_key_check(BlockDriverState *bs, const char *name);
665 2bac6019 balrog
666 7a6cba61 pbrook
/* Ensure contents are flushed to disk.  */
667 7a6cba61 pbrook
void bdrv_flush(BlockDriverState *bs);
668 33e3963e bellard
669 c4b1fcc0 bellard
#define BDRV_TYPE_HD     0
670 c4b1fcc0 bellard
#define BDRV_TYPE_CDROM  1
671 c4b1fcc0 bellard
#define BDRV_TYPE_FLOPPY 2
672 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_AUTO   0
673 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_NONE   1
674 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_LBA    2
675 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_LARGE  3
676 4dbb0f50 ths
#define BIOS_ATA_TRANSLATION_RECHS  4
677 c4b1fcc0 bellard
678 5fafdf24 ths
void bdrv_set_geometry_hint(BlockDriverState *bs,
679 c4b1fcc0 bellard
                            int cyls, int heads, int secs);
680 c4b1fcc0 bellard
void bdrv_set_type_hint(BlockDriverState *bs, int type);
681 46d4767d bellard
void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
682 5fafdf24 ths
void bdrv_get_geometry_hint(BlockDriverState *bs,
683 c4b1fcc0 bellard
                            int *pcyls, int *pheads, int *psecs);
684 c4b1fcc0 bellard
int bdrv_get_type_hint(BlockDriverState *bs);
685 46d4767d bellard
int bdrv_get_translation_hint(BlockDriverState *bs);
686 c4b1fcc0 bellard
int bdrv_is_removable(BlockDriverState *bs);
687 c4b1fcc0 bellard
int bdrv_is_read_only(BlockDriverState *bs);
688 c4b1fcc0 bellard
int bdrv_is_inserted(BlockDriverState *bs);
689 19cb3738 bellard
int bdrv_media_changed(BlockDriverState *bs);
690 c4b1fcc0 bellard
int bdrv_is_locked(BlockDriverState *bs);
691 c4b1fcc0 bellard
void bdrv_set_locked(BlockDriverState *bs, int locked);
692 19cb3738 bellard
void bdrv_eject(BlockDriverState *bs, int eject_flag);
693 5fafdf24 ths
void bdrv_set_change_cb(BlockDriverState *bs,
694 c4b1fcc0 bellard
                        void (*change_cb)(void *opaque), void *opaque);
695 ea2384d3 bellard
void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
696 c4b1fcc0 bellard
void bdrv_info(void);
697 c4b1fcc0 bellard
BlockDriverState *bdrv_find(const char *name);
698 82c643ff bellard
void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
699 ea2384d3 bellard
int bdrv_is_encrypted(BlockDriverState *bs);
700 ea2384d3 bellard
int bdrv_set_key(BlockDriverState *bs, const char *key);
701 5fafdf24 ths
void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
702 ea2384d3 bellard
                         void *opaque);
703 ea2384d3 bellard
const char *bdrv_get_device_name(BlockDriverState *bs);
704 5fafdf24 ths
int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
705 faea38e7 bellard
                          const uint8_t *buf, int nb_sectors);
706 faea38e7 bellard
int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
707 c4b1fcc0 bellard
708 5fafdf24 ths
void bdrv_get_backing_filename(BlockDriverState *bs,
709 83f64091 bellard
                               char *filename, int filename_size);
710 5fafdf24 ths
int bdrv_snapshot_create(BlockDriverState *bs,
711 faea38e7 bellard
                         QEMUSnapshotInfo *sn_info);
712 5fafdf24 ths
int bdrv_snapshot_goto(BlockDriverState *bs,
713 faea38e7 bellard
                       const char *snapshot_id);
714 faea38e7 bellard
int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
715 5fafdf24 ths
int bdrv_snapshot_list(BlockDriverState *bs,
716 faea38e7 bellard
                       QEMUSnapshotInfo **psn_info);
717 faea38e7 bellard
char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
718 faea38e7 bellard
719 faea38e7 bellard
char *get_human_readable_size(char *buf, int buf_size, int64_t size);
720 83f64091 bellard
int path_is_absolute(const char *path);
721 83f64091 bellard
void path_combine(char *dest, int dest_size,
722 83f64091 bellard
                  const char *base_path,
723 83f64091 bellard
                  const char *filename);
724 ea2384d3 bellard
725 ea2384d3 bellard
#ifndef QEMU_TOOL
726 54fa5af5 bellard
727 5fafdf24 ths
typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
728 54fa5af5 bellard
                                 int boot_device,
729 54fa5af5 bellard
             DisplayState *ds, const char **fd_filename, int snapshot,
730 54fa5af5 bellard
             const char *kernel_filename, const char *kernel_cmdline,
731 94fc95cd j_mayer
             const char *initrd_filename, const char *cpu_model);
732 54fa5af5 bellard
733 54fa5af5 bellard
typedef struct QEMUMachine {
734 54fa5af5 bellard
    const char *name;
735 54fa5af5 bellard
    const char *desc;
736 54fa5af5 bellard
    QEMUMachineInitFunc *init;
737 54fa5af5 bellard
    struct QEMUMachine *next;
738 54fa5af5 bellard
} QEMUMachine;
739 54fa5af5 bellard
740 54fa5af5 bellard
int qemu_register_machine(QEMUMachine *m);
741 54fa5af5 bellard
742 54fa5af5 bellard
typedef void SetIRQFunc(void *opaque, int irq_num, int level);
743 54fa5af5 bellard
744 d537cf6c pbrook
#include "hw/irq.h"
745 d537cf6c pbrook
746 26aa7d72 bellard
/* ISA bus */
747 26aa7d72 bellard
748 26aa7d72 bellard
extern target_phys_addr_t isa_mem_base;
749 26aa7d72 bellard
750 26aa7d72 bellard
typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
751 26aa7d72 bellard
typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
752 26aa7d72 bellard
753 5fafdf24 ths
int register_ioport_read(int start, int length, int size,
754 26aa7d72 bellard
                         IOPortReadFunc *func, void *opaque);
755 5fafdf24 ths
int register_ioport_write(int start, int length, int size,
756 26aa7d72 bellard
                          IOPortWriteFunc *func, void *opaque);
757 69b91039 bellard
void isa_unassign_ioport(int start, int length);
758 69b91039 bellard
759 aef445bd pbrook
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
760 aef445bd pbrook
761 69b91039 bellard
/* PCI bus */
762 69b91039 bellard
763 69b91039 bellard
extern target_phys_addr_t pci_mem_base;
764 69b91039 bellard
765 46e50e9d bellard
typedef struct PCIBus PCIBus;
766 69b91039 bellard
typedef struct PCIDevice PCIDevice;
767 69b91039 bellard
768 5fafdf24 ths
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
769 69b91039 bellard
                                uint32_t address, uint32_t data, int len);
770 5fafdf24 ths
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
771 69b91039 bellard
                                   uint32_t address, int len);
772 5fafdf24 ths
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
773 69b91039 bellard
                                uint32_t addr, uint32_t size, int type);
774 69b91039 bellard
775 69b91039 bellard
#define PCI_ADDRESS_SPACE_MEM                0x00
776 69b91039 bellard
#define PCI_ADDRESS_SPACE_IO                0x01
777 69b91039 bellard
#define PCI_ADDRESS_SPACE_MEM_PREFETCH        0x08
778 69b91039 bellard
779 69b91039 bellard
typedef struct PCIIORegion {
780 5768f5ac bellard
    uint32_t addr; /* current PCI mapping address. -1 means not mapped */
781 69b91039 bellard
    uint32_t size;
782 69b91039 bellard
    uint8_t type;
783 69b91039 bellard
    PCIMapIORegionFunc *map_func;
784 69b91039 bellard
} PCIIORegion;
785 69b91039 bellard
786 8a8696a3 bellard
#define PCI_ROM_SLOT 6
787 8a8696a3 bellard
#define PCI_NUM_REGIONS 7
788 502a5395 pbrook
789 502a5395 pbrook
#define PCI_DEVICES_MAX 64
790 502a5395 pbrook
791 502a5395 pbrook
#define PCI_VENDOR_ID                0x00        /* 16 bits */
792 502a5395 pbrook
#define PCI_DEVICE_ID                0x02        /* 16 bits */
793 502a5395 pbrook
#define PCI_COMMAND                0x04        /* 16 bits */
794 502a5395 pbrook
#define  PCI_COMMAND_IO                0x1        /* Enable response in I/O space */
795 502a5395 pbrook
#define  PCI_COMMAND_MEMORY        0x2        /* Enable response in Memory space */
796 502a5395 pbrook
#define PCI_CLASS_DEVICE        0x0a    /* Device class */
797 502a5395 pbrook
#define PCI_INTERRUPT_LINE        0x3c        /* 8 bits */
798 502a5395 pbrook
#define PCI_INTERRUPT_PIN        0x3d        /* 8 bits */
799 502a5395 pbrook
#define PCI_MIN_GNT                0x3e        /* 8 bits */
800 502a5395 pbrook
#define PCI_MAX_LAT                0x3f        /* 8 bits */
801 502a5395 pbrook
802 69b91039 bellard
struct PCIDevice {
803 69b91039 bellard
    /* PCI config space */
804 69b91039 bellard
    uint8_t config[256];
805 69b91039 bellard
806 69b91039 bellard
    /* the following fields are read only */
807 46e50e9d bellard
    PCIBus *bus;
808 69b91039 bellard
    int devfn;
809 69b91039 bellard
    char name[64];
810 8a8696a3 bellard
    PCIIORegion io_regions[PCI_NUM_REGIONS];
811 3b46e624 ths
812 69b91039 bellard
    /* do not access the following fields */
813 69b91039 bellard
    PCIConfigReadFunc *config_read;
814 69b91039 bellard
    PCIConfigWriteFunc *config_write;
815 502a5395 pbrook
    /* ??? This is a PC-specific hack, and should be removed.  */
816 5768f5ac bellard
    int irq_index;
817 d2b59317 pbrook
818 d537cf6c pbrook
    /* IRQ objects for the INTA-INTD pins.  */
819 d537cf6c pbrook
    qemu_irq *irq;
820 d537cf6c pbrook
821 d2b59317 pbrook
    /* Current IRQ levels.  Used internally by the generic PCI code.  */
822 d2b59317 pbrook
    int irq_state[4];
823 69b91039 bellard
};
824 69b91039 bellard
825 46e50e9d bellard
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
826 46e50e9d bellard
                               int instance_size, int devfn,
827 5fafdf24 ths
                               PCIConfigReadFunc *config_read,
828 69b91039 bellard
                               PCIConfigWriteFunc *config_write);
829 69b91039 bellard
830 5fafdf24 ths
void pci_register_io_region(PCIDevice *pci_dev, int region_num,
831 5fafdf24 ths
                            uint32_t size, int type,
832 69b91039 bellard
                            PCIMapIORegionFunc *map_func);
833 69b91039 bellard
834 5fafdf24 ths
uint32_t pci_default_read_config(PCIDevice *d,
835 5768f5ac bellard
                                 uint32_t address, int len);
836 5fafdf24 ths
void pci_default_write_config(PCIDevice *d,
837 5768f5ac bellard
                              uint32_t address, uint32_t val, int len);
838 89b6b508 bellard
void pci_device_save(PCIDevice *s, QEMUFile *f);
839 89b6b508 bellard
int pci_device_load(PCIDevice *s, QEMUFile *f);
840 5768f5ac bellard
841 d537cf6c pbrook
typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
842 d2b59317 pbrook
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
843 d2b59317 pbrook
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
844 d537cf6c pbrook
                         qemu_irq *pic, int devfn_min, int nirq);
845 502a5395 pbrook
846 abcebc7e ths
void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
847 502a5395 pbrook
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
848 502a5395 pbrook
uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
849 502a5395 pbrook
int pci_bus_num(PCIBus *s);
850 80b3ada7 pbrook
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
851 9995c51f bellard
852 5768f5ac bellard
void pci_info(void);
853 80b3ada7 pbrook
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
854 80b3ada7 pbrook
                        pci_map_irq_fn map_irq, const char *name);
855 26aa7d72 bellard
856 502a5395 pbrook
/* prep_pci.c */
857 d537cf6c pbrook
PCIBus *pci_prep_init(qemu_irq *pic);
858 77d4bc34 bellard
859 502a5395 pbrook
/* grackle_pci.c */
860 d537cf6c pbrook
PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic);
861 502a5395 pbrook
862 502a5395 pbrook
/* unin_pci.c */
863 d537cf6c pbrook
PCIBus *pci_pmac_init(qemu_irq *pic);
864 502a5395 pbrook
865 502a5395 pbrook
/* apb_pci.c */
866 5b9693dc blueswir1
PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
867 d537cf6c pbrook
                     qemu_irq *pic);
868 502a5395 pbrook
869 d537cf6c pbrook
PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
870 502a5395 pbrook
871 502a5395 pbrook
/* piix_pci.c */
872 d537cf6c pbrook
PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
873 f00fc47c bellard
void i440fx_set_smm(PCIDevice *d, int val);
874 8f1c91d8 ths
int piix3_init(PCIBus *bus, int devfn);
875 f00fc47c bellard
void i440fx_init_memory_mappings(PCIDevice *d);
876 a41b2ff2 pbrook
877 5856de80 ths
int piix4_init(PCIBus *bus, int devfn);
878 5856de80 ths
879 28b9b5af bellard
/* openpic.c */
880 e9df014c j_mayer
/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
881 47103572 j_mayer
enum {
882 e9df014c j_mayer
    OPENPIC_OUTPUT_INT = 0, /* IRQ                       */
883 e9df014c j_mayer
    OPENPIC_OUTPUT_CINT,    /* critical IRQ              */
884 e9df014c j_mayer
    OPENPIC_OUTPUT_MCK,     /* Machine check event       */
885 e9df014c j_mayer
    OPENPIC_OUTPUT_DEBUG,   /* Inconditional debug event */
886 e9df014c j_mayer
    OPENPIC_OUTPUT_RESET,   /* Core reset event          */
887 e9df014c j_mayer
    OPENPIC_OUTPUT_NB,
888 47103572 j_mayer
};
889 e9df014c j_mayer
qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
890 e9df014c j_mayer
                        qemu_irq **irqs, qemu_irq irq_out);
891 28b9b5af bellard
892 54fa5af5 bellard
/* heathrow_pic.c */
893 d537cf6c pbrook
qemu_irq *heathrow_pic_init(int *pmem_index);
894 54fa5af5 bellard
895 fde7d5bd ths
/* gt64xxx.c */
896 d537cf6c pbrook
PCIBus *pci_gt64120_init(qemu_irq *pic);
897 fde7d5bd ths
898 6a36d84e bellard
#ifdef HAS_AUDIO
899 6a36d84e bellard
struct soundhw {
900 6a36d84e bellard
    const char *name;
901 6a36d84e bellard
    const char *descr;
902 6a36d84e bellard
    int enabled;
903 6a36d84e bellard
    int isa;
904 6a36d84e bellard
    union {
905 d537cf6c pbrook
        int (*init_isa) (AudioState *s, qemu_irq *pic);
906 6a36d84e bellard
        int (*init_pci) (PCIBus *bus, AudioState *s);
907 6a36d84e bellard
    } init;
908 6a36d84e bellard
};
909 6a36d84e bellard
910 6a36d84e bellard
extern struct soundhw soundhw[];
911 6a36d84e bellard
#endif
912 6a36d84e bellard
913 313aa567 bellard
/* vga.c */
914 313aa567 bellard
915 eee0b836 blueswir1
#ifndef TARGET_SPARC
916 74a14f22 bellard
#define VGA_RAM_SIZE (8192 * 1024)
917 eee0b836 blueswir1
#else
918 eee0b836 blueswir1
#define VGA_RAM_SIZE (9 * 1024 * 1024)
919 eee0b836 blueswir1
#endif
920 313aa567 bellard
921 82c643ff bellard
struct DisplayState {
922 313aa567 bellard
    uint8_t *data;
923 313aa567 bellard
    int linesize;
924 313aa567 bellard
    int depth;
925 d3079cd2 bellard
    int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
926 82c643ff bellard
    int width;
927 82c643ff bellard
    int height;
928 24236869 bellard
    void *opaque;
929 740733bb ths
    QEMUTimer *gui_timer;
930 24236869 bellard
931 313aa567 bellard
    void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
932 313aa567 bellard
    void (*dpy_resize)(struct DisplayState *s, int w, int h);
933 313aa567 bellard
    void (*dpy_refresh)(struct DisplayState *s);
934 d34cab9f ths
    void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
935 d34cab9f ths
                     int dst_x, int dst_y, int w, int h);
936 d34cab9f ths
    void (*dpy_fill)(struct DisplayState *s, int x, int y,
937 d34cab9f ths
                     int w, int h, uint32_t c);
938 d34cab9f ths
    void (*mouse_set)(int x, int y, int on);
939 d34cab9f ths
    void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
940 d34cab9f ths
                          uint8_t *image, uint8_t *mask);
941 82c643ff bellard
};
942 313aa567 bellard
943 313aa567 bellard
static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
944 313aa567 bellard
{
945 313aa567 bellard
    s->dpy_update(s, x, y, w, h);
946 313aa567 bellard
}
947 313aa567 bellard
948 313aa567 bellard
static inline void dpy_resize(DisplayState *s, int w, int h)
949 313aa567 bellard
{
950 313aa567 bellard
    s->dpy_resize(s, w, h);
951 313aa567 bellard
}
952 313aa567 bellard
953 5fafdf24 ths
int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
954 89b6b508 bellard
                 unsigned long vga_ram_offset, int vga_ram_size);
955 5fafdf24 ths
int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
956 89b6b508 bellard
                 unsigned long vga_ram_offset, int vga_ram_size,
957 89b6b508 bellard
                 unsigned long vga_bios_offset, int vga_bios_size);
958 2abec30b ths
int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
959 2abec30b ths
                    unsigned long vga_ram_offset, int vga_ram_size,
960 2abec30b ths
                    target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
961 2abec30b ths
                    int it_shift);
962 313aa567 bellard
963 d6bfa22f bellard
/* cirrus_vga.c */
964 5fafdf24 ths
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
965 d6bfa22f bellard
                         unsigned long vga_ram_offset, int vga_ram_size);
966 5fafdf24 ths
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
967 d6bfa22f bellard
                         unsigned long vga_ram_offset, int vga_ram_size);
968 d6bfa22f bellard
969 d34cab9f ths
/* vmware_vga.c */
970 d34cab9f ths
void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
971 d34cab9f ths
                     unsigned long vga_ram_offset, int vga_ram_size);
972 d34cab9f ths
973 313aa567 bellard
/* sdl.c */
974 43523e93 ths
void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
975 313aa567 bellard
976 da4dbf74 bellard
/* cocoa.m */
977 da4dbf74 bellard
void cocoa_display_init(DisplayState *ds, int full_screen);
978 da4dbf74 bellard
979 24236869 bellard
/* vnc.c */
980 71cab5ca ths
void vnc_display_init(DisplayState *ds);
981 71cab5ca ths
void vnc_display_close(DisplayState *ds);
982 71cab5ca ths
int vnc_display_open(DisplayState *ds, const char *display);
983 70848515 ths
int vnc_display_password(DisplayState *ds, const char *password);
984 a9ce8590 bellard
void do_info_vnc(void);
985 24236869 bellard
986 6070dd07 ths
/* x_keymap.c */
987 6070dd07 ths
extern uint8_t _translate_keycode(const int key);
988 6070dd07 ths
989 5391d806 bellard
/* ide.c */
990 5391d806 bellard
#define MAX_DISKS 4
991 5391d806 bellard
992 faea38e7 bellard
extern BlockDriverState *bs_table[MAX_DISKS + 1];
993 a1bb27b1 pbrook
extern BlockDriverState *sd_bdrv;
994 3e3d5815 balrog
extern BlockDriverState *mtd_bdrv;
995 5391d806 bellard
996 d537cf6c pbrook
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
997 69b91039 bellard
                  BlockDriverState *hd0, BlockDriverState *hd1);
998 54fa5af5 bellard
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
999 54fa5af5 bellard
                         int secondary_ide_enabled);
1000 d537cf6c pbrook
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1001 d537cf6c pbrook
                        qemu_irq *pic);
1002 afcc3cdf ths
void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1003 afcc3cdf ths
                        qemu_irq *pic);
1004 d537cf6c pbrook
int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
1005 5391d806 bellard
1006 2e5d83bb pbrook
/* cdrom.c */
1007 2e5d83bb pbrook
int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
1008 2e5d83bb pbrook
int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
1009 2e5d83bb pbrook
1010 9542611a ths
/* ds1225y.c */
1011 9542611a ths
typedef struct ds1225y_t ds1225y_t;
1012 71db710f blueswir1
ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
1013 9542611a ths
1014 1d14ffa9 bellard
/* es1370.c */
1015 c0fe3827 bellard
int es1370_init (PCIBus *bus, AudioState *s);
1016 1d14ffa9 bellard
1017 fb065187 bellard
/* sb16.c */
1018 d537cf6c pbrook
int SB16_init (AudioState *s, qemu_irq *pic);
1019 fb065187 bellard
1020 fb065187 bellard
/* adlib.c */
1021 d537cf6c pbrook
int Adlib_init (AudioState *s, qemu_irq *pic);
1022 fb065187 bellard
1023 fb065187 bellard
/* gus.c */
1024 d537cf6c pbrook
int GUS_init (AudioState *s, qemu_irq *pic);
1025 27503323 bellard
1026 27503323 bellard
/* dma.c */
1027 85571bc7 bellard
typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
1028 27503323 bellard
int DMA_get_channel_mode (int nchan);
1029 85571bc7 bellard
int DMA_read_memory (int nchan, void *buf, int pos, int size);
1030 85571bc7 bellard
int DMA_write_memory (int nchan, void *buf, int pos, int size);
1031 27503323 bellard
void DMA_hold_DREQ (int nchan);
1032 27503323 bellard
void DMA_release_DREQ (int nchan);
1033 16f62432 bellard
void DMA_schedule(int nchan);
1034 27503323 bellard
void DMA_run (void);
1035 28b9b5af bellard
void DMA_init (int high_page_enable);
1036 27503323 bellard
void DMA_register_channel (int nchan,
1037 85571bc7 bellard
                           DMA_transfer_handler transfer_handler,
1038 85571bc7 bellard
                           void *opaque);
1039 7138fcfb bellard
/* fdc.c */
1040 7138fcfb bellard
#define MAX_FD 2
1041 7138fcfb bellard
extern BlockDriverState *fd_table[MAX_FD];
1042 7138fcfb bellard
1043 baca51fa bellard
typedef struct fdctrl_t fdctrl_t;
1044 baca51fa bellard
1045 5fafdf24 ths
fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1046 5dcb6b91 blueswir1
                       target_phys_addr_t io_base,
1047 baca51fa bellard
                       BlockDriverState **fds);
1048 baca51fa bellard
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1049 7138fcfb bellard
1050 663e8e51 ths
/* eepro100.c */
1051 663e8e51 ths
1052 663e8e51 ths
void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1053 663e8e51 ths
void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1054 663e8e51 ths
void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1055 663e8e51 ths
1056 80cabfad bellard
/* ne2000.c */
1057 80cabfad bellard
1058 d537cf6c pbrook
void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1059 abcebc7e ths
void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1060 80cabfad bellard
1061 a41b2ff2 pbrook
/* rtl8139.c */
1062 a41b2ff2 pbrook
1063 abcebc7e ths
void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1064 a41b2ff2 pbrook
1065 e3c2613f bellard
/* pcnet.c */
1066 e3c2613f bellard
1067 abcebc7e ths
void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1068 70c0de96 blueswir1
void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1069 2d069bab blueswir1
                qemu_irq irq, qemu_irq *reset);
1070 67e999be bellard
1071 6bf5b4e8 ths
/* mipsnet.c */
1072 6bf5b4e8 ths
void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
1073 6bf5b4e8 ths
1074 548df2ac ths
/* vmmouse.c */
1075 548df2ac ths
void *vmmouse_init(void *m);
1076 e3c2613f bellard
1077 591a6d62 ths
/* vmport.c */
1078 591a6d62 ths
#ifdef TARGET_I386
1079 591a6d62 ths
void vmport_init(CPUState *env);
1080 591a6d62 ths
void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
1081 591a6d62 ths
#endif
1082 591a6d62 ths
1083 80cabfad bellard
/* pckbd.c */
1084 80cabfad bellard
1085 b92bb99b ths
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1086 71db710f blueswir1
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
1087 71db710f blueswir1
                   target_phys_addr_t base, int it_shift);
1088 80cabfad bellard
1089 80cabfad bellard
/* mc146818rtc.c */
1090 80cabfad bellard
1091 8a7ddc38 bellard
typedef struct RTCState RTCState;
1092 80cabfad bellard
1093 d537cf6c pbrook
RTCState *rtc_init(int base, qemu_irq irq);
1094 18c6e2ff ths
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
1095 8a7ddc38 bellard
void rtc_set_memory(RTCState *s, int addr, int val);
1096 8a7ddc38 bellard
void rtc_set_date(RTCState *s, const struct tm *tm);
1097 80cabfad bellard
1098 80cabfad bellard
/* serial.c */
1099 80cabfad bellard
1100 c4b1fcc0 bellard
typedef struct SerialState SerialState;
1101 d537cf6c pbrook
SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1102 71db710f blueswir1
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
1103 d537cf6c pbrook
                             qemu_irq irq, CharDriverState *chr,
1104 a4bc3afc ths
                             int ioregister);
1105 a4bc3afc ths
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1106 a4bc3afc ths
void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1107 a4bc3afc ths
uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1108 a4bc3afc ths
void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1109 a4bc3afc ths
uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1110 a4bc3afc ths
void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1111 80cabfad bellard
1112 6508fe59 bellard
/* parallel.c */
1113 6508fe59 bellard
1114 6508fe59 bellard
typedef struct ParallelState ParallelState;
1115 d537cf6c pbrook
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1116 d60532ca ths
ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
1117 6508fe59 bellard
1118 80cabfad bellard
/* i8259.c */
1119 80cabfad bellard
1120 3de388f6 bellard
typedef struct PicState2 PicState2;
1121 3de388f6 bellard
extern PicState2 *isa_pic;
1122 80cabfad bellard
void pic_set_irq(int irq, int level);
1123 54fa5af5 bellard
void pic_set_irq_new(void *opaque, int irq, int level);
1124 d537cf6c pbrook
qemu_irq *i8259_init(qemu_irq parent_irq);
1125 d592d303 bellard
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1126 d592d303 bellard
                          void *alt_irq_opaque);
1127 3de388f6 bellard
int pic_read_irq(PicState2 *s);
1128 3de388f6 bellard
void pic_update_irq(PicState2 *s);
1129 3de388f6 bellard
uint32_t pic_intack_read(PicState2 *s);
1130 c20709aa bellard
void pic_info(void);
1131 4a0fb71e bellard
void irq_info(void);
1132 80cabfad bellard
1133 c27004ec bellard
/* APIC */
1134 d592d303 bellard
typedef struct IOAPICState IOAPICState;
1135 d592d303 bellard
1136 c27004ec bellard
int apic_init(CPUState *env);
1137 0e21e12b ths
int apic_accept_pic_intr(CPUState *env);
1138 c27004ec bellard
int apic_get_interrupt(CPUState *env);
1139 d592d303 bellard
IOAPICState *ioapic_init(void);
1140 d592d303 bellard
void ioapic_set_irq(void *opaque, int vector, int level);
1141 c27004ec bellard
1142 80cabfad bellard
/* i8254.c */
1143 80cabfad bellard
1144 80cabfad bellard
#define PIT_FREQ 1193182
1145 80cabfad bellard
1146 ec844b96 bellard
typedef struct PITState PITState;
1147 ec844b96 bellard
1148 d537cf6c pbrook
PITState *pit_init(int base, qemu_irq irq);
1149 ec844b96 bellard
void pit_set_gate(PITState *pit, int channel, int val);
1150 ec844b96 bellard
int pit_get_gate(PITState *pit, int channel);
1151 fd06c375 bellard
int pit_get_initial_count(PITState *pit, int channel);
1152 fd06c375 bellard
int pit_get_mode(PITState *pit, int channel);
1153 ec844b96 bellard
int pit_get_out(PITState *pit, int channel, int64_t current_time);
1154 80cabfad bellard
1155 31211df1 ths
/* jazz_led.c */
1156 31211df1 ths
extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
1157 31211df1 ths
1158 fd06c375 bellard
/* pcspk.c */
1159 fd06c375 bellard
void pcspk_init(PITState *);
1160 d537cf6c pbrook
int pcspk_audio_init(AudioState *, qemu_irq *pic);
1161 fd06c375 bellard
1162 0ff596d0 pbrook
#include "hw/i2c.h"
1163 0ff596d0 pbrook
1164 3fffc223 ths
#include "hw/smbus.h"
1165 3fffc223 ths
1166 6515b203 bellard
/* acpi.c */
1167 6515b203 bellard
extern int acpi_enabled;
1168 7b717336 ths
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
1169 3fffc223 ths
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1170 6515b203 bellard
void acpi_bios_init(void);
1171 6515b203 bellard
1172 f1ccf904 ths
/* Axis ETRAX.  */
1173 f1ccf904 ths
extern QEMUMachine bareetraxfs_machine;
1174 f1ccf904 ths
1175 80cabfad bellard
/* pc.c */
1176 54fa5af5 bellard
extern QEMUMachine pc_machine;
1177 3dbbdc25 bellard
extern QEMUMachine isapc_machine;
1178 52ca8d6a bellard
extern int fd_bootchk;
1179 80cabfad bellard
1180 6a00d601 bellard
void ioport_set_a20(int enable);
1181 6a00d601 bellard
int ioport_get_a20(void);
1182 6a00d601 bellard
1183 26aa7d72 bellard
/* ppc.c */
1184 54fa5af5 bellard
extern QEMUMachine prep_machine;
1185 54fa5af5 bellard
extern QEMUMachine core99_machine;
1186 54fa5af5 bellard
extern QEMUMachine heathrow_machine;
1187 1a6c0886 j_mayer
extern QEMUMachine ref405ep_machine;
1188 1a6c0886 j_mayer
extern QEMUMachine taihu_machine;
1189 54fa5af5 bellard
1190 6af0bf9c bellard
/* mips_r4k.c */
1191 6af0bf9c bellard
extern QEMUMachine mips_machine;
1192 6af0bf9c bellard
1193 5856de80 ths
/* mips_malta.c */
1194 5856de80 ths
extern QEMUMachine mips_malta_machine;
1195 5856de80 ths
1196 ad6fe1d2 ths
/* mips_pica61.c */
1197 ad6fe1d2 ths
extern QEMUMachine mips_pica61_machine;
1198 ad6fe1d2 ths
1199 6bf5b4e8 ths
/* mips_mipssim.c */
1200 6bf5b4e8 ths
extern QEMUMachine mips_mipssim_machine;
1201 6bf5b4e8 ths
1202 6bf5b4e8 ths
/* mips_int.c */
1203 6bf5b4e8 ths
extern void cpu_mips_irq_init_cpu(CPUState *env);
1204 6bf5b4e8 ths
1205 e16fe40c ths
/* mips_timer.c */
1206 e16fe40c ths
extern void cpu_mips_clock_init(CPUState *);
1207 e16fe40c ths
extern void cpu_mips_irqctrl_init (void);
1208 e16fe40c ths
1209 27c7ca7e bellard
/* shix.c */
1210 27c7ca7e bellard
extern QEMUMachine shix_machine;
1211 27c7ca7e bellard
1212 0d78f544 ths
/* r2d.c */
1213 0d78f544 ths
extern QEMUMachine r2d_machine;
1214 0d78f544 ths
1215 8cc43fef bellard
#ifdef TARGET_PPC
1216 47103572 j_mayer
/* PowerPC hardware exceptions management helpers */
1217 8ecc7913 j_mayer
typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1218 8ecc7913 j_mayer
typedef struct clk_setup_t clk_setup_t;
1219 8ecc7913 j_mayer
struct clk_setup_t {
1220 8ecc7913 j_mayer
    clk_setup_cb cb;
1221 8ecc7913 j_mayer
    void *opaque;
1222 8ecc7913 j_mayer
};
1223 8ecc7913 j_mayer
static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1224 8ecc7913 j_mayer
{
1225 8ecc7913 j_mayer
    if (clk->cb != NULL)
1226 8ecc7913 j_mayer
        (*clk->cb)(clk->opaque, freq);
1227 8ecc7913 j_mayer
}
1228 8ecc7913 j_mayer
1229 8ecc7913 j_mayer
clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1230 2e719ba3 j_mayer
/* Embedded PowerPC DCR management */
1231 2e719ba3 j_mayer
typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1232 2e719ba3 j_mayer
typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1233 2e719ba3 j_mayer
int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1234 2e719ba3 j_mayer
                  int (*dcr_write_error)(int dcrn));
1235 2e719ba3 j_mayer
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1236 2e719ba3 j_mayer
                      dcr_read_cb drc_read, dcr_write_cb dcr_write);
1237 8ecc7913 j_mayer
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1238 4a057712 j_mayer
/* Embedded PowerPC reset */
1239 4a057712 j_mayer
void ppc40x_core_reset (CPUState *env);
1240 4a057712 j_mayer
void ppc40x_chip_reset (CPUState *env);
1241 4a057712 j_mayer
void ppc40x_system_reset (CPUState *env);
1242 8cc43fef bellard
#endif
1243 64201201 bellard
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1244 77d4bc34 bellard
1245 77d4bc34 bellard
extern CPUWriteMemoryFunc *PPC_io_write[];
1246 77d4bc34 bellard
extern CPUReadMemoryFunc *PPC_io_read[];
1247 54fa5af5 bellard
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1248 26aa7d72 bellard
1249 e95c8d51 bellard
/* sun4m.c */
1250 e0353fe2 blueswir1
extern QEMUMachine ss5_machine, ss10_machine;
1251 e95c8d51 bellard
1252 e95c8d51 bellard
/* iommu.c */
1253 5dcb6b91 blueswir1
void *iommu_init(target_phys_addr_t addr);
1254 67e999be bellard
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1255 a917d384 pbrook
                                 uint8_t *buf, int len, int is_write);
1256 67e999be bellard
static inline void sparc_iommu_memory_read(void *opaque,
1257 67e999be bellard
                                           target_phys_addr_t addr,
1258 67e999be bellard
                                           uint8_t *buf, int len)
1259 67e999be bellard
{
1260 67e999be bellard
    sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1261 67e999be bellard
}
1262 e95c8d51 bellard
1263 67e999be bellard
static inline void sparc_iommu_memory_write(void *opaque,
1264 67e999be bellard
                                            target_phys_addr_t addr,
1265 67e999be bellard
                                            uint8_t *buf, int len)
1266 67e999be bellard
{
1267 67e999be bellard
    sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1268 67e999be bellard
}
1269 e95c8d51 bellard
1270 e95c8d51 bellard
/* tcx.c */
1271 5dcb6b91 blueswir1
void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
1272 5dcb6b91 blueswir1
              unsigned long vram_offset, int vram_size, int width, int height,
1273 eee0b836 blueswir1
              int depth);
1274 e80cfcfc bellard
1275 e80cfcfc bellard
/* slavio_intctl.c */
1276 5dcb6b91 blueswir1
void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1277 d537cf6c pbrook
                         const uint32_t *intbit_to_level,
1278 d7edfd27 blueswir1
                         qemu_irq **irq, qemu_irq **cpu_irq,
1279 b3a23197 blueswir1
                         qemu_irq **parent_irq, unsigned int cputimer);
1280 e80cfcfc bellard
void slavio_pic_info(void *opaque);
1281 e80cfcfc bellard
void slavio_irq_info(void *opaque);
1282 e95c8d51 bellard
1283 5fe141fd bellard
/* loader.c */
1284 5fe141fd bellard
int get_image_size(const char *filename);
1285 5fe141fd bellard
int load_image(const char *filename, uint8_t *addr);
1286 74287114 ths
int load_elf(const char *filename, int64_t virt_to_phys_addend,
1287 74287114 ths
             uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1288 e80cfcfc bellard
int load_aout(const char *filename, uint8_t *addr);
1289 1c7b3754 pbrook
int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1290 e80cfcfc bellard
1291 e80cfcfc bellard
/* slavio_timer.c */
1292 81732d19 blueswir1
void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
1293 81732d19 blueswir1
                           qemu_irq *cpu_irqs);
1294 8d5f07fa bellard
1295 e80cfcfc bellard
/* slavio_serial.c */
1296 5dcb6b91 blueswir1
SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
1297 5dcb6b91 blueswir1
                                CharDriverState *chr1, CharDriverState *chr2);
1298 5dcb6b91 blueswir1
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1299 e95c8d51 bellard
1300 3475187d bellard
/* slavio_misc.c */
1301 5dcb6b91 blueswir1
void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
1302 5dcb6b91 blueswir1
                       qemu_irq irq);
1303 3475187d bellard
void slavio_set_power_fail(void *opaque, int power_failing);
1304 3475187d bellard
1305 6f7e9aec bellard
/* esp.c */
1306 fa1fb14c ths
void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1307 5dcb6b91 blueswir1
void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1308 2d069bab blueswir1
               void *dma_opaque, qemu_irq irq, qemu_irq *reset);
1309 67e999be bellard
1310 67e999be bellard
/* sparc32_dma.c */
1311 70c0de96 blueswir1
void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1312 2d069bab blueswir1
                       void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
1313 5fafdf24 ths
void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1314 9b94dc32 bellard
                       uint8_t *buf, int len, int do_bswap);
1315 5fafdf24 ths
void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1316 9b94dc32 bellard
                        uint8_t *buf, int len, int do_bswap);
1317 67e999be bellard
void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1318 67e999be bellard
void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1319 6f7e9aec bellard
1320 b8174937 bellard
/* cs4231.c */
1321 b8174937 bellard
void cs_init(target_phys_addr_t base, int irq, void *intctl);
1322 b8174937 bellard
1323 3475187d bellard
/* sun4u.c */
1324 3475187d bellard
extern QEMUMachine sun4u_machine;
1325 3475187d bellard
1326 64201201 bellard
/* NVRAM helpers */
1327 64201201 bellard
#include "hw/m48t59.h"
1328 64201201 bellard
1329 64201201 bellard
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1330 64201201 bellard
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1331 64201201 bellard
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1332 64201201 bellard
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1333 64201201 bellard
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1334 64201201 bellard
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1335 64201201 bellard
void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1336 64201201 bellard
                       const unsigned char *str, uint32_t max);
1337 64201201 bellard
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1338 64201201 bellard
void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1339 64201201 bellard
                    uint32_t start, uint32_t count);
1340 64201201 bellard
int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1341 64201201 bellard
                          const unsigned char *arch,
1342 64201201 bellard
                          uint32_t RAM_size, int boot_device,
1343 64201201 bellard
                          uint32_t kernel_image, uint32_t kernel_size,
1344 28b9b5af bellard
                          const char *cmdline,
1345 64201201 bellard
                          uint32_t initrd_image, uint32_t initrd_size,
1346 28b9b5af bellard
                          uint32_t NVRAM_image,
1347 28b9b5af bellard
                          int width, int height, int depth);
1348 64201201 bellard
1349 63066f4f bellard
/* adb.c */
1350 63066f4f bellard
1351 63066f4f bellard
#define MAX_ADB_DEVICES 16
1352 63066f4f bellard
1353 e2733d20 bellard
#define ADB_MAX_OUT_LEN 16
1354 63066f4f bellard
1355 e2733d20 bellard
typedef struct ADBDevice ADBDevice;
1356 63066f4f bellard
1357 e2733d20 bellard
/* buf = NULL means polling */
1358 e2733d20 bellard
typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1359 e2733d20 bellard
                              const uint8_t *buf, int len);
1360 12c28fed bellard
typedef int ADBDeviceReset(ADBDevice *d);
1361 12c28fed bellard
1362 63066f4f bellard
struct ADBDevice {
1363 63066f4f bellard
    struct ADBBusState *bus;
1364 63066f4f bellard
    int devaddr;
1365 63066f4f bellard
    int handler;
1366 e2733d20 bellard
    ADBDeviceRequest *devreq;
1367 12c28fed bellard
    ADBDeviceReset *devreset;
1368 63066f4f bellard
    void *opaque;
1369 63066f4f bellard
};
1370 63066f4f bellard
1371 63066f4f bellard
typedef struct ADBBusState {
1372 63066f4f bellard
    ADBDevice devices[MAX_ADB_DEVICES];
1373 63066f4f bellard
    int nb_devices;
1374 e2733d20 bellard
    int poll_index;
1375 63066f4f bellard
} ADBBusState;
1376 63066f4f bellard
1377 e2733d20 bellard
int adb_request(ADBBusState *s, uint8_t *buf_out,
1378 e2733d20 bellard
                const uint8_t *buf, int len);
1379 e2733d20 bellard
int adb_poll(ADBBusState *s, uint8_t *buf_out);
1380 63066f4f bellard
1381 5fafdf24 ths
ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1382 5fafdf24 ths
                               ADBDeviceRequest *devreq,
1383 5fafdf24 ths
                               ADBDeviceReset *devreset,
1384 63066f4f bellard
                               void *opaque);
1385 63066f4f bellard
void adb_kbd_init(ADBBusState *bus);
1386 63066f4f bellard
void adb_mouse_init(ADBBusState *bus);
1387 63066f4f bellard
1388 63066f4f bellard
/* cuda.c */
1389 63066f4f bellard
1390 63066f4f bellard
extern ADBBusState adb_bus;
1391 d537cf6c pbrook
int cuda_init(qemu_irq irq);
1392 63066f4f bellard
1393 bb36d470 bellard
#include "hw/usb.h"
1394 bb36d470 bellard
1395 a594cfbf bellard
/* usb ports of the VM */
1396 a594cfbf bellard
1397 0d92ed30 pbrook
void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1398 0d92ed30 pbrook
                            usb_attachfn attach);
1399 a594cfbf bellard
1400 0d92ed30 pbrook
#define VM_USB_HUB_SIZE 8
1401 a594cfbf bellard
1402 a594cfbf bellard
void do_usb_add(const char *devname);
1403 a594cfbf bellard
void do_usb_del(const char *devname);
1404 a594cfbf bellard
void usb_info(void);
1405 a594cfbf bellard
1406 2e5d83bb pbrook
/* scsi-disk.c */
1407 4d611c9a pbrook
enum scsi_reason {
1408 4d611c9a pbrook
    SCSI_REASON_DONE, /* Command complete.  */
1409 4d611c9a pbrook
    SCSI_REASON_DATA  /* Transfer complete, more data required.  */
1410 4d611c9a pbrook
};
1411 4d611c9a pbrook
1412 2e5d83bb pbrook
typedef struct SCSIDevice SCSIDevice;
1413 a917d384 pbrook
typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1414 a917d384 pbrook
                                  uint32_t arg);
1415 2e5d83bb pbrook
1416 2e5d83bb pbrook
SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1417 a917d384 pbrook
                           int tcq,
1418 2e5d83bb pbrook
                           scsi_completionfn completion,
1419 2e5d83bb pbrook
                           void *opaque);
1420 2e5d83bb pbrook
void scsi_disk_destroy(SCSIDevice *s);
1421 2e5d83bb pbrook
1422 0fc5c15a pbrook
int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1423 4d611c9a pbrook
/* SCSI data transfers are asynchrnonous.  However, unlike the block IO
1424 4d611c9a pbrook
   layer the completion routine may be called directly by
1425 4d611c9a pbrook
   scsi_{read,write}_data.  */
1426 a917d384 pbrook
void scsi_read_data(SCSIDevice *s, uint32_t tag);
1427 a917d384 pbrook
int scsi_write_data(SCSIDevice *s, uint32_t tag);
1428 a917d384 pbrook
void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1429 a917d384 pbrook
uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1430 2e5d83bb pbrook
1431 7d8406be pbrook
/* lsi53c895a.c */
1432 7d8406be pbrook
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1433 7d8406be pbrook
void *lsi_scsi_init(PCIBus *bus, int devfn);
1434 7d8406be pbrook
1435 b5ff1b31 bellard
/* integratorcp.c */
1436 3371d272 pbrook
extern QEMUMachine integratorcp_machine;
1437 b5ff1b31 bellard
1438 cdbdb648 pbrook
/* versatilepb.c */
1439 cdbdb648 pbrook
extern QEMUMachine versatilepb_machine;
1440 16406950 pbrook
extern QEMUMachine versatileab_machine;
1441 cdbdb648 pbrook
1442 e69954b9 pbrook
/* realview.c */
1443 e69954b9 pbrook
extern QEMUMachine realview_machine;
1444 e69954b9 pbrook
1445 b00052e4 balrog
/* spitz.c */
1446 b00052e4 balrog
extern QEMUMachine akitapda_machine;
1447 b00052e4 balrog
extern QEMUMachine spitzpda_machine;
1448 b00052e4 balrog
extern QEMUMachine borzoipda_machine;
1449 b00052e4 balrog
extern QEMUMachine terrierpda_machine;
1450 b00052e4 balrog
1451 c3d2689d balrog
/* palm.c */
1452 c3d2689d balrog
extern QEMUMachine palmte_machine;
1453 c3d2689d balrog
1454 daa57963 bellard
/* ps2.c */
1455 daa57963 bellard
void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1456 daa57963 bellard
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1457 daa57963 bellard
void ps2_write_mouse(void *, int val);
1458 daa57963 bellard
void ps2_write_keyboard(void *, int val);
1459 daa57963 bellard
uint32_t ps2_read_data(void *);
1460 daa57963 bellard
void ps2_queue(void *, int b);
1461 f94f5d71 pbrook
void ps2_keyboard_set_translation(void *opaque, int mode);
1462 548df2ac ths
void ps2_mouse_fake_event(void *opaque);
1463 daa57963 bellard
1464 80337b66 bellard
/* smc91c111.c */
1465 d537cf6c pbrook
void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1466 80337b66 bellard
1467 7e1543c2 pbrook
/* pl031.c */
1468 7e1543c2 pbrook
void pl031_init(uint32_t base, qemu_irq irq);
1469 7e1543c2 pbrook
1470 bdd5003a pbrook
/* pl110.c */
1471 d537cf6c pbrook
void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1472 bdd5003a pbrook
1473 cdbdb648 pbrook
/* pl011.c */
1474 d537cf6c pbrook
void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1475 cdbdb648 pbrook
1476 cdbdb648 pbrook
/* pl050.c */
1477 d537cf6c pbrook
void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1478 cdbdb648 pbrook
1479 cdbdb648 pbrook
/* pl080.c */
1480 d537cf6c pbrook
void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1481 cdbdb648 pbrook
1482 a1bb27b1 pbrook
/* pl181.c */
1483 a1bb27b1 pbrook
void pl181_init(uint32_t base, BlockDriverState *bd,
1484 d537cf6c pbrook
                qemu_irq irq0, qemu_irq irq1);
1485 a1bb27b1 pbrook
1486 cdbdb648 pbrook
/* pl190.c */
1487 d537cf6c pbrook
qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1488 cdbdb648 pbrook
1489 cdbdb648 pbrook
/* arm-timer.c */
1490 d537cf6c pbrook
void sp804_init(uint32_t base, qemu_irq irq);
1491 d537cf6c pbrook
void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1492 cdbdb648 pbrook
1493 e69954b9 pbrook
/* arm_sysctl.c */
1494 e69954b9 pbrook
void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1495 e69954b9 pbrook
1496 e69954b9 pbrook
/* arm_gic.c */
1497 d537cf6c pbrook
qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1498 e69954b9 pbrook
1499 16406950 pbrook
/* arm_boot.c */
1500 16406950 pbrook
1501 daf90626 pbrook
void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1502 16406950 pbrook
                     const char *kernel_cmdline, const char *initrd_filename,
1503 9d551997 balrog
                     int board_id, target_phys_addr_t loader_start);
1504 16406950 pbrook
1505 27c7ca7e bellard
/* sh7750.c */
1506 27c7ca7e bellard
struct SH7750State;
1507 27c7ca7e bellard
1508 008a8818 pbrook
struct SH7750State *sh7750_init(CPUState * cpu);
1509 27c7ca7e bellard
1510 27c7ca7e bellard
typedef struct {
1511 27c7ca7e bellard
    /* The callback will be triggered if any of the designated lines change */
1512 27c7ca7e bellard
    uint16_t portamask_trigger;
1513 27c7ca7e bellard
    uint16_t portbmask_trigger;
1514 27c7ca7e bellard
    /* Return 0 if no action was taken */
1515 27c7ca7e bellard
    int (*port_change_cb) (uint16_t porta, uint16_t portb,
1516 27c7ca7e bellard
                           uint16_t * periph_pdtra,
1517 27c7ca7e bellard
                           uint16_t * periph_portdira,
1518 27c7ca7e bellard
                           uint16_t * periph_pdtrb,
1519 27c7ca7e bellard
                           uint16_t * periph_portdirb);
1520 27c7ca7e bellard
} sh7750_io_device;
1521 27c7ca7e bellard
1522 27c7ca7e bellard
int sh7750_register_io_device(struct SH7750State *s,
1523 27c7ca7e bellard
                              sh7750_io_device * device);
1524 cd1a3f68 ths
/* sh_timer.c */
1525 cd1a3f68 ths
#define TMU012_FEAT_TOCR   (1 << 0)
1526 cd1a3f68 ths
#define TMU012_FEAT_3CHAN  (1 << 1)
1527 cd1a3f68 ths
#define TMU012_FEAT_EXTCLK (1 << 2)
1528 cd1a3f68 ths
void tmu012_init(uint32_t base, int feat, uint32_t freq);
1529 cd1a3f68 ths
1530 2f062c72 ths
/* sh_serial.c */
1531 2f062c72 ths
#define SH_SERIAL_FEAT_SCIF (1 << 0)
1532 2f062c72 ths
void sh_serial_init (target_phys_addr_t base, int feat,
1533 2f062c72 ths
                     uint32_t freq, CharDriverState *chr);
1534 2f062c72 ths
1535 27c7ca7e bellard
/* tc58128.c */
1536 27c7ca7e bellard
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1537 27c7ca7e bellard
1538 29133e9a bellard
/* NOR flash devices */
1539 86f55663 j_mayer
#define MAX_PFLASH 4
1540 86f55663 j_mayer
extern BlockDriverState *pflash_table[MAX_PFLASH];
1541 29133e9a bellard
typedef struct pflash_t pflash_t;
1542 29133e9a bellard
1543 71db710f blueswir1
pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
1544 29133e9a bellard
                           BlockDriverState *bs,
1545 71db710f blueswir1
                           uint32_t sector_len, int nb_blocs, int width,
1546 5fafdf24 ths
                           uint16_t id0, uint16_t id1,
1547 29133e9a bellard
                           uint16_t id2, uint16_t id3);
1548 29133e9a bellard
1549 3e3d5815 balrog
/* nand.c */
1550 3e3d5815 balrog
struct nand_flash_s;
1551 3e3d5815 balrog
struct nand_flash_s *nand_init(int manf_id, int chip_id);
1552 3e3d5815 balrog
void nand_done(struct nand_flash_s *s);
1553 5fafdf24 ths
void nand_setpins(struct nand_flash_s *s,
1554 3e3d5815 balrog
                int cle, int ale, int ce, int wp, int gnd);
1555 3e3d5815 balrog
void nand_getpins(struct nand_flash_s *s, int *rb);
1556 3e3d5815 balrog
void nand_setio(struct nand_flash_s *s, uint8_t value);
1557 3e3d5815 balrog
uint8_t nand_getio(struct nand_flash_s *s);
1558 3e3d5815 balrog
1559 3e3d5815 balrog
#define NAND_MFR_TOSHIBA        0x98
1560 3e3d5815 balrog
#define NAND_MFR_SAMSUNG        0xec
1561 3e3d5815 balrog
#define NAND_MFR_FUJITSU        0x04
1562 3e3d5815 balrog
#define NAND_MFR_NATIONAL        0x8f
1563 3e3d5815 balrog
#define NAND_MFR_RENESAS        0x07
1564 3e3d5815 balrog
#define NAND_MFR_STMICRO        0x20
1565 3e3d5815 balrog
#define NAND_MFR_HYNIX                0xad
1566 3e3d5815 balrog
#define NAND_MFR_MICRON                0x2c
1567 3e3d5815 balrog
1568 9ff6755b balrog
/* ecc.c */
1569 9ff6755b balrog
struct ecc_state_s {
1570 9ff6755b balrog
    uint8_t cp;                /* Column parity */
1571 9ff6755b balrog
    uint16_t lp[2];        /* Line parity */
1572 9ff6755b balrog
    uint16_t count;
1573 9ff6755b balrog
};
1574 9ff6755b balrog
1575 9ff6755b balrog
uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
1576 9ff6755b balrog
void ecc_reset(struct ecc_state_s *s);
1577 9ff6755b balrog
void ecc_put(QEMUFile *f, struct ecc_state_s *s);
1578 9ff6755b balrog
void ecc_get(QEMUFile *f, struct ecc_state_s *s);
1579 3e3d5815 balrog
1580 2a1d1880 balrog
/* GPIO */
1581 2a1d1880 balrog
typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1582 2a1d1880 balrog
1583 fd5a3b33 balrog
/* ads7846.c */
1584 fd5a3b33 balrog
struct ads7846_state_s;
1585 fd5a3b33 balrog
uint32_t ads7846_read(void *opaque);
1586 fd5a3b33 balrog
void ads7846_write(void *opaque, uint32_t value);
1587 fd5a3b33 balrog
struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1588 fd5a3b33 balrog
1589 c824cacd balrog
/* max111x.c */
1590 c824cacd balrog
struct max111x_s;
1591 c824cacd balrog
uint32_t max111x_read(void *opaque);
1592 c824cacd balrog
void max111x_write(void *opaque, uint32_t value);
1593 c824cacd balrog
struct max111x_s *max1110_init(qemu_irq cb);
1594 c824cacd balrog
struct max111x_s *max1111_init(qemu_irq cb);
1595 c824cacd balrog
void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1596 c824cacd balrog
1597 201a51fc balrog
/* PCMCIA/Cardbus */
1598 201a51fc balrog
1599 201a51fc balrog
struct pcmcia_socket_s {
1600 201a51fc balrog
    qemu_irq irq;
1601 201a51fc balrog
    int attached;
1602 201a51fc balrog
    const char *slot_string;
1603 201a51fc balrog
    const char *card_string;
1604 201a51fc balrog
};
1605 201a51fc balrog
1606 201a51fc balrog
void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1607 201a51fc balrog
void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1608 201a51fc balrog
void pcmcia_info(void);
1609 201a51fc balrog
1610 201a51fc balrog
struct pcmcia_card_s {
1611 201a51fc balrog
    void *state;
1612 201a51fc balrog
    struct pcmcia_socket_s *slot;
1613 201a51fc balrog
    int (*attach)(void *state);
1614 201a51fc balrog
    int (*detach)(void *state);
1615 201a51fc balrog
    const uint8_t *cis;
1616 201a51fc balrog
    int cis_len;
1617 201a51fc balrog
1618 201a51fc balrog
    /* Only valid if attached */
1619 9e315fa9 balrog
    uint8_t (*attr_read)(void *state, uint32_t address);
1620 9e315fa9 balrog
    void (*attr_write)(void *state, uint32_t address, uint8_t value);
1621 9e315fa9 balrog
    uint16_t (*common_read)(void *state, uint32_t address);
1622 9e315fa9 balrog
    void (*common_write)(void *state, uint32_t address, uint16_t value);
1623 9e315fa9 balrog
    uint16_t (*io_read)(void *state, uint32_t address);
1624 9e315fa9 balrog
    void (*io_write)(void *state, uint32_t address, uint16_t value);
1625 201a51fc balrog
};
1626 201a51fc balrog
1627 201a51fc balrog
#define CISTPL_DEVICE                0x01        /* 5V Device Information Tuple */
1628 201a51fc balrog
#define CISTPL_NO_LINK                0x14        /* No Link Tuple */
1629 201a51fc balrog
#define CISTPL_VERS_1                0x15        /* Level 1 Version Tuple */
1630 201a51fc balrog
#define CISTPL_JEDEC_C                0x18        /* JEDEC ID Tuple */
1631 201a51fc balrog
#define CISTPL_JEDEC_A                0x19        /* JEDEC ID Tuple */
1632 201a51fc balrog
#define CISTPL_CONFIG                0x1a        /* Configuration Tuple */
1633 201a51fc balrog
#define CISTPL_CFTABLE_ENTRY        0x1b        /* 16-bit PCCard Configuration */
1634 201a51fc balrog
#define CISTPL_DEVICE_OC        0x1c        /* Additional Device Information */
1635 201a51fc balrog
#define CISTPL_DEVICE_OA        0x1d        /* Additional Device Information */
1636 201a51fc balrog
#define CISTPL_DEVICE_GEO        0x1e        /* Additional Device Information */
1637 201a51fc balrog
#define CISTPL_DEVICE_GEO_A        0x1f        /* Additional Device Information */
1638 201a51fc balrog
#define CISTPL_MANFID                0x20        /* Manufacture ID Tuple */
1639 201a51fc balrog
#define CISTPL_FUNCID                0x21        /* Function ID Tuple */
1640 201a51fc balrog
#define CISTPL_FUNCE                0x22        /* Function Extension Tuple */
1641 201a51fc balrog
#define CISTPL_END                0xff        /* Tuple End */
1642 201a51fc balrog
#define CISTPL_ENDMARK                0xff
1643 201a51fc balrog
1644 201a51fc balrog
/* dscm1xxxx.c */
1645 201a51fc balrog
struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1646 201a51fc balrog
1647 6963d7af pbrook
/* ptimer.c */
1648 6963d7af pbrook
typedef struct ptimer_state ptimer_state;
1649 6963d7af pbrook
typedef void (*ptimer_cb)(void *opaque);
1650 6963d7af pbrook
1651 6963d7af pbrook
ptimer_state *ptimer_init(QEMUBH *bh);
1652 6963d7af pbrook
void ptimer_set_period(ptimer_state *s, int64_t period);
1653 6963d7af pbrook
void ptimer_set_freq(ptimer_state *s, uint32_t freq);
1654 8d05ea8a blueswir1
void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
1655 8d05ea8a blueswir1
uint64_t ptimer_get_count(ptimer_state *s);
1656 8d05ea8a blueswir1
void ptimer_set_count(ptimer_state *s, uint64_t count);
1657 6963d7af pbrook
void ptimer_run(ptimer_state *s, int oneshot);
1658 6963d7af pbrook
void ptimer_stop(ptimer_state *s);
1659 8d05ea8a blueswir1
void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
1660 8d05ea8a blueswir1
void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
1661 6963d7af pbrook
1662 c1713132 balrog
#include "hw/pxa.h"
1663 c1713132 balrog
1664 c3d2689d balrog
#include "hw/omap.h"
1665 c3d2689d balrog
1666 20dcee94 pbrook
/* mcf_uart.c */
1667 20dcee94 pbrook
uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
1668 20dcee94 pbrook
void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
1669 20dcee94 pbrook
void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
1670 20dcee94 pbrook
void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
1671 20dcee94 pbrook
                      CharDriverState *chr);
1672 20dcee94 pbrook
1673 20dcee94 pbrook
/* mcf_intc.c */
1674 20dcee94 pbrook
qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
1675 20dcee94 pbrook
1676 7e049b8a pbrook
/* mcf_fec.c */
1677 7e049b8a pbrook
void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
1678 7e049b8a pbrook
1679 0633879f pbrook
/* mcf5206.c */
1680 0633879f pbrook
qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
1681 0633879f pbrook
1682 0633879f pbrook
/* an5206.c */
1683 0633879f pbrook
extern QEMUMachine an5206_machine;
1684 0633879f pbrook
1685 20dcee94 pbrook
/* mcf5208.c */
1686 20dcee94 pbrook
extern QEMUMachine mcf5208evb_machine;
1687 20dcee94 pbrook
1688 4046d913 pbrook
#include "gdbstub.h"
1689 4046d913 pbrook
1690 ea2384d3 bellard
#endif /* defined(QEMU_TOOL) */
1691 ea2384d3 bellard
1692 c4b1fcc0 bellard
/* monitor.c */
1693 82c643ff bellard
void monitor_init(CharDriverState *hd, int show_banner);
1694 ea2384d3 bellard
void term_puts(const char *str);
1695 ea2384d3 bellard
void term_vprintf(const char *fmt, va_list ap);
1696 40c3bac3 bellard
void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1697 fef30743 ths
void term_print_filename(const char *filename);
1698 c4b1fcc0 bellard
void term_flush(void);
1699 c4b1fcc0 bellard
void term_print_help(void);
1700 ea2384d3 bellard
void monitor_readline(const char *prompt, int is_password,
1701 ea2384d3 bellard
                      char *buf, int buf_size);
1702 ea2384d3 bellard
1703 ea2384d3 bellard
/* readline.c */
1704 ea2384d3 bellard
typedef void ReadLineFunc(void *opaque, const char *str);
1705 ea2384d3 bellard
1706 ea2384d3 bellard
extern int completion_index;
1707 ea2384d3 bellard
void add_completion(const char *str);
1708 ea2384d3 bellard
void readline_handle_byte(int ch);
1709 ea2384d3 bellard
void readline_find_completion(const char *cmdline);
1710 ea2384d3 bellard
const char *readline_get_history(unsigned int index);
1711 ea2384d3 bellard
void readline_start(const char *prompt, int is_password,
1712 ea2384d3 bellard
                    ReadLineFunc *readline_func, void *opaque);
1713 c4b1fcc0 bellard
1714 5e6ad6f9 bellard
void kqemu_record_dump(void);
1715 5e6ad6f9 bellard
1716 fc01f7e7 bellard
#endif /* VL_H */