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1 | 2055283b | Peter Maydell | /*
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2 | 2055283b | Peter Maydell | * ARM Versatile Express emulation.
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3 | 2055283b | Peter Maydell | *
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4 | 2055283b | Peter Maydell | * Copyright (c) 2010 - 2011 B Labs Ltd.
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5 | 2055283b | Peter Maydell | * Copyright (c) 2011 Linaro Limited
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6 | 2055283b | Peter Maydell | * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
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7 | 2055283b | Peter Maydell | *
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8 | 2055283b | Peter Maydell | * This program is free software; you can redistribute it and/or modify
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9 | 2055283b | Peter Maydell | * it under the terms of the GNU General Public License version 2 as
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10 | 2055283b | Peter Maydell | * published by the Free Software Foundation.
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11 | 2055283b | Peter Maydell | *
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12 | 2055283b | Peter Maydell | * This program is distributed in the hope that it will be useful,
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13 | 2055283b | Peter Maydell | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 2055283b | Peter Maydell | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | 2055283b | Peter Maydell | * GNU General Public License for more details.
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16 | 2055283b | Peter Maydell | *
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17 | 2055283b | Peter Maydell | * You should have received a copy of the GNU General Public License along
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18 | 2055283b | Peter Maydell | * with this program; if not, see <http://www.gnu.org/licenses/>.
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19 | 6b620ca3 | Paolo Bonzini | *
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20 | 6b620ca3 | Paolo Bonzini | * Contributions after 2012-01-13 are licensed under the terms of the
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21 | 6b620ca3 | Paolo Bonzini | * GNU GPL, version 2 or (at your option) any later version.
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22 | 2055283b | Peter Maydell | */
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23 | 2055283b | Peter Maydell | |
24 | 2055283b | Peter Maydell | #include "sysbus.h" |
25 | 2055283b | Peter Maydell | #include "arm-misc.h" |
26 | 2055283b | Peter Maydell | #include "primecell.h" |
27 | 2055283b | Peter Maydell | #include "devices.h" |
28 | 2055283b | Peter Maydell | #include "net.h" |
29 | 2055283b | Peter Maydell | #include "sysemu.h" |
30 | 2055283b | Peter Maydell | #include "boards.h" |
31 | e6d17b05 | Avi Kivity | #include "exec-memory.h" |
32 | 2055283b | Peter Maydell | |
33 | 2055283b | Peter Maydell | #define VEXPRESS_BOARD_ID 0x8e0 |
34 | 2055283b | Peter Maydell | |
35 | aac1e02c | Peter Maydell | static struct arm_boot_info vexpress_binfo; |
36 | 2558e0a6 | Peter Maydell | |
37 | 2558e0a6 | Peter Maydell | /* Address maps for peripherals:
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38 | 2558e0a6 | Peter Maydell | * the Versatile Express motherboard has two possible maps,
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39 | 2558e0a6 | Peter Maydell | * the "legacy" one (used for A9) and the "Cortex-A Series"
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40 | 2558e0a6 | Peter Maydell | * map (used for newer cores).
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41 | 2558e0a6 | Peter Maydell | * Individual daughterboards can also have different maps for
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42 | 2558e0a6 | Peter Maydell | * their peripherals.
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43 | 2558e0a6 | Peter Maydell | */
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44 | 2558e0a6 | Peter Maydell | |
45 | 2558e0a6 | Peter Maydell | enum {
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46 | 2558e0a6 | Peter Maydell | VE_SYSREGS, |
47 | 2558e0a6 | Peter Maydell | VE_SP810, |
48 | 2558e0a6 | Peter Maydell | VE_SERIALPCI, |
49 | 2558e0a6 | Peter Maydell | VE_PL041, |
50 | 2558e0a6 | Peter Maydell | VE_MMCI, |
51 | 2558e0a6 | Peter Maydell | VE_KMI0, |
52 | 2558e0a6 | Peter Maydell | VE_KMI1, |
53 | 2558e0a6 | Peter Maydell | VE_UART0, |
54 | 2558e0a6 | Peter Maydell | VE_UART1, |
55 | 2558e0a6 | Peter Maydell | VE_UART2, |
56 | 2558e0a6 | Peter Maydell | VE_UART3, |
57 | 2558e0a6 | Peter Maydell | VE_WDT, |
58 | 2558e0a6 | Peter Maydell | VE_TIMER01, |
59 | 2558e0a6 | Peter Maydell | VE_TIMER23, |
60 | 2558e0a6 | Peter Maydell | VE_SERIALDVI, |
61 | 2558e0a6 | Peter Maydell | VE_RTC, |
62 | 2558e0a6 | Peter Maydell | VE_COMPACTFLASH, |
63 | 2558e0a6 | Peter Maydell | VE_CLCD, |
64 | 2558e0a6 | Peter Maydell | VE_NORFLASH0, |
65 | 2558e0a6 | Peter Maydell | VE_NORFLASH0ALIAS, |
66 | 2558e0a6 | Peter Maydell | VE_NORFLASH1, |
67 | 2558e0a6 | Peter Maydell | VE_SRAM, |
68 | 2558e0a6 | Peter Maydell | VE_VIDEORAM, |
69 | 2558e0a6 | Peter Maydell | VE_ETHERNET, |
70 | 2558e0a6 | Peter Maydell | VE_USB, |
71 | 2558e0a6 | Peter Maydell | VE_DAPROM, |
72 | 2558e0a6 | Peter Maydell | }; |
73 | 2558e0a6 | Peter Maydell | |
74 | 2558e0a6 | Peter Maydell | static target_phys_addr_t motherboard_legacy_map[] = {
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75 | 2558e0a6 | Peter Maydell | /* CS7: 0x10000000 .. 0x10020000 */
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76 | 2558e0a6 | Peter Maydell | [VE_SYSREGS] = 0x10000000,
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77 | 2558e0a6 | Peter Maydell | [VE_SP810] = 0x10001000,
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78 | 2558e0a6 | Peter Maydell | [VE_SERIALPCI] = 0x10002000,
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79 | 2558e0a6 | Peter Maydell | [VE_PL041] = 0x10004000,
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80 | 2558e0a6 | Peter Maydell | [VE_MMCI] = 0x10005000,
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81 | 2558e0a6 | Peter Maydell | [VE_KMI0] = 0x10006000,
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82 | 2558e0a6 | Peter Maydell | [VE_KMI1] = 0x10007000,
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83 | 2558e0a6 | Peter Maydell | [VE_UART0] = 0x10009000,
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84 | 2558e0a6 | Peter Maydell | [VE_UART1] = 0x1000a000,
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85 | 2558e0a6 | Peter Maydell | [VE_UART2] = 0x1000b000,
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86 | 2558e0a6 | Peter Maydell | [VE_UART3] = 0x1000c000,
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87 | 2558e0a6 | Peter Maydell | [VE_WDT] = 0x1000f000,
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88 | 2558e0a6 | Peter Maydell | [VE_TIMER01] = 0x10011000,
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89 | 2558e0a6 | Peter Maydell | [VE_TIMER23] = 0x10012000,
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90 | 2558e0a6 | Peter Maydell | [VE_SERIALDVI] = 0x10016000,
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91 | 2558e0a6 | Peter Maydell | [VE_RTC] = 0x10017000,
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92 | 2558e0a6 | Peter Maydell | [VE_COMPACTFLASH] = 0x1001a000,
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93 | 2558e0a6 | Peter Maydell | [VE_CLCD] = 0x1001f000,
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94 | 2558e0a6 | Peter Maydell | /* CS0: 0x40000000 .. 0x44000000 */
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95 | 2558e0a6 | Peter Maydell | [VE_NORFLASH0] = 0x40000000,
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96 | 2558e0a6 | Peter Maydell | /* CS1: 0x44000000 .. 0x48000000 */
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97 | 2558e0a6 | Peter Maydell | [VE_NORFLASH1] = 0x44000000,
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98 | 2558e0a6 | Peter Maydell | /* CS2: 0x48000000 .. 0x4a000000 */
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99 | 2558e0a6 | Peter Maydell | [VE_SRAM] = 0x48000000,
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100 | 2558e0a6 | Peter Maydell | /* CS3: 0x4c000000 .. 0x50000000 */
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101 | 2558e0a6 | Peter Maydell | [VE_VIDEORAM] = 0x4c000000,
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102 | 2558e0a6 | Peter Maydell | [VE_ETHERNET] = 0x4e000000,
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103 | 2558e0a6 | Peter Maydell | [VE_USB] = 0x4f000000,
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104 | 2055283b | Peter Maydell | }; |
105 | 2055283b | Peter Maydell | |
106 | 961f195e | Peter Maydell | static target_phys_addr_t motherboard_aseries_map[] = {
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107 | 961f195e | Peter Maydell | /* CS0: 0x00000000 .. 0x0c000000 */
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108 | 961f195e | Peter Maydell | [VE_NORFLASH0] = 0x00000000,
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109 | 961f195e | Peter Maydell | [VE_NORFLASH0ALIAS] = 0x08000000,
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110 | 961f195e | Peter Maydell | /* CS4: 0x0c000000 .. 0x10000000 */
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111 | 961f195e | Peter Maydell | [VE_NORFLASH1] = 0x0c000000,
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112 | 961f195e | Peter Maydell | /* CS5: 0x10000000 .. 0x14000000 */
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113 | 961f195e | Peter Maydell | /* CS1: 0x14000000 .. 0x18000000 */
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114 | 961f195e | Peter Maydell | [VE_SRAM] = 0x14000000,
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115 | 961f195e | Peter Maydell | /* CS2: 0x18000000 .. 0x1c000000 */
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116 | 961f195e | Peter Maydell | [VE_VIDEORAM] = 0x18000000,
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117 | 961f195e | Peter Maydell | [VE_ETHERNET] = 0x1a000000,
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118 | 961f195e | Peter Maydell | [VE_USB] = 0x1b000000,
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119 | 961f195e | Peter Maydell | /* CS3: 0x1c000000 .. 0x20000000 */
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120 | 961f195e | Peter Maydell | [VE_DAPROM] = 0x1c000000,
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121 | 961f195e | Peter Maydell | [VE_SYSREGS] = 0x1c010000,
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122 | 961f195e | Peter Maydell | [VE_SP810] = 0x1c020000,
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123 | 961f195e | Peter Maydell | [VE_SERIALPCI] = 0x1c030000,
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124 | 961f195e | Peter Maydell | [VE_PL041] = 0x1c040000,
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125 | 961f195e | Peter Maydell | [VE_MMCI] = 0x1c050000,
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126 | 961f195e | Peter Maydell | [VE_KMI0] = 0x1c060000,
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127 | 961f195e | Peter Maydell | [VE_KMI1] = 0x1c070000,
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128 | 961f195e | Peter Maydell | [VE_UART0] = 0x1c090000,
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129 | 961f195e | Peter Maydell | [VE_UART1] = 0x1c0a0000,
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130 | 961f195e | Peter Maydell | [VE_UART2] = 0x1c0b0000,
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131 | 961f195e | Peter Maydell | [VE_UART3] = 0x1c0c0000,
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132 | 961f195e | Peter Maydell | [VE_WDT] = 0x1c0f0000,
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133 | 961f195e | Peter Maydell | [VE_TIMER01] = 0x1c110000,
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134 | 961f195e | Peter Maydell | [VE_TIMER23] = 0x1c120000,
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135 | 961f195e | Peter Maydell | [VE_SERIALDVI] = 0x1c160000,
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136 | 961f195e | Peter Maydell | [VE_RTC] = 0x1c170000,
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137 | 961f195e | Peter Maydell | [VE_COMPACTFLASH] = 0x1c1a0000,
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138 | 961f195e | Peter Maydell | [VE_CLCD] = 0x1c1f0000,
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139 | 961f195e | Peter Maydell | }; |
140 | 961f195e | Peter Maydell | |
141 | 4c3b29b8 | Peter Maydell | /* Structure defining the peculiarities of a specific daughterboard */
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142 | 4c3b29b8 | Peter Maydell | |
143 | 4c3b29b8 | Peter Maydell | typedef struct VEDBoardInfo VEDBoardInfo; |
144 | 4c3b29b8 | Peter Maydell | |
145 | 4c3b29b8 | Peter Maydell | typedef void DBoardInitFn(const VEDBoardInfo *daughterboard, |
146 | 4c3b29b8 | Peter Maydell | ram_addr_t ram_size, |
147 | 4c3b29b8 | Peter Maydell | const char *cpu_model, |
148 | 4c3b29b8 | Peter Maydell | qemu_irq *pic, uint32_t *proc_id); |
149 | 4c3b29b8 | Peter Maydell | |
150 | 4c3b29b8 | Peter Maydell | struct VEDBoardInfo {
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151 | 4c3b29b8 | Peter Maydell | const target_phys_addr_t *motherboard_map;
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152 | 4c3b29b8 | Peter Maydell | target_phys_addr_t loader_start; |
153 | 96eacf64 | Peter Maydell | const target_phys_addr_t gic_cpu_if_addr;
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154 | 4c3b29b8 | Peter Maydell | DBoardInitFn *init; |
155 | 4c3b29b8 | Peter Maydell | }; |
156 | 4c3b29b8 | Peter Maydell | |
157 | 4c3b29b8 | Peter Maydell | static void a9_daughterboard_init(const VEDBoardInfo *daughterboard, |
158 | 4c3b29b8 | Peter Maydell | ram_addr_t ram_size, |
159 | 4c3b29b8 | Peter Maydell | const char *cpu_model, |
160 | 4c3b29b8 | Peter Maydell | qemu_irq *pic, uint32_t *proc_id) |
161 | 2055283b | Peter Maydell | { |
162 | 5ae93306 | Andreas Fรคrber | CPUARMState *env = NULL;
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163 | e6d17b05 | Avi Kivity | MemoryRegion *sysmem = get_system_memory(); |
164 | e6d17b05 | Avi Kivity | MemoryRegion *ram = g_new(MemoryRegion, 1);
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165 | e6d17b05 | Avi Kivity | MemoryRegion *lowram = g_new(MemoryRegion, 1);
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166 | 4c3b29b8 | Peter Maydell | DeviceState *dev; |
167 | 2055283b | Peter Maydell | SysBusDevice *busdev; |
168 | 2055283b | Peter Maydell | qemu_irq *irqp; |
169 | 2055283b | Peter Maydell | int n;
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170 | 2055283b | Peter Maydell | qemu_irq cpu_irq[4];
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171 | 4c3b29b8 | Peter Maydell | ram_addr_t low_ram_size; |
172 | 2055283b | Peter Maydell | |
173 | 2055283b | Peter Maydell | if (!cpu_model) {
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174 | 2055283b | Peter Maydell | cpu_model = "cortex-a9";
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175 | 2055283b | Peter Maydell | } |
176 | 2055283b | Peter Maydell | |
177 | 4c3b29b8 | Peter Maydell | *proc_id = 0x0c000191;
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178 | 4c3b29b8 | Peter Maydell | |
179 | 2055283b | Peter Maydell | for (n = 0; n < smp_cpus; n++) { |
180 | 2055283b | Peter Maydell | env = cpu_init(cpu_model); |
181 | 2055283b | Peter Maydell | if (!env) {
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182 | 2055283b | Peter Maydell | fprintf(stderr, "Unable to find CPU definition\n");
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183 | 2055283b | Peter Maydell | exit(1);
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184 | 2055283b | Peter Maydell | } |
185 | 2055283b | Peter Maydell | irqp = arm_pic_init_cpu(env); |
186 | 2055283b | Peter Maydell | cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; |
187 | 2055283b | Peter Maydell | } |
188 | 2055283b | Peter Maydell | |
189 | 2055283b | Peter Maydell | if (ram_size > 0x40000000) { |
190 | 2055283b | Peter Maydell | /* 1GB is the maximum the address space permits */
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191 | 4c3b29b8 | Peter Maydell | fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n");
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192 | 2055283b | Peter Maydell | exit(1);
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193 | 2055283b | Peter Maydell | } |
194 | 2055283b | Peter Maydell | |
195 | c5705a77 | Avi Kivity | memory_region_init_ram(ram, "vexpress.highmem", ram_size);
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196 | c5705a77 | Avi Kivity | vmstate_register_ram_global(ram); |
197 | 2055283b | Peter Maydell | low_ram_size = ram_size; |
198 | 2055283b | Peter Maydell | if (low_ram_size > 0x4000000) { |
199 | 2055283b | Peter Maydell | low_ram_size = 0x4000000;
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200 | 2055283b | Peter Maydell | } |
201 | 2055283b | Peter Maydell | /* RAM is from 0x60000000 upwards. The bottom 64MB of the
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202 | 2055283b | Peter Maydell | * address space should in theory be remappable to various
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203 | 2055283b | Peter Maydell | * things including ROM or RAM; we always map the RAM there.
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204 | 2055283b | Peter Maydell | */
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205 | e6d17b05 | Avi Kivity | memory_region_init_alias(lowram, "vexpress.lowmem", ram, 0, low_ram_size); |
206 | e6d17b05 | Avi Kivity | memory_region_add_subregion(sysmem, 0x0, lowram);
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207 | e6d17b05 | Avi Kivity | memory_region_add_subregion(sysmem, 0x60000000, ram);
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208 | 2055283b | Peter Maydell | |
209 | 2055283b | Peter Maydell | /* 0x1e000000 A9MPCore (SCU) private memory region */
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210 | 2055283b | Peter Maydell | dev = qdev_create(NULL, "a9mpcore_priv"); |
211 | 2055283b | Peter Maydell | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
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212 | 2055283b | Peter Maydell | qdev_init_nofail(dev); |
213 | 2055283b | Peter Maydell | busdev = sysbus_from_qdev(dev); |
214 | 96eacf64 | Peter Maydell | sysbus_mmio_map(busdev, 0, 0x1e000000); |
215 | 2055283b | Peter Maydell | for (n = 0; n < smp_cpus; n++) { |
216 | 2055283b | Peter Maydell | sysbus_connect_irq(busdev, n, cpu_irq[n]); |
217 | 2055283b | Peter Maydell | } |
218 | 2055283b | Peter Maydell | /* Interrupts [42:0] are from the motherboard;
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219 | 2055283b | Peter Maydell | * [47:43] are reserved; [63:48] are daughterboard
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220 | 2055283b | Peter Maydell | * peripherals. Note that some documentation numbers
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221 | 2055283b | Peter Maydell | * external interrupts starting from 32 (because the
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222 | 2055283b | Peter Maydell | * A9MP has internal interrupts 0..31).
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223 | 2055283b | Peter Maydell | */
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224 | 2055283b | Peter Maydell | for (n = 0; n < 64; n++) { |
225 | 2055283b | Peter Maydell | pic[n] = qdev_get_gpio_in(dev, n); |
226 | 2055283b | Peter Maydell | } |
227 | 2055283b | Peter Maydell | |
228 | 4c3b29b8 | Peter Maydell | /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
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229 | 4c3b29b8 | Peter Maydell | |
230 | 4c3b29b8 | Peter Maydell | /* 0x10020000 PL111 CLCD (daughterboard) */
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231 | 4c3b29b8 | Peter Maydell | sysbus_create_simple("pl111", 0x10020000, pic[44]); |
232 | 4c3b29b8 | Peter Maydell | |
233 | 4c3b29b8 | Peter Maydell | /* 0x10060000 AXI RAM */
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234 | 4c3b29b8 | Peter Maydell | /* 0x100e0000 PL341 Dynamic Memory Controller */
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235 | 4c3b29b8 | Peter Maydell | /* 0x100e1000 PL354 Static Memory Controller */
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236 | 4c3b29b8 | Peter Maydell | /* 0x100e2000 System Configuration Controller */
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237 | 4c3b29b8 | Peter Maydell | |
238 | 4c3b29b8 | Peter Maydell | sysbus_create_simple("sp804", 0x100e4000, pic[48]); |
239 | 4c3b29b8 | Peter Maydell | /* 0x100e5000 SP805 Watchdog module */
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240 | 4c3b29b8 | Peter Maydell | /* 0x100e6000 BP147 TrustZone Protection Controller */
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241 | 4c3b29b8 | Peter Maydell | /* 0x100e9000 PL301 'Fast' AXI matrix */
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242 | 4c3b29b8 | Peter Maydell | /* 0x100ea000 PL301 'Slow' AXI matrix */
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243 | 4c3b29b8 | Peter Maydell | /* 0x100ec000 TrustZone Address Space Controller */
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244 | 4c3b29b8 | Peter Maydell | /* 0x10200000 CoreSight debug APB */
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245 | 4c3b29b8 | Peter Maydell | /* 0x1e00a000 PL310 L2 Cache Controller */
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246 | 4c3b29b8 | Peter Maydell | sysbus_create_varargs("l2x0", 0x1e00a000, NULL); |
247 | 4c3b29b8 | Peter Maydell | } |
248 | 4c3b29b8 | Peter Maydell | |
249 | 4c3b29b8 | Peter Maydell | static const VEDBoardInfo a9_daughterboard = { |
250 | 4c3b29b8 | Peter Maydell | .motherboard_map = motherboard_legacy_map, |
251 | 4c3b29b8 | Peter Maydell | .loader_start = 0x60000000,
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252 | 96eacf64 | Peter Maydell | .gic_cpu_if_addr = 0x1e000100,
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253 | 4c3b29b8 | Peter Maydell | .init = a9_daughterboard_init, |
254 | 4c3b29b8 | Peter Maydell | }; |
255 | 4c3b29b8 | Peter Maydell | |
256 | 961f195e | Peter Maydell | static void a15_daughterboard_init(const VEDBoardInfo *daughterboard, |
257 | 961f195e | Peter Maydell | ram_addr_t ram_size, |
258 | 961f195e | Peter Maydell | const char *cpu_model, |
259 | 961f195e | Peter Maydell | qemu_irq *pic, uint32_t *proc_id) |
260 | 961f195e | Peter Maydell | { |
261 | 961f195e | Peter Maydell | int n;
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262 | 5ae93306 | Andreas Fรคrber | CPUARMState *env = NULL;
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263 | 961f195e | Peter Maydell | MemoryRegion *sysmem = get_system_memory(); |
264 | 961f195e | Peter Maydell | MemoryRegion *ram = g_new(MemoryRegion, 1);
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265 | 961f195e | Peter Maydell | MemoryRegion *sram = g_new(MemoryRegion, 1);
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266 | 961f195e | Peter Maydell | qemu_irq cpu_irq[4];
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267 | 961f195e | Peter Maydell | DeviceState *dev; |
268 | 961f195e | Peter Maydell | SysBusDevice *busdev; |
269 | 961f195e | Peter Maydell | |
270 | 961f195e | Peter Maydell | if (!cpu_model) {
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271 | 961f195e | Peter Maydell | cpu_model = "cortex-a15";
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272 | 961f195e | Peter Maydell | } |
273 | 961f195e | Peter Maydell | |
274 | 961f195e | Peter Maydell | *proc_id = 0x14000217;
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275 | 961f195e | Peter Maydell | |
276 | 961f195e | Peter Maydell | for (n = 0; n < smp_cpus; n++) { |
277 | 961f195e | Peter Maydell | qemu_irq *irqp; |
278 | 961f195e | Peter Maydell | env = cpu_init(cpu_model); |
279 | 961f195e | Peter Maydell | if (!env) {
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280 | 961f195e | Peter Maydell | fprintf(stderr, "Unable to find CPU definition\n");
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281 | 961f195e | Peter Maydell | exit(1);
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282 | 961f195e | Peter Maydell | } |
283 | 961f195e | Peter Maydell | irqp = arm_pic_init_cpu(env); |
284 | 961f195e | Peter Maydell | cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; |
285 | 961f195e | Peter Maydell | } |
286 | 961f195e | Peter Maydell | |
287 | 961f195e | Peter Maydell | if (ram_size > 0x80000000) { |
288 | 961f195e | Peter Maydell | fprintf(stderr, "vexpress-a15: cannot model more than 2GB RAM\n");
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289 | 961f195e | Peter Maydell | exit(1);
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290 | 961f195e | Peter Maydell | } |
291 | 961f195e | Peter Maydell | |
292 | 961f195e | Peter Maydell | memory_region_init_ram(ram, "vexpress.highmem", ram_size);
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293 | 961f195e | Peter Maydell | vmstate_register_ram_global(ram); |
294 | 961f195e | Peter Maydell | /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
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295 | 961f195e | Peter Maydell | memory_region_add_subregion(sysmem, 0x80000000, ram);
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296 | 961f195e | Peter Maydell | |
297 | 961f195e | Peter Maydell | /* 0x2c000000 A15MPCore private memory region (GIC) */
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298 | 961f195e | Peter Maydell | dev = qdev_create(NULL, "a15mpcore_priv"); |
299 | 961f195e | Peter Maydell | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
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300 | 961f195e | Peter Maydell | qdev_init_nofail(dev); |
301 | 961f195e | Peter Maydell | busdev = sysbus_from_qdev(dev); |
302 | 961f195e | Peter Maydell | sysbus_mmio_map(busdev, 0, 0x2c000000); |
303 | 961f195e | Peter Maydell | for (n = 0; n < smp_cpus; n++) { |
304 | 961f195e | Peter Maydell | sysbus_connect_irq(busdev, n, cpu_irq[n]); |
305 | 961f195e | Peter Maydell | } |
306 | 961f195e | Peter Maydell | /* Interrupts [42:0] are from the motherboard;
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307 | 961f195e | Peter Maydell | * [47:43] are reserved; [63:48] are daughterboard
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308 | 961f195e | Peter Maydell | * peripherals. Note that some documentation numbers
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309 | 961f195e | Peter Maydell | * external interrupts starting from 32 (because there
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310 | 961f195e | Peter Maydell | * are internal interrupts 0..31).
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311 | 961f195e | Peter Maydell | */
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312 | 961f195e | Peter Maydell | for (n = 0; n < 64; n++) { |
313 | 961f195e | Peter Maydell | pic[n] = qdev_get_gpio_in(dev, n); |
314 | 961f195e | Peter Maydell | } |
315 | 961f195e | Peter Maydell | |
316 | 961f195e | Peter Maydell | /* A15 daughterboard peripherals: */
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317 | 961f195e | Peter Maydell | |
318 | 961f195e | Peter Maydell | /* 0x20000000: CoreSight interfaces: not modelled */
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319 | 961f195e | Peter Maydell | /* 0x2a000000: PL301 AXI interconnect: not modelled */
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320 | 961f195e | Peter Maydell | /* 0x2a420000: SCC: not modelled */
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321 | 961f195e | Peter Maydell | /* 0x2a430000: system counter: not modelled */
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322 | 961f195e | Peter Maydell | /* 0x2b000000: HDLCD controller: not modelled */
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323 | 961f195e | Peter Maydell | /* 0x2b060000: SP805 watchdog: not modelled */
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324 | 961f195e | Peter Maydell | /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
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325 | 961f195e | Peter Maydell | /* 0x2e000000: system SRAM */
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326 | 961f195e | Peter Maydell | memory_region_init_ram(sram, "vexpress.a15sram", 0x10000); |
327 | 961f195e | Peter Maydell | vmstate_register_ram_global(sram); |
328 | 961f195e | Peter Maydell | memory_region_add_subregion(sysmem, 0x2e000000, sram);
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329 | 961f195e | Peter Maydell | |
330 | 961f195e | Peter Maydell | /* 0x7ffb0000: DMA330 DMA controller: not modelled */
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331 | 961f195e | Peter Maydell | /* 0x7ffd0000: PL354 static memory controller: not modelled */
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332 | 961f195e | Peter Maydell | } |
333 | 961f195e | Peter Maydell | |
334 | 961f195e | Peter Maydell | static const VEDBoardInfo a15_daughterboard = { |
335 | 961f195e | Peter Maydell | .motherboard_map = motherboard_aseries_map, |
336 | 961f195e | Peter Maydell | .loader_start = 0x80000000,
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337 | 961f195e | Peter Maydell | .gic_cpu_if_addr = 0x2c002000,
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338 | 961f195e | Peter Maydell | .init = a15_daughterboard_init, |
339 | 961f195e | Peter Maydell | }; |
340 | 961f195e | Peter Maydell | |
341 | 4c3b29b8 | Peter Maydell | static void vexpress_common_init(const VEDBoardInfo *daughterboard, |
342 | 4c3b29b8 | Peter Maydell | ram_addr_t ram_size, |
343 | 4c3b29b8 | Peter Maydell | const char *boot_device, |
344 | 4c3b29b8 | Peter Maydell | const char *kernel_filename, |
345 | 4c3b29b8 | Peter Maydell | const char *kernel_cmdline, |
346 | 4c3b29b8 | Peter Maydell | const char *initrd_filename, |
347 | 4c3b29b8 | Peter Maydell | const char *cpu_model) |
348 | 4c3b29b8 | Peter Maydell | { |
349 | 4c3b29b8 | Peter Maydell | DeviceState *dev, *sysctl, *pl041; |
350 | 4c3b29b8 | Peter Maydell | qemu_irq pic[64];
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351 | 4c3b29b8 | Peter Maydell | uint32_t proc_id; |
352 | 4c3b29b8 | Peter Maydell | uint32_t sys_id; |
353 | 4c3b29b8 | Peter Maydell | ram_addr_t vram_size, sram_size; |
354 | 4c3b29b8 | Peter Maydell | MemoryRegion *sysmem = get_system_memory(); |
355 | 4c3b29b8 | Peter Maydell | MemoryRegion *vram = g_new(MemoryRegion, 1);
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356 | 4c3b29b8 | Peter Maydell | MemoryRegion *sram = g_new(MemoryRegion, 1);
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357 | 4c3b29b8 | Peter Maydell | const target_phys_addr_t *map = daughterboard->motherboard_map;
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358 | 4c3b29b8 | Peter Maydell | |
359 | 4c3b29b8 | Peter Maydell | daughterboard->init(daughterboard, ram_size, cpu_model, pic, &proc_id); |
360 | 4c3b29b8 | Peter Maydell | |
361 | 2558e0a6 | Peter Maydell | /* Motherboard peripherals: the wiring is the same but the
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362 | 2558e0a6 | Peter Maydell | * addresses vary between the legacy and A-Series memory maps.
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363 | 2558e0a6 | Peter Maydell | */
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364 | 2558e0a6 | Peter Maydell | |
365 | 2055283b | Peter Maydell | sys_id = 0x1190f500;
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366 | 2055283b | Peter Maydell | |
367 | 2055283b | Peter Maydell | sysctl = qdev_create(NULL, "realview_sysctl"); |
368 | 2055283b | Peter Maydell | qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
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369 | 2055283b | Peter Maydell | qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
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370 | 7a65c8cc | Peter Maydell | qdev_init_nofail(sysctl); |
371 | 2558e0a6 | Peter Maydell | sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, map[VE_SYSREGS]);
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372 | 2558e0a6 | Peter Maydell | |
373 | 2558e0a6 | Peter Maydell | /* VE_SP810: not modelled */
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374 | 2558e0a6 | Peter Maydell | /* VE_SERIALPCI: not modelled */
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375 | 2055283b | Peter Maydell | |
376 | 03a0e944 | Peter Maydell | pl041 = qdev_create(NULL, "pl041"); |
377 | 03a0e944 | Peter Maydell | qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); |
378 | 03a0e944 | Peter Maydell | qdev_init_nofail(pl041); |
379 | 2558e0a6 | Peter Maydell | sysbus_mmio_map(sysbus_from_qdev(pl041), 0, map[VE_PL041]);
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380 | 03a0e944 | Peter Maydell | sysbus_connect_irq(sysbus_from_qdev(pl041), 0, pic[11]); |
381 | 2055283b | Peter Maydell | |
382 | 2558e0a6 | Peter Maydell | dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); |
383 | 2055283b | Peter Maydell | /* Wire up MMC card detect and read-only signals */
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384 | 2055283b | Peter Maydell | qdev_connect_gpio_out(dev, 0,
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385 | 2055283b | Peter Maydell | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); |
386 | 2055283b | Peter Maydell | qdev_connect_gpio_out(dev, 1,
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387 | 2055283b | Peter Maydell | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); |
388 | 2055283b | Peter Maydell | |
389 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); |
390 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); |
391 | 2055283b | Peter Maydell | |
392 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl011", map[VE_UART0], pic[5]); |
393 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl011", map[VE_UART1], pic[6]); |
394 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl011", map[VE_UART2], pic[7]); |
395 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl011", map[VE_UART3], pic[8]); |
396 | 2055283b | Peter Maydell | |
397 | 2558e0a6 | Peter Maydell | sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); |
398 | 2558e0a6 | Peter Maydell | sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); |
399 | 2055283b | Peter Maydell | |
400 | 2558e0a6 | Peter Maydell | /* VE_SERIALDVI: not modelled */
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401 | 2055283b | Peter Maydell | |
402 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ |
403 | 2055283b | Peter Maydell | |
404 | 2558e0a6 | Peter Maydell | /* VE_COMPACTFLASH: not modelled */
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405 | 2055283b | Peter Maydell | |
406 | b7206878 | Peter Maydell | sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); |
407 | 2055283b | Peter Maydell | |
408 | 2558e0a6 | Peter Maydell | /* VE_NORFLASH0: not modelled */
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409 | 2558e0a6 | Peter Maydell | /* VE_NORFLASH0ALIAS: not modelled */
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410 | 2558e0a6 | Peter Maydell | /* VE_NORFLASH1: not modelled */
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411 | 2558e0a6 | Peter Maydell | |
412 | 2055283b | Peter Maydell | sram_size = 0x2000000;
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413 | c5705a77 | Avi Kivity | memory_region_init_ram(sram, "vexpress.sram", sram_size);
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414 | c5705a77 | Avi Kivity | vmstate_register_ram_global(sram); |
415 | 2558e0a6 | Peter Maydell | memory_region_add_subregion(sysmem, map[VE_SRAM], sram); |
416 | 2055283b | Peter Maydell | |
417 | 2055283b | Peter Maydell | vram_size = 0x800000;
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418 | c5705a77 | Avi Kivity | memory_region_init_ram(vram, "vexpress.vram", vram_size);
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419 | c5705a77 | Avi Kivity | vmstate_register_ram_global(vram); |
420 | 2558e0a6 | Peter Maydell | memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); |
421 | 2055283b | Peter Maydell | |
422 | 2055283b | Peter Maydell | /* 0x4e000000 LAN9118 Ethernet */
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423 | 2055283b | Peter Maydell | if (nd_table[0].vlan) { |
424 | 2558e0a6 | Peter Maydell | lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); |
425 | 2055283b | Peter Maydell | } |
426 | 2055283b | Peter Maydell | |
427 | 2558e0a6 | Peter Maydell | /* VE_USB: not modelled */
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428 | 2558e0a6 | Peter Maydell | |
429 | 2558e0a6 | Peter Maydell | /* VE_DAPROM: not modelled */
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430 | 2055283b | Peter Maydell | |
431 | 2055283b | Peter Maydell | vexpress_binfo.ram_size = ram_size; |
432 | 2055283b | Peter Maydell | vexpress_binfo.kernel_filename = kernel_filename; |
433 | 2055283b | Peter Maydell | vexpress_binfo.kernel_cmdline = kernel_cmdline; |
434 | 2055283b | Peter Maydell | vexpress_binfo.initrd_filename = initrd_filename; |
435 | 2055283b | Peter Maydell | vexpress_binfo.nb_cpus = smp_cpus; |
436 | 2055283b | Peter Maydell | vexpress_binfo.board_id = VEXPRESS_BOARD_ID; |
437 | 4c3b29b8 | Peter Maydell | vexpress_binfo.loader_start = daughterboard->loader_start; |
438 | aac1e02c | Peter Maydell | vexpress_binfo.smp_loader_start = map[VE_SRAM]; |
439 | 2558e0a6 | Peter Maydell | vexpress_binfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
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440 | 96eacf64 | Peter Maydell | vexpress_binfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; |
441 | 2055283b | Peter Maydell | arm_load_kernel(first_cpu, &vexpress_binfo); |
442 | 2055283b | Peter Maydell | } |
443 | 2055283b | Peter Maydell | |
444 | 4c3b29b8 | Peter Maydell | static void vexpress_a9_init(ram_addr_t ram_size, |
445 | 4c3b29b8 | Peter Maydell | const char *boot_device, |
446 | 4c3b29b8 | Peter Maydell | const char *kernel_filename, |
447 | 4c3b29b8 | Peter Maydell | const char *kernel_cmdline, |
448 | 4c3b29b8 | Peter Maydell | const char *initrd_filename, |
449 | 4c3b29b8 | Peter Maydell | const char *cpu_model) |
450 | 4c3b29b8 | Peter Maydell | { |
451 | 4c3b29b8 | Peter Maydell | vexpress_common_init(&a9_daughterboard, |
452 | 4c3b29b8 | Peter Maydell | ram_size, boot_device, kernel_filename, |
453 | 4c3b29b8 | Peter Maydell | kernel_cmdline, initrd_filename, cpu_model); |
454 | 4c3b29b8 | Peter Maydell | } |
455 | 2055283b | Peter Maydell | |
456 | 961f195e | Peter Maydell | static void vexpress_a15_init(ram_addr_t ram_size, |
457 | 961f195e | Peter Maydell | const char *boot_device, |
458 | 961f195e | Peter Maydell | const char *kernel_filename, |
459 | 961f195e | Peter Maydell | const char *kernel_cmdline, |
460 | 961f195e | Peter Maydell | const char *initrd_filename, |
461 | 961f195e | Peter Maydell | const char *cpu_model) |
462 | 961f195e | Peter Maydell | { |
463 | 961f195e | Peter Maydell | vexpress_common_init(&a15_daughterboard, |
464 | 961f195e | Peter Maydell | ram_size, boot_device, kernel_filename, |
465 | 961f195e | Peter Maydell | kernel_cmdline, initrd_filename, cpu_model); |
466 | 961f195e | Peter Maydell | } |
467 | 961f195e | Peter Maydell | |
468 | 2055283b | Peter Maydell | static QEMUMachine vexpress_a9_machine = {
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469 | 2055283b | Peter Maydell | .name = "vexpress-a9",
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470 | 2055283b | Peter Maydell | .desc = "ARM Versatile Express for Cortex-A9",
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471 | 2055283b | Peter Maydell | .init = vexpress_a9_init, |
472 | 2055283b | Peter Maydell | .use_scsi = 1,
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473 | 2055283b | Peter Maydell | .max_cpus = 4,
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474 | 2055283b | Peter Maydell | }; |
475 | 2055283b | Peter Maydell | |
476 | 961f195e | Peter Maydell | static QEMUMachine vexpress_a15_machine = {
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477 | 961f195e | Peter Maydell | .name = "vexpress-a15",
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478 | 961f195e | Peter Maydell | .desc = "ARM Versatile Express for Cortex-A15",
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479 | 961f195e | Peter Maydell | .init = vexpress_a15_init, |
480 | 961f195e | Peter Maydell | .use_scsi = 1,
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481 | 961f195e | Peter Maydell | .max_cpus = 4,
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482 | 961f195e | Peter Maydell | }; |
483 | 961f195e | Peter Maydell | |
484 | 2055283b | Peter Maydell | static void vexpress_machine_init(void) |
485 | 2055283b | Peter Maydell | { |
486 | 2055283b | Peter Maydell | qemu_register_machine(&vexpress_a9_machine); |
487 | 961f195e | Peter Maydell | qemu_register_machine(&vexpress_a15_machine); |
488 | 2055283b | Peter Maydell | } |
489 | 2055283b | Peter Maydell | |
490 | 2055283b | Peter Maydell | machine_init(vexpress_machine_init); |