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/*
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* QEMU Ultrasparc APB PCI host
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/* XXX This file and most of its contents are somewhat misnamed. The
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Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
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the secondary PCI bridge. */
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#include "sysbus.h" |
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#include "pci.h" |
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#include "pci_host.h" |
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#include "pci_bridge.h" |
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#include "pci_internals.h" |
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#include "apb_pci.h" |
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#include "sysemu.h" |
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#include "exec-memory.h" |
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/* debug APB */
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//#define DEBUG_APB
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#ifdef DEBUG_APB
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#define APB_DPRINTF(fmt, ...) \
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do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define APB_DPRINTF(fmt, ...)
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#endif
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/*
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* Chipset docs:
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* PBM: "UltraSPARC IIi User's Manual",
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* http://www.sun.com/processors/manuals/805-0087.pdf
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*
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* APB: "Advanced PCI Bridge (APB) User's Manual",
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* http://www.sun.com/processors/manuals/805-1251.pdf
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*/
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#define PBM_PCI_IMR_MASK 0x7fffffff |
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#define PBM_PCI_IMR_ENABLED 0x80000000 |
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#define POR (1 << 31) |
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#define SOFT_POR (1 << 30) |
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#define SOFT_XIR (1 << 29) |
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#define BTN_POR (1 << 28) |
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#define BTN_XIR (1 << 27) |
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#define RESET_MASK 0xf8000000 |
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#define RESET_WCMASK 0x98000000 |
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#define RESET_WMASK 0x60000000 |
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#define MAX_IVEC 0x30 |
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typedef struct APBState { |
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SysBusDevice busdev; |
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PCIBus *bus; |
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MemoryRegion apb_config; |
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MemoryRegion pci_config; |
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MemoryRegion pci_mmio; |
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MemoryRegion pci_ioport; |
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uint32_t iommu[4];
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uint32_t pci_control[16];
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uint32_t pci_irq_map[8];
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uint32_t obio_irq_map[32];
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qemu_irq *pbm_irqs; |
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qemu_irq *ivec_irqs; |
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uint32_t reset_control; |
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unsigned int nr_resets; |
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} APBState; |
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static void pci_apb_set_irq(void *opaque, int irq_num, int level); |
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static void apb_config_writel (void *opaque, target_phys_addr_t addr, |
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uint64_t val, unsigned size)
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{ |
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APBState *s = opaque; |
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %" PRIx64 "\n", __func__, addr, val); |
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switch (addr & 0xffff) { |
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case 0x30 ... 0x4f: /* DMA error registers */ |
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/* XXX: not implemented yet */
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break;
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case 0x200 ... 0x20b: /* IOMMU */ |
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s->iommu[(addr & 0xf) >> 2] = val; |
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break;
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case 0x20c ... 0x3ff: /* IOMMU flush */ |
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break;
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case 0xc00 ... 0xc3f: /* PCI interrupt control */ |
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if (addr & 4) { |
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s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK; |
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s->pci_irq_map[(addr & 0x3f) >> 3] |= val & ~PBM_PCI_IMR_MASK; |
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} |
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break;
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case 0x1000 ... 0x1080: /* OBIO interrupt control */ |
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if (addr & 4) { |
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s->obio_irq_map[(addr & 0xff) >> 3] &= PBM_PCI_IMR_MASK; |
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s->obio_irq_map[(addr & 0xff) >> 3] |= val & ~PBM_PCI_IMR_MASK; |
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} |
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break;
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case 0x1400 ... 0x143f: /* PCI interrupt clear */ |
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if (addr & 4) { |
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pci_apb_set_irq(s, (addr & 0x3f) >> 3, 0); |
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} |
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break;
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case 0x1800 ... 0x1860: /* OBIO interrupt clear */ |
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if (addr & 4) { |
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pci_apb_set_irq(s, 0x20 | ((addr & 0xff) >> 3), 0); |
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} |
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break;
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case 0x2000 ... 0x202f: /* PCI control */ |
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s->pci_control[(addr & 0x3f) >> 2] = val; |
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break;
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case 0xf020 ... 0xf027: /* Reset control */ |
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if (addr & 4) { |
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val &= RESET_MASK; |
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s->reset_control &= ~(val & RESET_WCMASK); |
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s->reset_control |= val & RESET_WMASK; |
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if (val & SOFT_POR) {
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s->nr_resets = 0;
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qemu_system_reset_request(); |
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} else if (val & SOFT_XIR) { |
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qemu_system_reset_request(); |
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} |
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} |
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break;
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case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */ |
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case 0xa400 ... 0xa67f: /* IOMMU diagnostics */ |
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case 0xa800 ... 0xa80f: /* Interrupt diagnostics */ |
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case 0xf000 ... 0xf01f: /* FFB config, memory control */ |
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/* we don't care */
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default:
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break;
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} |
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} |
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static uint64_t apb_config_readl (void *opaque, |
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target_phys_addr_t addr, unsigned size)
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{ |
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APBState *s = opaque; |
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uint32_t val; |
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switch (addr & 0xffff) { |
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case 0x30 ... 0x4f: /* DMA error registers */ |
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val = 0;
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/* XXX: not implemented yet */
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break;
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case 0x200 ... 0x20b: /* IOMMU */ |
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val = s->iommu[(addr & 0xf) >> 2]; |
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break;
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case 0x20c ... 0x3ff: /* IOMMU flush */ |
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val = 0;
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break;
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case 0xc00 ... 0xc3f: /* PCI interrupt control */ |
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if (addr & 4) { |
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val = s->pci_irq_map[(addr & 0x3f) >> 3]; |
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} else {
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val = 0;
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} |
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break;
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case 0x1000 ... 0x1080: /* OBIO interrupt control */ |
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if (addr & 4) { |
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val = s->obio_irq_map[(addr & 0xff) >> 3]; |
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} else {
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val = 0;
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} |
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break;
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case 0x2000 ... 0x202f: /* PCI control */ |
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val = s->pci_control[(addr & 0x3f) >> 2]; |
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break;
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case 0xf020 ... 0xf027: /* Reset control */ |
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if (addr & 4) { |
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val = s->reset_control; |
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} else {
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val = 0;
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} |
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break;
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case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */ |
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case 0xa400 ... 0xa67f: /* IOMMU diagnostics */ |
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case 0xa800 ... 0xa80f: /* Interrupt diagnostics */ |
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case 0xf000 ... 0xf01f: /* FFB config, memory control */ |
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/* we don't care */
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default:
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val = 0;
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break;
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} |
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val); |
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return val;
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} |
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static const MemoryRegionOps apb_config_ops = { |
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.read = apb_config_readl, |
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.write = apb_config_writel, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
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static void apb_pci_config_write(void *opaque, target_phys_addr_t addr, |
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uint64_t val, unsigned size)
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{ |
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APBState *s = opaque; |
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val = qemu_bswap_len(val, size); |
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %" PRIx64 "\n", __func__, addr, val); |
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pci_data_write(s->bus, addr, val, size); |
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} |
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static uint64_t apb_pci_config_read(void *opaque, target_phys_addr_t addr, |
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unsigned size)
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{ |
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uint32_t ret; |
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APBState *s = opaque; |
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ret = pci_data_read(s->bus, addr, size); |
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ret = qemu_bswap_len(ret, size); |
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret); |
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return ret;
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} |
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static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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cpu_outb(addr & IOPORTS_MASK, val); |
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} |
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static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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cpu_outw(addr & IOPORTS_MASK, bswap16(val)); |
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} |
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static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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cpu_outl(addr & IOPORTS_MASK, bswap32(val)); |
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} |
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static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr) |
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{ |
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uint32_t val; |
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val = cpu_inb(addr & IOPORTS_MASK); |
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return val;
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} |
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static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr) |
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{ |
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uint32_t val; |
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val = bswap16(cpu_inw(addr & IOPORTS_MASK)); |
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return val;
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} |
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static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr) |
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{ |
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uint32_t val; |
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val = bswap32(cpu_inl(addr & IOPORTS_MASK)); |
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return val;
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} |
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static const MemoryRegionOps pci_ioport_ops = { |
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.old_mmio = { |
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.read = { pci_apb_ioreadb, pci_apb_ioreadw, pci_apb_ioreadl }, |
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.write = { pci_apb_iowriteb, pci_apb_iowritew, pci_apb_iowritel, }, |
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}, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
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/* The APB host has an IRQ line for each IRQ line of each slot. */
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static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num) |
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{ |
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return ((pci_dev->devfn & 0x18) >> 1) + irq_num; |
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} |
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static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num) |
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{ |
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int bus_offset;
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if (pci_dev->devfn & 1) |
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bus_offset = 16;
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else
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bus_offset = 0;
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return bus_offset + irq_num;
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} |
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static void pci_apb_set_irq(void *opaque, int irq_num, int level) |
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{ |
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APBState *s = opaque; |
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/* PCI IRQ map onto the first 32 INO. */
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if (irq_num < 32) { |
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if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) { |
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APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
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qemu_set_irq(s->ivec_irqs[irq_num], level); |
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} else {
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APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
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qemu_irq_lower(s->ivec_irqs[irq_num]); |
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} |
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} else {
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/* OBIO IRQ map onto the next 16 INO. */
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if (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED) { |
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APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
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qemu_set_irq(s->ivec_irqs[irq_num], level); |
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} else {
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APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
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qemu_irq_lower(s->ivec_irqs[irq_num]); |
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} |
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} |
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} |
327 |
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static int apb_pci_bridge_initfn(PCIDevice *dev) |
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{ |
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int rc;
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rc = pci_bridge_initfn(dev); |
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if (rc < 0) { |
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return rc;
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} |
336 |
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/*
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* command register:
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* According to PCI bridge spec, after reset
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* bus master bit is off
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* memory space enable bit is off
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* According to manual (805-1251.pdf).
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* the reset value should be zero unless the boot pin is tied high
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* (which is true) and thus it should be PCI_COMMAND_MEMORY.
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*/
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pci_set_word(dev->config + PCI_COMMAND, |
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PCI_COMMAND_MEMORY); |
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pci_set_word(dev->config + PCI_STATUS, |
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PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | |
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PCI_STATUS_DEVSEL_MEDIUM); |
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return 0; |
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} |
353 |
|
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PCIBus *pci_apb_init(target_phys_addr_t special_base, |
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target_phys_addr_t mem_base, |
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qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3, |
357 |
qemu_irq **pbm_irqs) |
358 |
{ |
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DeviceState *dev; |
360 |
SysBusDevice *s; |
361 |
APBState *d; |
362 |
PCIDevice *pci_dev; |
363 |
PCIBridge *br; |
364 |
|
365 |
/* Ultrasparc PBM main bus */
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dev = qdev_create(NULL, "pbm"); |
367 |
qdev_init_nofail(dev); |
368 |
s = sysbus_from_qdev(dev); |
369 |
/* apb_config */
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370 |
sysbus_mmio_map(s, 0, special_base);
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371 |
/* PCI configuration space */
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372 |
sysbus_mmio_map(s, 1, special_base + 0x1000000ULL); |
373 |
/* pci_ioport */
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374 |
sysbus_mmio_map(s, 2, special_base + 0x2000000ULL); |
375 |
d = FROM_SYSBUS(APBState, s); |
376 |
|
377 |
memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL); |
378 |
memory_region_add_subregion(get_system_memory(), mem_base, &d->pci_mmio); |
379 |
|
380 |
d->bus = pci_register_bus(&d->busdev.qdev, "pci",
|
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pci_apb_set_irq, pci_pbm_map_irq, d, |
382 |
&d->pci_mmio, |
383 |
get_system_io(), |
384 |
0, 32); |
385 |
|
386 |
*pbm_irqs = d->pbm_irqs; |
387 |
d->ivec_irqs = ivec_irqs; |
388 |
|
389 |
pci_create_simple(d->bus, 0, "pbm-pci"); |
390 |
|
391 |
/* APB secondary busses */
|
392 |
pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 0), true, |
393 |
"pbm-bridge");
|
394 |
br = DO_UPCAST(PCIBridge, dev, pci_dev); |
395 |
pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
|
396 |
pci_apb_map_irq); |
397 |
qdev_init_nofail(&pci_dev->qdev); |
398 |
*bus2 = pci_bridge_get_sec_bus(br); |
399 |
|
400 |
pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 1), true, |
401 |
"pbm-bridge");
|
402 |
br = DO_UPCAST(PCIBridge, dev, pci_dev); |
403 |
pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
|
404 |
pci_apb_map_irq); |
405 |
qdev_init_nofail(&pci_dev->qdev); |
406 |
*bus3 = pci_bridge_get_sec_bus(br); |
407 |
|
408 |
return d->bus;
|
409 |
} |
410 |
|
411 |
static void pci_pbm_reset(DeviceState *d) |
412 |
{ |
413 |
unsigned int i; |
414 |
APBState *s = container_of(d, APBState, busdev.qdev); |
415 |
|
416 |
for (i = 0; i < 8; i++) { |
417 |
s->pci_irq_map[i] &= PBM_PCI_IMR_MASK; |
418 |
} |
419 |
for (i = 0; i < 32; i++) { |
420 |
s->obio_irq_map[i] &= PBM_PCI_IMR_MASK; |
421 |
} |
422 |
|
423 |
if (s->nr_resets++ == 0) { |
424 |
/* Power on reset */
|
425 |
s->reset_control = POR; |
426 |
} |
427 |
} |
428 |
|
429 |
static const MemoryRegionOps pci_config_ops = { |
430 |
.read = apb_pci_config_read, |
431 |
.write = apb_pci_config_write, |
432 |
.endianness = DEVICE_NATIVE_ENDIAN, |
433 |
}; |
434 |
|
435 |
static int pci_pbm_init_device(SysBusDevice *dev) |
436 |
{ |
437 |
APBState *s; |
438 |
unsigned int i; |
439 |
|
440 |
s = FROM_SYSBUS(APBState, dev); |
441 |
for (i = 0; i < 8; i++) { |
442 |
s->pci_irq_map[i] = (0x1f << 6) | (i << 2); |
443 |
} |
444 |
for (i = 0; i < 32; i++) { |
445 |
s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i; |
446 |
} |
447 |
s->pbm_irqs = qemu_allocate_irqs(pci_apb_set_irq, s, MAX_IVEC); |
448 |
|
449 |
/* apb_config */
|
450 |
memory_region_init_io(&s->apb_config, &apb_config_ops, s, "apb-config",
|
451 |
0x10000);
|
452 |
/* at region 0 */
|
453 |
sysbus_init_mmio(dev, &s->apb_config); |
454 |
|
455 |
memory_region_init_io(&s->pci_config, &pci_config_ops, s, "apb-pci-config",
|
456 |
0x1000000);
|
457 |
/* at region 1 */
|
458 |
sysbus_init_mmio(dev, &s->pci_config); |
459 |
|
460 |
/* pci_ioport */
|
461 |
memory_region_init_io(&s->pci_ioport, &pci_ioport_ops, s, |
462 |
"apb-pci-ioport", 0x10000); |
463 |
/* at region 2 */
|
464 |
sysbus_init_mmio(dev, &s->pci_ioport); |
465 |
|
466 |
return 0; |
467 |
} |
468 |
|
469 |
static int pbm_pci_host_init(PCIDevice *d) |
470 |
{ |
471 |
pci_set_word(d->config + PCI_COMMAND, |
472 |
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
473 |
pci_set_word(d->config + PCI_STATUS, |
474 |
PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | |
475 |
PCI_STATUS_DEVSEL_MEDIUM); |
476 |
return 0; |
477 |
} |
478 |
|
479 |
static void pbm_pci_host_class_init(ObjectClass *klass, void *data) |
480 |
{ |
481 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
482 |
|
483 |
k->init = pbm_pci_host_init; |
484 |
k->vendor_id = PCI_VENDOR_ID_SUN; |
485 |
k->device_id = PCI_DEVICE_ID_SUN_SABRE; |
486 |
k->class_id = PCI_CLASS_BRIDGE_HOST; |
487 |
} |
488 |
|
489 |
static TypeInfo pbm_pci_host_info = {
|
490 |
.name = "pbm-pci",
|
491 |
.parent = TYPE_PCI_DEVICE, |
492 |
.instance_size = sizeof(PCIDevice),
|
493 |
.class_init = pbm_pci_host_class_init, |
494 |
}; |
495 |
|
496 |
static void pbm_host_class_init(ObjectClass *klass, void *data) |
497 |
{ |
498 |
DeviceClass *dc = DEVICE_CLASS(klass); |
499 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
500 |
|
501 |
k->init = pci_pbm_init_device; |
502 |
dc->reset = pci_pbm_reset; |
503 |
} |
504 |
|
505 |
static TypeInfo pbm_host_info = {
|
506 |
.name = "pbm",
|
507 |
.parent = TYPE_SYS_BUS_DEVICE, |
508 |
.instance_size = sizeof(APBState),
|
509 |
.class_init = pbm_host_class_init, |
510 |
}; |
511 |
|
512 |
static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data) |
513 |
{ |
514 |
DeviceClass *dc = DEVICE_CLASS(klass); |
515 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
516 |
|
517 |
k->init = apb_pci_bridge_initfn; |
518 |
k->exit = pci_bridge_exitfn; |
519 |
k->vendor_id = PCI_VENDOR_ID_SUN; |
520 |
k->device_id = PCI_DEVICE_ID_SUN_SIMBA; |
521 |
k->revision = 0x11;
|
522 |
k->config_write = pci_bridge_write_config; |
523 |
k->is_bridge = 1;
|
524 |
dc->reset = pci_bridge_reset; |
525 |
dc->vmsd = &vmstate_pci_device; |
526 |
} |
527 |
|
528 |
static TypeInfo pbm_pci_bridge_info = {
|
529 |
.name = "pbm-bridge",
|
530 |
.parent = TYPE_PCI_DEVICE, |
531 |
.instance_size = sizeof(PCIBridge),
|
532 |
.class_init = pbm_pci_bridge_class_init, |
533 |
}; |
534 |
|
535 |
static void pbm_register_types(void) |
536 |
{ |
537 |
type_register_static(&pbm_host_info); |
538 |
type_register_static(&pbm_pci_host_info); |
539 |
type_register_static(&pbm_pci_bridge_info); |
540 |
} |
541 |
|
542 |
type_init(pbm_register_types) |