root / hw / arm_gic_internal.h @ fa2ddcb4
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1 | 1e8cae4d | Peter Maydell | /*
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2 | 1e8cae4d | Peter Maydell | * ARM GIC support - internal interfaces
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3 | 1e8cae4d | Peter Maydell | *
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4 | 1e8cae4d | Peter Maydell | * Copyright (c) 2012 Linaro Limited
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5 | 1e8cae4d | Peter Maydell | * Written by Peter Maydell
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6 | 1e8cae4d | Peter Maydell | *
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7 | 1e8cae4d | Peter Maydell | * This program is free software; you can redistribute it and/or modify
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8 | 1e8cae4d | Peter Maydell | * it under the terms of the GNU General Public License as published by
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9 | 1e8cae4d | Peter Maydell | * the Free Software Foundation, either version 2 of the License, or
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10 | 1e8cae4d | Peter Maydell | * (at your option) any later version.
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11 | 1e8cae4d | Peter Maydell | *
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12 | 1e8cae4d | Peter Maydell | * This program is distributed in the hope that it will be useful,
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13 | 1e8cae4d | Peter Maydell | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 1e8cae4d | Peter Maydell | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | 1e8cae4d | Peter Maydell | * GNU General Public License for more details.
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16 | 1e8cae4d | Peter Maydell | *
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17 | 1e8cae4d | Peter Maydell | * You should have received a copy of the GNU General Public License along
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18 | 1e8cae4d | Peter Maydell | * with this program; if not, see <http://www.gnu.org/licenses/>.
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19 | 1e8cae4d | Peter Maydell | */
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20 | 1e8cae4d | Peter Maydell | |
21 | 1e8cae4d | Peter Maydell | #ifndef QEMU_ARM_GIC_INTERNAL_H
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22 | 1e8cae4d | Peter Maydell | #define QEMU_ARM_GIC_INTERNAL_H
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23 | 1e8cae4d | Peter Maydell | |
24 | 1e8cae4d | Peter Maydell | #include "sysbus.h" |
25 | 1e8cae4d | Peter Maydell | |
26 | 1e8cae4d | Peter Maydell | /* Maximum number of possible interrupts, determined by the GIC architecture */
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27 | 1e8cae4d | Peter Maydell | #define GIC_MAXIRQ 1020 |
28 | 1e8cae4d | Peter Maydell | /* First 32 are private to each CPU (SGIs and PPIs). */
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29 | 1e8cae4d | Peter Maydell | #define GIC_INTERNAL 32 |
30 | 1e8cae4d | Peter Maydell | /* Maximum number of possible CPU interfaces, determined by GIC architecture */
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31 | 1e8cae4d | Peter Maydell | #define NCPU 8 |
32 | 1e8cae4d | Peter Maydell | |
33 | 1e8cae4d | Peter Maydell | #define ALL_CPU_MASK ((unsigned)(((1 << NCPU) - 1))) |
34 | 1e8cae4d | Peter Maydell | |
35 | 1e8cae4d | Peter Maydell | /* The NVIC has 16 internal vectors. However these are not exposed
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36 | 1e8cae4d | Peter Maydell | through the normal GIC interface. */
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37 | 1e8cae4d | Peter Maydell | #define GIC_BASE_IRQ ((s->revision == REV_NVIC) ? 32 : 0) |
38 | 1e8cae4d | Peter Maydell | |
39 | 1e8cae4d | Peter Maydell | #define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm)
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40 | 1e8cae4d | Peter Maydell | #define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm)
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41 | 1e8cae4d | Peter Maydell | #define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0) |
42 | 1e8cae4d | Peter Maydell | #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
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43 | 1e8cae4d | Peter Maydell | #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
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44 | 1e8cae4d | Peter Maydell | #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0) |
45 | 1e8cae4d | Peter Maydell | #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
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46 | 1e8cae4d | Peter Maydell | #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
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47 | 1e8cae4d | Peter Maydell | #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0) |
48 | 1e8cae4d | Peter Maydell | #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1 |
49 | 1e8cae4d | Peter Maydell | #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0 |
50 | 1e8cae4d | Peter Maydell | #define GIC_TEST_MODEL(irq) s->irq_state[irq].model
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51 | 1e8cae4d | Peter Maydell | #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
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52 | 1e8cae4d | Peter Maydell | #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
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53 | 1e8cae4d | Peter Maydell | #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0) |
54 | 1e8cae4d | Peter Maydell | #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1 |
55 | 1e8cae4d | Peter Maydell | #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0 |
56 | 1e8cae4d | Peter Maydell | #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
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57 | 1e8cae4d | Peter Maydell | #define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \
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58 | 1e8cae4d | Peter Maydell | s->priority1[irq][cpu] : \ |
59 | 1e8cae4d | Peter Maydell | s->priority2[(irq) - GIC_INTERNAL]) |
60 | 1e8cae4d | Peter Maydell | #define GIC_TARGET(irq) s->irq_target[irq]
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61 | 1e8cae4d | Peter Maydell | |
62 | 1e8cae4d | Peter Maydell | typedef struct gic_irq_state { |
63 | 1e8cae4d | Peter Maydell | /* The enable bits are only banked for per-cpu interrupts. */
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64 | 1e8cae4d | Peter Maydell | unsigned enabled:NCPU;
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65 | 1e8cae4d | Peter Maydell | unsigned pending:NCPU;
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66 | 1e8cae4d | Peter Maydell | unsigned active:NCPU;
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67 | 1e8cae4d | Peter Maydell | unsigned level:NCPU;
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68 | 1e8cae4d | Peter Maydell | unsigned model:1; /* 0 = N:N, 1 = 1:N */ |
69 | 1e8cae4d | Peter Maydell | unsigned trigger:1; /* nonzero = edge triggered. */ |
70 | 1e8cae4d | Peter Maydell | } gic_irq_state; |
71 | 1e8cae4d | Peter Maydell | |
72 | 1e8cae4d | Peter Maydell | typedef struct gic_state { |
73 | 1e8cae4d | Peter Maydell | SysBusDevice busdev; |
74 | 1e8cae4d | Peter Maydell | qemu_irq parent_irq[NCPU]; |
75 | 1e8cae4d | Peter Maydell | int enabled;
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76 | 1e8cae4d | Peter Maydell | int cpu_enabled[NCPU];
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77 | 1e8cae4d | Peter Maydell | |
78 | 1e8cae4d | Peter Maydell | gic_irq_state irq_state[GIC_MAXIRQ]; |
79 | 1e8cae4d | Peter Maydell | int irq_target[GIC_MAXIRQ];
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80 | 1e8cae4d | Peter Maydell | int priority1[GIC_INTERNAL][NCPU];
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81 | 1e8cae4d | Peter Maydell | int priority2[GIC_MAXIRQ - GIC_INTERNAL];
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82 | 1e8cae4d | Peter Maydell | int last_active[GIC_MAXIRQ][NCPU];
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83 | 1e8cae4d | Peter Maydell | |
84 | 1e8cae4d | Peter Maydell | int priority_mask[NCPU];
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85 | 1e8cae4d | Peter Maydell | int running_irq[NCPU];
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86 | 1e8cae4d | Peter Maydell | int running_priority[NCPU];
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87 | 1e8cae4d | Peter Maydell | int current_pending[NCPU];
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88 | 1e8cae4d | Peter Maydell | |
89 | 1e8cae4d | Peter Maydell | uint32_t num_cpu; |
90 | 1e8cae4d | Peter Maydell | |
91 | 1e8cae4d | Peter Maydell | MemoryRegion iomem; /* Distributor */
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92 | 1e8cae4d | Peter Maydell | /* This is just so we can have an opaque pointer which identifies
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93 | 1e8cae4d | Peter Maydell | * both this GIC and which CPU interface we should be accessing.
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94 | 1e8cae4d | Peter Maydell | */
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95 | 1e8cae4d | Peter Maydell | struct gic_state *backref[NCPU];
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96 | 1e8cae4d | Peter Maydell | MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */ |
97 | 1e8cae4d | Peter Maydell | uint32_t num_irq; |
98 | 1e8cae4d | Peter Maydell | uint32_t revision; |
99 | 1e8cae4d | Peter Maydell | } gic_state; |
100 | 1e8cae4d | Peter Maydell | |
101 | 1e8cae4d | Peter Maydell | /* The special cases for the revision property: */
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102 | 1e8cae4d | Peter Maydell | #define REV_11MPCORE 0 |
103 | 1e8cae4d | Peter Maydell | #define REV_NVIC 0xffffffff |
104 | 1e8cae4d | Peter Maydell | |
105 | 1e8cae4d | Peter Maydell | void gic_set_pending_private(gic_state *s, int cpu, int irq); |
106 | 1e8cae4d | Peter Maydell | uint32_t gic_acknowledge_irq(gic_state *s, int cpu);
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107 | 1e8cae4d | Peter Maydell | void gic_complete_irq(gic_state *s, int cpu, int irq); |
108 | 1e8cae4d | Peter Maydell | void gic_update(gic_state *s);
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109 | 1e8cae4d | Peter Maydell | void gic_init_irqs_and_distributor(gic_state *s, int num_irq); |
110 | 1e8cae4d | Peter Maydell | |
111 | 1e8cae4d | Peter Maydell | #define TYPE_ARM_GIC_COMMON "arm_gic_common" |
112 | 1e8cae4d | Peter Maydell | #define ARM_GIC_COMMON(obj) \
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113 | 1e8cae4d | Peter Maydell | OBJECT_CHECK(gic_state, (obj), TYPE_ARM_GIC_COMMON) |
114 | 1e8cae4d | Peter Maydell | #define ARM_GIC_COMMON_CLASS(klass) \
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115 | 1e8cae4d | Peter Maydell | OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON) |
116 | 1e8cae4d | Peter Maydell | #define ARM_GIC_COMMON_GET_CLASS(obj) \
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117 | 1e8cae4d | Peter Maydell | OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON) |
118 | 1e8cae4d | Peter Maydell | |
119 | 1e8cae4d | Peter Maydell | typedef struct ARMGICCommonClass { |
120 | 1e8cae4d | Peter Maydell | SysBusDeviceClass parent_class; |
121 | 1e8cae4d | Peter Maydell | } ARMGICCommonClass; |
122 | 1e8cae4d | Peter Maydell | |
123 | 1e8cae4d | Peter Maydell | #define TYPE_ARM_GIC "arm_gic" |
124 | 1e8cae4d | Peter Maydell | #define ARM_GIC(obj) \
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125 | 1e8cae4d | Peter Maydell | OBJECT_CHECK(gic_state, (obj), TYPE_ARM_GIC) |
126 | 1e8cae4d | Peter Maydell | #define ARM_GIC_CLASS(klass) \
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127 | 1e8cae4d | Peter Maydell | OBJECT_CLASS_CHECK(ARMGICClass, (klass), TYPE_ARM_GIC) |
128 | 1e8cae4d | Peter Maydell | #define ARM_GIC_GET_CLASS(obj) \
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129 | 1e8cae4d | Peter Maydell | OBJECT_GET_CLASS(ARMGICClass, (obj), TYPE_ARM_GIC) |
130 | 1e8cae4d | Peter Maydell | |
131 | 1e8cae4d | Peter Maydell | typedef struct ARMGICClass { |
132 | 1e8cae4d | Peter Maydell | ARMGICCommonClass parent_class; |
133 | 1e8cae4d | Peter Maydell | int (*parent_init)(SysBusDevice *dev);
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134 | 1e8cae4d | Peter Maydell | } ARMGICClass; |
135 | 1e8cae4d | Peter Maydell | |
136 | 1e8cae4d | Peter Maydell | #endif /* !QEMU_ARM_GIC_INTERNAL_H */ |