root / hw / pci.h @ fa6c6065
History | View | Annotate | Download (14.6 kB)
1 |
#ifndef QEMU_PCI_H
|
---|---|
2 |
#define QEMU_PCI_H
|
3 |
|
4 |
#include "qemu-common.h" |
5 |
#include "qobject.h" |
6 |
|
7 |
#include "qdev.h" |
8 |
#include "memory.h" |
9 |
|
10 |
/* PCI includes legacy ISA access. */
|
11 |
#include "isa.h" |
12 |
|
13 |
#include "pcie.h" |
14 |
|
15 |
/* PCI bus */
|
16 |
|
17 |
#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
18 |
#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
19 |
#define PCI_FUNC(devfn) ((devfn) & 0x07) |
20 |
#define PCI_SLOT_MAX 32 |
21 |
#define PCI_FUNC_MAX 8 |
22 |
|
23 |
/* Class, Vendor and Device IDs from Linux's pci_ids.h */
|
24 |
#include "pci_ids.h" |
25 |
|
26 |
/* QEMU-specific Vendor and Device ID definitions */
|
27 |
|
28 |
/* IBM (0x1014) */
|
29 |
#define PCI_DEVICE_ID_IBM_440GX 0x027f |
30 |
#define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff |
31 |
|
32 |
/* Hitachi (0x1054) */
|
33 |
#define PCI_VENDOR_ID_HITACHI 0x1054 |
34 |
#define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e |
35 |
|
36 |
/* Apple (0x106b) */
|
37 |
#define PCI_DEVICE_ID_APPLE_343S1201 0x0010 |
38 |
#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e |
39 |
#define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f |
40 |
#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 |
41 |
#define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f |
42 |
|
43 |
/* Realtek (0x10ec) */
|
44 |
#define PCI_DEVICE_ID_REALTEK_8029 0x8029 |
45 |
|
46 |
/* Xilinx (0x10ee) */
|
47 |
#define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 |
48 |
|
49 |
/* Marvell (0x11ab) */
|
50 |
#define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 |
51 |
|
52 |
/* QEMU/Bochs VGA (0x1234) */
|
53 |
#define PCI_VENDOR_ID_QEMU 0x1234 |
54 |
#define PCI_DEVICE_ID_QEMU_VGA 0x1111 |
55 |
|
56 |
/* VMWare (0x15ad) */
|
57 |
#define PCI_VENDOR_ID_VMWARE 0x15ad |
58 |
#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 |
59 |
#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 |
60 |
#define PCI_DEVICE_ID_VMWARE_NET 0x0720 |
61 |
#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 |
62 |
#define PCI_DEVICE_ID_VMWARE_IDE 0x1729 |
63 |
|
64 |
/* Intel (0x8086) */
|
65 |
#define PCI_DEVICE_ID_INTEL_82551IT 0x1209 |
66 |
#define PCI_DEVICE_ID_INTEL_82557 0x1229 |
67 |
#define PCI_DEVICE_ID_INTEL_82801IR 0x2922 |
68 |
|
69 |
/* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
|
70 |
#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
71 |
#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 |
72 |
#define PCI_SUBDEVICE_ID_QEMU 0x1100 |
73 |
|
74 |
#define PCI_DEVICE_ID_VIRTIO_NET 0x1000 |
75 |
#define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 |
76 |
#define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 |
77 |
#define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
78 |
|
79 |
#define FMT_PCIBUS PRIx64
|
80 |
|
81 |
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
82 |
uint32_t address, uint32_t data, int len);
|
83 |
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
|
84 |
uint32_t address, int len);
|
85 |
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, |
86 |
pcibus_t addr, pcibus_t size, int type);
|
87 |
typedef int PCIUnregisterFunc(PCIDevice *pci_dev); |
88 |
|
89 |
typedef struct PCIIORegion { |
90 |
pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
|
91 |
#define PCI_BAR_UNMAPPED (~(pcibus_t)0) |
92 |
pcibus_t size; |
93 |
pcibus_t filtered_size; |
94 |
uint8_t type; |
95 |
PCIMapIORegionFunc *map_func; |
96 |
MemoryRegion *memory; |
97 |
MemoryRegion *address_space; |
98 |
} PCIIORegion; |
99 |
|
100 |
#define PCI_ROM_SLOT 6 |
101 |
#define PCI_NUM_REGIONS 7 |
102 |
|
103 |
#include "pci_regs.h" |
104 |
|
105 |
/* PCI HEADER_TYPE */
|
106 |
#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 |
107 |
|
108 |
/* Size of the standard PCI config header */
|
109 |
#define PCI_CONFIG_HEADER_SIZE 0x40 |
110 |
/* Size of the standard PCI config space */
|
111 |
#define PCI_CONFIG_SPACE_SIZE 0x100 |
112 |
/* Size of the standart PCIe config space: 4KB */
|
113 |
#define PCIE_CONFIG_SPACE_SIZE 0x1000 |
114 |
|
115 |
#define PCI_NUM_PINS 4 /* A-D */ |
116 |
|
117 |
/* Bits in cap_present field. */
|
118 |
enum {
|
119 |
QEMU_PCI_CAP_MSI = 0x1,
|
120 |
QEMU_PCI_CAP_MSIX = 0x2,
|
121 |
QEMU_PCI_CAP_EXPRESS = 0x4,
|
122 |
|
123 |
/* multifunction capable device */
|
124 |
#define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 |
125 |
QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
|
126 |
|
127 |
/* command register SERR bit enabled */
|
128 |
#define QEMU_PCI_CAP_SERR_BITNR 4 |
129 |
QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
|
130 |
}; |
131 |
|
132 |
struct PCIDevice {
|
133 |
DeviceState qdev; |
134 |
/* PCI config space */
|
135 |
uint8_t *config; |
136 |
|
137 |
/* Used to enable config checks on load. Note that writable bits are
|
138 |
* never checked even if set in cmask. */
|
139 |
uint8_t *cmask; |
140 |
|
141 |
/* Used to implement R/W bytes */
|
142 |
uint8_t *wmask; |
143 |
|
144 |
/* Used to implement RW1C(Write 1 to Clear) bytes */
|
145 |
uint8_t *w1cmask; |
146 |
|
147 |
/* Used to allocate config space for capabilities. */
|
148 |
uint8_t *used; |
149 |
|
150 |
/* the following fields are read only */
|
151 |
PCIBus *bus; |
152 |
uint32_t devfn; |
153 |
char name[64]; |
154 |
PCIIORegion io_regions[PCI_NUM_REGIONS]; |
155 |
|
156 |
/* do not access the following fields */
|
157 |
PCIConfigReadFunc *config_read; |
158 |
PCIConfigWriteFunc *config_write; |
159 |
|
160 |
/* IRQ objects for the INTA-INTD pins. */
|
161 |
qemu_irq *irq; |
162 |
|
163 |
/* Current IRQ levels. Used internally by the generic PCI code. */
|
164 |
uint8_t irq_state; |
165 |
|
166 |
/* Capability bits */
|
167 |
uint32_t cap_present; |
168 |
|
169 |
/* Offset of MSI-X capability in config space */
|
170 |
uint8_t msix_cap; |
171 |
|
172 |
/* MSI-X entries */
|
173 |
int msix_entries_nr;
|
174 |
|
175 |
/* Space to store MSIX table */
|
176 |
uint8_t *msix_table_page; |
177 |
/* MMIO index used to map MSIX table and pending bit entries. */
|
178 |
MemoryRegion msix_mmio; |
179 |
/* Reference-count for entries actually in use by driver. */
|
180 |
unsigned *msix_entry_used;
|
181 |
/* Region including the MSI-X table */
|
182 |
uint32_t msix_bar_size; |
183 |
/* Version id needed for VMState */
|
184 |
int32_t version_id; |
185 |
|
186 |
/* Offset of MSI capability in config space */
|
187 |
uint8_t msi_cap; |
188 |
|
189 |
/* PCI Express */
|
190 |
PCIExpressDevice exp; |
191 |
|
192 |
/* Location of option rom */
|
193 |
char *romfile;
|
194 |
ram_addr_t rom_offset; |
195 |
uint32_t rom_bar; |
196 |
}; |
197 |
|
198 |
PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
199 |
int instance_size, int devfn, |
200 |
PCIConfigReadFunc *config_read, |
201 |
PCIConfigWriteFunc *config_write); |
202 |
|
203 |
void pci_register_bar(PCIDevice *pci_dev, int region_num, |
204 |
pcibus_t size, uint8_t type, |
205 |
PCIMapIORegionFunc *map_func); |
206 |
void pci_register_bar_region(PCIDevice *pci_dev, int region_num, |
207 |
uint8_t attr, MemoryRegion *memory); |
208 |
pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
|
209 |
|
210 |
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
|
211 |
uint8_t offset, uint8_t size); |
212 |
|
213 |
void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
|
214 |
|
215 |
void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
|
216 |
|
217 |
uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); |
218 |
|
219 |
|
220 |
uint32_t pci_default_read_config(PCIDevice *d, |
221 |
uint32_t address, int len);
|
222 |
void pci_default_write_config(PCIDevice *d,
|
223 |
uint32_t address, uint32_t val, int len);
|
224 |
void pci_device_save(PCIDevice *s, QEMUFile *f);
|
225 |
int pci_device_load(PCIDevice *s, QEMUFile *f);
|
226 |
|
227 |
typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); |
228 |
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
229 |
|
230 |
typedef enum { |
231 |
PCI_HOTPLUG_DISABLED, |
232 |
PCI_HOTPLUG_ENABLED, |
233 |
PCI_COLDPLUG_ENABLED, |
234 |
} PCIHotplugState; |
235 |
|
236 |
typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, |
237 |
PCIHotplugState state); |
238 |
void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
|
239 |
const char *name, |
240 |
MemoryRegion *address_space_mem, |
241 |
MemoryRegion *address_space_io, |
242 |
uint8_t devfn_min); |
243 |
PCIBus *pci_bus_new(DeviceState *parent, const char *name, |
244 |
MemoryRegion *address_space_mem, |
245 |
MemoryRegion *address_space_io, |
246 |
uint8_t devfn_min); |
247 |
void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
|
248 |
void *irq_opaque, int nirq); |
249 |
int pci_bus_get_irq_level(PCIBus *bus, int irq_num); |
250 |
void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
|
251 |
PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
252 |
pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
253 |
void *irq_opaque,
|
254 |
MemoryRegion *address_space_mem, |
255 |
MemoryRegion *address_space_io, |
256 |
uint8_t devfn_min, int nirq);
|
257 |
void pci_device_reset(PCIDevice *dev);
|
258 |
void pci_bus_reset(PCIBus *bus);
|
259 |
|
260 |
void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
|
261 |
|
262 |
PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
263 |
const char *default_devaddr); |
264 |
PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
265 |
const char *default_devaddr); |
266 |
int pci_bus_num(PCIBus *s);
|
267 |
void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d)); |
268 |
PCIBus *pci_find_root_bus(int domain);
|
269 |
int pci_find_domain(const PCIBus *bus); |
270 |
PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
|
271 |
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
|
272 |
int pci_qdev_find_device(const char *id, PCIDevice **pdev); |
273 |
PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr); |
274 |
|
275 |
int pci_parse_devaddr(const char *addr, int *domp, int *busp, |
276 |
unsigned int *slotp, unsigned int *funcp); |
277 |
int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
278 |
unsigned *slotp);
|
279 |
|
280 |
void do_pci_info_print(Monitor *mon, const QObject *data); |
281 |
void do_pci_info(Monitor *mon, QObject **ret_data);
|
282 |
void pci_bridge_update_mappings(PCIBus *b);
|
283 |
|
284 |
void pci_device_deassert_intx(PCIDevice *dev);
|
285 |
|
286 |
static inline void |
287 |
pci_set_byte(uint8_t *config, uint8_t val) |
288 |
{ |
289 |
*config = val; |
290 |
} |
291 |
|
292 |
static inline uint8_t |
293 |
pci_get_byte(const uint8_t *config)
|
294 |
{ |
295 |
return *config;
|
296 |
} |
297 |
|
298 |
static inline void |
299 |
pci_set_word(uint8_t *config, uint16_t val) |
300 |
{ |
301 |
cpu_to_le16wu((uint16_t *)config, val); |
302 |
} |
303 |
|
304 |
static inline uint16_t |
305 |
pci_get_word(const uint8_t *config)
|
306 |
{ |
307 |
return le16_to_cpupu((const uint16_t *)config); |
308 |
} |
309 |
|
310 |
static inline void |
311 |
pci_set_long(uint8_t *config, uint32_t val) |
312 |
{ |
313 |
cpu_to_le32wu((uint32_t *)config, val); |
314 |
} |
315 |
|
316 |
static inline uint32_t |
317 |
pci_get_long(const uint8_t *config)
|
318 |
{ |
319 |
return le32_to_cpupu((const uint32_t *)config); |
320 |
} |
321 |
|
322 |
static inline void |
323 |
pci_set_quad(uint8_t *config, uint64_t val) |
324 |
{ |
325 |
cpu_to_le64w((uint64_t *)config, val); |
326 |
} |
327 |
|
328 |
static inline uint64_t |
329 |
pci_get_quad(const uint8_t *config)
|
330 |
{ |
331 |
return le64_to_cpup((const uint64_t *)config); |
332 |
} |
333 |
|
334 |
static inline void |
335 |
pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) |
336 |
{ |
337 |
pci_set_word(&pci_config[PCI_VENDOR_ID], val); |
338 |
} |
339 |
|
340 |
static inline void |
341 |
pci_config_set_device_id(uint8_t *pci_config, uint16_t val) |
342 |
{ |
343 |
pci_set_word(&pci_config[PCI_DEVICE_ID], val); |
344 |
} |
345 |
|
346 |
static inline void |
347 |
pci_config_set_revision(uint8_t *pci_config, uint8_t val) |
348 |
{ |
349 |
pci_set_byte(&pci_config[PCI_REVISION_ID], val); |
350 |
} |
351 |
|
352 |
static inline void |
353 |
pci_config_set_class(uint8_t *pci_config, uint16_t val) |
354 |
{ |
355 |
pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); |
356 |
} |
357 |
|
358 |
static inline void |
359 |
pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) |
360 |
{ |
361 |
pci_set_byte(&pci_config[PCI_CLASS_PROG], val); |
362 |
} |
363 |
|
364 |
static inline void |
365 |
pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) |
366 |
{ |
367 |
pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); |
368 |
} |
369 |
|
370 |
/*
|
371 |
* helper functions to do bit mask operation on configuration space.
|
372 |
* Just to set bit, use test-and-set and discard returned value.
|
373 |
* Just to clear bit, use test-and-clear and discard returned value.
|
374 |
* NOTE: They aren't atomic.
|
375 |
*/
|
376 |
static inline uint8_t |
377 |
pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) |
378 |
{ |
379 |
uint8_t val = pci_get_byte(config); |
380 |
pci_set_byte(config, val & ~mask); |
381 |
return val & mask;
|
382 |
} |
383 |
|
384 |
static inline uint8_t |
385 |
pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) |
386 |
{ |
387 |
uint8_t val = pci_get_byte(config); |
388 |
pci_set_byte(config, val | mask); |
389 |
return val & mask;
|
390 |
} |
391 |
|
392 |
static inline uint16_t |
393 |
pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) |
394 |
{ |
395 |
uint16_t val = pci_get_word(config); |
396 |
pci_set_word(config, val & ~mask); |
397 |
return val & mask;
|
398 |
} |
399 |
|
400 |
static inline uint16_t |
401 |
pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) |
402 |
{ |
403 |
uint16_t val = pci_get_word(config); |
404 |
pci_set_word(config, val | mask); |
405 |
return val & mask;
|
406 |
} |
407 |
|
408 |
static inline uint32_t |
409 |
pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) |
410 |
{ |
411 |
uint32_t val = pci_get_long(config); |
412 |
pci_set_long(config, val & ~mask); |
413 |
return val & mask;
|
414 |
} |
415 |
|
416 |
static inline uint32_t |
417 |
pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) |
418 |
{ |
419 |
uint32_t val = pci_get_long(config); |
420 |
pci_set_long(config, val | mask); |
421 |
return val & mask;
|
422 |
} |
423 |
|
424 |
static inline uint64_t |
425 |
pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) |
426 |
{ |
427 |
uint64_t val = pci_get_quad(config); |
428 |
pci_set_quad(config, val & ~mask); |
429 |
return val & mask;
|
430 |
} |
431 |
|
432 |
static inline uint64_t |
433 |
pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) |
434 |
{ |
435 |
uint64_t val = pci_get_quad(config); |
436 |
pci_set_quad(config, val | mask); |
437 |
return val & mask;
|
438 |
} |
439 |
|
440 |
typedef int (*pci_qdev_initfn)(PCIDevice *dev); |
441 |
typedef struct { |
442 |
DeviceInfo qdev; |
443 |
pci_qdev_initfn init; |
444 |
PCIUnregisterFunc *exit; |
445 |
PCIConfigReadFunc *config_read; |
446 |
PCIConfigWriteFunc *config_write; |
447 |
|
448 |
uint16_t vendor_id; |
449 |
uint16_t device_id; |
450 |
uint8_t revision; |
451 |
uint16_t class_id; |
452 |
uint16_t subsystem_vendor_id; /* only for header type = 0 */
|
453 |
uint16_t subsystem_id; /* only for header type = 0 */
|
454 |
|
455 |
/*
|
456 |
* pci-to-pci bridge or normal device.
|
457 |
* This doesn't mean pci host switch.
|
458 |
* When card bus bridge is supported, this would be enhanced.
|
459 |
*/
|
460 |
int is_bridge;
|
461 |
|
462 |
/* pcie stuff */
|
463 |
int is_express; /* is this device pci express? */ |
464 |
|
465 |
/* device isn't hot-pluggable */
|
466 |
int no_hotplug;
|
467 |
|
468 |
/* rom bar */
|
469 |
const char *romfile; |
470 |
} PCIDeviceInfo; |
471 |
|
472 |
void pci_qdev_register(PCIDeviceInfo *info);
|
473 |
void pci_qdev_register_many(PCIDeviceInfo *info);
|
474 |
|
475 |
PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
476 |
const char *name); |
477 |
PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
|
478 |
bool multifunction,
|
479 |
const char *name); |
480 |
PCIDevice *pci_try_create_multifunction(PCIBus *bus, int devfn,
|
481 |
bool multifunction,
|
482 |
const char *name); |
483 |
PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); |
484 |
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); |
485 |
PCIDevice *pci_try_create(PCIBus *bus, int devfn, const char *name); |
486 |
|
487 |
static inline int pci_is_express(const PCIDevice *d) |
488 |
{ |
489 |
return d->cap_present & QEMU_PCI_CAP_EXPRESS;
|
490 |
} |
491 |
|
492 |
static inline uint32_t pci_config_size(const PCIDevice *d) |
493 |
{ |
494 |
return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
|
495 |
} |
496 |
|
497 |
#endif
|