Revision fab7fe42 target-ppc/fpu_helper.c
| b/target-ppc/fpu_helper.c | ||
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| 600 | 600 |
return farg1.ll; |
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} |
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/* fctiw - fctiw. */ |
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uint64_t helper_fctiw(CPUPPCState *env, uint64_t arg) |
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{
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CPU_DoubleU farg; |
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farg.ll = arg; |
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if (unlikely(float64_is_signaling_nan(farg.d))) {
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/* sNaN conversion */ |
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farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN | |
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POWERPC_EXCP_FP_VXCVI, 1); |
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} else if (unlikely(float64_is_quiet_nan(farg.d) || |
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float64_is_infinity(farg.d))) {
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/* qNan / infinity conversion */ |
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farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); |
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} else {
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farg.ll = float64_to_int32(farg.d, &env->fp_status); |
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/* XXX: higher bits are not supposed to be significant. |
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* to make tests easier, return the same as a real PowerPC 750 |
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*/ |
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farg.ll |= 0xFFF80000ULL << 32; |
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} |
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return farg.ll; |
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} |
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/* fctiwz - fctiwz. */ |
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uint64_t helper_fctiwz(CPUPPCState *env, uint64_t arg) |
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{
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CPU_DoubleU farg; |
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farg.ll = arg; |
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#define FPU_FCTI(op, cvt, nanval) \ |
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uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \ |
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{ \
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CPU_DoubleU farg; \ |
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\ |
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farg.ll = arg; \ |
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farg.ll = float64_to_##cvt(farg.d, &env->fp_status); \ |
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\ |
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if (unlikely(env->fp_status.float_exception_flags)) { \
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if (float64_is_any_nan(arg)) { \
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fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \ |
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if (float64_is_signaling_nan(arg)) { \
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fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); \ |
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} \ |
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farg.ll = nanval; \ |
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} else if (env->fp_status.float_exception_flags & \ |
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float_flag_invalid) { \
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fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \ |
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} \ |
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helper_float_check_status(env); \ |
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} \ |
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return farg.ll; \ |
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} |
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if (unlikely(float64_is_signaling_nan(farg.d))) {
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/* sNaN conversion */ |
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farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN | |
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POWERPC_EXCP_FP_VXCVI, 1); |
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} else if (unlikely(float64_is_quiet_nan(farg.d) || |
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float64_is_infinity(farg.d))) {
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/* qNan / infinity conversion */ |
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farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); |
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} else {
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farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status); |
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/* XXX: higher bits are not supposed to be significant. |
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* to make tests easier, return the same as a real PowerPC 750 |
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*/ |
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farg.ll |= 0xFFF80000ULL << 32; |
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} |
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return farg.ll; |
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} |
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FPU_FCTI(fctiw, int32, 0x80000000) |
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FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000) |
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FPU_FCTI(fctiwu, uint32, 0x00000000) |
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FPU_FCTI(fctiwuz, uint32_round_to_zero, 0x00000000) |
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#if defined(TARGET_PPC64) |
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FPU_FCTI(fctid, int64, 0x8000000000000000) |
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FPU_FCTI(fctidz, int64_round_to_zero, 0x8000000000000000) |
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FPU_FCTI(fctidu, uint64, 0x0000000000000000) |
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FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000) |
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#endif |
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#if defined(TARGET_PPC64) |
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/* fcfid - fcfid. */ |
| ... | ... | |
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return farg.ll; |
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} |
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/* fctid - fctid. */ |
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uint64_t helper_fctid(CPUPPCState *env, uint64_t arg) |
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{
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CPU_DoubleU farg; |
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farg.ll = arg; |
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if (unlikely(float64_is_signaling_nan(farg.d))) {
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/* sNaN conversion */ |
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farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN | |
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POWERPC_EXCP_FP_VXCVI, 1); |
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} else if (unlikely(float64_is_quiet_nan(farg.d) || |
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float64_is_infinity(farg.d))) {
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/* qNan / infinity conversion */ |
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farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); |
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} else {
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farg.ll = float64_to_int64(farg.d, &env->fp_status); |
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} |
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return farg.ll; |
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} |
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/* fctidz - fctidz. */ |
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uint64_t helper_fctidz(CPUPPCState *env, uint64_t arg) |
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{
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CPU_DoubleU farg; |
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farg.ll = arg; |
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if (unlikely(float64_is_signaling_nan(farg.d))) {
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/* sNaN conversion */ |
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farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN | |
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POWERPC_EXCP_FP_VXCVI, 1); |
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} else if (unlikely(float64_is_quiet_nan(farg.d) || |
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float64_is_infinity(farg.d))) {
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/* qNan / infinity conversion */ |
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farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); |
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} else {
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farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status); |
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} |
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return farg.ll; |
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} |
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| 704 | 650 |
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#endif |
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