root / alpha-dis.c @ facc68be
History | View | Annotate | Download (80.5 kB)
1 | a993ba85 | bellard | /* alpha-dis.c -- Disassemble Alpha AXP instructions
|
---|---|---|---|
2 | a993ba85 | bellard | Copyright 1996, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
|
3 | a993ba85 | bellard | Contributed by Richard Henderson <rth@tamu.edu>,
|
4 | a993ba85 | bellard | patterned after the PPC opcode handling written by Ian Lance Taylor.
|
5 | a993ba85 | bellard | |
6 | a993ba85 | bellard | This file is part of GDB, GAS, and the GNU binutils.
|
7 | a993ba85 | bellard | |
8 | a993ba85 | bellard | GDB, GAS, and the GNU binutils are free software; you can redistribute
|
9 | a993ba85 | bellard | them and/or modify them under the terms of the GNU General Public
|
10 | a993ba85 | bellard | License as published by the Free Software Foundation; either version
|
11 | a993ba85 | bellard | 2, or (at your option) any later version.
|
12 | a993ba85 | bellard | |
13 | a993ba85 | bellard | GDB, GAS, and the GNU binutils are distributed in the hope that they
|
14 | a993ba85 | bellard | will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
15 | a993ba85 | bellard | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
16 | a993ba85 | bellard | the GNU General Public License for more details.
|
17 | a993ba85 | bellard | |
18 | a993ba85 | bellard | You should have received a copy of the GNU General Public License
|
19 | a993ba85 | bellard | along with this file; see the file COPYING. If not, write to the Free
|
20 | a993ba85 | bellard | Software Foundation, 59 Temple Place - Suite 330, Boston, MA
|
21 | a993ba85 | bellard | 02111-1307, USA. */
|
22 | a993ba85 | bellard | |
23 | a993ba85 | bellard | #include <stdio.h> |
24 | a993ba85 | bellard | #include "dis-asm.h" |
25 | a993ba85 | bellard | |
26 | a993ba85 | bellard | #define ATTRIBUTE_UNUSED __attribute__((unused))
|
27 | a993ba85 | bellard | #define _(x) x
|
28 | a993ba85 | bellard | |
29 | a993ba85 | bellard | /* The opcode table is an array of struct alpha_opcode. */
|
30 | a993ba85 | bellard | |
31 | a993ba85 | bellard | struct alpha_opcode
|
32 | a993ba85 | bellard | { |
33 | a993ba85 | bellard | /* The opcode name. */
|
34 | a993ba85 | bellard | const char *name; |
35 | a993ba85 | bellard | |
36 | a993ba85 | bellard | /* The opcode itself. Those bits which will be filled in with
|
37 | a993ba85 | bellard | operands are zeroes. */
|
38 | a993ba85 | bellard | unsigned opcode;
|
39 | a993ba85 | bellard | |
40 | a993ba85 | bellard | /* The opcode mask. This is used by the disassembler. This is a
|
41 | a993ba85 | bellard | mask containing ones indicating those bits which must match the
|
42 | a993ba85 | bellard | opcode field, and zeroes indicating those bits which need not
|
43 | a993ba85 | bellard | match (and are presumably filled in by operands). */
|
44 | a993ba85 | bellard | unsigned mask;
|
45 | a993ba85 | bellard | |
46 | a993ba85 | bellard | /* One bit flags for the opcode. These are primarily used to
|
47 | a993ba85 | bellard | indicate specific processors and environments support the
|
48 | a993ba85 | bellard | instructions. The defined values are listed below. */
|
49 | a993ba85 | bellard | unsigned flags;
|
50 | a993ba85 | bellard | |
51 | a993ba85 | bellard | /* An array of operand codes. Each code is an index into the
|
52 | a993ba85 | bellard | operand table. They appear in the order which the operands must
|
53 | a993ba85 | bellard | appear in assembly code, and are terminated by a zero. */
|
54 | a993ba85 | bellard | unsigned char operands[4]; |
55 | a993ba85 | bellard | }; |
56 | a993ba85 | bellard | |
57 | a993ba85 | bellard | /* The table itself is sorted by major opcode number, and is otherwise
|
58 | a993ba85 | bellard | in the order in which the disassembler should consider
|
59 | a993ba85 | bellard | instructions. */
|
60 | a993ba85 | bellard | extern const struct alpha_opcode alpha_opcodes[]; |
61 | a993ba85 | bellard | extern const unsigned alpha_num_opcodes; |
62 | a993ba85 | bellard | |
63 | a993ba85 | bellard | /* Values defined for the flags field of a struct alpha_opcode. */
|
64 | a993ba85 | bellard | |
65 | a993ba85 | bellard | /* CPU Availability */
|
66 | a993ba85 | bellard | #define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */ |
67 | a993ba85 | bellard | #define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */ |
68 | a993ba85 | bellard | #define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */ |
69 | a993ba85 | bellard | #define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */ |
70 | a993ba85 | bellard | #define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */ |
71 | a993ba85 | bellard | #define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */ |
72 | a993ba85 | bellard | #define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */ |
73 | a993ba85 | bellard | |
74 | a993ba85 | bellard | #define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6))
|
75 | a993ba85 | bellard | |
76 | a993ba85 | bellard | /* A macro to extract the major opcode from an instruction. */
|
77 | a993ba85 | bellard | #define AXP_OP(i) (((i) >> 26) & 0x3F) |
78 | a993ba85 | bellard | |
79 | a993ba85 | bellard | /* The total number of major opcodes. */
|
80 | a993ba85 | bellard | #define AXP_NOPS 0x40 |
81 | a993ba85 | bellard | |
82 | a993ba85 | bellard | |
83 | a993ba85 | bellard | /* The operands table is an array of struct alpha_operand. */
|
84 | a993ba85 | bellard | |
85 | a993ba85 | bellard | struct alpha_operand
|
86 | a993ba85 | bellard | { |
87 | a993ba85 | bellard | /* The number of bits in the operand. */
|
88 | a993ba85 | bellard | unsigned int bits : 5; |
89 | a993ba85 | bellard | |
90 | a993ba85 | bellard | /* How far the operand is left shifted in the instruction. */
|
91 | a993ba85 | bellard | unsigned int shift : 5; |
92 | a993ba85 | bellard | |
93 | a993ba85 | bellard | /* The default relocation type for this operand. */
|
94 | a993ba85 | bellard | signed int default_reloc : 16; |
95 | a993ba85 | bellard | |
96 | a993ba85 | bellard | /* One bit syntax flags. */
|
97 | a993ba85 | bellard | unsigned int flags : 16; |
98 | a993ba85 | bellard | |
99 | a993ba85 | bellard | /* Insertion function. This is used by the assembler. To insert an
|
100 | a993ba85 | bellard | operand value into an instruction, check this field.
|
101 | a993ba85 | bellard | |
102 | a993ba85 | bellard | If it is NULL, execute
|
103 | a993ba85 | bellard | i |= (op & ((1 << o->bits) - 1)) << o->shift;
|
104 | a993ba85 | bellard | (i is the instruction which we are filling in, o is a pointer to
|
105 | a993ba85 | bellard | this structure, and op is the opcode value; this assumes twos
|
106 | a993ba85 | bellard | complement arithmetic).
|
107 | a993ba85 | bellard | |
108 | a993ba85 | bellard | If this field is not NULL, then simply call it with the
|
109 | a993ba85 | bellard | instruction and the operand value. It will return the new value
|
110 | a993ba85 | bellard | of the instruction. If the ERRMSG argument is not NULL, then if
|
111 | a993ba85 | bellard | the operand value is illegal, *ERRMSG will be set to a warning
|
112 | a993ba85 | bellard | string (the operand will be inserted in any case). If the
|
113 | a993ba85 | bellard | operand value is legal, *ERRMSG will be unchanged (most operands
|
114 | a993ba85 | bellard | can accept any value). */
|
115 | a993ba85 | bellard | unsigned (*insert) PARAMS ((unsigned instruction, int op, |
116 | a993ba85 | bellard | const char **errmsg)); |
117 | a993ba85 | bellard | |
118 | a993ba85 | bellard | /* Extraction function. This is used by the disassembler. To
|
119 | a993ba85 | bellard | extract this operand type from an instruction, check this field.
|
120 | a993ba85 | bellard | |
121 | a993ba85 | bellard | If it is NULL, compute
|
122 | a993ba85 | bellard | op = ((i) >> o->shift) & ((1 << o->bits) - 1);
|
123 | a993ba85 | bellard | if ((o->flags & AXP_OPERAND_SIGNED) != 0
|
124 | a993ba85 | bellard | && (op & (1 << (o->bits - 1))) != 0)
|
125 | a993ba85 | bellard | op -= 1 << o->bits;
|
126 | a993ba85 | bellard | (i is the instruction, o is a pointer to this structure, and op
|
127 | a993ba85 | bellard | is the result; this assumes twos complement arithmetic).
|
128 | a993ba85 | bellard | |
129 | a993ba85 | bellard | If this field is not NULL, then simply call it with the
|
130 | a993ba85 | bellard | instruction value. It will return the value of the operand. If
|
131 | a993ba85 | bellard | the INVALID argument is not NULL, *INVALID will be set to
|
132 | a993ba85 | bellard | non-zero if this operand type can not actually be extracted from
|
133 | a993ba85 | bellard | this operand (i.e., the instruction does not match). If the
|
134 | a993ba85 | bellard | operand is valid, *INVALID will not be changed. */
|
135 | a993ba85 | bellard | int (*extract) PARAMS ((unsigned instruction, int *invalid)); |
136 | a993ba85 | bellard | }; |
137 | a993ba85 | bellard | |
138 | a993ba85 | bellard | /* Elements in the table are retrieved by indexing with values from
|
139 | a993ba85 | bellard | the operands field of the alpha_opcodes table. */
|
140 | a993ba85 | bellard | |
141 | a993ba85 | bellard | extern const struct alpha_operand alpha_operands[]; |
142 | a993ba85 | bellard | extern const unsigned alpha_num_operands; |
143 | a993ba85 | bellard | |
144 | a993ba85 | bellard | /* Values defined for the flags field of a struct alpha_operand. */
|
145 | a993ba85 | bellard | |
146 | a993ba85 | bellard | /* Mask for selecting the type for typecheck purposes */
|
147 | a993ba85 | bellard | #define AXP_OPERAND_TYPECHECK_MASK \
|
148 | a993ba85 | bellard | (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR | \ |
149 | a993ba85 | bellard | AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | \ |
150 | a993ba85 | bellard | AXP_OPERAND_UNSIGNED) |
151 | a993ba85 | bellard | |
152 | a993ba85 | bellard | /* This operand does not actually exist in the assembler input. This
|
153 | a993ba85 | bellard | is used to support extended mnemonics, for which two operands fields
|
154 | a993ba85 | bellard | are identical. The assembler should call the insert function with
|
155 | a993ba85 | bellard | any op value. The disassembler should call the extract function,
|
156 | a993ba85 | bellard | ignore the return value, and check the value placed in the invalid
|
157 | a993ba85 | bellard | argument. */
|
158 | a993ba85 | bellard | #define AXP_OPERAND_FAKE 01 |
159 | a993ba85 | bellard | |
160 | a993ba85 | bellard | /* The operand should be wrapped in parentheses rather than separated
|
161 | a993ba85 | bellard | from the previous by a comma. This is used for the load and store
|
162 | a993ba85 | bellard | instructions which want their operands to look like "Ra,disp(Rb)". */
|
163 | a993ba85 | bellard | #define AXP_OPERAND_PARENS 02 |
164 | a993ba85 | bellard | |
165 | a993ba85 | bellard | /* Used in combination with PARENS, this supresses the supression of
|
166 | a993ba85 | bellard | the comma. This is used for "jmp Ra,(Rb),hint". */
|
167 | a993ba85 | bellard | #define AXP_OPERAND_COMMA 04 |
168 | a993ba85 | bellard | |
169 | a993ba85 | bellard | /* This operand names an integer register. */
|
170 | a993ba85 | bellard | #define AXP_OPERAND_IR 010 |
171 | a993ba85 | bellard | |
172 | a993ba85 | bellard | /* This operand names a floating point register. */
|
173 | a993ba85 | bellard | #define AXP_OPERAND_FPR 020 |
174 | a993ba85 | bellard | |
175 | a993ba85 | bellard | /* This operand is a relative branch displacement. The disassembler
|
176 | a993ba85 | bellard | prints these symbolically if possible. */
|
177 | a993ba85 | bellard | #define AXP_OPERAND_RELATIVE 040 |
178 | a993ba85 | bellard | |
179 | a993ba85 | bellard | /* This operand takes signed values. */
|
180 | a993ba85 | bellard | #define AXP_OPERAND_SIGNED 0100 |
181 | a993ba85 | bellard | |
182 | a993ba85 | bellard | /* This operand takes unsigned values. This exists primarily so that
|
183 | a993ba85 | bellard | a flags value of 0 can be treated as end-of-arguments. */
|
184 | a993ba85 | bellard | #define AXP_OPERAND_UNSIGNED 0200 |
185 | a993ba85 | bellard | |
186 | a993ba85 | bellard | /* Supress overflow detection on this field. This is used for hints. */
|
187 | a993ba85 | bellard | #define AXP_OPERAND_NOOVERFLOW 0400 |
188 | a993ba85 | bellard | |
189 | a993ba85 | bellard | /* Mask for optional argument default value. */
|
190 | a993ba85 | bellard | #define AXP_OPERAND_OPTIONAL_MASK 07000 |
191 | a993ba85 | bellard | |
192 | a993ba85 | bellard | /* This operand defaults to zero. This is used for jump hints. */
|
193 | a993ba85 | bellard | #define AXP_OPERAND_DEFAULT_ZERO 01000 |
194 | a993ba85 | bellard | |
195 | a993ba85 | bellard | /* This operand should default to the first (real) operand and is used
|
196 | a993ba85 | bellard | in conjunction with AXP_OPERAND_OPTIONAL. This allows
|
197 | a993ba85 | bellard | "and $0,3,$0" to be written as "and $0,3", etc. I don't like
|
198 | a993ba85 | bellard | it, but it's what DEC does. */
|
199 | a993ba85 | bellard | #define AXP_OPERAND_DEFAULT_FIRST 02000 |
200 | a993ba85 | bellard | |
201 | a993ba85 | bellard | /* Similarly, this operand should default to the second (real) operand.
|
202 | a993ba85 | bellard | This allows "negl $0" instead of "negl $0,$0". */
|
203 | a993ba85 | bellard | #define AXP_OPERAND_DEFAULT_SECOND 04000 |
204 | a993ba85 | bellard | |
205 | a993ba85 | bellard | |
206 | a993ba85 | bellard | /* Register common names */
|
207 | a993ba85 | bellard | |
208 | a993ba85 | bellard | #define AXP_REG_V0 0 |
209 | a993ba85 | bellard | #define AXP_REG_T0 1 |
210 | a993ba85 | bellard | #define AXP_REG_T1 2 |
211 | a993ba85 | bellard | #define AXP_REG_T2 3 |
212 | a993ba85 | bellard | #define AXP_REG_T3 4 |
213 | a993ba85 | bellard | #define AXP_REG_T4 5 |
214 | a993ba85 | bellard | #define AXP_REG_T5 6 |
215 | a993ba85 | bellard | #define AXP_REG_T6 7 |
216 | a993ba85 | bellard | #define AXP_REG_T7 8 |
217 | a993ba85 | bellard | #define AXP_REG_S0 9 |
218 | a993ba85 | bellard | #define AXP_REG_S1 10 |
219 | a993ba85 | bellard | #define AXP_REG_S2 11 |
220 | a993ba85 | bellard | #define AXP_REG_S3 12 |
221 | a993ba85 | bellard | #define AXP_REG_S4 13 |
222 | a993ba85 | bellard | #define AXP_REG_S5 14 |
223 | a993ba85 | bellard | #define AXP_REG_FP 15 |
224 | a993ba85 | bellard | #define AXP_REG_A0 16 |
225 | a993ba85 | bellard | #define AXP_REG_A1 17 |
226 | a993ba85 | bellard | #define AXP_REG_A2 18 |
227 | a993ba85 | bellard | #define AXP_REG_A3 19 |
228 | a993ba85 | bellard | #define AXP_REG_A4 20 |
229 | a993ba85 | bellard | #define AXP_REG_A5 21 |
230 | a993ba85 | bellard | #define AXP_REG_T8 22 |
231 | a993ba85 | bellard | #define AXP_REG_T9 23 |
232 | a993ba85 | bellard | #define AXP_REG_T10 24 |
233 | a993ba85 | bellard | #define AXP_REG_T11 25 |
234 | a993ba85 | bellard | #define AXP_REG_RA 26 |
235 | a993ba85 | bellard | #define AXP_REG_PV 27 |
236 | a993ba85 | bellard | #define AXP_REG_T12 27 |
237 | a993ba85 | bellard | #define AXP_REG_AT 28 |
238 | a993ba85 | bellard | #define AXP_REG_GP 29 |
239 | a993ba85 | bellard | #define AXP_REG_SP 30 |
240 | a993ba85 | bellard | #define AXP_REG_ZERO 31 |
241 | a993ba85 | bellard | |
242 | a993ba85 | bellard | #define bfd_mach_alpha_ev4 0x10 |
243 | a993ba85 | bellard | #define bfd_mach_alpha_ev5 0x20 |
244 | a993ba85 | bellard | #define bfd_mach_alpha_ev6 0x30 |
245 | a993ba85 | bellard | |
246 | a993ba85 | bellard | enum bfd_reloc_code_real {
|
247 | a993ba85 | bellard | BFD_RELOC_23_PCREL_S2, |
248 | a993ba85 | bellard | BFD_RELOC_ALPHA_HINT |
249 | a993ba85 | bellard | }; |
250 | a993ba85 | bellard | |
251 | a993ba85 | bellard | /* This file holds the Alpha AXP opcode table. The opcode table includes
|
252 | a993ba85 | bellard | almost all of the extended instruction mnemonics. This permits the
|
253 | a993ba85 | bellard | disassembler to use them, and simplifies the assembler logic, at the
|
254 | a993ba85 | bellard | cost of increasing the table size. The table is strictly constant
|
255 | a993ba85 | bellard | data, so the compiler should be able to put it in the text segment.
|
256 | a993ba85 | bellard | |
257 | a993ba85 | bellard | This file also holds the operand table. All knowledge about inserting
|
258 | a993ba85 | bellard | and extracting operands from instructions is kept in this file.
|
259 | a993ba85 | bellard | |
260 | a993ba85 | bellard | The information for the base instruction set was compiled from the
|
261 | a993ba85 | bellard | _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE,
|
262 | a993ba85 | bellard | version 2.
|
263 | a993ba85 | bellard | |
264 | a993ba85 | bellard | The information for the post-ev5 architecture extensions BWX, CIX and
|
265 | a993ba85 | bellard | MAX came from version 3 of this same document, which is also available
|
266 | a993ba85 | bellard | on-line at http://ftp.digital.com/pub/Digital/info/semiconductor
|
267 | a993ba85 | bellard | /literature/alphahb2.pdf
|
268 | a993ba85 | bellard | |
269 | a993ba85 | bellard | The information for the EV4 PALcode instructions was compiled from
|
270 | a993ba85 | bellard | _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware
|
271 | a993ba85 | bellard | Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary
|
272 | a993ba85 | bellard | revision dated June 1994.
|
273 | a993ba85 | bellard | |
274 | a993ba85 | bellard | The information for the EV5 PALcode instructions was compiled from
|
275 | a993ba85 | bellard | _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital
|
276 | a993ba85 | bellard | Order Number EC-QAEQB-TE, preliminary revision dated April 1995. */
|
277 | a993ba85 | bellard | |
278 | a993ba85 | bellard | /* Local insertion and extraction functions */
|
279 | a993ba85 | bellard | |
280 | a993ba85 | bellard | static unsigned insert_rba PARAMS((unsigned, int, const char **)); |
281 | a993ba85 | bellard | static unsigned insert_rca PARAMS((unsigned, int, const char **)); |
282 | a993ba85 | bellard | static unsigned insert_za PARAMS((unsigned, int, const char **)); |
283 | a993ba85 | bellard | static unsigned insert_zb PARAMS((unsigned, int, const char **)); |
284 | a993ba85 | bellard | static unsigned insert_zc PARAMS((unsigned, int, const char **)); |
285 | a993ba85 | bellard | static unsigned insert_bdisp PARAMS((unsigned, int, const char **)); |
286 | a993ba85 | bellard | static unsigned insert_jhint PARAMS((unsigned, int, const char **)); |
287 | a993ba85 | bellard | static unsigned insert_ev6hwjhint PARAMS((unsigned, int, const char **)); |
288 | a993ba85 | bellard | |
289 | a993ba85 | bellard | static int extract_rba PARAMS((unsigned, int *)); |
290 | a993ba85 | bellard | static int extract_rca PARAMS((unsigned, int *)); |
291 | a993ba85 | bellard | static int extract_za PARAMS((unsigned, int *)); |
292 | a993ba85 | bellard | static int extract_zb PARAMS((unsigned, int *)); |
293 | a993ba85 | bellard | static int extract_zc PARAMS((unsigned, int *)); |
294 | a993ba85 | bellard | static int extract_bdisp PARAMS((unsigned, int *)); |
295 | a993ba85 | bellard | static int extract_jhint PARAMS((unsigned, int *)); |
296 | a993ba85 | bellard | static int extract_ev6hwjhint PARAMS((unsigned, int *)); |
297 | a993ba85 | bellard | |
298 | a993ba85 | bellard | |
299 | a993ba85 | bellard | /* The operands table */
|
300 | a993ba85 | bellard | |
301 | a993ba85 | bellard | const struct alpha_operand alpha_operands[] = |
302 | a993ba85 | bellard | { |
303 | a993ba85 | bellard | /* The fields are bits, shift, insert, extract, flags */
|
304 | a993ba85 | bellard | /* The zero index is used to indicate end-of-list */
|
305 | a993ba85 | bellard | #define UNUSED 0 |
306 | a993ba85 | bellard | { 0, 0, 0, 0, 0, 0 }, |
307 | a993ba85 | bellard | |
308 | a993ba85 | bellard | /* The plain integer register fields */
|
309 | a993ba85 | bellard | #define RA (UNUSED + 1) |
310 | a993ba85 | bellard | { 5, 21, 0, AXP_OPERAND_IR, 0, 0 }, |
311 | a993ba85 | bellard | #define RB (RA + 1) |
312 | a993ba85 | bellard | { 5, 16, 0, AXP_OPERAND_IR, 0, 0 }, |
313 | a993ba85 | bellard | #define RC (RB + 1) |
314 | a993ba85 | bellard | { 5, 0, 0, AXP_OPERAND_IR, 0, 0 }, |
315 | a993ba85 | bellard | |
316 | a993ba85 | bellard | /* The plain fp register fields */
|
317 | a993ba85 | bellard | #define FA (RC + 1) |
318 | a993ba85 | bellard | { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 }, |
319 | a993ba85 | bellard | #define FB (FA + 1) |
320 | a993ba85 | bellard | { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 }, |
321 | a993ba85 | bellard | #define FC (FB + 1) |
322 | a993ba85 | bellard | { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 }, |
323 | a993ba85 | bellard | |
324 | a993ba85 | bellard | /* The integer registers when they are ZERO */
|
325 | a993ba85 | bellard | #define ZA (FC + 1) |
326 | a993ba85 | bellard | { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za }, |
327 | a993ba85 | bellard | #define ZB (ZA + 1) |
328 | a993ba85 | bellard | { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb }, |
329 | a993ba85 | bellard | #define ZC (ZB + 1) |
330 | a993ba85 | bellard | { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc }, |
331 | a993ba85 | bellard | |
332 | a993ba85 | bellard | /* The RB field when it needs parentheses */
|
333 | a993ba85 | bellard | #define PRB (ZC + 1) |
334 | a993ba85 | bellard | { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 }, |
335 | a993ba85 | bellard | |
336 | a993ba85 | bellard | /* The RB field when it needs parentheses _and_ a preceding comma */
|
337 | a993ba85 | bellard | #define CPRB (PRB + 1) |
338 | a993ba85 | bellard | { 5, 16, 0, |
339 | a993ba85 | bellard | AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 }, |
340 | a993ba85 | bellard | |
341 | a993ba85 | bellard | /* The RB field when it must be the same as the RA field */
|
342 | a993ba85 | bellard | #define RBA (CPRB + 1) |
343 | a993ba85 | bellard | { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba }, |
344 | a993ba85 | bellard | |
345 | a993ba85 | bellard | /* The RC field when it must be the same as the RB field */
|
346 | a993ba85 | bellard | #define RCA (RBA + 1) |
347 | a993ba85 | bellard | { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca }, |
348 | a993ba85 | bellard | |
349 | a993ba85 | bellard | /* The RC field when it can *default* to RA */
|
350 | a993ba85 | bellard | #define DRC1 (RCA + 1) |
351 | a993ba85 | bellard | { 5, 0, 0, |
352 | a993ba85 | bellard | AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, |
353 | a993ba85 | bellard | |
354 | a993ba85 | bellard | /* The RC field when it can *default* to RB */
|
355 | a993ba85 | bellard | #define DRC2 (DRC1 + 1) |
356 | a993ba85 | bellard | { 5, 0, 0, |
357 | a993ba85 | bellard | AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, |
358 | a993ba85 | bellard | |
359 | a993ba85 | bellard | /* The FC field when it can *default* to RA */
|
360 | a993ba85 | bellard | #define DFC1 (DRC2 + 1) |
361 | a993ba85 | bellard | { 5, 0, 0, |
362 | a993ba85 | bellard | AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, |
363 | a993ba85 | bellard | |
364 | a993ba85 | bellard | /* The FC field when it can *default* to RB */
|
365 | a993ba85 | bellard | #define DFC2 (DFC1 + 1) |
366 | a993ba85 | bellard | { 5, 0, 0, |
367 | a993ba85 | bellard | AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, |
368 | a993ba85 | bellard | |
369 | a993ba85 | bellard | /* The unsigned 8-bit literal of Operate format insns */
|
370 | a993ba85 | bellard | #define LIT (DFC2 + 1) |
371 | a993ba85 | bellard | { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 }, |
372 | a993ba85 | bellard | |
373 | a993ba85 | bellard | /* The signed 16-bit displacement of Memory format insns. From here
|
374 | a993ba85 | bellard | we can't tell what relocation should be used, so don't use a default. */
|
375 | a993ba85 | bellard | #define MDISP (LIT + 1) |
376 | a993ba85 | bellard | { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 }, |
377 | a993ba85 | bellard | |
378 | a993ba85 | bellard | /* The signed "23-bit" aligned displacement of Branch format insns */
|
379 | a993ba85 | bellard | #define BDISP (MDISP + 1) |
380 | a993ba85 | bellard | { 21, 0, BFD_RELOC_23_PCREL_S2, |
381 | a993ba85 | bellard | AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp }, |
382 | a993ba85 | bellard | |
383 | a993ba85 | bellard | /* The 26-bit PALcode function */
|
384 | a993ba85 | bellard | #define PALFN (BDISP + 1) |
385 | a993ba85 | bellard | { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 }, |
386 | a993ba85 | bellard | |
387 | a993ba85 | bellard | /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */
|
388 | a993ba85 | bellard | #define JMPHINT (PALFN + 1) |
389 | a993ba85 | bellard | { 14, 0, BFD_RELOC_ALPHA_HINT, |
390 | a993ba85 | bellard | AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, |
391 | a993ba85 | bellard | insert_jhint, extract_jhint }, |
392 | a993ba85 | bellard | |
393 | a993ba85 | bellard | /* The optional hint to RET/JSR_COROUTINE */
|
394 | a993ba85 | bellard | #define RETHINT (JMPHINT + 1) |
395 | a993ba85 | bellard | { 14, 0, -RETHINT, |
396 | a993ba85 | bellard | AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 }, |
397 | a993ba85 | bellard | |
398 | a993ba85 | bellard | /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns */
|
399 | a993ba85 | bellard | #define EV4HWDISP (RETHINT + 1) |
400 | a993ba85 | bellard | #define EV6HWDISP (EV4HWDISP)
|
401 | a993ba85 | bellard | { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, |
402 | a993ba85 | bellard | |
403 | a993ba85 | bellard | /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */
|
404 | a993ba85 | bellard | #define EV4HWINDEX (EV4HWDISP + 1) |
405 | a993ba85 | bellard | { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, |
406 | a993ba85 | bellard | |
407 | a993ba85 | bellard | /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns
|
408 | a993ba85 | bellard | that occur in DEC PALcode. */
|
409 | a993ba85 | bellard | #define EV4EXTHWINDEX (EV4HWINDEX + 1) |
410 | a993ba85 | bellard | { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, |
411 | a993ba85 | bellard | |
412 | a993ba85 | bellard | /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */
|
413 | a993ba85 | bellard | #define EV5HWDISP (EV4EXTHWINDEX + 1) |
414 | a993ba85 | bellard | { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, |
415 | a993ba85 | bellard | |
416 | a993ba85 | bellard | /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */
|
417 | a993ba85 | bellard | #define EV5HWINDEX (EV5HWDISP + 1) |
418 | a993ba85 | bellard | { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, |
419 | a993ba85 | bellard | |
420 | a993ba85 | bellard | /* The 16-bit combined index/scoreboard mask for the ev6
|
421 | a993ba85 | bellard | hw_m[ft]pr (pal19/pal1d) insns */
|
422 | a993ba85 | bellard | #define EV6HWINDEX (EV5HWINDEX + 1) |
423 | a993ba85 | bellard | { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, |
424 | a993ba85 | bellard | |
425 | a993ba85 | bellard | /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn */
|
426 | a993ba85 | bellard | #define EV6HWJMPHINT (EV6HWINDEX+ 1) |
427 | a993ba85 | bellard | { 8, 0, -EV6HWJMPHINT, |
428 | a993ba85 | bellard | AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, |
429 | a993ba85 | bellard | insert_ev6hwjhint, extract_ev6hwjhint } |
430 | a993ba85 | bellard | }; |
431 | a993ba85 | bellard | |
432 | a993ba85 | bellard | const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands); |
433 | a993ba85 | bellard | |
434 | a993ba85 | bellard | /* The RB field when it is the same as the RA field in the same insn.
|
435 | a993ba85 | bellard | This operand is marked fake. The insertion function just copies
|
436 | a993ba85 | bellard | the RA field into the RB field, and the extraction function just
|
437 | a993ba85 | bellard | checks that the fields are the same. */
|
438 | a993ba85 | bellard | |
439 | a993ba85 | bellard | /*ARGSUSED*/
|
440 | a993ba85 | bellard | static unsigned |
441 | a993ba85 | bellard | insert_rba(insn, value, errmsg) |
442 | a993ba85 | bellard | unsigned insn;
|
443 | a993ba85 | bellard | int value ATTRIBUTE_UNUSED;
|
444 | a993ba85 | bellard | const char **errmsg ATTRIBUTE_UNUSED; |
445 | a993ba85 | bellard | { |
446 | a993ba85 | bellard | return insn | (((insn >> 21) & 0x1f) << 16); |
447 | a993ba85 | bellard | } |
448 | a993ba85 | bellard | |
449 | a993ba85 | bellard | static int |
450 | a993ba85 | bellard | extract_rba(insn, invalid) |
451 | a993ba85 | bellard | unsigned insn;
|
452 | a993ba85 | bellard | int *invalid;
|
453 | a993ba85 | bellard | { |
454 | a993ba85 | bellard | if (invalid != (int *) NULL |
455 | a993ba85 | bellard | && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) |
456 | a993ba85 | bellard | *invalid = 1;
|
457 | a993ba85 | bellard | return 0; |
458 | a993ba85 | bellard | } |
459 | a993ba85 | bellard | |
460 | a993ba85 | bellard | |
461 | a993ba85 | bellard | /* The same for the RC field */
|
462 | a993ba85 | bellard | |
463 | a993ba85 | bellard | /*ARGSUSED*/
|
464 | a993ba85 | bellard | static unsigned |
465 | a993ba85 | bellard | insert_rca(insn, value, errmsg) |
466 | a993ba85 | bellard | unsigned insn;
|
467 | a993ba85 | bellard | int value ATTRIBUTE_UNUSED;
|
468 | a993ba85 | bellard | const char **errmsg ATTRIBUTE_UNUSED; |
469 | a993ba85 | bellard | { |
470 | a993ba85 | bellard | return insn | ((insn >> 21) & 0x1f); |
471 | a993ba85 | bellard | } |
472 | a993ba85 | bellard | |
473 | a993ba85 | bellard | static int |
474 | a993ba85 | bellard | extract_rca(insn, invalid) |
475 | a993ba85 | bellard | unsigned insn;
|
476 | a993ba85 | bellard | int *invalid;
|
477 | a993ba85 | bellard | { |
478 | a993ba85 | bellard | if (invalid != (int *) NULL |
479 | a993ba85 | bellard | && ((insn >> 21) & 0x1f) != (insn & 0x1f)) |
480 | a993ba85 | bellard | *invalid = 1;
|
481 | a993ba85 | bellard | return 0; |
482 | a993ba85 | bellard | } |
483 | a993ba85 | bellard | |
484 | a993ba85 | bellard | |
485 | a993ba85 | bellard | /* Fake arguments in which the registers must be set to ZERO */
|
486 | a993ba85 | bellard | |
487 | a993ba85 | bellard | /*ARGSUSED*/
|
488 | a993ba85 | bellard | static unsigned |
489 | a993ba85 | bellard | insert_za(insn, value, errmsg) |
490 | a993ba85 | bellard | unsigned insn;
|
491 | a993ba85 | bellard | int value ATTRIBUTE_UNUSED;
|
492 | a993ba85 | bellard | const char **errmsg ATTRIBUTE_UNUSED; |
493 | a993ba85 | bellard | { |
494 | a993ba85 | bellard | return insn | (31 << 21); |
495 | a993ba85 | bellard | } |
496 | a993ba85 | bellard | |
497 | a993ba85 | bellard | static int |
498 | a993ba85 | bellard | extract_za(insn, invalid) |
499 | a993ba85 | bellard | unsigned insn;
|
500 | a993ba85 | bellard | int *invalid;
|
501 | a993ba85 | bellard | { |
502 | a993ba85 | bellard | if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31) |
503 | a993ba85 | bellard | *invalid = 1;
|
504 | a993ba85 | bellard | return 0; |
505 | a993ba85 | bellard | } |
506 | a993ba85 | bellard | |
507 | a993ba85 | bellard | /*ARGSUSED*/
|
508 | a993ba85 | bellard | static unsigned |
509 | a993ba85 | bellard | insert_zb(insn, value, errmsg) |
510 | a993ba85 | bellard | unsigned insn;
|
511 | a993ba85 | bellard | int value ATTRIBUTE_UNUSED;
|
512 | a993ba85 | bellard | const char **errmsg ATTRIBUTE_UNUSED; |
513 | a993ba85 | bellard | { |
514 | a993ba85 | bellard | return insn | (31 << 16); |
515 | a993ba85 | bellard | } |
516 | a993ba85 | bellard | |
517 | a993ba85 | bellard | static int |
518 | a993ba85 | bellard | extract_zb(insn, invalid) |
519 | a993ba85 | bellard | unsigned insn;
|
520 | a993ba85 | bellard | int *invalid;
|
521 | a993ba85 | bellard | { |
522 | a993ba85 | bellard | if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31) |
523 | a993ba85 | bellard | *invalid = 1;
|
524 | a993ba85 | bellard | return 0; |
525 | a993ba85 | bellard | } |
526 | a993ba85 | bellard | |
527 | a993ba85 | bellard | /*ARGSUSED*/
|
528 | a993ba85 | bellard | static unsigned |
529 | a993ba85 | bellard | insert_zc(insn, value, errmsg) |
530 | a993ba85 | bellard | unsigned insn;
|
531 | a993ba85 | bellard | int value ATTRIBUTE_UNUSED;
|
532 | a993ba85 | bellard | const char **errmsg ATTRIBUTE_UNUSED; |
533 | a993ba85 | bellard | { |
534 | a993ba85 | bellard | return insn | 31; |
535 | a993ba85 | bellard | } |
536 | a993ba85 | bellard | |
537 | a993ba85 | bellard | static int |
538 | a993ba85 | bellard | extract_zc(insn, invalid) |
539 | a993ba85 | bellard | unsigned insn;
|
540 | a993ba85 | bellard | int *invalid;
|
541 | a993ba85 | bellard | { |
542 | a993ba85 | bellard | if (invalid != (int *) NULL && (insn & 0x1f) != 31) |
543 | a993ba85 | bellard | *invalid = 1;
|
544 | a993ba85 | bellard | return 0; |
545 | a993ba85 | bellard | } |
546 | a993ba85 | bellard | |
547 | a993ba85 | bellard | |
548 | a993ba85 | bellard | /* The displacement field of a Branch format insn. */
|
549 | a993ba85 | bellard | |
550 | a993ba85 | bellard | static unsigned |
551 | a993ba85 | bellard | insert_bdisp(insn, value, errmsg) |
552 | a993ba85 | bellard | unsigned insn;
|
553 | a993ba85 | bellard | int value;
|
554 | a993ba85 | bellard | const char **errmsg; |
555 | a993ba85 | bellard | { |
556 | a993ba85 | bellard | if (errmsg != (const char **)NULL && (value & 3)) |
557 | a993ba85 | bellard | *errmsg = _("branch operand unaligned");
|
558 | a993ba85 | bellard | return insn | ((value / 4) & 0x1FFFFF); |
559 | a993ba85 | bellard | } |
560 | a993ba85 | bellard | |
561 | a993ba85 | bellard | /*ARGSUSED*/
|
562 | a993ba85 | bellard | static int |
563 | a993ba85 | bellard | extract_bdisp(insn, invalid) |
564 | a993ba85 | bellard | unsigned insn;
|
565 | a993ba85 | bellard | int *invalid ATTRIBUTE_UNUSED;
|
566 | a993ba85 | bellard | { |
567 | a993ba85 | bellard | return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000); |
568 | a993ba85 | bellard | } |
569 | a993ba85 | bellard | |
570 | a993ba85 | bellard | |
571 | a993ba85 | bellard | /* The hint field of a JMP/JSR insn. */
|
572 | a993ba85 | bellard | |
573 | a993ba85 | bellard | static unsigned |
574 | a993ba85 | bellard | insert_jhint(insn, value, errmsg) |
575 | a993ba85 | bellard | unsigned insn;
|
576 | a993ba85 | bellard | int value;
|
577 | a993ba85 | bellard | const char **errmsg; |
578 | a993ba85 | bellard | { |
579 | a993ba85 | bellard | if (errmsg != (const char **)NULL && (value & 3)) |
580 | a993ba85 | bellard | *errmsg = _("jump hint unaligned");
|
581 | a993ba85 | bellard | return insn | ((value / 4) & 0x3FFF); |
582 | a993ba85 | bellard | } |
583 | a993ba85 | bellard | |
584 | a993ba85 | bellard | /*ARGSUSED*/
|
585 | a993ba85 | bellard | static int |
586 | a993ba85 | bellard | extract_jhint(insn, invalid) |
587 | a993ba85 | bellard | unsigned insn;
|
588 | a993ba85 | bellard | int *invalid ATTRIBUTE_UNUSED;
|
589 | a993ba85 | bellard | { |
590 | a993ba85 | bellard | return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000); |
591 | a993ba85 | bellard | } |
592 | a993ba85 | bellard | |
593 | a993ba85 | bellard | /* The hint field of an EV6 HW_JMP/JSR insn. */
|
594 | a993ba85 | bellard | |
595 | a993ba85 | bellard | static unsigned |
596 | a993ba85 | bellard | insert_ev6hwjhint(insn, value, errmsg) |
597 | a993ba85 | bellard | unsigned insn;
|
598 | a993ba85 | bellard | int value;
|
599 | a993ba85 | bellard | const char **errmsg; |
600 | a993ba85 | bellard | { |
601 | a993ba85 | bellard | if (errmsg != (const char **)NULL && (value & 3)) |
602 | a993ba85 | bellard | *errmsg = _("jump hint unaligned");
|
603 | a993ba85 | bellard | return insn | ((value / 4) & 0x1FFF); |
604 | a993ba85 | bellard | } |
605 | a993ba85 | bellard | |
606 | a993ba85 | bellard | /*ARGSUSED*/
|
607 | a993ba85 | bellard | static int |
608 | a993ba85 | bellard | extract_ev6hwjhint(insn, invalid) |
609 | a993ba85 | bellard | unsigned insn;
|
610 | a993ba85 | bellard | int *invalid ATTRIBUTE_UNUSED;
|
611 | a993ba85 | bellard | { |
612 | a993ba85 | bellard | return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000); |
613 | a993ba85 | bellard | } |
614 | a993ba85 | bellard | |
615 | a993ba85 | bellard | |
616 | a993ba85 | bellard | /* Macros used to form opcodes */
|
617 | a993ba85 | bellard | |
618 | a993ba85 | bellard | /* The main opcode */
|
619 | a993ba85 | bellard | #define OP(x) (((x) & 0x3F) << 26) |
620 | a993ba85 | bellard | #define OP_MASK 0xFC000000 |
621 | a993ba85 | bellard | |
622 | a993ba85 | bellard | /* Branch format instructions */
|
623 | a993ba85 | bellard | #define BRA_(oo) OP(oo)
|
624 | a993ba85 | bellard | #define BRA_MASK OP_MASK
|
625 | a993ba85 | bellard | #define BRA(oo) BRA_(oo), BRA_MASK
|
626 | a993ba85 | bellard | |
627 | a993ba85 | bellard | /* Floating point format instructions */
|
628 | a993ba85 | bellard | #define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5)) |
629 | a993ba85 | bellard | #define FP_MASK (OP_MASK | 0xFFE0) |
630 | a993ba85 | bellard | #define FP(oo,fff) FP_(oo,fff), FP_MASK
|
631 | a993ba85 | bellard | |
632 | a993ba85 | bellard | /* Memory format instructions */
|
633 | a993ba85 | bellard | #define MEM_(oo) OP(oo)
|
634 | a993ba85 | bellard | #define MEM_MASK OP_MASK
|
635 | a993ba85 | bellard | #define MEM(oo) MEM_(oo), MEM_MASK
|
636 | a993ba85 | bellard | |
637 | a993ba85 | bellard | /* Memory/Func Code format instructions */
|
638 | a993ba85 | bellard | #define MFC_(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF)) |
639 | a993ba85 | bellard | #define MFC_MASK (OP_MASK | 0xFFFF) |
640 | a993ba85 | bellard | #define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK
|
641 | a993ba85 | bellard | |
642 | a993ba85 | bellard | /* Memory/Branch format instructions */
|
643 | a993ba85 | bellard | #define MBR_(oo,h) (OP(oo) | (((h) & 3) << 14)) |
644 | a993ba85 | bellard | #define MBR_MASK (OP_MASK | 0xC000) |
645 | a993ba85 | bellard | #define MBR(oo,h) MBR_(oo,h), MBR_MASK
|
646 | a993ba85 | bellard | |
647 | a993ba85 | bellard | /* Operate format instructions. The OPRL variant specifies a
|
648 | a993ba85 | bellard | literal second argument. */
|
649 | a993ba85 | bellard | #define OPR_(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5)) |
650 | a993ba85 | bellard | #define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000) |
651 | a993ba85 | bellard | #define OPR_MASK (OP_MASK | 0x1FE0) |
652 | a993ba85 | bellard | #define OPR(oo,ff) OPR_(oo,ff), OPR_MASK
|
653 | a993ba85 | bellard | #define OPRL(oo,ff) OPRL_(oo,ff), OPR_MASK
|
654 | a993ba85 | bellard | |
655 | a993ba85 | bellard | /* Generic PALcode format instructions */
|
656 | a993ba85 | bellard | #define PCD_(oo) OP(oo)
|
657 | a993ba85 | bellard | #define PCD_MASK OP_MASK
|
658 | a993ba85 | bellard | #define PCD(oo) PCD_(oo), PCD_MASK
|
659 | a993ba85 | bellard | |
660 | a993ba85 | bellard | /* Specific PALcode instructions */
|
661 | a993ba85 | bellard | #define SPCD_(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF)) |
662 | a993ba85 | bellard | #define SPCD_MASK 0xFFFFFFFF |
663 | a993ba85 | bellard | #define SPCD(oo,ffff) SPCD_(oo,ffff), SPCD_MASK
|
664 | a993ba85 | bellard | |
665 | a993ba85 | bellard | /* Hardware memory (hw_{ld,st}) instructions */
|
666 | a993ba85 | bellard | #define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) |
667 | a993ba85 | bellard | #define EV4HWMEM_MASK (OP_MASK | 0xF000) |
668 | a993ba85 | bellard | #define EV4HWMEM(oo,f) EV4HWMEM_(oo,f), EV4HWMEM_MASK
|
669 | a993ba85 | bellard | |
670 | a993ba85 | bellard | #define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10)) |
671 | a993ba85 | bellard | #define EV5HWMEM_MASK (OP_MASK | 0xF800) |
672 | a993ba85 | bellard | #define EV5HWMEM(oo,f) EV5HWMEM_(oo,f), EV5HWMEM_MASK
|
673 | a993ba85 | bellard | |
674 | a993ba85 | bellard | #define EV6HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) |
675 | a993ba85 | bellard | #define EV6HWMEM_MASK (OP_MASK | 0xF000) |
676 | a993ba85 | bellard | #define EV6HWMEM(oo,f) EV6HWMEM_(oo,f), EV6HWMEM_MASK
|
677 | a993ba85 | bellard | |
678 | a993ba85 | bellard | #define EV6HWMBR_(oo,h) (OP(oo) | (((h) & 7) << 13)) |
679 | a993ba85 | bellard | #define EV6HWMBR_MASK (OP_MASK | 0xE000) |
680 | a993ba85 | bellard | #define EV6HWMBR(oo,h) EV6HWMBR_(oo,h), EV6HWMBR_MASK
|
681 | a993ba85 | bellard | |
682 | a993ba85 | bellard | /* Abbreviations for instruction subsets. */
|
683 | a993ba85 | bellard | #define BASE AXP_OPCODE_BASE
|
684 | a993ba85 | bellard | #define EV4 AXP_OPCODE_EV4
|
685 | a993ba85 | bellard | #define EV5 AXP_OPCODE_EV5
|
686 | a993ba85 | bellard | #define EV6 AXP_OPCODE_EV6
|
687 | a993ba85 | bellard | #define BWX AXP_OPCODE_BWX
|
688 | a993ba85 | bellard | #define CIX AXP_OPCODE_CIX
|
689 | a993ba85 | bellard | #define MAX AXP_OPCODE_MAX
|
690 | a993ba85 | bellard | |
691 | a993ba85 | bellard | /* Common combinations of arguments */
|
692 | a993ba85 | bellard | #define ARG_NONE { 0 } |
693 | a993ba85 | bellard | #define ARG_BRA { RA, BDISP }
|
694 | a993ba85 | bellard | #define ARG_FBRA { FA, BDISP }
|
695 | a993ba85 | bellard | #define ARG_FP { FA, FB, DFC1 }
|
696 | a993ba85 | bellard | #define ARG_FPZ1 { ZA, FB, DFC1 }
|
697 | a993ba85 | bellard | #define ARG_MEM { RA, MDISP, PRB }
|
698 | a993ba85 | bellard | #define ARG_FMEM { FA, MDISP, PRB }
|
699 | a993ba85 | bellard | #define ARG_OPR { RA, RB, DRC1 }
|
700 | a993ba85 | bellard | #define ARG_OPRL { RA, LIT, DRC1 }
|
701 | a993ba85 | bellard | #define ARG_OPRZ1 { ZA, RB, DRC1 }
|
702 | a993ba85 | bellard | #define ARG_OPRLZ1 { ZA, LIT, RC }
|
703 | a993ba85 | bellard | #define ARG_PCD { PALFN }
|
704 | a993ba85 | bellard | #define ARG_EV4HWMEM { RA, EV4HWDISP, PRB }
|
705 | a993ba85 | bellard | #define ARG_EV4HWMPR { RA, RBA, EV4HWINDEX }
|
706 | a993ba85 | bellard | #define ARG_EV5HWMEM { RA, EV5HWDISP, PRB }
|
707 | a993ba85 | bellard | #define ARG_EV6HWMEM { RA, EV6HWDISP, PRB }
|
708 | a993ba85 | bellard | |
709 | a993ba85 | bellard | /* The opcode table.
|
710 | a993ba85 | bellard | |
711 | a993ba85 | bellard | The format of the opcode table is:
|
712 | a993ba85 | bellard | |
713 | a993ba85 | bellard | NAME OPCODE MASK { OPERANDS }
|
714 | a993ba85 | bellard | |
715 | a993ba85 | bellard | NAME is the name of the instruction.
|
716 | a993ba85 | bellard | |
717 | a993ba85 | bellard | OPCODE is the instruction opcode.
|
718 | a993ba85 | bellard | |
719 | a993ba85 | bellard | MASK is the opcode mask; this is used to tell the disassembler
|
720 | a993ba85 | bellard | which bits in the actual opcode must match OPCODE.
|
721 | a993ba85 | bellard | |
722 | a993ba85 | bellard | OPERANDS is the list of operands.
|
723 | a993ba85 | bellard | |
724 | a993ba85 | bellard | The preceding macros merge the text of the OPCODE and MASK fields.
|
725 | a993ba85 | bellard | |
726 | a993ba85 | bellard | The disassembler reads the table in order and prints the first
|
727 | a993ba85 | bellard | instruction which matches, so this table is sorted to put more
|
728 | a993ba85 | bellard | specific instructions before more general instructions.
|
729 | a993ba85 | bellard | |
730 | a993ba85 | bellard | Otherwise, it is sorted by major opcode and minor function code.
|
731 | a993ba85 | bellard | |
732 | a993ba85 | bellard | There are three classes of not-really-instructions in this table:
|
733 | a993ba85 | bellard | |
734 | a993ba85 | bellard | ALIAS is another name for another instruction. Some of
|
735 | a993ba85 | bellard | these come from the Architecture Handbook, some
|
736 | a993ba85 | bellard | come from the original gas opcode tables. In all
|
737 | a993ba85 | bellard | cases, the functionality of the opcode is unchanged.
|
738 | a993ba85 | bellard | |
739 | a993ba85 | bellard | PSEUDO a stylized code form endorsed by Chapter A.4 of the
|
740 | a993ba85 | bellard | Architecture Handbook.
|
741 | a993ba85 | bellard | |
742 | a993ba85 | bellard | EXTRA a stylized code form found in the original gas tables.
|
743 | a993ba85 | bellard | |
744 | a993ba85 | bellard | And two annotations:
|
745 | a993ba85 | bellard | |
746 | a993ba85 | bellard | EV56 BUT opcodes that are officially introduced as of the ev56,
|
747 | a993ba85 | bellard | but with defined results on previous implementations.
|
748 | a993ba85 | bellard | |
749 | a993ba85 | bellard | EV56 UNA opcodes that were introduced as of the ev56 with
|
750 | a993ba85 | bellard | presumably undefined results on previous implementations
|
751 | a993ba85 | bellard | that were not assigned to a particular extension.
|
752 | a993ba85 | bellard | */
|
753 | a993ba85 | bellard | |
754 | a993ba85 | bellard | const struct alpha_opcode alpha_opcodes[] = { |
755 | a993ba85 | bellard | { "halt", SPCD(0x00,0x0000), BASE, ARG_NONE }, |
756 | a993ba85 | bellard | { "draina", SPCD(0x00,0x0002), BASE, ARG_NONE }, |
757 | a993ba85 | bellard | { "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE }, |
758 | a993ba85 | bellard | { "bugchk", SPCD(0x00,0x0081), BASE, ARG_NONE }, |
759 | a993ba85 | bellard | { "callsys", SPCD(0x00,0x0083), BASE, ARG_NONE }, |
760 | a993ba85 | bellard | { "chmk", SPCD(0x00,0x0083), BASE, ARG_NONE }, |
761 | a993ba85 | bellard | { "imb", SPCD(0x00,0x0086), BASE, ARG_NONE }, |
762 | a993ba85 | bellard | { "rduniq", SPCD(0x00,0x009e), BASE, ARG_NONE }, |
763 | a993ba85 | bellard | { "wruniq", SPCD(0x00,0x009f), BASE, ARG_NONE }, |
764 | a993ba85 | bellard | { "gentrap", SPCD(0x00,0x00aa), BASE, ARG_NONE }, |
765 | a993ba85 | bellard | { "call_pal", PCD(0x00), BASE, ARG_PCD }, |
766 | a993ba85 | bellard | { "pal", PCD(0x00), BASE, ARG_PCD }, /* alias */ |
767 | a993ba85 | bellard | |
768 | a993ba85 | bellard | { "lda", MEM(0x08), BASE, { RA, MDISP, ZB } }, /* pseudo */ |
769 | a993ba85 | bellard | { "lda", MEM(0x08), BASE, ARG_MEM }, |
770 | a993ba85 | bellard | { "ldah", MEM(0x09), BASE, { RA, MDISP, ZB } }, /* pseudo */ |
771 | a993ba85 | bellard | { "ldah", MEM(0x09), BASE, ARG_MEM }, |
772 | a993ba85 | bellard | { "ldbu", MEM(0x0A), BWX, ARG_MEM }, |
773 | a993ba85 | bellard | { "unop", MEM_(0x0B) | (30 << 16), |
774 | a993ba85 | bellard | MEM_MASK, BASE, { ZA } }, /* pseudo */
|
775 | a993ba85 | bellard | { "ldq_u", MEM(0x0B), BASE, ARG_MEM }, |
776 | a993ba85 | bellard | { "ldwu", MEM(0x0C), BWX, ARG_MEM }, |
777 | a993ba85 | bellard | { "stw", MEM(0x0D), BWX, ARG_MEM }, |
778 | a993ba85 | bellard | { "stb", MEM(0x0E), BWX, ARG_MEM }, |
779 | a993ba85 | bellard | { "stq_u", MEM(0x0F), BASE, ARG_MEM }, |
780 | a993ba85 | bellard | |
781 | a993ba85 | bellard | { "sextl", OPR(0x10,0x00), BASE, ARG_OPRZ1 }, /* pseudo */ |
782 | a993ba85 | bellard | { "sextl", OPRL(0x10,0x00), BASE, ARG_OPRLZ1 }, /* pseudo */ |
783 | a993ba85 | bellard | { "addl", OPR(0x10,0x00), BASE, ARG_OPR }, |
784 | a993ba85 | bellard | { "addl", OPRL(0x10,0x00), BASE, ARG_OPRL }, |
785 | a993ba85 | bellard | { "s4addl", OPR(0x10,0x02), BASE, ARG_OPR }, |
786 | a993ba85 | bellard | { "s4addl", OPRL(0x10,0x02), BASE, ARG_OPRL }, |
787 | a993ba85 | bellard | { "negl", OPR(0x10,0x09), BASE, ARG_OPRZ1 }, /* pseudo */ |
788 | a993ba85 | bellard | { "negl", OPRL(0x10,0x09), BASE, ARG_OPRLZ1 }, /* pseudo */ |
789 | a993ba85 | bellard | { "subl", OPR(0x10,0x09), BASE, ARG_OPR }, |
790 | a993ba85 | bellard | { "subl", OPRL(0x10,0x09), BASE, ARG_OPRL }, |
791 | a993ba85 | bellard | { "s4subl", OPR(0x10,0x0B), BASE, ARG_OPR }, |
792 | a993ba85 | bellard | { "s4subl", OPRL(0x10,0x0B), BASE, ARG_OPRL }, |
793 | a993ba85 | bellard | { "cmpbge", OPR(0x10,0x0F), BASE, ARG_OPR }, |
794 | a993ba85 | bellard | { "cmpbge", OPRL(0x10,0x0F), BASE, ARG_OPRL }, |
795 | a993ba85 | bellard | { "s8addl", OPR(0x10,0x12), BASE, ARG_OPR }, |
796 | a993ba85 | bellard | { "s8addl", OPRL(0x10,0x12), BASE, ARG_OPRL }, |
797 | a993ba85 | bellard | { "s8subl", OPR(0x10,0x1B), BASE, ARG_OPR }, |
798 | a993ba85 | bellard | { "s8subl", OPRL(0x10,0x1B), BASE, ARG_OPRL }, |
799 | a993ba85 | bellard | { "cmpult", OPR(0x10,0x1D), BASE, ARG_OPR }, |
800 | a993ba85 | bellard | { "cmpult", OPRL(0x10,0x1D), BASE, ARG_OPRL }, |
801 | a993ba85 | bellard | { "addq", OPR(0x10,0x20), BASE, ARG_OPR }, |
802 | a993ba85 | bellard | { "addq", OPRL(0x10,0x20), BASE, ARG_OPRL }, |
803 | a993ba85 | bellard | { "s4addq", OPR(0x10,0x22), BASE, ARG_OPR }, |
804 | a993ba85 | bellard | { "s4addq", OPRL(0x10,0x22), BASE, ARG_OPRL }, |
805 | a993ba85 | bellard | { "negq", OPR(0x10,0x29), BASE, ARG_OPRZ1 }, /* pseudo */ |
806 | a993ba85 | bellard | { "negq", OPRL(0x10,0x29), BASE, ARG_OPRLZ1 }, /* pseudo */ |
807 | a993ba85 | bellard | { "subq", OPR(0x10,0x29), BASE, ARG_OPR }, |
808 | a993ba85 | bellard | { "subq", OPRL(0x10,0x29), BASE, ARG_OPRL }, |
809 | a993ba85 | bellard | { "s4subq", OPR(0x10,0x2B), BASE, ARG_OPR }, |
810 | a993ba85 | bellard | { "s4subq", OPRL(0x10,0x2B), BASE, ARG_OPRL }, |
811 | a993ba85 | bellard | { "cmpeq", OPR(0x10,0x2D), BASE, ARG_OPR }, |
812 | a993ba85 | bellard | { "cmpeq", OPRL(0x10,0x2D), BASE, ARG_OPRL }, |
813 | a993ba85 | bellard | { "s8addq", OPR(0x10,0x32), BASE, ARG_OPR }, |
814 | a993ba85 | bellard | { "s8addq", OPRL(0x10,0x32), BASE, ARG_OPRL }, |
815 | a993ba85 | bellard | { "s8subq", OPR(0x10,0x3B), BASE, ARG_OPR }, |
816 | a993ba85 | bellard | { "s8subq", OPRL(0x10,0x3B), BASE, ARG_OPRL }, |
817 | a993ba85 | bellard | { "cmpule", OPR(0x10,0x3D), BASE, ARG_OPR }, |
818 | a993ba85 | bellard | { "cmpule", OPRL(0x10,0x3D), BASE, ARG_OPRL }, |
819 | a993ba85 | bellard | { "addl/v", OPR(0x10,0x40), BASE, ARG_OPR }, |
820 | a993ba85 | bellard | { "addl/v", OPRL(0x10,0x40), BASE, ARG_OPRL }, |
821 | a993ba85 | bellard | { "negl/v", OPR(0x10,0x49), BASE, ARG_OPRZ1 }, /* pseudo */ |
822 | a993ba85 | bellard | { "negl/v", OPRL(0x10,0x49), BASE, ARG_OPRLZ1 }, /* pseudo */ |
823 | a993ba85 | bellard | { "subl/v", OPR(0x10,0x49), BASE, ARG_OPR }, |
824 | a993ba85 | bellard | { "subl/v", OPRL(0x10,0x49), BASE, ARG_OPRL }, |
825 | a993ba85 | bellard | { "cmplt", OPR(0x10,0x4D), BASE, ARG_OPR }, |
826 | a993ba85 | bellard | { "cmplt", OPRL(0x10,0x4D), BASE, ARG_OPRL }, |
827 | a993ba85 | bellard | { "addq/v", OPR(0x10,0x60), BASE, ARG_OPR }, |
828 | a993ba85 | bellard | { "addq/v", OPRL(0x10,0x60), BASE, ARG_OPRL }, |
829 | a993ba85 | bellard | { "negq/v", OPR(0x10,0x69), BASE, ARG_OPRZ1 }, /* pseudo */ |
830 | a993ba85 | bellard | { "negq/v", OPRL(0x10,0x69), BASE, ARG_OPRLZ1 }, /* pseudo */ |
831 | a993ba85 | bellard | { "subq/v", OPR(0x10,0x69), BASE, ARG_OPR }, |
832 | a993ba85 | bellard | { "subq/v", OPRL(0x10,0x69), BASE, ARG_OPRL }, |
833 | a993ba85 | bellard | { "cmple", OPR(0x10,0x6D), BASE, ARG_OPR }, |
834 | a993ba85 | bellard | { "cmple", OPRL(0x10,0x6D), BASE, ARG_OPRL }, |
835 | a993ba85 | bellard | |
836 | a993ba85 | bellard | { "and", OPR(0x11,0x00), BASE, ARG_OPR }, |
837 | a993ba85 | bellard | { "and", OPRL(0x11,0x00), BASE, ARG_OPRL }, |
838 | a993ba85 | bellard | { "andnot", OPR(0x11,0x08), BASE, ARG_OPR }, /* alias */ |
839 | a993ba85 | bellard | { "andnot", OPRL(0x11,0x08), BASE, ARG_OPRL }, /* alias */ |
840 | a993ba85 | bellard | { "bic", OPR(0x11,0x08), BASE, ARG_OPR }, |
841 | a993ba85 | bellard | { "bic", OPRL(0x11,0x08), BASE, ARG_OPRL }, |
842 | a993ba85 | bellard | { "cmovlbs", OPR(0x11,0x14), BASE, ARG_OPR }, |
843 | a993ba85 | bellard | { "cmovlbs", OPRL(0x11,0x14), BASE, ARG_OPRL }, |
844 | a993ba85 | bellard | { "cmovlbc", OPR(0x11,0x16), BASE, ARG_OPR }, |
845 | a993ba85 | bellard | { "cmovlbc", OPRL(0x11,0x16), BASE, ARG_OPRL }, |
846 | a993ba85 | bellard | { "nop", OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */ |
847 | a993ba85 | bellard | { "clr", OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */ |
848 | a993ba85 | bellard | { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */ |
849 | a993ba85 | bellard | { "mov", OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */ |
850 | a993ba85 | bellard | { "mov", OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */ |
851 | a993ba85 | bellard | { "or", OPR(0x11,0x20), BASE, ARG_OPR }, /* alias */ |
852 | a993ba85 | bellard | { "or", OPRL(0x11,0x20), BASE, ARG_OPRL }, /* alias */ |
853 | a993ba85 | bellard | { "bis", OPR(0x11,0x20), BASE, ARG_OPR }, |
854 | a993ba85 | bellard | { "bis", OPRL(0x11,0x20), BASE, ARG_OPRL }, |
855 | a993ba85 | bellard | { "cmoveq", OPR(0x11,0x24), BASE, ARG_OPR }, |
856 | a993ba85 | bellard | { "cmoveq", OPRL(0x11,0x24), BASE, ARG_OPRL }, |
857 | a993ba85 | bellard | { "cmovne", OPR(0x11,0x26), BASE, ARG_OPR }, |
858 | a993ba85 | bellard | { "cmovne", OPRL(0x11,0x26), BASE, ARG_OPRL }, |
859 | a993ba85 | bellard | { "not", OPR(0x11,0x28), BASE, ARG_OPRZ1 }, /* pseudo */ |
860 | a993ba85 | bellard | { "not", OPRL(0x11,0x28), BASE, ARG_OPRLZ1 }, /* pseudo */ |
861 | a993ba85 | bellard | { "ornot", OPR(0x11,0x28), BASE, ARG_OPR }, |
862 | a993ba85 | bellard | { "ornot", OPRL(0x11,0x28), BASE, ARG_OPRL }, |
863 | a993ba85 | bellard | { "xor", OPR(0x11,0x40), BASE, ARG_OPR }, |
864 | a993ba85 | bellard | { "xor", OPRL(0x11,0x40), BASE, ARG_OPRL }, |
865 | a993ba85 | bellard | { "cmovlt", OPR(0x11,0x44), BASE, ARG_OPR }, |
866 | a993ba85 | bellard | { "cmovlt", OPRL(0x11,0x44), BASE, ARG_OPRL }, |
867 | a993ba85 | bellard | { "cmovge", OPR(0x11,0x46), BASE, ARG_OPR }, |
868 | a993ba85 | bellard | { "cmovge", OPRL(0x11,0x46), BASE, ARG_OPRL }, |
869 | a993ba85 | bellard | { "eqv", OPR(0x11,0x48), BASE, ARG_OPR }, |
870 | a993ba85 | bellard | { "eqv", OPRL(0x11,0x48), BASE, ARG_OPRL }, |
871 | a993ba85 | bellard | { "xornot", OPR(0x11,0x48), BASE, ARG_OPR }, /* alias */ |
872 | a993ba85 | bellard | { "xornot", OPRL(0x11,0x48), BASE, ARG_OPRL }, /* alias */ |
873 | a993ba85 | bellard | { "amask", OPR(0x11,0x61), BASE, ARG_OPRZ1 }, /* ev56 but */ |
874 | a993ba85 | bellard | { "amask", OPRL(0x11,0x61), BASE, ARG_OPRLZ1 }, /* ev56 but */ |
875 | a993ba85 | bellard | { "cmovle", OPR(0x11,0x64), BASE, ARG_OPR }, |
876 | a993ba85 | bellard | { "cmovle", OPRL(0x11,0x64), BASE, ARG_OPRL }, |
877 | a993ba85 | bellard | { "cmovgt", OPR(0x11,0x66), BASE, ARG_OPR }, |
878 | a993ba85 | bellard | { "cmovgt", OPRL(0x11,0x66), BASE, ARG_OPRL }, |
879 | a993ba85 | bellard | { "implver", OPRL_(0x11,0x6C)|(31<<21)|(1<<13), |
880 | a993ba85 | bellard | 0xFFFFFFE0, BASE, { RC } }, /* ev56 but */ |
881 | a993ba85 | bellard | |
882 | a993ba85 | bellard | { "mskbl", OPR(0x12,0x02), BASE, ARG_OPR }, |
883 | a993ba85 | bellard | { "mskbl", OPRL(0x12,0x02), BASE, ARG_OPRL }, |
884 | a993ba85 | bellard | { "extbl", OPR(0x12,0x06), BASE, ARG_OPR }, |
885 | a993ba85 | bellard | { "extbl", OPRL(0x12,0x06), BASE, ARG_OPRL }, |
886 | a993ba85 | bellard | { "insbl", OPR(0x12,0x0B), BASE, ARG_OPR }, |
887 | a993ba85 | bellard | { "insbl", OPRL(0x12,0x0B), BASE, ARG_OPRL }, |
888 | a993ba85 | bellard | { "mskwl", OPR(0x12,0x12), BASE, ARG_OPR }, |
889 | a993ba85 | bellard | { "mskwl", OPRL(0x12,0x12), BASE, ARG_OPRL }, |
890 | a993ba85 | bellard | { "extwl", OPR(0x12,0x16), BASE, ARG_OPR }, |
891 | a993ba85 | bellard | { "extwl", OPRL(0x12,0x16), BASE, ARG_OPRL }, |
892 | a993ba85 | bellard | { "inswl", OPR(0x12,0x1B), BASE, ARG_OPR }, |
893 | a993ba85 | bellard | { "inswl", OPRL(0x12,0x1B), BASE, ARG_OPRL }, |
894 | a993ba85 | bellard | { "mskll", OPR(0x12,0x22), BASE, ARG_OPR }, |
895 | a993ba85 | bellard | { "mskll", OPRL(0x12,0x22), BASE, ARG_OPRL }, |
896 | a993ba85 | bellard | { "extll", OPR(0x12,0x26), BASE, ARG_OPR }, |
897 | a993ba85 | bellard | { "extll", OPRL(0x12,0x26), BASE, ARG_OPRL }, |
898 | a993ba85 | bellard | { "insll", OPR(0x12,0x2B), BASE, ARG_OPR }, |
899 | a993ba85 | bellard | { "insll", OPRL(0x12,0x2B), BASE, ARG_OPRL }, |
900 | a993ba85 | bellard | { "zap", OPR(0x12,0x30), BASE, ARG_OPR }, |
901 | a993ba85 | bellard | { "zap", OPRL(0x12,0x30), BASE, ARG_OPRL }, |
902 | a993ba85 | bellard | { "zapnot", OPR(0x12,0x31), BASE, ARG_OPR }, |
903 | a993ba85 | bellard | { "zapnot", OPRL(0x12,0x31), BASE, ARG_OPRL }, |
904 | a993ba85 | bellard | { "mskql", OPR(0x12,0x32), BASE, ARG_OPR }, |
905 | a993ba85 | bellard | { "mskql", OPRL(0x12,0x32), BASE, ARG_OPRL }, |
906 | a993ba85 | bellard | { "srl", OPR(0x12,0x34), BASE, ARG_OPR }, |
907 | a993ba85 | bellard | { "srl", OPRL(0x12,0x34), BASE, ARG_OPRL }, |
908 | a993ba85 | bellard | { "extql", OPR(0x12,0x36), BASE, ARG_OPR }, |
909 | a993ba85 | bellard | { "extql", OPRL(0x12,0x36), BASE, ARG_OPRL }, |
910 | a993ba85 | bellard | { "sll", OPR(0x12,0x39), BASE, ARG_OPR }, |
911 | a993ba85 | bellard | { "sll", OPRL(0x12,0x39), BASE, ARG_OPRL }, |
912 | a993ba85 | bellard | { "insql", OPR(0x12,0x3B), BASE, ARG_OPR }, |
913 | a993ba85 | bellard | { "insql", OPRL(0x12,0x3B), BASE, ARG_OPRL }, |
914 | a993ba85 | bellard | { "sra", OPR(0x12,0x3C), BASE, ARG_OPR }, |
915 | a993ba85 | bellard | { "sra", OPRL(0x12,0x3C), BASE, ARG_OPRL }, |
916 | a993ba85 | bellard | { "mskwh", OPR(0x12,0x52), BASE, ARG_OPR }, |
917 | a993ba85 | bellard | { "mskwh", OPRL(0x12,0x52), BASE, ARG_OPRL }, |
918 | a993ba85 | bellard | { "inswh", OPR(0x12,0x57), BASE, ARG_OPR }, |
919 | a993ba85 | bellard | { "inswh", OPRL(0x12,0x57), BASE, ARG_OPRL }, |
920 | a993ba85 | bellard | { "extwh", OPR(0x12,0x5A), BASE, ARG_OPR }, |
921 | a993ba85 | bellard | { "extwh", OPRL(0x12,0x5A), BASE, ARG_OPRL }, |
922 | a993ba85 | bellard | { "msklh", OPR(0x12,0x62), BASE, ARG_OPR }, |
923 | a993ba85 | bellard | { "msklh", OPRL(0x12,0x62), BASE, ARG_OPRL }, |
924 | a993ba85 | bellard | { "inslh", OPR(0x12,0x67), BASE, ARG_OPR }, |
925 | a993ba85 | bellard | { "inslh", OPRL(0x12,0x67), BASE, ARG_OPRL }, |
926 | a993ba85 | bellard | { "extlh", OPR(0x12,0x6A), BASE, ARG_OPR }, |
927 | a993ba85 | bellard | { "extlh", OPRL(0x12,0x6A), BASE, ARG_OPRL }, |
928 | a993ba85 | bellard | { "mskqh", OPR(0x12,0x72), BASE, ARG_OPR }, |
929 | a993ba85 | bellard | { "mskqh", OPRL(0x12,0x72), BASE, ARG_OPRL }, |
930 | a993ba85 | bellard | { "insqh", OPR(0x12,0x77), BASE, ARG_OPR }, |
931 | a993ba85 | bellard | { "insqh", OPRL(0x12,0x77), BASE, ARG_OPRL }, |
932 | a993ba85 | bellard | { "extqh", OPR(0x12,0x7A), BASE, ARG_OPR }, |
933 | a993ba85 | bellard | { "extqh", OPRL(0x12,0x7A), BASE, ARG_OPRL }, |
934 | a993ba85 | bellard | |
935 | a993ba85 | bellard | { "mull", OPR(0x13,0x00), BASE, ARG_OPR }, |
936 | a993ba85 | bellard | { "mull", OPRL(0x13,0x00), BASE, ARG_OPRL }, |
937 | a993ba85 | bellard | { "mulq", OPR(0x13,0x20), BASE, ARG_OPR }, |
938 | a993ba85 | bellard | { "mulq", OPRL(0x13,0x20), BASE, ARG_OPRL }, |
939 | a993ba85 | bellard | { "umulh", OPR(0x13,0x30), BASE, ARG_OPR }, |
940 | a993ba85 | bellard | { "umulh", OPRL(0x13,0x30), BASE, ARG_OPRL }, |
941 | a993ba85 | bellard | { "mull/v", OPR(0x13,0x40), BASE, ARG_OPR }, |
942 | a993ba85 | bellard | { "mull/v", OPRL(0x13,0x40), BASE, ARG_OPRL }, |
943 | a993ba85 | bellard | { "mulq/v", OPR(0x13,0x60), BASE, ARG_OPR }, |
944 | a993ba85 | bellard | { "mulq/v", OPRL(0x13,0x60), BASE, ARG_OPRL }, |
945 | a993ba85 | bellard | |
946 | a993ba85 | bellard | { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } }, |
947 | a993ba85 | bellard | { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 }, |
948 | a993ba85 | bellard | { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 }, |
949 | a993ba85 | bellard | { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } }, |
950 | a993ba85 | bellard | { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } }, |
951 | a993ba85 | bellard | { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 }, |
952 | a993ba85 | bellard | { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 }, |
953 | a993ba85 | bellard | { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 }, |
954 | a993ba85 | bellard | { "sqrtt/m", FP(0x14,0x06B), CIX, ARG_FPZ1 }, |
955 | a993ba85 | bellard | { "sqrtf", FP(0x14,0x08A), CIX, ARG_FPZ1 }, |
956 | a993ba85 | bellard | { "sqrts", FP(0x14,0x08B), CIX, ARG_FPZ1 }, |
957 | a993ba85 | bellard | { "sqrtg", FP(0x14,0x0AA), CIX, ARG_FPZ1 }, |
958 | a993ba85 | bellard | { "sqrtt", FP(0x14,0x0AB), CIX, ARG_FPZ1 }, |
959 | a993ba85 | bellard | { "sqrts/d", FP(0x14,0x0CB), CIX, ARG_FPZ1 }, |
960 | a993ba85 | bellard | { "sqrtt/d", FP(0x14,0x0EB), CIX, ARG_FPZ1 }, |
961 | a993ba85 | bellard | { "sqrtf/uc", FP(0x14,0x10A), CIX, ARG_FPZ1 }, |
962 | a993ba85 | bellard | { "sqrts/uc", FP(0x14,0x10B), CIX, ARG_FPZ1 }, |
963 | a993ba85 | bellard | { "sqrtg/uc", FP(0x14,0x12A), CIX, ARG_FPZ1 }, |
964 | a993ba85 | bellard | { "sqrtt/uc", FP(0x14,0x12B), CIX, ARG_FPZ1 }, |
965 | a993ba85 | bellard | { "sqrts/um", FP(0x14,0x14B), CIX, ARG_FPZ1 }, |
966 | a993ba85 | bellard | { "sqrtt/um", FP(0x14,0x16B), CIX, ARG_FPZ1 }, |
967 | a993ba85 | bellard | { "sqrtf/u", FP(0x14,0x18A), CIX, ARG_FPZ1 }, |
968 | a993ba85 | bellard | { "sqrts/u", FP(0x14,0x18B), CIX, ARG_FPZ1 }, |
969 | a993ba85 | bellard | { "sqrtg/u", FP(0x14,0x1AA), CIX, ARG_FPZ1 }, |
970 | a993ba85 | bellard | { "sqrtt/u", FP(0x14,0x1AB), CIX, ARG_FPZ1 }, |
971 | a993ba85 | bellard | { "sqrts/ud", FP(0x14,0x1CB), CIX, ARG_FPZ1 }, |
972 | a993ba85 | bellard | { "sqrtt/ud", FP(0x14,0x1EB), CIX, ARG_FPZ1 }, |
973 | a993ba85 | bellard | { "sqrtf/sc", FP(0x14,0x40A), CIX, ARG_FPZ1 }, |
974 | a993ba85 | bellard | { "sqrtg/sc", FP(0x14,0x42A), CIX, ARG_FPZ1 }, |
975 | a993ba85 | bellard | { "sqrtf/s", FP(0x14,0x48A), CIX, ARG_FPZ1 }, |
976 | a993ba85 | bellard | { "sqrtg/s", FP(0x14,0x4AA), CIX, ARG_FPZ1 }, |
977 | a993ba85 | bellard | { "sqrtf/suc", FP(0x14,0x50A), CIX, ARG_FPZ1 }, |
978 | a993ba85 | bellard | { "sqrts/suc", FP(0x14,0x50B), CIX, ARG_FPZ1 }, |
979 | a993ba85 | bellard | { "sqrtg/suc", FP(0x14,0x52A), CIX, ARG_FPZ1 }, |
980 | a993ba85 | bellard | { "sqrtt/suc", FP(0x14,0x52B), CIX, ARG_FPZ1 }, |
981 | a993ba85 | bellard | { "sqrts/sum", FP(0x14,0x54B), CIX, ARG_FPZ1 }, |
982 | a993ba85 | bellard | { "sqrtt/sum", FP(0x14,0x56B), CIX, ARG_FPZ1 }, |
983 | a993ba85 | bellard | { "sqrtf/su", FP(0x14,0x58A), CIX, ARG_FPZ1 }, |
984 | a993ba85 | bellard | { "sqrts/su", FP(0x14,0x58B), CIX, ARG_FPZ1 }, |
985 | a993ba85 | bellard | { "sqrtg/su", FP(0x14,0x5AA), CIX, ARG_FPZ1 }, |
986 | a993ba85 | bellard | { "sqrtt/su", FP(0x14,0x5AB), CIX, ARG_FPZ1 }, |
987 | a993ba85 | bellard | { "sqrts/sud", FP(0x14,0x5CB), CIX, ARG_FPZ1 }, |
988 | a993ba85 | bellard | { "sqrtt/sud", FP(0x14,0x5EB), CIX, ARG_FPZ1 }, |
989 | a993ba85 | bellard | { "sqrts/suic", FP(0x14,0x70B), CIX, ARG_FPZ1 }, |
990 | a993ba85 | bellard | { "sqrtt/suic", FP(0x14,0x72B), CIX, ARG_FPZ1 }, |
991 | a993ba85 | bellard | { "sqrts/suim", FP(0x14,0x74B), CIX, ARG_FPZ1 }, |
992 | a993ba85 | bellard | { "sqrtt/suim", FP(0x14,0x76B), CIX, ARG_FPZ1 }, |
993 | a993ba85 | bellard | { "sqrts/sui", FP(0x14,0x78B), CIX, ARG_FPZ1 }, |
994 | a993ba85 | bellard | { "sqrtt/sui", FP(0x14,0x7AB), CIX, ARG_FPZ1 }, |
995 | a993ba85 | bellard | { "sqrts/suid", FP(0x14,0x7CB), CIX, ARG_FPZ1 }, |
996 | a993ba85 | bellard | { "sqrtt/suid", FP(0x14,0x7EB), CIX, ARG_FPZ1 }, |
997 | a993ba85 | bellard | |
998 | a993ba85 | bellard | { "addf/c", FP(0x15,0x000), BASE, ARG_FP }, |
999 | a993ba85 | bellard | { "subf/c", FP(0x15,0x001), BASE, ARG_FP }, |
1000 | a993ba85 | bellard | { "mulf/c", FP(0x15,0x002), BASE, ARG_FP }, |
1001 | a993ba85 | bellard | { "divf/c", FP(0x15,0x003), BASE, ARG_FP }, |
1002 | a993ba85 | bellard | { "cvtdg/c", FP(0x15,0x01E), BASE, ARG_FPZ1 }, |
1003 | a993ba85 | bellard | { "addg/c", FP(0x15,0x020), BASE, ARG_FP }, |
1004 | a993ba85 | bellard | { "subg/c", FP(0x15,0x021), BASE, ARG_FP }, |
1005 | a993ba85 | bellard | { "mulg/c", FP(0x15,0x022), BASE, ARG_FP }, |
1006 | a993ba85 | bellard | { "divg/c", FP(0x15,0x023), BASE, ARG_FP }, |
1007 | a993ba85 | bellard | { "cvtgf/c", FP(0x15,0x02C), BASE, ARG_FPZ1 }, |
1008 | a993ba85 | bellard | { "cvtgd/c", FP(0x15,0x02D), BASE, ARG_FPZ1 }, |
1009 | a993ba85 | bellard | { "cvtgq/c", FP(0x15,0x02F), BASE, ARG_FPZ1 }, |
1010 | a993ba85 | bellard | { "cvtqf/c", FP(0x15,0x03C), BASE, ARG_FPZ1 }, |
1011 | a993ba85 | bellard | { "cvtqg/c", FP(0x15,0x03E), BASE, ARG_FPZ1 }, |
1012 | a993ba85 | bellard | { "addf", FP(0x15,0x080), BASE, ARG_FP }, |
1013 | a993ba85 | bellard | { "negf", FP(0x15,0x081), BASE, ARG_FPZ1 }, /* pseudo */ |
1014 | a993ba85 | bellard | { "subf", FP(0x15,0x081), BASE, ARG_FP }, |
1015 | a993ba85 | bellard | { "mulf", FP(0x15,0x082), BASE, ARG_FP }, |
1016 | a993ba85 | bellard | { "divf", FP(0x15,0x083), BASE, ARG_FP }, |
1017 | a993ba85 | bellard | { "cvtdg", FP(0x15,0x09E), BASE, ARG_FPZ1 }, |
1018 | a993ba85 | bellard | { "addg", FP(0x15,0x0A0), BASE, ARG_FP }, |
1019 | a993ba85 | bellard | { "negg", FP(0x15,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ |
1020 | a993ba85 | bellard | { "subg", FP(0x15,0x0A1), BASE, ARG_FP }, |
1021 | a993ba85 | bellard | { "mulg", FP(0x15,0x0A2), BASE, ARG_FP }, |
1022 | a993ba85 | bellard | { "divg", FP(0x15,0x0A3), BASE, ARG_FP }, |
1023 | a993ba85 | bellard | { "cmpgeq", FP(0x15,0x0A5), BASE, ARG_FP }, |
1024 | a993ba85 | bellard | { "cmpglt", FP(0x15,0x0A6), BASE, ARG_FP }, |
1025 | a993ba85 | bellard | { "cmpgle", FP(0x15,0x0A7), BASE, ARG_FP }, |
1026 | a993ba85 | bellard | { "cvtgf", FP(0x15,0x0AC), BASE, ARG_FPZ1 }, |
1027 | a993ba85 | bellard | { "cvtgd", FP(0x15,0x0AD), BASE, ARG_FPZ1 }, |
1028 | a993ba85 | bellard | { "cvtgq", FP(0x15,0x0AF), BASE, ARG_FPZ1 }, |
1029 | a993ba85 | bellard | { "cvtqf", FP(0x15,0x0BC), BASE, ARG_FPZ1 }, |
1030 | a993ba85 | bellard | { "cvtqg", FP(0x15,0x0BE), BASE, ARG_FPZ1 }, |
1031 | a993ba85 | bellard | { "addf/uc", FP(0x15,0x100), BASE, ARG_FP }, |
1032 | a993ba85 | bellard | { "subf/uc", FP(0x15,0x101), BASE, ARG_FP }, |
1033 | a993ba85 | bellard | { "mulf/uc", FP(0x15,0x102), BASE, ARG_FP }, |
1034 | a993ba85 | bellard | { "divf/uc", FP(0x15,0x103), BASE, ARG_FP }, |
1035 | a993ba85 | bellard | { "cvtdg/uc", FP(0x15,0x11E), BASE, ARG_FPZ1 }, |
1036 | a993ba85 | bellard | { "addg/uc", FP(0x15,0x120), BASE, ARG_FP }, |
1037 | a993ba85 | bellard | { "subg/uc", FP(0x15,0x121), BASE, ARG_FP }, |
1038 | a993ba85 | bellard | { "mulg/uc", FP(0x15,0x122), BASE, ARG_FP }, |
1039 | a993ba85 | bellard | { "divg/uc", FP(0x15,0x123), BASE, ARG_FP }, |
1040 | a993ba85 | bellard | { "cvtgf/uc", FP(0x15,0x12C), BASE, ARG_FPZ1 }, |
1041 | a993ba85 | bellard | { "cvtgd/uc", FP(0x15,0x12D), BASE, ARG_FPZ1 }, |
1042 | a993ba85 | bellard | { "cvtgq/vc", FP(0x15,0x12F), BASE, ARG_FPZ1 }, |
1043 | a993ba85 | bellard | { "addf/u", FP(0x15,0x180), BASE, ARG_FP }, |
1044 | a993ba85 | bellard | { "subf/u", FP(0x15,0x181), BASE, ARG_FP }, |
1045 | a993ba85 | bellard | { "mulf/u", FP(0x15,0x182), BASE, ARG_FP }, |
1046 | a993ba85 | bellard | { "divf/u", FP(0x15,0x183), BASE, ARG_FP }, |
1047 | a993ba85 | bellard | { "cvtdg/u", FP(0x15,0x19E), BASE, ARG_FPZ1 }, |
1048 | a993ba85 | bellard | { "addg/u", FP(0x15,0x1A0), BASE, ARG_FP }, |
1049 | a993ba85 | bellard | { "subg/u", FP(0x15,0x1A1), BASE, ARG_FP }, |
1050 | a993ba85 | bellard | { "mulg/u", FP(0x15,0x1A2), BASE, ARG_FP }, |
1051 | a993ba85 | bellard | { "divg/u", FP(0x15,0x1A3), BASE, ARG_FP }, |
1052 | a993ba85 | bellard | { "cvtgf/u", FP(0x15,0x1AC), BASE, ARG_FPZ1 }, |
1053 | a993ba85 | bellard | { "cvtgd/u", FP(0x15,0x1AD), BASE, ARG_FPZ1 }, |
1054 | a993ba85 | bellard | { "cvtgq/v", FP(0x15,0x1AF), BASE, ARG_FPZ1 }, |
1055 | a993ba85 | bellard | { "addf/sc", FP(0x15,0x400), BASE, ARG_FP }, |
1056 | a993ba85 | bellard | { "subf/sc", FP(0x15,0x401), BASE, ARG_FP }, |
1057 | a993ba85 | bellard | { "mulf/sc", FP(0x15,0x402), BASE, ARG_FP }, |
1058 | a993ba85 | bellard | { "divf/sc", FP(0x15,0x403), BASE, ARG_FP }, |
1059 | a993ba85 | bellard | { "cvtdg/sc", FP(0x15,0x41E), BASE, ARG_FPZ1 }, |
1060 | a993ba85 | bellard | { "addg/sc", FP(0x15,0x420), BASE, ARG_FP }, |
1061 | a993ba85 | bellard | { "subg/sc", FP(0x15,0x421), BASE, ARG_FP }, |
1062 | a993ba85 | bellard | { "mulg/sc", FP(0x15,0x422), BASE, ARG_FP }, |
1063 | a993ba85 | bellard | { "divg/sc", FP(0x15,0x423), BASE, ARG_FP }, |
1064 | a993ba85 | bellard | { "cvtgf/sc", FP(0x15,0x42C), BASE, ARG_FPZ1 }, |
1065 | a993ba85 | bellard | { "cvtgd/sc", FP(0x15,0x42D), BASE, ARG_FPZ1 }, |
1066 | a993ba85 | bellard | { "cvtgq/sc", FP(0x15,0x42F), BASE, ARG_FPZ1 }, |
1067 | a993ba85 | bellard | { "addf/s", FP(0x15,0x480), BASE, ARG_FP }, |
1068 | a993ba85 | bellard | { "negf/s", FP(0x15,0x481), BASE, ARG_FPZ1 }, /* pseudo */ |
1069 | a993ba85 | bellard | { "subf/s", FP(0x15,0x481), BASE, ARG_FP }, |
1070 | a993ba85 | bellard | { "mulf/s", FP(0x15,0x482), BASE, ARG_FP }, |
1071 | a993ba85 | bellard | { "divf/s", FP(0x15,0x483), BASE, ARG_FP }, |
1072 | a993ba85 | bellard | { "cvtdg/s", FP(0x15,0x49E), BASE, ARG_FPZ1 }, |
1073 | a993ba85 | bellard | { "addg/s", FP(0x15,0x4A0), BASE, ARG_FP }, |
1074 | a993ba85 | bellard | { "negg/s", FP(0x15,0x4A1), BASE, ARG_FPZ1 }, /* pseudo */ |
1075 | a993ba85 | bellard | { "subg/s", FP(0x15,0x4A1), BASE, ARG_FP }, |
1076 | a993ba85 | bellard | { "mulg/s", FP(0x15,0x4A2), BASE, ARG_FP }, |
1077 | a993ba85 | bellard | { "divg/s", FP(0x15,0x4A3), BASE, ARG_FP }, |
1078 | a993ba85 | bellard | { "cmpgeq/s", FP(0x15,0x4A5), BASE, ARG_FP }, |
1079 | a993ba85 | bellard | { "cmpglt/s", FP(0x15,0x4A6), BASE, ARG_FP }, |
1080 | a993ba85 | bellard | { "cmpgle/s", FP(0x15,0x4A7), BASE, ARG_FP }, |
1081 | a993ba85 | bellard | { "cvtgf/s", FP(0x15,0x4AC), BASE, ARG_FPZ1 }, |
1082 | a993ba85 | bellard | { "cvtgd/s", FP(0x15,0x4AD), BASE, ARG_FPZ1 }, |
1083 | a993ba85 | bellard | { "cvtgq/s", FP(0x15,0x4AF), BASE, ARG_FPZ1 }, |
1084 | a993ba85 | bellard | { "addf/suc", FP(0x15,0x500), BASE, ARG_FP }, |
1085 | a993ba85 | bellard | { "subf/suc", FP(0x15,0x501), BASE, ARG_FP }, |
1086 | a993ba85 | bellard | { "mulf/suc", FP(0x15,0x502), BASE, ARG_FP }, |
1087 | a993ba85 | bellard | { "divf/suc", FP(0x15,0x503), BASE, ARG_FP }, |
1088 | a993ba85 | bellard | { "cvtdg/suc", FP(0x15,0x51E), BASE, ARG_FPZ1 }, |
1089 | a993ba85 | bellard | { "addg/suc", FP(0x15,0x520), BASE, ARG_FP }, |
1090 | a993ba85 | bellard | { "subg/suc", FP(0x15,0x521), BASE, ARG_FP }, |
1091 | a993ba85 | bellard | { "mulg/suc", FP(0x15,0x522), BASE, ARG_FP }, |
1092 | a993ba85 | bellard | { "divg/suc", FP(0x15,0x523), BASE, ARG_FP }, |
1093 | a993ba85 | bellard | { "cvtgf/suc", FP(0x15,0x52C), BASE, ARG_FPZ1 }, |
1094 | a993ba85 | bellard | { "cvtgd/suc", FP(0x15,0x52D), BASE, ARG_FPZ1 }, |
1095 | a993ba85 | bellard | { "cvtgq/svc", FP(0x15,0x52F), BASE, ARG_FPZ1 }, |
1096 | a993ba85 | bellard | { "addf/su", FP(0x15,0x580), BASE, ARG_FP }, |
1097 | a993ba85 | bellard | { "subf/su", FP(0x15,0x581), BASE, ARG_FP }, |
1098 | a993ba85 | bellard | { "mulf/su", FP(0x15,0x582), BASE, ARG_FP }, |
1099 | a993ba85 | bellard | { "divf/su", FP(0x15,0x583), BASE, ARG_FP }, |
1100 | a993ba85 | bellard | { "cvtdg/su", FP(0x15,0x59E), BASE, ARG_FPZ1 }, |
1101 | a993ba85 | bellard | { "addg/su", FP(0x15,0x5A0), BASE, ARG_FP }, |
1102 | a993ba85 | bellard | { "subg/su", FP(0x15,0x5A1), BASE, ARG_FP }, |
1103 | a993ba85 | bellard | { "mulg/su", FP(0x15,0x5A2), BASE, ARG_FP }, |
1104 | a993ba85 | bellard | { "divg/su", FP(0x15,0x5A3), BASE, ARG_FP }, |
1105 | a993ba85 | bellard | { "cvtgf/su", FP(0x15,0x5AC), BASE, ARG_FPZ1 }, |
1106 | a993ba85 | bellard | { "cvtgd/su", FP(0x15,0x5AD), BASE, ARG_FPZ1 }, |
1107 | a993ba85 | bellard | { "cvtgq/sv", FP(0x15,0x5AF), BASE, ARG_FPZ1 }, |
1108 | a993ba85 | bellard | |
1109 | a993ba85 | bellard | { "adds/c", FP(0x16,0x000), BASE, ARG_FP }, |
1110 | a993ba85 | bellard | { "subs/c", FP(0x16,0x001), BASE, ARG_FP }, |
1111 | a993ba85 | bellard | { "muls/c", FP(0x16,0x002), BASE, ARG_FP }, |
1112 | a993ba85 | bellard | { "divs/c", FP(0x16,0x003), BASE, ARG_FP }, |
1113 | a993ba85 | bellard | { "addt/c", FP(0x16,0x020), BASE, ARG_FP }, |
1114 | a993ba85 | bellard | { "subt/c", FP(0x16,0x021), BASE, ARG_FP }, |
1115 | a993ba85 | bellard | { "mult/c", FP(0x16,0x022), BASE, ARG_FP }, |
1116 | a993ba85 | bellard | { "divt/c", FP(0x16,0x023), BASE, ARG_FP }, |
1117 | a993ba85 | bellard | { "cvtts/c", FP(0x16,0x02C), BASE, ARG_FPZ1 }, |
1118 | a993ba85 | bellard | { "cvttq/c", FP(0x16,0x02F), BASE, ARG_FPZ1 }, |
1119 | a993ba85 | bellard | { "cvtqs/c", FP(0x16,0x03C), BASE, ARG_FPZ1 }, |
1120 | a993ba85 | bellard | { "cvtqt/c", FP(0x16,0x03E), BASE, ARG_FPZ1 }, |
1121 | a993ba85 | bellard | { "adds/m", FP(0x16,0x040), BASE, ARG_FP }, |
1122 | a993ba85 | bellard | { "subs/m", FP(0x16,0x041), BASE, ARG_FP }, |
1123 | a993ba85 | bellard | { "muls/m", FP(0x16,0x042), BASE, ARG_FP }, |
1124 | a993ba85 | bellard | { "divs/m", FP(0x16,0x043), BASE, ARG_FP }, |
1125 | a993ba85 | bellard | { "addt/m", FP(0x16,0x060), BASE, ARG_FP }, |
1126 | a993ba85 | bellard | { "subt/m", FP(0x16,0x061), BASE, ARG_FP }, |
1127 | a993ba85 | bellard | { "mult/m", FP(0x16,0x062), BASE, ARG_FP }, |
1128 | a993ba85 | bellard | { "divt/m", FP(0x16,0x063), BASE, ARG_FP }, |
1129 | a993ba85 | bellard | { "cvtts/m", FP(0x16,0x06C), BASE, ARG_FPZ1 }, |
1130 | a993ba85 | bellard | { "cvttq/m", FP(0x16,0x06F), BASE, ARG_FPZ1 }, |
1131 | a993ba85 | bellard | { "cvtqs/m", FP(0x16,0x07C), BASE, ARG_FPZ1 }, |
1132 | a993ba85 | bellard | { "cvtqt/m", FP(0x16,0x07E), BASE, ARG_FPZ1 }, |
1133 | a993ba85 | bellard | { "adds", FP(0x16,0x080), BASE, ARG_FP }, |
1134 | a993ba85 | bellard | { "negs", FP(0x16,0x081), BASE, ARG_FPZ1 }, /* pseudo */ |
1135 | a993ba85 | bellard | { "subs", FP(0x16,0x081), BASE, ARG_FP }, |
1136 | a993ba85 | bellard | { "muls", FP(0x16,0x082), BASE, ARG_FP }, |
1137 | a993ba85 | bellard | { "divs", FP(0x16,0x083), BASE, ARG_FP }, |
1138 | a993ba85 | bellard | { "addt", FP(0x16,0x0A0), BASE, ARG_FP }, |
1139 | a993ba85 | bellard | { "negt", FP(0x16,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ |
1140 | a993ba85 | bellard | { "subt", FP(0x16,0x0A1), BASE, ARG_FP }, |
1141 | a993ba85 | bellard | { "mult", FP(0x16,0x0A2), BASE, ARG_FP }, |
1142 | a993ba85 | bellard | { "divt", FP(0x16,0x0A3), BASE, ARG_FP }, |
1143 | a993ba85 | bellard | { "cmptun", FP(0x16,0x0A4), BASE, ARG_FP }, |
1144 | a993ba85 | bellard | { "cmpteq", FP(0x16,0x0A5), BASE, ARG_FP }, |
1145 | a993ba85 | bellard | { "cmptlt", FP(0x16,0x0A6), BASE, ARG_FP }, |
1146 | a993ba85 | bellard | { "cmptle", FP(0x16,0x0A7), BASE, ARG_FP }, |
1147 | a993ba85 | bellard | { "cvtts", FP(0x16,0x0AC), BASE, ARG_FPZ1 }, |
1148 | a993ba85 | bellard | { "cvttq", FP(0x16,0x0AF), BASE, ARG_FPZ1 }, |
1149 | a993ba85 | bellard | { "cvtqs", FP(0x16,0x0BC), BASE, ARG_FPZ1 }, |
1150 | a993ba85 | bellard | { "cvtqt", FP(0x16,0x0BE), BASE, ARG_FPZ1 }, |
1151 | a993ba85 | bellard | { "adds/d", FP(0x16,0x0C0), BASE, ARG_FP }, |
1152 | a993ba85 | bellard | { "subs/d", FP(0x16,0x0C1), BASE, ARG_FP }, |
1153 | a993ba85 | bellard | { "muls/d", FP(0x16,0x0C2), BASE, ARG_FP }, |
1154 | a993ba85 | bellard | { "divs/d", FP(0x16,0x0C3), BASE, ARG_FP }, |
1155 | a993ba85 | bellard | { "addt/d", FP(0x16,0x0E0), BASE, ARG_FP }, |
1156 | a993ba85 | bellard | { "subt/d", FP(0x16,0x0E1), BASE, ARG_FP }, |
1157 | a993ba85 | bellard | { "mult/d", FP(0x16,0x0E2), BASE, ARG_FP }, |
1158 | a993ba85 | bellard | { "divt/d", FP(0x16,0x0E3), BASE, ARG_FP }, |
1159 | a993ba85 | bellard | { "cvtts/d", FP(0x16,0x0EC), BASE, ARG_FPZ1 }, |
1160 | a993ba85 | bellard | { "cvttq/d", FP(0x16,0x0EF), BASE, ARG_FPZ1 }, |
1161 | a993ba85 | bellard | { "cvtqs/d", FP(0x16,0x0FC), BASE, ARG_FPZ1 }, |
1162 | a993ba85 | bellard | { "cvtqt/d", FP(0x16,0x0FE), BASE, ARG_FPZ1 }, |
1163 | a993ba85 | bellard | { "adds/uc", FP(0x16,0x100), BASE, ARG_FP }, |
1164 | a993ba85 | bellard | { "subs/uc", FP(0x16,0x101), BASE, ARG_FP }, |
1165 | a993ba85 | bellard | { "muls/uc", FP(0x16,0x102), BASE, ARG_FP }, |
1166 | a993ba85 | bellard | { "divs/uc", FP(0x16,0x103), BASE, ARG_FP }, |
1167 | a993ba85 | bellard | { "addt/uc", FP(0x16,0x120), BASE, ARG_FP }, |
1168 | a993ba85 | bellard | { "subt/uc", FP(0x16,0x121), BASE, ARG_FP }, |
1169 | a993ba85 | bellard | { "mult/uc", FP(0x16,0x122), BASE, ARG_FP }, |
1170 | a993ba85 | bellard | { "divt/uc", FP(0x16,0x123), BASE, ARG_FP }, |
1171 | a993ba85 | bellard | { "cvtts/uc", FP(0x16,0x12C), BASE, ARG_FPZ1 }, |
1172 | a993ba85 | bellard | { "cvttq/vc", FP(0x16,0x12F), BASE, ARG_FPZ1 }, |
1173 | a993ba85 | bellard | { "adds/um", FP(0x16,0x140), BASE, ARG_FP }, |
1174 | a993ba85 | bellard | { "subs/um", FP(0x16,0x141), BASE, ARG_FP }, |
1175 | a993ba85 | bellard | { "muls/um", FP(0x16,0x142), BASE, ARG_FP }, |
1176 | a993ba85 | bellard | { "divs/um", FP(0x16,0x143), BASE, ARG_FP }, |
1177 | a993ba85 | bellard | { "addt/um", FP(0x16,0x160), BASE, ARG_FP }, |
1178 | a993ba85 | bellard | { "subt/um", FP(0x16,0x161), BASE, ARG_FP }, |
1179 | a993ba85 | bellard | { "mult/um", FP(0x16,0x162), BASE, ARG_FP }, |
1180 | a993ba85 | bellard | { "divt/um", FP(0x16,0x163), BASE, ARG_FP }, |
1181 | a993ba85 | bellard | { "cvtts/um", FP(0x16,0x16C), BASE, ARG_FPZ1 }, |
1182 | a993ba85 | bellard | { "cvttq/vm", FP(0x16,0x16F), BASE, ARG_FPZ1 }, |
1183 | a993ba85 | bellard | { "adds/u", FP(0x16,0x180), BASE, ARG_FP }, |
1184 | a993ba85 | bellard | { "subs/u", FP(0x16,0x181), BASE, ARG_FP }, |
1185 | a993ba85 | bellard | { "muls/u", FP(0x16,0x182), BASE, ARG_FP }, |
1186 | a993ba85 | bellard | { "divs/u", FP(0x16,0x183), BASE, ARG_FP }, |
1187 | a993ba85 | bellard | { "addt/u", FP(0x16,0x1A0), BASE, ARG_FP }, |
1188 | a993ba85 | bellard | { "subt/u", FP(0x16,0x1A1), BASE, ARG_FP }, |
1189 | a993ba85 | bellard | { "mult/u", FP(0x16,0x1A2), BASE, ARG_FP }, |
1190 | a993ba85 | bellard | { "divt/u", FP(0x16,0x1A3), BASE, ARG_FP }, |
1191 | a993ba85 | bellard | { "cvtts/u", FP(0x16,0x1AC), BASE, ARG_FPZ1 }, |
1192 | a993ba85 | bellard | { "cvttq/v", FP(0x16,0x1AF), BASE, ARG_FPZ1 }, |
1193 | a993ba85 | bellard | { "adds/ud", FP(0x16,0x1C0), BASE, ARG_FP }, |
1194 | a993ba85 | bellard | { "subs/ud", FP(0x16,0x1C1), BASE, ARG_FP }, |
1195 | a993ba85 | bellard | { "muls/ud", FP(0x16,0x1C2), BASE, ARG_FP }, |
1196 | a993ba85 | bellard | { "divs/ud", FP(0x16,0x1C3), BASE, ARG_FP }, |
1197 | a993ba85 | bellard | { "addt/ud", FP(0x16,0x1E0), BASE, ARG_FP }, |
1198 | a993ba85 | bellard | { "subt/ud", FP(0x16,0x1E1), BASE, ARG_FP }, |
1199 | a993ba85 | bellard | { "mult/ud", FP(0x16,0x1E2), BASE, ARG_FP }, |
1200 | a993ba85 | bellard | { "divt/ud", FP(0x16,0x1E3), BASE, ARG_FP }, |
1201 | a993ba85 | bellard | { "cvtts/ud", FP(0x16,0x1EC), BASE, ARG_FPZ1 }, |
1202 | a993ba85 | bellard | { "cvttq/vd", FP(0x16,0x1EF), BASE, ARG_FPZ1 }, |
1203 | a993ba85 | bellard | { "cvtst", FP(0x16,0x2AC), BASE, ARG_FPZ1 }, |
1204 | a993ba85 | bellard | { "adds/suc", FP(0x16,0x500), BASE, ARG_FP }, |
1205 | a993ba85 | bellard | { "subs/suc", FP(0x16,0x501), BASE, ARG_FP }, |
1206 | a993ba85 | bellard | { "muls/suc", FP(0x16,0x502), BASE, ARG_FP }, |
1207 | a993ba85 | bellard | { "divs/suc", FP(0x16,0x503), BASE, ARG_FP }, |
1208 | a993ba85 | bellard | { "addt/suc", FP(0x16,0x520), BASE, ARG_FP }, |
1209 | a993ba85 | bellard | { "subt/suc", FP(0x16,0x521), BASE, ARG_FP }, |
1210 | a993ba85 | bellard | { "mult/suc", FP(0x16,0x522), BASE, ARG_FP }, |
1211 | a993ba85 | bellard | { "divt/suc", FP(0x16,0x523), BASE, ARG_FP }, |
1212 | a993ba85 | bellard | { "cvtts/suc", FP(0x16,0x52C), BASE, ARG_FPZ1 }, |
1213 | a993ba85 | bellard | { "cvttq/svc", FP(0x16,0x52F), BASE, ARG_FPZ1 }, |
1214 | a993ba85 | bellard | { "adds/sum", FP(0x16,0x540), BASE, ARG_FP }, |
1215 | a993ba85 | bellard | { "subs/sum", FP(0x16,0x541), BASE, ARG_FP }, |
1216 | a993ba85 | bellard | { "muls/sum", FP(0x16,0x542), BASE, ARG_FP }, |
1217 | a993ba85 | bellard | { "divs/sum", FP(0x16,0x543), BASE, ARG_FP }, |
1218 | a993ba85 | bellard | { "addt/sum", FP(0x16,0x560), BASE, ARG_FP }, |
1219 | a993ba85 | bellard | { "subt/sum", FP(0x16,0x561), BASE, ARG_FP }, |
1220 | a993ba85 | bellard | { "mult/sum", FP(0x16,0x562), BASE, ARG_FP }, |
1221 | a993ba85 | bellard | { "divt/sum", FP(0x16,0x563), BASE, ARG_FP }, |
1222 | a993ba85 | bellard | { "cvtts/sum", FP(0x16,0x56C), BASE, ARG_FPZ1 }, |
1223 | a993ba85 | bellard | { "cvttq/svm", FP(0x16,0x56F), BASE, ARG_FPZ1 }, |
1224 | a993ba85 | bellard | { "adds/su", FP(0x16,0x580), BASE, ARG_FP }, |
1225 | a993ba85 | bellard | { "negs/su", FP(0x16,0x581), BASE, ARG_FPZ1 }, /* pseudo */ |
1226 | a993ba85 | bellard | { "subs/su", FP(0x16,0x581), BASE, ARG_FP }, |
1227 | a993ba85 | bellard | { "muls/su", FP(0x16,0x582), BASE, ARG_FP }, |
1228 | a993ba85 | bellard | { "divs/su", FP(0x16,0x583), BASE, ARG_FP }, |
1229 | a993ba85 | bellard | { "addt/su", FP(0x16,0x5A0), BASE, ARG_FP }, |
1230 | a993ba85 | bellard | { "negt/su", FP(0x16,0x5A1), BASE, ARG_FPZ1 }, /* pseudo */ |
1231 | a993ba85 | bellard | { "subt/su", FP(0x16,0x5A1), BASE, ARG_FP }, |
1232 | a993ba85 | bellard | { "mult/su", FP(0x16,0x5A2), BASE, ARG_FP }, |
1233 | a993ba85 | bellard | { "divt/su", FP(0x16,0x5A3), BASE, ARG_FP }, |
1234 | a993ba85 | bellard | { "cmptun/su", FP(0x16,0x5A4), BASE, ARG_FP }, |
1235 | a993ba85 | bellard | { "cmpteq/su", FP(0x16,0x5A5), BASE, ARG_FP }, |
1236 | a993ba85 | bellard | { "cmptlt/su", FP(0x16,0x5A6), BASE, ARG_FP }, |
1237 | a993ba85 | bellard | { "cmptle/su", FP(0x16,0x5A7), BASE, ARG_FP }, |
1238 | a993ba85 | bellard | { "cvtts/su", FP(0x16,0x5AC), BASE, ARG_FPZ1 }, |
1239 | a993ba85 | bellard | { "cvttq/sv", FP(0x16,0x5AF), BASE, ARG_FPZ1 }, |
1240 | a993ba85 | bellard | { "adds/sud", FP(0x16,0x5C0), BASE, ARG_FP }, |
1241 | a993ba85 | bellard | { "subs/sud", FP(0x16,0x5C1), BASE, ARG_FP }, |
1242 | a993ba85 | bellard | { "muls/sud", FP(0x16,0x5C2), BASE, ARG_FP }, |
1243 | a993ba85 | bellard | { "divs/sud", FP(0x16,0x5C3), BASE, ARG_FP }, |
1244 | a993ba85 | bellard | { "addt/sud", FP(0x16,0x5E0), BASE, ARG_FP }, |
1245 | a993ba85 | bellard | { "subt/sud", FP(0x16,0x5E1), BASE, ARG_FP }, |
1246 | a993ba85 | bellard | { "mult/sud", FP(0x16,0x5E2), BASE, ARG_FP }, |
1247 | a993ba85 | bellard | { "divt/sud", FP(0x16,0x5E3), BASE, ARG_FP }, |
1248 | a993ba85 | bellard | { "cvtts/sud", FP(0x16,0x5EC), BASE, ARG_FPZ1 }, |
1249 | a993ba85 | bellard | { "cvttq/svd", FP(0x16,0x5EF), BASE, ARG_FPZ1 }, |
1250 | a993ba85 | bellard | { "cvtst/s", FP(0x16,0x6AC), BASE, ARG_FPZ1 }, |
1251 | a993ba85 | bellard | { "adds/suic", FP(0x16,0x700), BASE, ARG_FP }, |
1252 | a993ba85 | bellard | { "subs/suic", FP(0x16,0x701), BASE, ARG_FP }, |
1253 | a993ba85 | bellard | { "muls/suic", FP(0x16,0x702), BASE, ARG_FP }, |
1254 | a993ba85 | bellard | { "divs/suic", FP(0x16,0x703), BASE, ARG_FP }, |
1255 | a993ba85 | bellard | { "addt/suic", FP(0x16,0x720), BASE, ARG_FP }, |
1256 | a993ba85 | bellard | { "subt/suic", FP(0x16,0x721), BASE, ARG_FP }, |
1257 | a993ba85 | bellard | { "mult/suic", FP(0x16,0x722), BASE, ARG_FP }, |
1258 | a993ba85 | bellard | { "divt/suic", FP(0x16,0x723), BASE, ARG_FP }, |
1259 | a993ba85 | bellard | { "cvtts/suic", FP(0x16,0x72C), BASE, ARG_FPZ1 }, |
1260 | a993ba85 | bellard | { "cvttq/svic", FP(0x16,0x72F), BASE, ARG_FPZ1 }, |
1261 | a993ba85 | bellard | { "cvtqs/suic", FP(0x16,0x73C), BASE, ARG_FPZ1 }, |
1262 | a993ba85 | bellard | { "cvtqt/suic", FP(0x16,0x73E), BASE, ARG_FPZ1 }, |
1263 | a993ba85 | bellard | { "adds/suim", FP(0x16,0x740), BASE, ARG_FP }, |
1264 | a993ba85 | bellard | { "subs/suim", FP(0x16,0x741), BASE, ARG_FP }, |
1265 | a993ba85 | bellard | { "muls/suim", FP(0x16,0x742), BASE, ARG_FP }, |
1266 | a993ba85 | bellard | { "divs/suim", FP(0x16,0x743), BASE, ARG_FP }, |
1267 | a993ba85 | bellard | { "addt/suim", FP(0x16,0x760), BASE, ARG_FP }, |
1268 | a993ba85 | bellard | { "subt/suim", FP(0x16,0x761), BASE, ARG_FP }, |
1269 | a993ba85 | bellard | { "mult/suim", FP(0x16,0x762), BASE, ARG_FP }, |
1270 | a993ba85 | bellard | { "divt/suim", FP(0x16,0x763), BASE, ARG_FP }, |
1271 | a993ba85 | bellard | { "cvtts/suim", FP(0x16,0x76C), BASE, ARG_FPZ1 }, |
1272 | a993ba85 | bellard | { "cvttq/svim", FP(0x16,0x76F), BASE, ARG_FPZ1 }, |
1273 | a993ba85 | bellard | { "cvtqs/suim", FP(0x16,0x77C), BASE, ARG_FPZ1 }, |
1274 | a993ba85 | bellard | { "cvtqt/suim", FP(0x16,0x77E), BASE, ARG_FPZ1 }, |
1275 | a993ba85 | bellard | { "adds/sui", FP(0x16,0x780), BASE, ARG_FP }, |
1276 | a993ba85 | bellard | { "negs/sui", FP(0x16,0x781), BASE, ARG_FPZ1 }, /* pseudo */ |
1277 | a993ba85 | bellard | { "subs/sui", FP(0x16,0x781), BASE, ARG_FP }, |
1278 | a993ba85 | bellard | { "muls/sui", FP(0x16,0x782), BASE, ARG_FP }, |
1279 | a993ba85 | bellard | { "divs/sui", FP(0x16,0x783), BASE, ARG_FP }, |
1280 | a993ba85 | bellard | { "addt/sui", FP(0x16,0x7A0), BASE, ARG_FP }, |
1281 | a993ba85 | bellard | { "negt/sui", FP(0x16,0x7A1), BASE, ARG_FPZ1 }, /* pseudo */ |
1282 | a993ba85 | bellard | { "subt/sui", FP(0x16,0x7A1), BASE, ARG_FP }, |
1283 | a993ba85 | bellard | { "mult/sui", FP(0x16,0x7A2), BASE, ARG_FP }, |
1284 | a993ba85 | bellard | { "divt/sui", FP(0x16,0x7A3), BASE, ARG_FP }, |
1285 | a993ba85 | bellard | { "cvtts/sui", FP(0x16,0x7AC), BASE, ARG_FPZ1 }, |
1286 | a993ba85 | bellard | { "cvttq/svi", FP(0x16,0x7AF), BASE, ARG_FPZ1 }, |
1287 | a993ba85 | bellard | { "cvtqs/sui", FP(0x16,0x7BC), BASE, ARG_FPZ1 }, |
1288 | a993ba85 | bellard | { "cvtqt/sui", FP(0x16,0x7BE), BASE, ARG_FPZ1 }, |
1289 | a993ba85 | bellard | { "adds/suid", FP(0x16,0x7C0), BASE, ARG_FP }, |
1290 | a993ba85 | bellard | { "subs/suid", FP(0x16,0x7C1), BASE, ARG_FP }, |
1291 | a993ba85 | bellard | { "muls/suid", FP(0x16,0x7C2), BASE, ARG_FP }, |
1292 | a993ba85 | bellard | { "divs/suid", FP(0x16,0x7C3), BASE, ARG_FP }, |
1293 | a993ba85 | bellard | { "addt/suid", FP(0x16,0x7E0), BASE, ARG_FP }, |
1294 | a993ba85 | bellard | { "subt/suid", FP(0x16,0x7E1), BASE, ARG_FP }, |
1295 | a993ba85 | bellard | { "mult/suid", FP(0x16,0x7E2), BASE, ARG_FP }, |
1296 | a993ba85 | bellard | { "divt/suid", FP(0x16,0x7E3), BASE, ARG_FP }, |
1297 | a993ba85 | bellard | { "cvtts/suid", FP(0x16,0x7EC), BASE, ARG_FPZ1 }, |
1298 | a993ba85 | bellard | { "cvttq/svid", FP(0x16,0x7EF), BASE, ARG_FPZ1 }, |
1299 | a993ba85 | bellard | { "cvtqs/suid", FP(0x16,0x7FC), BASE, ARG_FPZ1 }, |
1300 | a993ba85 | bellard | { "cvtqt/suid", FP(0x16,0x7FE), BASE, ARG_FPZ1 }, |
1301 | a993ba85 | bellard | |
1302 | a993ba85 | bellard | { "cvtlq", FP(0x17,0x010), BASE, ARG_FPZ1 }, |
1303 | a993ba85 | bellard | { "fnop", FP(0x17,0x020), BASE, { ZA, ZB, ZC } }, /* pseudo */ |
1304 | a993ba85 | bellard | { "fclr", FP(0x17,0x020), BASE, { ZA, ZB, FC } }, /* pseudo */ |
1305 | a993ba85 | bellard | { "fabs", FP(0x17,0x020), BASE, ARG_FPZ1 }, /* pseudo */ |
1306 | a993ba85 | bellard | { "fmov", FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */ |
1307 | a993ba85 | bellard | { "cpys", FP(0x17,0x020), BASE, ARG_FP }, |
1308 | a993ba85 | bellard | { "fneg", FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */ |
1309 | a993ba85 | bellard | { "cpysn", FP(0x17,0x021), BASE, ARG_FP }, |
1310 | a993ba85 | bellard | { "cpyse", FP(0x17,0x022), BASE, ARG_FP }, |
1311 | a993ba85 | bellard | { "mt_fpcr", FP(0x17,0x024), BASE, { FA, RBA, RCA } }, |
1312 | a993ba85 | bellard | { "mf_fpcr", FP(0x17,0x025), BASE, { FA, RBA, RCA } }, |
1313 | a993ba85 | bellard | { "fcmoveq", FP(0x17,0x02A), BASE, ARG_FP }, |
1314 | a993ba85 | bellard | { "fcmovne", FP(0x17,0x02B), BASE, ARG_FP }, |
1315 | a993ba85 | bellard | { "fcmovlt", FP(0x17,0x02C), BASE, ARG_FP }, |
1316 | a993ba85 | bellard | { "fcmovge", FP(0x17,0x02D), BASE, ARG_FP }, |
1317 | a993ba85 | bellard | { "fcmovle", FP(0x17,0x02E), BASE, ARG_FP }, |
1318 | a993ba85 | bellard | { "fcmovgt", FP(0x17,0x02F), BASE, ARG_FP }, |
1319 | a993ba85 | bellard | { "cvtql", FP(0x17,0x030), BASE, ARG_FPZ1 }, |
1320 | a993ba85 | bellard | { "cvtql/v", FP(0x17,0x130), BASE, ARG_FPZ1 }, |
1321 | a993ba85 | bellard | { "cvtql/sv", FP(0x17,0x530), BASE, ARG_FPZ1 }, |
1322 | a993ba85 | bellard | |
1323 | a993ba85 | bellard | { "trapb", MFC(0x18,0x0000), BASE, ARG_NONE }, |
1324 | a993ba85 | bellard | { "draint", MFC(0x18,0x0000), BASE, ARG_NONE }, /* alias */ |
1325 | a993ba85 | bellard | { "excb", MFC(0x18,0x0400), BASE, ARG_NONE }, |
1326 | a993ba85 | bellard | { "mb", MFC(0x18,0x4000), BASE, ARG_NONE }, |
1327 | a993ba85 | bellard | { "wmb", MFC(0x18,0x4400), BASE, ARG_NONE }, |
1328 | a993ba85 | bellard | { "fetch", MFC(0x18,0x8000), BASE, { ZA, PRB } }, |
1329 | a993ba85 | bellard | { "fetch_m", MFC(0x18,0xA000), BASE, { ZA, PRB } }, |
1330 | a993ba85 | bellard | { "rpcc", MFC(0x18,0xC000), BASE, { RA } }, |
1331 | a993ba85 | bellard | { "rc", MFC(0x18,0xE000), BASE, { RA } }, |
1332 | a993ba85 | bellard | { "ecb", MFC(0x18,0xE800), BASE, { ZA, PRB } }, /* ev56 una */ |
1333 | a993ba85 | bellard | { "rs", MFC(0x18,0xF000), BASE, { RA } }, |
1334 | a993ba85 | bellard | { "wh64", MFC(0x18,0xF800), BASE, { ZA, PRB } }, /* ev56 una */ |
1335 | a993ba85 | bellard | { "wh64en", MFC(0x18,0xFC00), BASE, { ZA, PRB } }, /* ev7 una */ |
1336 | a993ba85 | bellard | |
1337 | a993ba85 | bellard | { "hw_mfpr", OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, |
1338 | a993ba85 | bellard | { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, |
1339 | a993ba85 | bellard | { "hw_mfpr", OP(0x19), OP_MASK, EV6, { RA, ZB, EV6HWINDEX } }, |
1340 | a993ba85 | bellard | { "hw_mfpr/i", OPR(0x19,0x01), EV4, ARG_EV4HWMPR }, |
1341 | a993ba85 | bellard | { "hw_mfpr/a", OPR(0x19,0x02), EV4, ARG_EV4HWMPR }, |
1342 | a993ba85 | bellard | { "hw_mfpr/ai", OPR(0x19,0x03), EV4, ARG_EV4HWMPR }, |
1343 | a993ba85 | bellard | { "hw_mfpr/p", OPR(0x19,0x04), EV4, ARG_EV4HWMPR }, |
1344 | a993ba85 | bellard | { "hw_mfpr/pi", OPR(0x19,0x05), EV4, ARG_EV4HWMPR }, |
1345 | a993ba85 | bellard | { "hw_mfpr/pa", OPR(0x19,0x06), EV4, ARG_EV4HWMPR }, |
1346 | a993ba85 | bellard | { "hw_mfpr/pai", OPR(0x19,0x07), EV4, ARG_EV4HWMPR }, |
1347 | a993ba85 | bellard | { "pal19", PCD(0x19), BASE, ARG_PCD }, |
1348 | a993ba85 | bellard | |
1349 | a993ba85 | bellard | { "jmp", MBR_(0x1A,0), MBR_MASK | 0x3FFF, /* pseudo */ |
1350 | a993ba85 | bellard | BASE, { ZA, CPRB } }, |
1351 | a993ba85 | bellard | { "jmp", MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } }, |
1352 | a993ba85 | bellard | { "jsr", MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } }, |
1353 | a993ba85 | bellard | { "ret", MBR_(0x1A,2) | (31 << 21) | (26 << 16) | 1,/* pseudo */ |
1354 | a993ba85 | bellard | 0xFFFFFFFF, BASE, { 0 } }, |
1355 | a993ba85 | bellard | { "ret", MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } }, |
1356 | a993ba85 | bellard | { "jcr", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */ |
1357 | a993ba85 | bellard | { "jsr_coroutine", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, |
1358 | a993ba85 | bellard | |
1359 | a993ba85 | bellard | { "hw_ldl", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, |
1360 | a993ba85 | bellard | { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, |
1361 | a993ba85 | bellard | { "hw_ldl", EV6HWMEM(0x1B,0x8), EV6, ARG_EV6HWMEM }, |
1362 | a993ba85 | bellard | { "hw_ldl/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, |
1363 | a993ba85 | bellard | { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, |
1364 | a993ba85 | bellard | { "hw_ldl/a", EV6HWMEM(0x1B,0xC), EV6, ARG_EV6HWMEM }, |
1365 | a993ba85 | bellard | { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, |
1366 | a993ba85 | bellard | { "hw_ldl/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, |
1367 | a993ba85 | bellard | { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, |
1368 | a993ba85 | bellard | { "hw_ldl/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, |
1369 | a993ba85 | bellard | { "hw_ldl/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, |
1370 | a993ba85 | bellard | { "hw_ldl/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, |
1371 | a993ba85 | bellard | { "hw_ldl/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, |
1372 | a993ba85 | bellard | { "hw_ldl/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, |
1373 | a993ba85 | bellard | { "hw_ldl/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, |
1374 | a993ba85 | bellard | { "hw_ldl/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, |
1375 | a993ba85 | bellard | { "hw_ldl/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, |
1376 | a993ba85 | bellard | { "hw_ldl/p", EV6HWMEM(0x1B,0x0), EV6, ARG_EV6HWMEM }, |
1377 | a993ba85 | bellard | { "hw_ldl/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, |
1378 | a993ba85 | bellard | { "hw_ldl/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, |
1379 | a993ba85 | bellard | { "hw_ldl/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, |
1380 | a993ba85 | bellard | { "hw_ldl/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, |
1381 | a993ba85 | bellard | { "hw_ldl/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, |
1382 | a993ba85 | bellard | { "hw_ldl/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, |
1383 | a993ba85 | bellard | { "hw_ldl/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, |
1384 | a993ba85 | bellard | { "hw_ldl/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, |
1385 | a993ba85 | bellard | { "hw_ldl/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, |
1386 | a993ba85 | bellard | { "hw_ldl/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, |
1387 | a993ba85 | bellard | { "hw_ldl/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, |
1388 | a993ba85 | bellard | { "hw_ldl/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, |
1389 | a993ba85 | bellard | { "hw_ldl/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, |
1390 | a993ba85 | bellard | { "hw_ldl/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, |
1391 | a993ba85 | bellard | { "hw_ldl/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, |
1392 | a993ba85 | bellard | { "hw_ldl/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, |
1393 | a993ba85 | bellard | { "hw_ldl/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, |
1394 | a993ba85 | bellard | { "hw_ldl/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, |
1395 | a993ba85 | bellard | { "hw_ldl/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, |
1396 | a993ba85 | bellard | { "hw_ldl/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, |
1397 | a993ba85 | bellard | { "hw_ldl/v", EV6HWMEM(0x1B,0x4), EV6, ARG_EV6HWMEM }, |
1398 | a993ba85 | bellard | { "hw_ldl/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, |
1399 | a993ba85 | bellard | { "hw_ldl/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, |
1400 | a993ba85 | bellard | { "hw_ldl/w", EV6HWMEM(0x1B,0xA), EV6, ARG_EV6HWMEM }, |
1401 | a993ba85 | bellard | { "hw_ldl/wa", EV6HWMEM(0x1B,0xE), EV6, ARG_EV6HWMEM }, |
1402 | a993ba85 | bellard | { "hw_ldl/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, |
1403 | a993ba85 | bellard | { "hw_ldl/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, |
1404 | a993ba85 | bellard | { "hw_ldl/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, |
1405 | a993ba85 | bellard | { "hw_ldl_l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, |
1406 | a993ba85 | bellard | { "hw_ldl_l/a", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, |
1407 | a993ba85 | bellard | { "hw_ldl_l/av", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, |
1408 | a993ba85 | bellard | { "hw_ldl_l/aw", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, |
1409 | a993ba85 | bellard | { "hw_ldl_l/awv", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, |
1410 | a993ba85 | bellard | { "hw_ldl_l/p", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, |
1411 | a993ba85 | bellard | { "hw_ldl_l/p", EV6HWMEM(0x1B,0x2), EV6, ARG_EV6HWMEM }, |
1412 | a993ba85 | bellard | { "hw_ldl_l/pa", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, |
1413 | a993ba85 | bellard | { "hw_ldl_l/pav", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, |
1414 | a993ba85 | bellard | { "hw_ldl_l/paw", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, |
1415 | a993ba85 | bellard | { "hw_ldl_l/pawv", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, |
1416 | a993ba85 | bellard | { "hw_ldl_l/pv", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, |
1417 | a993ba85 | bellard | { "hw_ldl_l/pw", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, |
1418 | a993ba85 | bellard | { "hw_ldl_l/pwv", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, |
1419 | a993ba85 | bellard | { "hw_ldl_l/v", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, |
1420 | a993ba85 | bellard | { "hw_ldl_l/w", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, |
1421 | a993ba85 | bellard | { "hw_ldl_l/wv", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, |
1422 | a993ba85 | bellard | { "hw_ldq", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, |
1423 | a993ba85 | bellard | { "hw_ldq", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, |
1424 | a993ba85 | bellard | { "hw_ldq", EV6HWMEM(0x1B,0x9), EV6, ARG_EV6HWMEM }, |
1425 | a993ba85 | bellard | { "hw_ldq/a", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, |
1426 | a993ba85 | bellard | { "hw_ldq/a", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, |
1427 | a993ba85 | bellard | { "hw_ldq/a", EV6HWMEM(0x1B,0xD), EV6, ARG_EV6HWMEM }, |
1428 | a993ba85 | bellard | { "hw_ldq/al", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, |
1429 | a993ba85 | bellard | { "hw_ldq/ar", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, |
1430 | a993ba85 | bellard | { "hw_ldq/av", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, |
1431 | a993ba85 | bellard | { "hw_ldq/avl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, |
1432 | a993ba85 | bellard | { "hw_ldq/aw", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, |
1433 | a993ba85 | bellard | { "hw_ldq/awl", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, |
1434 | a993ba85 | bellard | { "hw_ldq/awv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, |
1435 | a993ba85 | bellard | { "hw_ldq/awvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, |
1436 | a993ba85 | bellard | { "hw_ldq/l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, |
1437 | a993ba85 | bellard | { "hw_ldq/p", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, |
1438 | a993ba85 | bellard | { "hw_ldq/p", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, |
1439 | a993ba85 | bellard | { "hw_ldq/p", EV6HWMEM(0x1B,0x1), EV6, ARG_EV6HWMEM }, |
1440 | a993ba85 | bellard | { "hw_ldq/pa", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, |
1441 | a993ba85 | bellard | { "hw_ldq/pa", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, |
1442 | a993ba85 | bellard | { "hw_ldq/pal", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, |
1443 | a993ba85 | bellard | { "hw_ldq/par", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, |
1444 | a993ba85 | bellard | { "hw_ldq/pav", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, |
1445 | a993ba85 | bellard | { "hw_ldq/pavl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, |
1446 | a993ba85 | bellard | { "hw_ldq/paw", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, |
1447 | a993ba85 | bellard | { "hw_ldq/pawl", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, |
1448 | a993ba85 | bellard | { "hw_ldq/pawv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, |
1449 | a993ba85 | bellard | { "hw_ldq/pawvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, |
1450 | a993ba85 | bellard | { "hw_ldq/pl", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, |
1451 | a993ba85 | bellard | { "hw_ldq/pr", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, |
1452 | a993ba85 | bellard | { "hw_ldq/pv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, |
1453 | a993ba85 | bellard | { "hw_ldq/pvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, |
1454 | a993ba85 | bellard | { "hw_ldq/pw", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, |
1455 | a993ba85 | bellard | { "hw_ldq/pwl", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, |
1456 | a993ba85 | bellard | { "hw_ldq/pwv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, |
1457 | a993ba85 | bellard | { "hw_ldq/pwvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, |
1458 | a993ba85 | bellard | { "hw_ldq/r", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, |
1459 | a993ba85 | bellard | { "hw_ldq/v", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, |
1460 | a993ba85 | bellard | { "hw_ldq/v", EV6HWMEM(0x1B,0x5), EV6, ARG_EV6HWMEM }, |
1461 | a993ba85 | bellard | { "hw_ldq/vl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, |
1462 | a993ba85 | bellard | { "hw_ldq/w", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, |
1463 | a993ba85 | bellard | { "hw_ldq/w", EV6HWMEM(0x1B,0xB), EV6, ARG_EV6HWMEM }, |
1464 | a993ba85 | bellard | { "hw_ldq/wa", EV6HWMEM(0x1B,0xF), EV6, ARG_EV6HWMEM }, |
1465 | a993ba85 | bellard | { "hw_ldq/wl", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, |
1466 | a993ba85 | bellard | { "hw_ldq/wv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, |
1467 | a993ba85 | bellard | { "hw_ldq/wvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, |
1468 | a993ba85 | bellard | { "hw_ldq_l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, |
1469 | a993ba85 | bellard | { "hw_ldq_l/a", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, |
1470 | a993ba85 | bellard | { "hw_ldq_l/av", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, |
1471 | a993ba85 | bellard | { "hw_ldq_l/aw", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, |
1472 | a993ba85 | bellard | { "hw_ldq_l/awv", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, |
1473 | a993ba85 | bellard | { "hw_ldq_l/p", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, |
1474 | a993ba85 | bellard | { "hw_ldq_l/p", EV6HWMEM(0x1B,0x3), EV6, ARG_EV6HWMEM }, |
1475 | a993ba85 | bellard | { "hw_ldq_l/pa", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, |
1476 | a993ba85 | bellard | { "hw_ldq_l/pav", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, |
1477 | a993ba85 | bellard | { "hw_ldq_l/paw", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, |
1478 | a993ba85 | bellard | { "hw_ldq_l/pawv", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, |
1479 | a993ba85 | bellard | { "hw_ldq_l/pv", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, |
1480 | a993ba85 | bellard | { "hw_ldq_l/pw", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, |
1481 | a993ba85 | bellard | { "hw_ldq_l/pwv", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, |
1482 | a993ba85 | bellard | { "hw_ldq_l/v", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, |
1483 | a993ba85 | bellard | { "hw_ldq_l/w", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, |
1484 | a993ba85 | bellard | { "hw_ldq_l/wv", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, |
1485 | a993ba85 | bellard | { "hw_ld", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, |
1486 | a993ba85 | bellard | { "hw_ld", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, |
1487 | a993ba85 | bellard | { "hw_ld/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, |
1488 | a993ba85 | bellard | { "hw_ld/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, |
1489 | a993ba85 | bellard | { "hw_ld/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, |
1490 | a993ba85 | bellard | { "hw_ld/aq", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, |
1491 | a993ba85 | bellard | { "hw_ld/aq", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, |
1492 | a993ba85 | bellard | { "hw_ld/aql", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, |
1493 | a993ba85 | bellard | { "hw_ld/aqv", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, |
1494 | a993ba85 | bellard | { "hw_ld/aqvl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, |
1495 | a993ba85 | bellard | { "hw_ld/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, |
1496 | a993ba85 | bellard | { "hw_ld/arq", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, |
1497 | a993ba85 | bellard | { "hw_ld/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, |
1498 | a993ba85 | bellard | { "hw_ld/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, |
1499 | a993ba85 | bellard | { "hw_ld/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, |
1500 | a993ba85 | bellard | { "hw_ld/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, |
1501 | a993ba85 | bellard | { "hw_ld/awq", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, |
1502 | a993ba85 | bellard | { "hw_ld/awql", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, |
1503 | a993ba85 | bellard | { "hw_ld/awqv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, |
1504 | a993ba85 | bellard | { "hw_ld/awqvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, |
1505 | a993ba85 | bellard | { "hw_ld/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, |
1506 | a993ba85 | bellard | { "hw_ld/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, |
1507 | a993ba85 | bellard | { "hw_ld/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, |
1508 | a993ba85 | bellard | { "hw_ld/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, |
1509 | a993ba85 | bellard | { "hw_ld/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, |
1510 | a993ba85 | bellard | { "hw_ld/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, |
1511 | a993ba85 | bellard | { "hw_ld/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, |
1512 | a993ba85 | bellard | { "hw_ld/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, |
1513 | a993ba85 | bellard | { "hw_ld/paq", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, |
1514 | a993ba85 | bellard | { "hw_ld/paq", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, |
1515 | a993ba85 | bellard | { "hw_ld/paql", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, |
1516 | a993ba85 | bellard | { "hw_ld/paqv", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, |
1517 | a993ba85 | bellard | { "hw_ld/paqvl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, |
1518 | a993ba85 | bellard | { "hw_ld/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, |
1519 | a993ba85 | bellard | { "hw_ld/parq", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, |
1520 | a993ba85 | bellard | { "hw_ld/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, |
1521 | a993ba85 | bellard | { "hw_ld/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, |
1522 | a993ba85 | bellard | { "hw_ld/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, |
1523 | a993ba85 | bellard | { "hw_ld/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, |
1524 | a993ba85 | bellard | { "hw_ld/pawq", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, |
1525 | a993ba85 | bellard | { "hw_ld/pawql", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, |
1526 | a993ba85 | bellard | { "hw_ld/pawqv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, |
1527 | a993ba85 | bellard | { "hw_ld/pawqvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, |
1528 | a993ba85 | bellard | { "hw_ld/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, |
1529 | a993ba85 | bellard | { "hw_ld/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, |
1530 | a993ba85 | bellard | { "hw_ld/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, |
1531 | a993ba85 | bellard | { "hw_ld/pq", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, |
1532 | a993ba85 | bellard | { "hw_ld/pq", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, |
1533 | a993ba85 | bellard | { "hw_ld/pql", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, |
1534 | a993ba85 | bellard | { "hw_ld/pqv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, |
1535 | a993ba85 | bellard | { "hw_ld/pqvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, |
1536 | a993ba85 | bellard | { "hw_ld/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, |
1537 | a993ba85 | bellard | { "hw_ld/prq", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, |
1538 | a993ba85 | bellard | { "hw_ld/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, |
1539 | a993ba85 | bellard | { "hw_ld/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, |
1540 | a993ba85 | bellard | { "hw_ld/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, |
1541 | a993ba85 | bellard | { "hw_ld/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, |
1542 | a993ba85 | bellard | { "hw_ld/pwq", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, |
1543 | a993ba85 | bellard | { "hw_ld/pwql", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, |
1544 | a993ba85 | bellard | { "hw_ld/pwqv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, |
1545 | a993ba85 | bellard | { "hw_ld/pwqvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, |
1546 | a993ba85 | bellard | { "hw_ld/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, |
1547 | a993ba85 | bellard | { "hw_ld/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, |
1548 | a993ba85 | bellard | { "hw_ld/q", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, |
1549 | a993ba85 | bellard | { "hw_ld/q", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, |
1550 | a993ba85 | bellard | { "hw_ld/ql", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, |
1551 | a993ba85 | bellard | { "hw_ld/qv", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, |
1552 | a993ba85 | bellard | { "hw_ld/qvl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, |
1553 | a993ba85 | bellard | { "hw_ld/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, |
1554 | a993ba85 | bellard | { "hw_ld/rq", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, |
1555 | a993ba85 | bellard | { "hw_ld/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, |
1556 | a993ba85 | bellard | { "hw_ld/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, |
1557 | a993ba85 | bellard | { "hw_ld/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, |
1558 | a993ba85 | bellard | { "hw_ld/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, |
1559 | a993ba85 | bellard | { "hw_ld/wq", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, |
1560 | a993ba85 | bellard | { "hw_ld/wql", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, |
1561 | a993ba85 | bellard | { "hw_ld/wqv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, |
1562 | a993ba85 | bellard | { "hw_ld/wqvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, |
1563 | a993ba85 | bellard | { "hw_ld/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, |
1564 | a993ba85 | bellard | { "hw_ld/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, |
1565 | a993ba85 | bellard | { "pal1b", PCD(0x1B), BASE, ARG_PCD }, |
1566 | a993ba85 | bellard | |
1567 | a993ba85 | bellard | { "sextb", OPR(0x1C, 0x00), BWX, ARG_OPRZ1 }, |
1568 | a993ba85 | bellard | { "sextw", OPR(0x1C, 0x01), BWX, ARG_OPRZ1 }, |
1569 | a993ba85 | bellard | { "ctpop", OPR(0x1C, 0x30), CIX, ARG_OPRZ1 }, |
1570 | a993ba85 | bellard | { "perr", OPR(0x1C, 0x31), MAX, ARG_OPR }, |
1571 | a993ba85 | bellard | { "ctlz", OPR(0x1C, 0x32), CIX, ARG_OPRZ1 }, |
1572 | a993ba85 | bellard | { "cttz", OPR(0x1C, 0x33), CIX, ARG_OPRZ1 }, |
1573 | a993ba85 | bellard | { "unpkbw", OPR(0x1C, 0x34), MAX, ARG_OPRZ1 }, |
1574 | a993ba85 | bellard | { "unpkbl", OPR(0x1C, 0x35), MAX, ARG_OPRZ1 }, |
1575 | a993ba85 | bellard | { "pkwb", OPR(0x1C, 0x36), MAX, ARG_OPRZ1 }, |
1576 | a993ba85 | bellard | { "pklb", OPR(0x1C, 0x37), MAX, ARG_OPRZ1 }, |
1577 | a993ba85 | bellard | { "minsb8", OPR(0x1C, 0x38), MAX, ARG_OPR }, |
1578 | a993ba85 | bellard | { "minsb8", OPRL(0x1C, 0x38), MAX, ARG_OPRL }, |
1579 | a993ba85 | bellard | { "minsw4", OPR(0x1C, 0x39), MAX, ARG_OPR }, |
1580 | a993ba85 | bellard | { "minsw4", OPRL(0x1C, 0x39), MAX, ARG_OPRL }, |
1581 | a993ba85 | bellard | { "minub8", OPR(0x1C, 0x3A), MAX, ARG_OPR }, |
1582 | a993ba85 | bellard | { "minub8", OPRL(0x1C, 0x3A), MAX, ARG_OPRL }, |
1583 | a993ba85 | bellard | { "minuw4", OPR(0x1C, 0x3B), MAX, ARG_OPR }, |
1584 | a993ba85 | bellard | { "minuw4", OPRL(0x1C, 0x3B), MAX, ARG_OPRL }, |
1585 | a993ba85 | bellard | { "maxub8", OPR(0x1C, 0x3C), MAX, ARG_OPR }, |
1586 | a993ba85 | bellard | { "maxub8", OPRL(0x1C, 0x3C), MAX, ARG_OPRL }, |
1587 | a993ba85 | bellard | { "maxuw4", OPR(0x1C, 0x3D), MAX, ARG_OPR }, |
1588 | a993ba85 | bellard | { "maxuw4", OPRL(0x1C, 0x3D), MAX, ARG_OPRL }, |
1589 | a993ba85 | bellard | { "maxsb8", OPR(0x1C, 0x3E), MAX, ARG_OPR }, |
1590 | a993ba85 | bellard | { "maxsb8", OPRL(0x1C, 0x3E), MAX, ARG_OPRL }, |
1591 | a993ba85 | bellard | { "maxsw4", OPR(0x1C, 0x3F), MAX, ARG_OPR }, |
1592 | a993ba85 | bellard | { "maxsw4", OPRL(0x1C, 0x3F), MAX, ARG_OPRL }, |
1593 | a993ba85 | bellard | { "ftoit", FP(0x1C, 0x70), CIX, { FA, ZB, RC } }, |
1594 | a993ba85 | bellard | { "ftois", FP(0x1C, 0x78), CIX, { FA, ZB, RC } }, |
1595 | a993ba85 | bellard | |
1596 | a993ba85 | bellard | { "hw_mtpr", OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, |
1597 | a993ba85 | bellard | { "hw_mtpr", OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, |
1598 | a993ba85 | bellard | { "hw_mtpr", OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } }, |
1599 | a993ba85 | bellard | { "hw_mtpr/i", OPR(0x1D,0x01), EV4, ARG_EV4HWMPR }, |
1600 | a993ba85 | bellard | { "hw_mtpr/a", OPR(0x1D,0x02), EV4, ARG_EV4HWMPR }, |
1601 | a993ba85 | bellard | { "hw_mtpr/ai", OPR(0x1D,0x03), EV4, ARG_EV4HWMPR }, |
1602 | a993ba85 | bellard | { "hw_mtpr/p", OPR(0x1D,0x04), EV4, ARG_EV4HWMPR }, |
1603 | a993ba85 | bellard | { "hw_mtpr/pi", OPR(0x1D,0x05), EV4, ARG_EV4HWMPR }, |
1604 | a993ba85 | bellard | { "hw_mtpr/pa", OPR(0x1D,0x06), EV4, ARG_EV4HWMPR }, |
1605 | a993ba85 | bellard | { "hw_mtpr/pai", OPR(0x1D,0x07), EV4, ARG_EV4HWMPR }, |
1606 | a993ba85 | bellard | { "pal1d", PCD(0x1D), BASE, ARG_PCD }, |
1607 | a993ba85 | bellard | |
1608 | a993ba85 | bellard | { "hw_rei", SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE }, |
1609 | a993ba85 | bellard | { "hw_rei_stall", SPCD(0x1E,0x3FFC000), EV5, ARG_NONE }, |
1610 | a993ba85 | bellard | { "hw_jmp", EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } }, |
1611 | a993ba85 | bellard | { "hw_jsr", EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } }, |
1612 | a993ba85 | bellard | { "hw_ret", EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } }, |
1613 | a993ba85 | bellard | { "hw_jcr", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, |
1614 | a993ba85 | bellard | { "hw_coroutine", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */ |
1615 | a993ba85 | bellard | { "hw_jmp/stall", EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } }, |
1616 | a993ba85 | bellard | { "hw_jsr/stall", EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } }, |
1617 | a993ba85 | bellard | { "hw_ret/stall", EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } }, |
1618 | a993ba85 | bellard | { "hw_jcr/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, |
1619 | a993ba85 | bellard | { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */ |
1620 | a993ba85 | bellard | { "pal1e", PCD(0x1E), BASE, ARG_PCD }, |
1621 | a993ba85 | bellard | |
1622 | a993ba85 | bellard | { "hw_stl", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, |
1623 | a993ba85 | bellard | { "hw_stl", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, |
1624 | a993ba85 | bellard | { "hw_stl", EV6HWMEM(0x1F,0x4), EV6, ARG_EV6HWMEM }, /* ??? 8 */ |
1625 | a993ba85 | bellard | { "hw_stl/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, |
1626 | a993ba85 | bellard | { "hw_stl/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, |
1627 | a993ba85 | bellard | { "hw_stl/a", EV6HWMEM(0x1F,0xC), EV6, ARG_EV6HWMEM }, |
1628 | a993ba85 | bellard | { "hw_stl/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, |
1629 | a993ba85 | bellard | { "hw_stl/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, |
1630 | a993ba85 | bellard | { "hw_stl/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, |
1631 | a993ba85 | bellard | { "hw_stl/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, |
1632 | a993ba85 | bellard | { "hw_stl/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, |
1633 | a993ba85 | bellard | { "hw_stl/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, |
1634 | a993ba85 | bellard | { "hw_stl/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, |
1635 | a993ba85 | bellard | { "hw_stl/p", EV6HWMEM(0x1F,0x0), EV6, ARG_EV6HWMEM }, |
1636 | a993ba85 | bellard | { "hw_stl/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, |
1637 | a993ba85 | bellard | { "hw_stl/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, |
1638 | a993ba85 | bellard | { "hw_stl/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, |
1639 | a993ba85 | bellard | { "hw_stl/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, |
1640 | a993ba85 | bellard | { "hw_stl/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, |
1641 | a993ba85 | bellard | { "hw_stl/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, |
1642 | a993ba85 | bellard | { "hw_stl/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, |
1643 | a993ba85 | bellard | { "hw_stl/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, |
1644 | a993ba85 | bellard | { "hw_stl/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, |
1645 | a993ba85 | bellard | { "hw_stl/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, |
1646 | a993ba85 | bellard | { "hw_stl/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, |
1647 | a993ba85 | bellard | { "hw_stl/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, |
1648 | a993ba85 | bellard | { "hw_stl_c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, |
1649 | a993ba85 | bellard | { "hw_stl_c/a", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, |
1650 | a993ba85 | bellard | { "hw_stl_c/av", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, |
1651 | a993ba85 | bellard | { "hw_stl_c/p", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, |
1652 | a993ba85 | bellard | { "hw_stl_c/p", EV6HWMEM(0x1F,0x2), EV6, ARG_EV6HWMEM }, |
1653 | a993ba85 | bellard | { "hw_stl_c/pa", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, |
1654 | a993ba85 | bellard | { "hw_stl_c/pav", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, |
1655 | a993ba85 | bellard | { "hw_stl_c/pv", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, |
1656 | a993ba85 | bellard | { "hw_stl_c/v", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, |
1657 | a993ba85 | bellard | { "hw_stq", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, |
1658 | a993ba85 | bellard | { "hw_stq", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, |
1659 | a993ba85 | bellard | { "hw_stq", EV6HWMEM(0x1F,0x5), EV6, ARG_EV6HWMEM }, /* ??? 9 */ |
1660 | a993ba85 | bellard | { "hw_stq/a", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, |
1661 | a993ba85 | bellard | { "hw_stq/a", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, |
1662 | a993ba85 | bellard | { "hw_stq/a", EV6HWMEM(0x1F,0xD), EV6, ARG_EV6HWMEM }, |
1663 | a993ba85 | bellard | { "hw_stq/ac", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, |
1664 | a993ba85 | bellard | { "hw_stq/ar", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, |
1665 | a993ba85 | bellard | { "hw_stq/av", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, |
1666 | a993ba85 | bellard | { "hw_stq/avc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, |
1667 | a993ba85 | bellard | { "hw_stq/c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, |
1668 | a993ba85 | bellard | { "hw_stq/p", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, |
1669 | a993ba85 | bellard | { "hw_stq/p", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, |
1670 | a993ba85 | bellard | { "hw_stq/p", EV6HWMEM(0x1F,0x1), EV6, ARG_EV6HWMEM }, |
1671 | a993ba85 | bellard | { "hw_stq/pa", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, |
1672 | a993ba85 | bellard | { "hw_stq/pa", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, |
1673 | a993ba85 | bellard | { "hw_stq/pac", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, |
1674 | a993ba85 | bellard | { "hw_stq/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, |
1675 | a993ba85 | bellard | { "hw_stq/par", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, |
1676 | a993ba85 | bellard | { "hw_stq/pav", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, |
1677 | a993ba85 | bellard | { "hw_stq/pavc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, |
1678 | a993ba85 | bellard | { "hw_stq/pc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, |
1679 | a993ba85 | bellard | { "hw_stq/pr", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, |
1680 | a993ba85 | bellard | { "hw_stq/pv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, |
1681 | a993ba85 | bellard | { "hw_stq/pvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, |
1682 | a993ba85 | bellard | { "hw_stq/r", EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM }, |
1683 | a993ba85 | bellard | { "hw_stq/v", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, |
1684 | a993ba85 | bellard | { "hw_stq/vc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, |
1685 | a993ba85 | bellard | { "hw_stq_c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, |
1686 | a993ba85 | bellard | { "hw_stq_c/a", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, |
1687 | a993ba85 | bellard | { "hw_stq_c/av", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, |
1688 | a993ba85 | bellard | { "hw_stq_c/p", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, |
1689 | a993ba85 | bellard | { "hw_stq_c/p", EV6HWMEM(0x1F,0x3), EV6, ARG_EV6HWMEM }, |
1690 | a993ba85 | bellard | { "hw_stq_c/pa", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, |
1691 | a993ba85 | bellard | { "hw_stq_c/pav", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, |
1692 | a993ba85 | bellard | { "hw_stq_c/pv", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, |
1693 | a993ba85 | bellard | { "hw_stq_c/v", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, |
1694 | a993ba85 | bellard | { "hw_st", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, |
1695 | a993ba85 | bellard | { "hw_st", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, |
1696 | a993ba85 | bellard | { "hw_st/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, |
1697 | a993ba85 | bellard | { "hw_st/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, |
1698 | a993ba85 | bellard | { "hw_st/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, |
1699 | a993ba85 | bellard | { "hw_st/aq", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, |
1700 | a993ba85 | bellard | { "hw_st/aq", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, |
1701 | a993ba85 | bellard | { "hw_st/aqc", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, |
1702 | a993ba85 | bellard | { "hw_st/aqv", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, |
1703 | a993ba85 | bellard | { "hw_st/aqvc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, |
1704 | a993ba85 | bellard | { "hw_st/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, |
1705 | a993ba85 | bellard | { "hw_st/arq", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, |
1706 | a993ba85 | bellard | { "hw_st/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, |
1707 | a993ba85 | bellard | { "hw_st/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, |
1708 | a993ba85 | bellard | { "hw_st/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, |
1709 | a993ba85 | bellard | { "hw_st/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, |
1710 | a993ba85 | bellard | { "hw_st/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, |
1711 | a993ba85 | bellard | { "hw_st/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, |
1712 | a993ba85 | bellard | { "hw_st/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, |
1713 | a993ba85 | bellard | { "hw_st/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, |
1714 | a993ba85 | bellard | { "hw_st/paq", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, |
1715 | a993ba85 | bellard | { "hw_st/paq", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, |
1716 | a993ba85 | bellard | { "hw_st/paqc", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, |
1717 | a993ba85 | bellard | { "hw_st/paqv", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, |
1718 | a993ba85 | bellard | { "hw_st/paqvc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, |
1719 | a993ba85 | bellard | { "hw_st/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, |
1720 | a993ba85 | bellard | { "hw_st/parq", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, |
1721 | a993ba85 | bellard | { "hw_st/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, |
1722 | a993ba85 | bellard | { "hw_st/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, |
1723 | a993ba85 | bellard | { "hw_st/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, |
1724 | a993ba85 | bellard | { "hw_st/pq", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, |
1725 | a993ba85 | bellard | { "hw_st/pq", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, |
1726 | a993ba85 | bellard | { "hw_st/pqc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, |
1727 | a993ba85 | bellard | { "hw_st/pqv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, |
1728 | a993ba85 | bellard | { "hw_st/pqvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, |
1729 | a993ba85 | bellard | { "hw_st/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, |
1730 | a993ba85 | bellard | { "hw_st/prq", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, |
1731 | a993ba85 | bellard | { "hw_st/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, |
1732 | a993ba85 | bellard | { "hw_st/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, |
1733 | a993ba85 | bellard | { "hw_st/q", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, |
1734 | a993ba85 | bellard | { "hw_st/q", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, |
1735 | a993ba85 | bellard | { "hw_st/qc", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, |
1736 | a993ba85 | bellard | { "hw_st/qv", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, |
1737 | a993ba85 | bellard | { "hw_st/qvc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, |
1738 | a993ba85 | bellard | { "hw_st/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, |
1739 | a993ba85 | bellard | { "hw_st/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, |
1740 | a993ba85 | bellard | { "hw_st/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, |
1741 | a993ba85 | bellard | { "pal1f", PCD(0x1F), BASE, ARG_PCD }, |
1742 | a993ba85 | bellard | |
1743 | a993ba85 | bellard | { "ldf", MEM(0x20), BASE, ARG_FMEM }, |
1744 | a993ba85 | bellard | { "ldg", MEM(0x21), BASE, ARG_FMEM }, |
1745 | a993ba85 | bellard | { "lds", MEM(0x22), BASE, ARG_FMEM }, |
1746 | a993ba85 | bellard | { "ldt", MEM(0x23), BASE, ARG_FMEM }, |
1747 | a993ba85 | bellard | { "stf", MEM(0x24), BASE, ARG_FMEM }, |
1748 | a993ba85 | bellard | { "stg", MEM(0x25), BASE, ARG_FMEM }, |
1749 | a993ba85 | bellard | { "sts", MEM(0x26), BASE, ARG_FMEM }, |
1750 | a993ba85 | bellard | { "stt", MEM(0x27), BASE, ARG_FMEM }, |
1751 | a993ba85 | bellard | |
1752 | a993ba85 | bellard | { "ldl", MEM(0x28), BASE, ARG_MEM }, |
1753 | a993ba85 | bellard | { "ldq", MEM(0x29), BASE, ARG_MEM }, |
1754 | a993ba85 | bellard | { "ldl_l", MEM(0x2A), BASE, ARG_MEM }, |
1755 | a993ba85 | bellard | { "ldq_l", MEM(0x2B), BASE, ARG_MEM }, |
1756 | a993ba85 | bellard | { "stl", MEM(0x2C), BASE, ARG_MEM }, |
1757 | a993ba85 | bellard | { "stq", MEM(0x2D), BASE, ARG_MEM }, |
1758 | a993ba85 | bellard | { "stl_c", MEM(0x2E), BASE, ARG_MEM }, |
1759 | a993ba85 | bellard | { "stq_c", MEM(0x2F), BASE, ARG_MEM }, |
1760 | a993ba85 | bellard | |
1761 | a993ba85 | bellard | { "br", BRA(0x30), BASE, { ZA, BDISP } }, /* pseudo */ |
1762 | a993ba85 | bellard | { "br", BRA(0x30), BASE, ARG_BRA }, |
1763 | a993ba85 | bellard | { "fbeq", BRA(0x31), BASE, ARG_FBRA }, |
1764 | a993ba85 | bellard | { "fblt", BRA(0x32), BASE, ARG_FBRA }, |
1765 | a993ba85 | bellard | { "fble", BRA(0x33), BASE, ARG_FBRA }, |
1766 | a993ba85 | bellard | { "bsr", BRA(0x34), BASE, ARG_BRA }, |
1767 | a993ba85 | bellard | { "fbne", BRA(0x35), BASE, ARG_FBRA }, |
1768 | a993ba85 | bellard | { "fbge", BRA(0x36), BASE, ARG_FBRA }, |
1769 | a993ba85 | bellard | { "fbgt", BRA(0x37), BASE, ARG_FBRA }, |
1770 | a993ba85 | bellard | { "blbc", BRA(0x38), BASE, ARG_BRA }, |
1771 | a993ba85 | bellard | { "beq", BRA(0x39), BASE, ARG_BRA }, |
1772 | a993ba85 | bellard | { "blt", BRA(0x3A), BASE, ARG_BRA }, |
1773 | a993ba85 | bellard | { "ble", BRA(0x3B), BASE, ARG_BRA }, |
1774 | a993ba85 | bellard | { "blbs", BRA(0x3C), BASE, ARG_BRA }, |
1775 | a993ba85 | bellard | { "bne", BRA(0x3D), BASE, ARG_BRA }, |
1776 | a993ba85 | bellard | { "bge", BRA(0x3E), BASE, ARG_BRA }, |
1777 | a993ba85 | bellard | { "bgt", BRA(0x3F), BASE, ARG_BRA }, |
1778 | a993ba85 | bellard | }; |
1779 | a993ba85 | bellard | |
1780 | a993ba85 | bellard | const unsigned alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes); |
1781 | a993ba85 | bellard | |
1782 | a993ba85 | bellard | /* OSF register names. */
|
1783 | a993ba85 | bellard | |
1784 | a993ba85 | bellard | static const char * const osf_regnames[64] = { |
1785 | a993ba85 | bellard | "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", |
1786 | a993ba85 | bellard | "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", |
1787 | a993ba85 | bellard | "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", |
1788 | a993ba85 | bellard | "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero", |
1789 | a993ba85 | bellard | "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", |
1790 | a993ba85 | bellard | "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", |
1791 | a993ba85 | bellard | "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", |
1792 | a993ba85 | bellard | "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" |
1793 | a993ba85 | bellard | }; |
1794 | a993ba85 | bellard | |
1795 | a993ba85 | bellard | /* VMS register names. */
|
1796 | a993ba85 | bellard | |
1797 | a993ba85 | bellard | static const char * const vms_regnames[64] = { |
1798 | a993ba85 | bellard | "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", |
1799 | a993ba85 | bellard | "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", |
1800 | a993ba85 | bellard | "R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23", |
1801 | a993ba85 | bellard | "R24", "AI", "RA", "PV", "AT", "FP", "SP", "RZ", |
1802 | a993ba85 | bellard | "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7", |
1803 | a993ba85 | bellard | "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15", |
1804 | a993ba85 | bellard | "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23", |
1805 | a993ba85 | bellard | "F24", "F25", "F26", "F27", "F28", "F29", "F30", "FZ" |
1806 | a993ba85 | bellard | }; |
1807 | a993ba85 | bellard | |
1808 | a993ba85 | bellard | /* Disassemble Alpha instructions. */
|
1809 | a993ba85 | bellard | |
1810 | a993ba85 | bellard | int
|
1811 | a993ba85 | bellard | print_insn_alpha (memaddr, info) |
1812 | a993ba85 | bellard | bfd_vma memaddr; |
1813 | a993ba85 | bellard | struct disassemble_info *info;
|
1814 | a993ba85 | bellard | { |
1815 | a993ba85 | bellard | static const struct alpha_opcode *opcode_index[AXP_NOPS+1]; |
1816 | a993ba85 | bellard | const char * const * regnames; |
1817 | a993ba85 | bellard | const struct alpha_opcode *opcode, *opcode_end; |
1818 | a993ba85 | bellard | const unsigned char *opindex; |
1819 | a993ba85 | bellard | unsigned insn, op, isa_mask;
|
1820 | a993ba85 | bellard | int need_comma;
|
1821 | a993ba85 | bellard | |
1822 | a993ba85 | bellard | /* Initialize the majorop table the first time through */
|
1823 | a993ba85 | bellard | if (!opcode_index[0]) |
1824 | a993ba85 | bellard | { |
1825 | a993ba85 | bellard | opcode = alpha_opcodes; |
1826 | a993ba85 | bellard | opcode_end = opcode + alpha_num_opcodes; |
1827 | a993ba85 | bellard | |
1828 | a993ba85 | bellard | for (op = 0; op < AXP_NOPS; ++op) |
1829 | a993ba85 | bellard | { |
1830 | a993ba85 | bellard | opcode_index[op] = opcode; |
1831 | a993ba85 | bellard | while (opcode < opcode_end && op == AXP_OP (opcode->opcode))
|
1832 | a993ba85 | bellard | ++opcode; |
1833 | a993ba85 | bellard | } |
1834 | a993ba85 | bellard | opcode_index[op] = opcode; |
1835 | a993ba85 | bellard | } |
1836 | a993ba85 | bellard | |
1837 | a993ba85 | bellard | if (info->flavour == bfd_target_evax_flavour)
|
1838 | a993ba85 | bellard | regnames = vms_regnames; |
1839 | a993ba85 | bellard | else
|
1840 | a993ba85 | bellard | regnames = osf_regnames; |
1841 | a993ba85 | bellard | |
1842 | a993ba85 | bellard | isa_mask = AXP_OPCODE_NOPAL; |
1843 | a993ba85 | bellard | switch (info->mach)
|
1844 | a993ba85 | bellard | { |
1845 | a993ba85 | bellard | case bfd_mach_alpha_ev4:
|
1846 | a993ba85 | bellard | isa_mask |= AXP_OPCODE_EV4; |
1847 | a993ba85 | bellard | break;
|
1848 | a993ba85 | bellard | case bfd_mach_alpha_ev5:
|
1849 | a993ba85 | bellard | isa_mask |= AXP_OPCODE_EV5; |
1850 | a993ba85 | bellard | break;
|
1851 | a993ba85 | bellard | case bfd_mach_alpha_ev6:
|
1852 | a993ba85 | bellard | isa_mask |= AXP_OPCODE_EV6; |
1853 | a993ba85 | bellard | break;
|
1854 | a993ba85 | bellard | } |
1855 | a993ba85 | bellard | |
1856 | a993ba85 | bellard | /* Read the insn into a host word */
|
1857 | a993ba85 | bellard | { |
1858 | a993ba85 | bellard | bfd_byte buffer[4];
|
1859 | a993ba85 | bellard | int status = (*info->read_memory_func) (memaddr, buffer, 4, info); |
1860 | a993ba85 | bellard | if (status != 0) |
1861 | a993ba85 | bellard | { |
1862 | a993ba85 | bellard | (*info->memory_error_func) (status, memaddr, info); |
1863 | a993ba85 | bellard | return -1; |
1864 | a993ba85 | bellard | } |
1865 | a993ba85 | bellard | insn = bfd_getl32 (buffer); |
1866 | a993ba85 | bellard | } |
1867 | a993ba85 | bellard | |
1868 | a993ba85 | bellard | /* Get the major opcode of the instruction. */
|
1869 | a993ba85 | bellard | op = AXP_OP (insn); |
1870 | a993ba85 | bellard | |
1871 | a993ba85 | bellard | /* Find the first match in the opcode table. */
|
1872 | a993ba85 | bellard | opcode_end = opcode_index[op + 1];
|
1873 | a993ba85 | bellard | for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode)
|
1874 | a993ba85 | bellard | { |
1875 | a993ba85 | bellard | if ((insn ^ opcode->opcode) & opcode->mask)
|
1876 | a993ba85 | bellard | continue;
|
1877 | a993ba85 | bellard | |
1878 | a993ba85 | bellard | if (!(opcode->flags & isa_mask))
|
1879 | a993ba85 | bellard | continue;
|
1880 | a993ba85 | bellard | |
1881 | a993ba85 | bellard | /* Make two passes over the operands. First see if any of them
|
1882 | a993ba85 | bellard | have extraction functions, and, if they do, make sure the
|
1883 | a993ba85 | bellard | instruction is valid. */
|
1884 | a993ba85 | bellard | { |
1885 | a993ba85 | bellard | int invalid = 0; |
1886 | a993ba85 | bellard | for (opindex = opcode->operands; *opindex != 0; opindex++) |
1887 | a993ba85 | bellard | { |
1888 | a993ba85 | bellard | const struct alpha_operand *operand = alpha_operands + *opindex; |
1889 | a993ba85 | bellard | if (operand->extract)
|
1890 | a993ba85 | bellard | (*operand->extract) (insn, &invalid); |
1891 | a993ba85 | bellard | } |
1892 | a993ba85 | bellard | if (invalid)
|
1893 | a993ba85 | bellard | continue;
|
1894 | a993ba85 | bellard | } |
1895 | a993ba85 | bellard | |
1896 | a993ba85 | bellard | /* The instruction is valid. */
|
1897 | a993ba85 | bellard | goto found;
|
1898 | a993ba85 | bellard | } |
1899 | a993ba85 | bellard | |
1900 | a993ba85 | bellard | /* No instruction found */
|
1901 | a993ba85 | bellard | (*info->fprintf_func) (info->stream, ".long %#08x", insn);
|
1902 | a993ba85 | bellard | |
1903 | a993ba85 | bellard | return 4; |
1904 | a993ba85 | bellard | |
1905 | a993ba85 | bellard | found:
|
1906 | a993ba85 | bellard | (*info->fprintf_func) (info->stream, "%s", opcode->name);
|
1907 | a993ba85 | bellard | if (opcode->operands[0] != 0) |
1908 | a993ba85 | bellard | (*info->fprintf_func) (info->stream, "\t");
|
1909 | a993ba85 | bellard | |
1910 | a993ba85 | bellard | /* Now extract and print the operands. */
|
1911 | a993ba85 | bellard | need_comma = 0;
|
1912 | a993ba85 | bellard | for (opindex = opcode->operands; *opindex != 0; opindex++) |
1913 | a993ba85 | bellard | { |
1914 | a993ba85 | bellard | const struct alpha_operand *operand = alpha_operands + *opindex; |
1915 | a993ba85 | bellard | int value;
|
1916 | a993ba85 | bellard | |
1917 | a993ba85 | bellard | /* Operands that are marked FAKE are simply ignored. We
|
1918 | a993ba85 | bellard | already made sure that the extract function considered
|
1919 | a993ba85 | bellard | the instruction to be valid. */
|
1920 | a993ba85 | bellard | if ((operand->flags & AXP_OPERAND_FAKE) != 0) |
1921 | a993ba85 | bellard | continue;
|
1922 | a993ba85 | bellard | |
1923 | a993ba85 | bellard | /* Extract the value from the instruction. */
|
1924 | a993ba85 | bellard | if (operand->extract)
|
1925 | a993ba85 | bellard | value = (*operand->extract) (insn, (int *) NULL); |
1926 | a993ba85 | bellard | else
|
1927 | a993ba85 | bellard | { |
1928 | a993ba85 | bellard | value = (insn >> operand->shift) & ((1 << operand->bits) - 1); |
1929 | a993ba85 | bellard | if (operand->flags & AXP_OPERAND_SIGNED)
|
1930 | a993ba85 | bellard | { |
1931 | a993ba85 | bellard | int signbit = 1 << (operand->bits - 1); |
1932 | a993ba85 | bellard | value = (value ^ signbit) - signbit; |
1933 | a993ba85 | bellard | } |
1934 | a993ba85 | bellard | } |
1935 | a993ba85 | bellard | |
1936 | a993ba85 | bellard | if (need_comma &&
|
1937 | a993ba85 | bellard | ((operand->flags & (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA)) |
1938 | a993ba85 | bellard | != AXP_OPERAND_PARENS)) |
1939 | a993ba85 | bellard | { |
1940 | a993ba85 | bellard | (*info->fprintf_func) (info->stream, ",");
|
1941 | a993ba85 | bellard | } |
1942 | a993ba85 | bellard | if (operand->flags & AXP_OPERAND_PARENS)
|
1943 | a993ba85 | bellard | (*info->fprintf_func) (info->stream, "(");
|
1944 | a993ba85 | bellard | |
1945 | a993ba85 | bellard | /* Print the operand as directed by the flags. */
|
1946 | a993ba85 | bellard | if (operand->flags & AXP_OPERAND_IR)
|
1947 | a993ba85 | bellard | (*info->fprintf_func) (info->stream, "%s", regnames[value]);
|
1948 | a993ba85 | bellard | else if (operand->flags & AXP_OPERAND_FPR) |
1949 | a993ba85 | bellard | (*info->fprintf_func) (info->stream, "%s", regnames[value + 32]); |
1950 | a993ba85 | bellard | else if (operand->flags & AXP_OPERAND_RELATIVE) |
1951 | a993ba85 | bellard | (*info->print_address_func) (memaddr + 4 + value, info);
|
1952 | a993ba85 | bellard | else if (operand->flags & AXP_OPERAND_SIGNED) |
1953 | a993ba85 | bellard | (*info->fprintf_func) (info->stream, "%d", value);
|
1954 | a993ba85 | bellard | else
|
1955 | a993ba85 | bellard | (*info->fprintf_func) (info->stream, "%#x", value);
|
1956 | a993ba85 | bellard | |
1957 | a993ba85 | bellard | if (operand->flags & AXP_OPERAND_PARENS)
|
1958 | a993ba85 | bellard | (*info->fprintf_func) (info->stream, ")");
|
1959 | a993ba85 | bellard | need_comma = 1;
|
1960 | a993ba85 | bellard | } |
1961 | a993ba85 | bellard | |
1962 | a993ba85 | bellard | return 4; |
1963 | a993ba85 | bellard | } |