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/*
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 *  i386 micro operations
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 * 
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include "exec-i386.h"
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/* n must be a constant to be efficient */
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static inline int lshift(int x, int n)
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{
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    if (n >= 0)
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        return x << n;
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    else
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        return x >> (-n);
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}
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/* we define the various pieces of code used by the JIT */
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#define REG EAX
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#define REGNAME _EAX
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG ECX
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#define REGNAME _ECX
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG EDX
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#define REGNAME _EDX
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG EBX
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#define REGNAME _EBX
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG ESP
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#define REGNAME _ESP
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG EBP
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#define REGNAME _EBP
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG ESI
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#define REGNAME _ESI
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG EDI
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#define REGNAME _EDI
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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/* operations with flags */
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/* update flags with T0 and T1 (add/sub case) */
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void OPPROTO op_update2_cc(void)
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{
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    CC_SRC = T1;
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    CC_DST = T0;
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}
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/* update flags with T0 (logic operation case) */
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void OPPROTO op_update1_cc(void)
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{
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    CC_DST = T0;
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}
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void OPPROTO op_update_neg_cc(void)
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{
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    CC_SRC = -T0;
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    CC_DST = T0;
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}
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void OPPROTO op_cmpl_T0_T1_cc(void)
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{
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    CC_SRC = T1;
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    CC_DST = T0 - T1;
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}
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void OPPROTO op_update_inc_cc(void)
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{
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    CC_SRC = cc_table[CC_OP].compute_c();
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    CC_DST = T0;
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}
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void OPPROTO op_testl_T0_T1_cc(void)
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{
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    CC_DST = T0 & T1;
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}
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/* operations without flags */
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void OPPROTO op_addl_T0_T1(void)
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{
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    T0 += T1;
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}
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void OPPROTO op_orl_T0_T1(void)
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{
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    T0 |= T1;
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}
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void OPPROTO op_andl_T0_T1(void)
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{
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    T0 &= T1;
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}
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void OPPROTO op_subl_T0_T1(void)
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{
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    T0 -= T1;
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}
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void OPPROTO op_xorl_T0_T1(void)
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{
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    T0 ^= T1;
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}
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void OPPROTO op_negl_T0(void)
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{
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    T0 = -T0;
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}
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void OPPROTO op_incl_T0(void)
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{
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    T0++;
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}
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void OPPROTO op_decl_T0(void)
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{
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    T0--;
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}
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void OPPROTO op_notl_T0(void)
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{
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    T0 = ~T0;
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}
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void OPPROTO op_bswapl_T0(void)
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{
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    T0 = bswap32(T0);
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}
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/* multiply/divide */
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void OPPROTO op_mulb_AL_T0(void)
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{
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    unsigned int res;
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    res = (uint8_t)EAX * (uint8_t)T0;
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    EAX = (EAX & 0xffff0000) | res;
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    CC_SRC = (res & 0xff00);
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}
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void OPPROTO op_imulb_AL_T0(void)
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{
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    int res;
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    res = (int8_t)EAX * (int8_t)T0;
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    EAX = (EAX & 0xffff0000) | (res & 0xffff);
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    CC_SRC = (res != (int8_t)res);
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}
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void OPPROTO op_mulw_AX_T0(void)
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{
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    unsigned int res;
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    res = (uint16_t)EAX * (uint16_t)T0;
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    EAX = (EAX & 0xffff0000) | (res & 0xffff);
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    EDX = (EDX & 0xffff0000) | ((res >> 16) & 0xffff);
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    CC_SRC = res >> 16;
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}
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void OPPROTO op_imulw_AX_T0(void)
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{
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    int res;
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    res = (int16_t)EAX * (int16_t)T0;
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    EAX = (EAX & 0xffff0000) | (res & 0xffff);
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    EDX = (EDX & 0xffff0000) | ((res >> 16) & 0xffff);
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    CC_SRC = (res != (int16_t)res);
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}
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void OPPROTO op_mull_EAX_T0(void)
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{
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    uint64_t res;
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    res = (uint64_t)((uint32_t)EAX) * (uint64_t)((uint32_t)T0);
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    EAX = res;
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    EDX = res >> 32;
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    CC_SRC = res >> 32;
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}
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void OPPROTO op_imull_EAX_T0(void)
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{
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    int64_t res;
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    res = (int64_t)((int32_t)EAX) * (int64_t)((int32_t)T0);
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    EAX = res;
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    EDX = res >> 32;
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    CC_SRC = (res != (int32_t)res);
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}
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void OPPROTO op_imulw_T0_T1(void)
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{
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    int res;
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    res = (int16_t)T0 * (int16_t)T1;
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    T0 = res;
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    CC_SRC = (res != (int16_t)res);
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}
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void OPPROTO op_imull_T0_T1(void)
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{
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    int64_t res;
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    res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1);
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    T0 = res;
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    CC_SRC = (res != (int32_t)res);
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}
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/* division, flags are undefined */
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/* XXX: add exceptions for overflow */
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void OPPROTO op_divb_AL_T0(void)
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{
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    unsigned int num, den, q, r;
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    num = (EAX & 0xffff);
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    den = (T0 & 0xff);
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    if (den == 0) {
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        EIP = PARAM1;
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        raise_exception(EXCP00_DIVZ);
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    }
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    q = (num / den) & 0xff;
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    r = (num % den) & 0xff;
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    EAX = (EAX & 0xffff0000) | (r << 8) | q;
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}
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void OPPROTO op_idivb_AL_T0(void)
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{
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    int num, den, q, r;
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    num = (int16_t)EAX;
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    den = (int8_t)T0;
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    if (den == 0) {
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        EIP = PARAM1;
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        raise_exception(EXCP00_DIVZ);
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    }
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    q = (num / den) & 0xff;
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    r = (num % den) & 0xff;
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    EAX = (EAX & 0xffff0000) | (r << 8) | q;
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}
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void OPPROTO op_divw_AX_T0(void)
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{
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    unsigned int num, den, q, r;
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    num = (EAX & 0xffff) | ((EDX & 0xffff) << 16);
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    den = (T0 & 0xffff);
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    if (den == 0) {
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        EIP = PARAM1;
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        raise_exception(EXCP00_DIVZ);
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    }
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    q = (num / den) & 0xffff;
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    r = (num % den) & 0xffff;
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    EAX = (EAX & 0xffff0000) | q;
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    EDX = (EDX & 0xffff0000) | r;
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}
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void OPPROTO op_idivw_AX_T0(void)
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{
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    int num, den, q, r;
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    num = (EAX & 0xffff) | ((EDX & 0xffff) << 16);
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    den = (int16_t)T0;
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    if (den == 0) {
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        EIP = PARAM1;
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        raise_exception(EXCP00_DIVZ);
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    }
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    q = (num / den) & 0xffff;
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    r = (num % den) & 0xffff;
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    EAX = (EAX & 0xffff0000) | q;
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    EDX = (EDX & 0xffff0000) | r;
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}
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void OPPROTO op_divl_EAX_T0(void)
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{
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    helper_divl_EAX_T0(PARAM1);
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}
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void OPPROTO op_idivl_EAX_T0(void)
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{
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    helper_idivl_EAX_T0(PARAM1);
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}
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/* constant load & misc op */
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void OPPROTO op_movl_T0_im(void)
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{
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    T0 = PARAM1;
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}
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void OPPROTO op_addl_T0_im(void)
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{
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    T0 += PARAM1;
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}
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void OPPROTO op_andl_T0_ffff(void)
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{
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    T0 = T0 & 0xffff;
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}
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void OPPROTO op_andl_T0_im(void)
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{
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    T0 = T0 & PARAM1;
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}
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void OPPROTO op_movl_T0_T1(void)
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{
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    T0 = T1;
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}
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void OPPROTO op_movl_T1_im(void)
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{
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    T1 = PARAM1;
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}
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void OPPROTO op_addl_T1_im(void)
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{
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    T1 += PARAM1;
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}
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void OPPROTO op_movl_T1_A0(void)
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{
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    T1 = A0;
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}
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void OPPROTO op_movl_A0_im(void)
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{
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    A0 = PARAM1;
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}
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void OPPROTO op_addl_A0_im(void)
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{
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    A0 += PARAM1;
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}
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void OPPROTO op_addl_A0_AL(void)
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{
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    A0 += (EAX & 0xff);
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}
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void OPPROTO op_andl_A0_ffff(void)
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{
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    A0 = A0 & 0xffff;
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}
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/* memory access */
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#define MEMSUFFIX
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#include "ops_mem.h"
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#define MEMSUFFIX _user
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#include "ops_mem.h"
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#define MEMSUFFIX _kernel
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#include "ops_mem.h"
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/* used for bit operations */
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void OPPROTO op_add_bitw_A0_T1(void)
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{
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    A0 += ((int32_t)T1 >> 4) << 1;
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}
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void OPPROTO op_add_bitl_A0_T1(void)
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{
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    A0 += ((int32_t)T1 >> 5) << 2;
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}
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/* indirect jump */
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void OPPROTO op_jmp_T0(void)
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{
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    EIP = T0;
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}
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void OPPROTO op_jmp_im(void)
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{
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    EIP = PARAM1;
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}
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void OPPROTO op_hlt(void)
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{
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    env->exception_index = EXCP_HLT;
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    cpu_loop_exit();
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}
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void OPPROTO op_debug(void)
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{
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    env->exception_index = EXCP_DEBUG;
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    cpu_loop_exit();
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}
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void OPPROTO op_raise_interrupt(void)
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{
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    int intno;
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    unsigned int next_eip;
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    intno = PARAM1;
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    next_eip = PARAM2;
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    raise_interrupt(intno, 1, 0, next_eip);
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}
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void OPPROTO op_raise_exception(void)
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{
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    int exception_index;
436 564c8f99 bellard
    exception_index = PARAM1;
437 564c8f99 bellard
    raise_exception(exception_index);
438 0ecfa993 bellard
}
439 0ecfa993 bellard
440 0ecfa993 bellard
void OPPROTO op_into(void)
441 0ecfa993 bellard
{
442 0ecfa993 bellard
    int eflags;
443 0ecfa993 bellard
    eflags = cc_table[CC_OP].compute_all();
444 0ecfa993 bellard
    if (eflags & CC_O) {
445 f4beb510 bellard
        raise_interrupt(EXCP04_INTO, 1, 0, PARAM1);
446 a4a0ffdb bellard
    }
447 504e56eb bellard
    FORCE_RET();
448 a4a0ffdb bellard
}
449 a4a0ffdb bellard
450 504e56eb bellard
void OPPROTO op_cli(void)
451 504e56eb bellard
{
452 504e56eb bellard
    env->eflags &= ~IF_MASK;
453 504e56eb bellard
}
454 504e56eb bellard
455 f631ef9b bellard
void OPPROTO op_sti(void)
456 f631ef9b bellard
{
457 504e56eb bellard
    env->eflags |= IF_MASK;
458 f631ef9b bellard
}
459 f631ef9b bellard
460 3f337316 bellard
void OPPROTO op_set_inhibit_irq(void)
461 3f337316 bellard
{
462 3f337316 bellard
    env->hflags |= HF_INHIBIT_IRQ_MASK;
463 3f337316 bellard
}
464 3f337316 bellard
465 3f337316 bellard
void OPPROTO op_reset_inhibit_irq(void)
466 3f337316 bellard
{
467 3f337316 bellard
    env->hflags &= ~HF_INHIBIT_IRQ_MASK;
468 3f337316 bellard
}
469 3f337316 bellard
470 3acace13 bellard
#if 0
471 f631ef9b bellard
/* vm86plus instructions */
472 f631ef9b bellard
void OPPROTO op_cli_vm(void)
473 f631ef9b bellard
{
474 f631ef9b bellard
    env->eflags &= ~VIF_MASK;
475 f631ef9b bellard
}
476 f631ef9b bellard

477 f631ef9b bellard
void OPPROTO op_sti_vm(void)
478 f631ef9b bellard
{
479 f631ef9b bellard
    env->eflags |= VIF_MASK;
480 f631ef9b bellard
    if (env->eflags & VIP_MASK) {
481 f631ef9b bellard
        EIP = PARAM1;
482 f631ef9b bellard
        raise_exception(EXCP0D_GPF);
483 f631ef9b bellard
    }
484 f631ef9b bellard
    FORCE_RET();
485 f631ef9b bellard
}
486 3acace13 bellard
#endif
487 f631ef9b bellard
488 a4a0ffdb bellard
void OPPROTO op_boundw(void)
489 a4a0ffdb bellard
{
490 a4a0ffdb bellard
    int low, high, v;
491 a4a0ffdb bellard
    low = ldsw((uint8_t *)A0);
492 a4a0ffdb bellard
    high = ldsw((uint8_t *)A0 + 2);
493 a4a0ffdb bellard
    v = (int16_t)T0;
494 f4beb510 bellard
    if (v < low || v > high) {
495 f4beb510 bellard
        EIP = PARAM1;
496 a4a0ffdb bellard
        raise_exception(EXCP05_BOUND);
497 f4beb510 bellard
    }
498 a4a0ffdb bellard
    FORCE_RET();
499 a4a0ffdb bellard
}
500 a4a0ffdb bellard
501 a4a0ffdb bellard
void OPPROTO op_boundl(void)
502 a4a0ffdb bellard
{
503 a4a0ffdb bellard
    int low, high, v;
504 a4a0ffdb bellard
    low = ldl((uint8_t *)A0);
505 a4a0ffdb bellard
    high = ldl((uint8_t *)A0 + 4);
506 a4a0ffdb bellard
    v = T0;
507 f4beb510 bellard
    if (v < low || v > high) {
508 f4beb510 bellard
        EIP = PARAM1;
509 a4a0ffdb bellard
        raise_exception(EXCP05_BOUND);
510 f4beb510 bellard
    }
511 a4a0ffdb bellard
    FORCE_RET();
512 a4a0ffdb bellard
}
513 a4a0ffdb bellard
514 a4a0ffdb bellard
void OPPROTO op_cmpxchg8b(void)
515 a4a0ffdb bellard
{
516 87f4827e bellard
    helper_cmpxchg8b();
517 0ecfa993 bellard
}
518 0ecfa993 bellard
519 d4e8164f bellard
void OPPROTO op_jmp_tb_next(void)
520 d4e8164f bellard
{
521 25731098 bellard
    JUMP_TB(op_jmp_tb_next, PARAM1, 0, PARAM2);
522 d4e8164f bellard
}
523 d4e8164f bellard
524 d4e8164f bellard
void OPPROTO op_movl_T0_0(void)
525 d4e8164f bellard
{
526 d4e8164f bellard
    T0 = 0;
527 d4e8164f bellard
}
528 d4e8164f bellard
529 9621339d bellard
void OPPROTO op_exit_tb(void)
530 9621339d bellard
{
531 9621339d bellard
    EXIT_TB();
532 9621339d bellard
}
533 9621339d bellard
534 d4e8164f bellard
/* multiple size ops */
535 7bfdb6d1 bellard
536 7bfdb6d1 bellard
#define ldul ldl
537 7bfdb6d1 bellard
538 7bfdb6d1 bellard
#define SHIFT 0
539 367e86e8 bellard
#include "ops_template.h"
540 7bfdb6d1 bellard
#undef SHIFT
541 7bfdb6d1 bellard
542 7bfdb6d1 bellard
#define SHIFT 1
543 367e86e8 bellard
#include "ops_template.h"
544 7bfdb6d1 bellard
#undef SHIFT
545 7bfdb6d1 bellard
546 7bfdb6d1 bellard
#define SHIFT 2
547 367e86e8 bellard
#include "ops_template.h"
548 7bfdb6d1 bellard
#undef SHIFT
549 7bfdb6d1 bellard
550 7bfdb6d1 bellard
/* sign extend */
551 7bfdb6d1 bellard
552 7bfdb6d1 bellard
void OPPROTO op_movsbl_T0_T0(void)
553 7bfdb6d1 bellard
{
554 7bfdb6d1 bellard
    T0 = (int8_t)T0;
555 7bfdb6d1 bellard
}
556 7bfdb6d1 bellard
557 7bfdb6d1 bellard
void OPPROTO op_movzbl_T0_T0(void)
558 7bfdb6d1 bellard
{
559 7bfdb6d1 bellard
    T0 = (uint8_t)T0;
560 7bfdb6d1 bellard
}
561 7bfdb6d1 bellard
562 7bfdb6d1 bellard
void OPPROTO op_movswl_T0_T0(void)
563 7bfdb6d1 bellard
{
564 7bfdb6d1 bellard
    T0 = (int16_t)T0;
565 7bfdb6d1 bellard
}
566 7bfdb6d1 bellard
567 7bfdb6d1 bellard
void OPPROTO op_movzwl_T0_T0(void)
568 7bfdb6d1 bellard
{
569 7bfdb6d1 bellard
    T0 = (uint16_t)T0;
570 7bfdb6d1 bellard
}
571 7bfdb6d1 bellard
572 7bfdb6d1 bellard
void OPPROTO op_movswl_EAX_AX(void)
573 7bfdb6d1 bellard
{
574 7bfdb6d1 bellard
    EAX = (int16_t)EAX;
575 7bfdb6d1 bellard
}
576 7bfdb6d1 bellard
577 7bfdb6d1 bellard
void OPPROTO op_movsbw_AX_AL(void)
578 7bfdb6d1 bellard
{
579 7bfdb6d1 bellard
    EAX = (EAX & 0xffff0000) | ((int8_t)EAX & 0xffff);
580 7bfdb6d1 bellard
}
581 7bfdb6d1 bellard
582 7bfdb6d1 bellard
void OPPROTO op_movslq_EDX_EAX(void)
583 7bfdb6d1 bellard
{
584 7bfdb6d1 bellard
    EDX = (int32_t)EAX >> 31;
585 7bfdb6d1 bellard
}
586 7bfdb6d1 bellard
587 7bfdb6d1 bellard
void OPPROTO op_movswl_DX_AX(void)
588 7bfdb6d1 bellard
{
589 7bfdb6d1 bellard
    EDX = (EDX & 0xffff0000) | (((int16_t)EAX >> 15) & 0xffff);
590 7bfdb6d1 bellard
}
591 7bfdb6d1 bellard
592 33417e70 bellard
/* string ops helpers */
593 33417e70 bellard
594 33417e70 bellard
void OPPROTO op_addl_ESI_T0(void)
595 33417e70 bellard
{
596 33417e70 bellard
    ESI += T0;
597 33417e70 bellard
}
598 33417e70 bellard
599 33417e70 bellard
void OPPROTO op_addw_ESI_T0(void)
600 33417e70 bellard
{
601 33417e70 bellard
    ESI = (ESI & ~0xffff) | ((ESI + T0) & 0xffff);
602 33417e70 bellard
}
603 33417e70 bellard
604 33417e70 bellard
void OPPROTO op_addl_EDI_T0(void)
605 33417e70 bellard
{
606 33417e70 bellard
    EDI += T0;
607 33417e70 bellard
}
608 33417e70 bellard
609 33417e70 bellard
void OPPROTO op_addw_EDI_T0(void)
610 33417e70 bellard
{
611 33417e70 bellard
    EDI = (EDI & ~0xffff) | ((EDI + T0) & 0xffff);
612 33417e70 bellard
}
613 33417e70 bellard
614 33417e70 bellard
void OPPROTO op_decl_ECX(void)
615 33417e70 bellard
{
616 33417e70 bellard
    ECX--;
617 33417e70 bellard
}
618 33417e70 bellard
619 33417e70 bellard
void OPPROTO op_decw_ECX(void)
620 33417e70 bellard
{
621 33417e70 bellard
    ECX = (ECX & ~0xffff) | ((ECX - 1) & 0xffff);
622 33417e70 bellard
}
623 33417e70 bellard
624 7bfdb6d1 bellard
/* push/pop */
625 7bfdb6d1 bellard
626 7bfdb6d1 bellard
void op_pushl_T0(void)
627 7bfdb6d1 bellard
{
628 7bfdb6d1 bellard
    uint32_t offset;
629 7bfdb6d1 bellard
    offset = ESP - 4;
630 7bfdb6d1 bellard
    stl((void *)offset, T0);
631 7bfdb6d1 bellard
    /* modify ESP after to handle exceptions correctly */
632 7bfdb6d1 bellard
    ESP = offset;
633 7bfdb6d1 bellard
}
634 7bfdb6d1 bellard
635 dab2ed99 bellard
void op_pushw_T0(void)
636 dab2ed99 bellard
{
637 dab2ed99 bellard
    uint32_t offset;
638 dab2ed99 bellard
    offset = ESP - 2;
639 dab2ed99 bellard
    stw((void *)offset, T0);
640 dab2ed99 bellard
    /* modify ESP after to handle exceptions correctly */
641 dab2ed99 bellard
    ESP = offset;
642 dab2ed99 bellard
}
643 dab2ed99 bellard
644 dab2ed99 bellard
void op_pushl_ss32_T0(void)
645 7bfdb6d1 bellard
{
646 7bfdb6d1 bellard
    uint32_t offset;
647 7bfdb6d1 bellard
    offset = ESP - 4;
648 d8bc1fd0 bellard
    stl(env->segs[R_SS].base + offset, T0);
649 dab2ed99 bellard
    /* modify ESP after to handle exceptions correctly */
650 dab2ed99 bellard
    ESP = offset;
651 dab2ed99 bellard
}
652 dab2ed99 bellard
653 dab2ed99 bellard
void op_pushw_ss32_T0(void)
654 dab2ed99 bellard
{
655 dab2ed99 bellard
    uint32_t offset;
656 dab2ed99 bellard
    offset = ESP - 2;
657 d8bc1fd0 bellard
    stw(env->segs[R_SS].base + offset, T0);
658 7bfdb6d1 bellard
    /* modify ESP after to handle exceptions correctly */
659 7bfdb6d1 bellard
    ESP = offset;
660 7bfdb6d1 bellard
}
661 7bfdb6d1 bellard
662 dab2ed99 bellard
void op_pushl_ss16_T0(void)
663 dab2ed99 bellard
{
664 dab2ed99 bellard
    uint32_t offset;
665 dab2ed99 bellard
    offset = (ESP - 4) & 0xffff;
666 d8bc1fd0 bellard
    stl(env->segs[R_SS].base + offset, T0);
667 dab2ed99 bellard
    /* modify ESP after to handle exceptions correctly */
668 dab2ed99 bellard
    ESP = (ESP & ~0xffff) | offset;
669 dab2ed99 bellard
}
670 dab2ed99 bellard
671 dab2ed99 bellard
void op_pushw_ss16_T0(void)
672 dab2ed99 bellard
{
673 dab2ed99 bellard
    uint32_t offset;
674 dab2ed99 bellard
    offset = (ESP - 2) & 0xffff;
675 d8bc1fd0 bellard
    stw(env->segs[R_SS].base + offset, T0);
676 dab2ed99 bellard
    /* modify ESP after to handle exceptions correctly */
677 dab2ed99 bellard
    ESP = (ESP & ~0xffff) | offset;
678 dab2ed99 bellard
}
679 dab2ed99 bellard
680 dab2ed99 bellard
/* NOTE: ESP update is done after */
681 7bfdb6d1 bellard
void op_popl_T0(void)
682 7bfdb6d1 bellard
{
683 7bfdb6d1 bellard
    T0 = ldl((void *)ESP);
684 dab2ed99 bellard
}
685 dab2ed99 bellard
686 dab2ed99 bellard
void op_popw_T0(void)
687 dab2ed99 bellard
{
688 dab2ed99 bellard
    T0 = lduw((void *)ESP);
689 dab2ed99 bellard
}
690 dab2ed99 bellard
691 dab2ed99 bellard
void op_popl_ss32_T0(void)
692 dab2ed99 bellard
{
693 d8bc1fd0 bellard
    T0 = ldl(env->segs[R_SS].base + ESP);
694 dab2ed99 bellard
}
695 dab2ed99 bellard
696 dab2ed99 bellard
void op_popw_ss32_T0(void)
697 dab2ed99 bellard
{
698 d8bc1fd0 bellard
    T0 = lduw(env->segs[R_SS].base + ESP);
699 dab2ed99 bellard
}
700 dab2ed99 bellard
701 dab2ed99 bellard
void op_popl_ss16_T0(void)
702 dab2ed99 bellard
{
703 d8bc1fd0 bellard
    T0 = ldl(env->segs[R_SS].base + (ESP & 0xffff));
704 dab2ed99 bellard
}
705 dab2ed99 bellard
706 dab2ed99 bellard
void op_popw_ss16_T0(void)
707 dab2ed99 bellard
{
708 d8bc1fd0 bellard
    T0 = lduw(env->segs[R_SS].base + (ESP & 0xffff));
709 dab2ed99 bellard
}
710 dab2ed99 bellard
711 dab2ed99 bellard
void op_addl_ESP_4(void)
712 dab2ed99 bellard
{
713 7bfdb6d1 bellard
    ESP += 4;
714 7bfdb6d1 bellard
}
715 7bfdb6d1 bellard
716 dab2ed99 bellard
void op_addl_ESP_2(void)
717 dab2ed99 bellard
{
718 dab2ed99 bellard
    ESP += 2;
719 dab2ed99 bellard
}
720 dab2ed99 bellard
721 dab2ed99 bellard
void op_addw_ESP_4(void)
722 dab2ed99 bellard
{
723 dab2ed99 bellard
    ESP = (ESP & ~0xffff) | ((ESP + 4) & 0xffff);
724 dab2ed99 bellard
}
725 dab2ed99 bellard
726 dab2ed99 bellard
void op_addw_ESP_2(void)
727 dab2ed99 bellard
{
728 dab2ed99 bellard
    ESP = (ESP & ~0xffff) | ((ESP + 2) & 0xffff);
729 dab2ed99 bellard
}
730 dab2ed99 bellard
731 7bfdb6d1 bellard
void op_addl_ESP_im(void)
732 7bfdb6d1 bellard
{
733 7bfdb6d1 bellard
    ESP += PARAM1;
734 7bfdb6d1 bellard
}
735 367e86e8 bellard
736 dab2ed99 bellard
void op_addw_ESP_im(void)
737 dab2ed99 bellard
{
738 dab2ed99 bellard
    ESP = (ESP & ~0xffff) | ((ESP + PARAM1) & 0xffff);
739 27362c82 bellard
}
740 27362c82 bellard
741 a4a0ffdb bellard
void OPPROTO op_rdtsc(void)
742 27362c82 bellard
{
743 87f4827e bellard
    helper_rdtsc();
744 27362c82 bellard
}
745 27362c82 bellard
746 a4a0ffdb bellard
void OPPROTO op_cpuid(void)
747 a4a0ffdb bellard
{
748 a4a0ffdb bellard
    helper_cpuid();
749 a4a0ffdb bellard
}
750 a4a0ffdb bellard
751 3c1cf9fa bellard
void OPPROTO op_rdmsr(void)
752 3c1cf9fa bellard
{
753 3c1cf9fa bellard
    helper_rdmsr();
754 3c1cf9fa bellard
}
755 3c1cf9fa bellard
756 3c1cf9fa bellard
void OPPROTO op_wrmsr(void)
757 3c1cf9fa bellard
{
758 3c1cf9fa bellard
    helper_wrmsr();
759 3c1cf9fa bellard
}
760 3c1cf9fa bellard
761 27362c82 bellard
/* bcd */
762 27362c82 bellard
763 27362c82 bellard
/* XXX: exception */
764 27362c82 bellard
void OPPROTO op_aam(void)
765 27362c82 bellard
{
766 27362c82 bellard
    int base = PARAM1;
767 27362c82 bellard
    int al, ah;
768 27362c82 bellard
    al = EAX & 0xff;
769 27362c82 bellard
    ah = al / base;
770 27362c82 bellard
    al = al % base;
771 27362c82 bellard
    EAX = (EAX & ~0xffff) | al | (ah << 8);
772 27362c82 bellard
    CC_DST = al;
773 27362c82 bellard
}
774 27362c82 bellard
775 27362c82 bellard
void OPPROTO op_aad(void)
776 27362c82 bellard
{
777 27362c82 bellard
    int base = PARAM1;
778 27362c82 bellard
    int al, ah;
779 27362c82 bellard
    al = EAX & 0xff;
780 27362c82 bellard
    ah = (EAX >> 8) & 0xff;
781 27362c82 bellard
    al = ((ah * base) + al) & 0xff;
782 27362c82 bellard
    EAX = (EAX & ~0xffff) | al;
783 27362c82 bellard
    CC_DST = al;
784 27362c82 bellard
}
785 27362c82 bellard
786 27362c82 bellard
void OPPROTO op_aaa(void)
787 27362c82 bellard
{
788 27362c82 bellard
    int icarry;
789 27362c82 bellard
    int al, ah, af;
790 27362c82 bellard
    int eflags;
791 27362c82 bellard
792 27362c82 bellard
    eflags = cc_table[CC_OP].compute_all();
793 27362c82 bellard
    af = eflags & CC_A;
794 27362c82 bellard
    al = EAX & 0xff;
795 27362c82 bellard
    ah = (EAX >> 8) & 0xff;
796 27362c82 bellard
797 27362c82 bellard
    icarry = (al > 0xf9);
798 27362c82 bellard
    if (((al & 0x0f) > 9 ) || af) {
799 27362c82 bellard
        al = (al + 6) & 0x0f;
800 27362c82 bellard
        ah = (ah + 1 + icarry) & 0xff;
801 27362c82 bellard
        eflags |= CC_C | CC_A;
802 27362c82 bellard
    } else {
803 27362c82 bellard
        eflags &= ~(CC_C | CC_A);
804 27362c82 bellard
        al &= 0x0f;
805 27362c82 bellard
    }
806 27362c82 bellard
    EAX = (EAX & ~0xffff) | al | (ah << 8);
807 27362c82 bellard
    CC_SRC = eflags;
808 27362c82 bellard
}
809 27362c82 bellard
810 27362c82 bellard
void OPPROTO op_aas(void)
811 27362c82 bellard
{
812 27362c82 bellard
    int icarry;
813 27362c82 bellard
    int al, ah, af;
814 27362c82 bellard
    int eflags;
815 27362c82 bellard
816 27362c82 bellard
    eflags = cc_table[CC_OP].compute_all();
817 27362c82 bellard
    af = eflags & CC_A;
818 27362c82 bellard
    al = EAX & 0xff;
819 27362c82 bellard
    ah = (EAX >> 8) & 0xff;
820 27362c82 bellard
821 27362c82 bellard
    icarry = (al < 6);
822 27362c82 bellard
    if (((al & 0x0f) > 9 ) || af) {
823 27362c82 bellard
        al = (al - 6) & 0x0f;
824 27362c82 bellard
        ah = (ah - 1 - icarry) & 0xff;
825 27362c82 bellard
        eflags |= CC_C | CC_A;
826 27362c82 bellard
    } else {
827 27362c82 bellard
        eflags &= ~(CC_C | CC_A);
828 27362c82 bellard
        al &= 0x0f;
829 27362c82 bellard
    }
830 27362c82 bellard
    EAX = (EAX & ~0xffff) | al | (ah << 8);
831 27362c82 bellard
    CC_SRC = eflags;
832 27362c82 bellard
}
833 27362c82 bellard
834 27362c82 bellard
void OPPROTO op_daa(void)
835 27362c82 bellard
{
836 27362c82 bellard
    int al, af, cf;
837 27362c82 bellard
    int eflags;
838 27362c82 bellard
839 27362c82 bellard
    eflags = cc_table[CC_OP].compute_all();
840 27362c82 bellard
    cf = eflags & CC_C;
841 27362c82 bellard
    af = eflags & CC_A;
842 27362c82 bellard
    al = EAX & 0xff;
843 27362c82 bellard
844 27362c82 bellard
    eflags = 0;
845 27362c82 bellard
    if (((al & 0x0f) > 9 ) || af) {
846 27362c82 bellard
        al = (al + 6) & 0xff;
847 27362c82 bellard
        eflags |= CC_A;
848 27362c82 bellard
    }
849 27362c82 bellard
    if ((al > 0x9f) || cf) {
850 27362c82 bellard
        al = (al + 0x60) & 0xff;
851 27362c82 bellard
        eflags |= CC_C;
852 27362c82 bellard
    }
853 27362c82 bellard
    EAX = (EAX & ~0xff) | al;
854 27362c82 bellard
    /* well, speed is not an issue here, so we compute the flags by hand */
855 27362c82 bellard
    eflags |= (al == 0) << 6; /* zf */
856 27362c82 bellard
    eflags |= parity_table[al]; /* pf */
857 27362c82 bellard
    eflags |= (al & 0x80); /* sf */
858 27362c82 bellard
    CC_SRC = eflags;
859 27362c82 bellard
}
860 27362c82 bellard
861 27362c82 bellard
void OPPROTO op_das(void)
862 27362c82 bellard
{
863 27362c82 bellard
    int al, al1, af, cf;
864 27362c82 bellard
    int eflags;
865 27362c82 bellard
866 27362c82 bellard
    eflags = cc_table[CC_OP].compute_all();
867 27362c82 bellard
    cf = eflags & CC_C;
868 27362c82 bellard
    af = eflags & CC_A;
869 27362c82 bellard
    al = EAX & 0xff;
870 27362c82 bellard
871 27362c82 bellard
    eflags = 0;
872 27362c82 bellard
    al1 = al;
873 27362c82 bellard
    if (((al & 0x0f) > 9 ) || af) {
874 27362c82 bellard
        eflags |= CC_A;
875 27362c82 bellard
        if (al < 6 || cf)
876 27362c82 bellard
            eflags |= CC_C;
877 27362c82 bellard
        al = (al - 6) & 0xff;
878 27362c82 bellard
    }
879 27362c82 bellard
    if ((al1 > 0x99) || cf) {
880 27362c82 bellard
        al = (al - 0x60) & 0xff;
881 27362c82 bellard
        eflags |= CC_C;
882 27362c82 bellard
    }
883 27362c82 bellard
    EAX = (EAX & ~0xff) | al;
884 27362c82 bellard
    /* well, speed is not an issue here, so we compute the flags by hand */
885 27362c82 bellard
    eflags |= (al == 0) << 6; /* zf */
886 27362c82 bellard
    eflags |= parity_table[al]; /* pf */
887 27362c82 bellard
    eflags |= (al & 0x80); /* sf */
888 27362c82 bellard
    CC_SRC = eflags;
889 27362c82 bellard
}
890 27362c82 bellard
891 6dbad63e bellard
/* segment handling */
892 6dbad63e bellard
893 2e255c6b bellard
/* never use it with R_CS */
894 6dbad63e bellard
void OPPROTO op_movl_seg_T0(void)
895 6dbad63e bellard
{
896 f4beb510 bellard
    load_seg(PARAM1, T0 & 0xffff, PARAM2);
897 f4beb510 bellard
}
898 f4beb510 bellard
899 f4beb510 bellard
/* faster VM86 version */
900 f4beb510 bellard
void OPPROTO op_movl_seg_T0_vm(void)
901 f4beb510 bellard
{
902 f4beb510 bellard
    int selector;
903 d8bc1fd0 bellard
    SegmentCache *sc;
904 f4beb510 bellard
    
905 f4beb510 bellard
    selector = T0 & 0xffff;
906 f4beb510 bellard
    /* env->segs[] access */
907 d8bc1fd0 bellard
    sc = (SegmentCache *)((char *)env + PARAM1);
908 d8bc1fd0 bellard
    sc->selector = selector;
909 d8bc1fd0 bellard
    sc->base = (void *)(selector << 4);
910 6dbad63e bellard
}
911 6dbad63e bellard
912 6dbad63e bellard
void OPPROTO op_movl_T0_seg(void)
913 6dbad63e bellard
{
914 d8bc1fd0 bellard
    T0 = env->segs[PARAM1].selector;
915 6dbad63e bellard
}
916 6dbad63e bellard
917 a4a0ffdb bellard
void OPPROTO op_movl_A0_seg(void)
918 a4a0ffdb bellard
{
919 a4a0ffdb bellard
    A0 = *(unsigned long *)((char *)env + PARAM1);
920 a4a0ffdb bellard
}
921 a4a0ffdb bellard
922 6dbad63e bellard
void OPPROTO op_addl_A0_seg(void)
923 6dbad63e bellard
{
924 6dbad63e bellard
    A0 += *(unsigned long *)((char *)env + PARAM1);
925 6dbad63e bellard
}
926 6dbad63e bellard
927 2792c4f2 bellard
void OPPROTO op_lsl(void)
928 2792c4f2 bellard
{
929 2792c4f2 bellard
    helper_lsl();
930 2792c4f2 bellard
}
931 2792c4f2 bellard
932 2792c4f2 bellard
void OPPROTO op_lar(void)
933 2792c4f2 bellard
{
934 2792c4f2 bellard
    helper_lar();
935 2792c4f2 bellard
}
936 2792c4f2 bellard
937 d8bc1fd0 bellard
/* T0: segment, T1:eip */
938 2c1794c4 bellard
void OPPROTO op_ljmp_protected_T0_T1(void)
939 d8bc1fd0 bellard
{
940 2c1794c4 bellard
    helper_ljmp_protected_T0_T1();
941 2c1794c4 bellard
}
942 2c1794c4 bellard
943 2c1794c4 bellard
void OPPROTO op_lcall_real_T0_T1(void)
944 2c1794c4 bellard
{
945 2c1794c4 bellard
    helper_lcall_real_T0_T1(PARAM1, PARAM2);
946 2c1794c4 bellard
}
947 2c1794c4 bellard
948 2c1794c4 bellard
void OPPROTO op_lcall_protected_T0_T1(void)
949 2c1794c4 bellard
{
950 2c1794c4 bellard
    helper_lcall_protected_T0_T1(PARAM1, PARAM2);
951 d8bc1fd0 bellard
}
952 d8bc1fd0 bellard
953 8f186479 bellard
void OPPROTO op_iret_real(void)
954 8f186479 bellard
{
955 8f186479 bellard
    helper_iret_real(PARAM1);
956 8f186479 bellard
}
957 8f186479 bellard
958 90a9fdae bellard
void OPPROTO op_iret_protected(void)
959 90a9fdae bellard
{
960 90a9fdae bellard
    helper_iret_protected(PARAM1);
961 90a9fdae bellard
}
962 90a9fdae bellard
963 2c1794c4 bellard
void OPPROTO op_lret_protected(void)
964 2c1794c4 bellard
{
965 2c1794c4 bellard
    helper_lret_protected(PARAM1, PARAM2);
966 2c1794c4 bellard
}
967 2c1794c4 bellard
968 d8bc1fd0 bellard
void OPPROTO op_lldt_T0(void)
969 d8bc1fd0 bellard
{
970 d8bc1fd0 bellard
    helper_lldt_T0();
971 d8bc1fd0 bellard
}
972 d8bc1fd0 bellard
973 d8bc1fd0 bellard
void OPPROTO op_ltr_T0(void)
974 d8bc1fd0 bellard
{
975 d8bc1fd0 bellard
    helper_ltr_T0();
976 d8bc1fd0 bellard
}
977 d8bc1fd0 bellard
978 d8bc1fd0 bellard
/* CR registers access */
979 d8bc1fd0 bellard
void OPPROTO op_movl_crN_T0(void)
980 d8bc1fd0 bellard
{
981 d8bc1fd0 bellard
    helper_movl_crN_T0(PARAM1);
982 d8bc1fd0 bellard
}
983 d8bc1fd0 bellard
984 d8bc1fd0 bellard
/* DR registers access */
985 d8bc1fd0 bellard
void OPPROTO op_movl_drN_T0(void)
986 d8bc1fd0 bellard
{
987 d8bc1fd0 bellard
    helper_movl_drN_T0(PARAM1);
988 d8bc1fd0 bellard
}
989 d8bc1fd0 bellard
990 d8bc1fd0 bellard
void OPPROTO op_lmsw_T0(void)
991 d8bc1fd0 bellard
{
992 d8bc1fd0 bellard
    /* only 4 lower bits of CR0 are modified */
993 d8bc1fd0 bellard
    T0 = (env->cr[0] & ~0xf) | (T0 & 0xf);
994 d8bc1fd0 bellard
    helper_movl_crN_T0(0);
995 d8bc1fd0 bellard
}
996 d8bc1fd0 bellard
997 90a9fdae bellard
void OPPROTO op_invlpg_A0(void)
998 90a9fdae bellard
{
999 90a9fdae bellard
    helper_invlpg(A0);
1000 90a9fdae bellard
}
1001 90a9fdae bellard
1002 d8bc1fd0 bellard
void OPPROTO op_movl_T0_env(void)
1003 d8bc1fd0 bellard
{
1004 d8bc1fd0 bellard
    T0 = *(uint32_t *)((char *)env + PARAM1);
1005 d8bc1fd0 bellard
}
1006 d8bc1fd0 bellard
1007 d8bc1fd0 bellard
void OPPROTO op_movl_env_T0(void)
1008 d8bc1fd0 bellard
{
1009 d8bc1fd0 bellard
    *(uint32_t *)((char *)env + PARAM1) = T0;
1010 d8bc1fd0 bellard
}
1011 d8bc1fd0 bellard
1012 d8bc1fd0 bellard
void OPPROTO op_movl_env_T1(void)
1013 d8bc1fd0 bellard
{
1014 d8bc1fd0 bellard
    *(uint32_t *)((char *)env + PARAM1) = T1;
1015 d8bc1fd0 bellard
}
1016 d8bc1fd0 bellard
1017 d8bc1fd0 bellard
void OPPROTO op_clts(void)
1018 d8bc1fd0 bellard
{
1019 d8bc1fd0 bellard
    env->cr[0] &= ~CR0_TS_MASK;
1020 d8bc1fd0 bellard
}
1021 d8bc1fd0 bellard
1022 367e86e8 bellard
/* flags handling */
1023 367e86e8 bellard
1024 d4e8164f bellard
/* slow jumps cases : in order to avoid calling a function with a
1025 d4e8164f bellard
   pointer (which can generate a stack frame on PowerPC), we use
1026 d4e8164f bellard
   op_setcc to set T0 and then call op_jcc. */
1027 d4e8164f bellard
void OPPROTO op_jcc(void)
1028 367e86e8 bellard
{
1029 d4e8164f bellard
    if (T0)
1030 25731098 bellard
        JUMP_TB(op_jcc, PARAM1, 0, PARAM2);
1031 367e86e8 bellard
    else
1032 25731098 bellard
        JUMP_TB(op_jcc, PARAM1, 1, PARAM3);
1033 0ecfa993 bellard
    FORCE_RET();
1034 367e86e8 bellard
}
1035 367e86e8 bellard
1036 367e86e8 bellard
/* slow set cases (compute x86 flags) */
1037 367e86e8 bellard
void OPPROTO op_seto_T0_cc(void)
1038 367e86e8 bellard
{
1039 367e86e8 bellard
    int eflags;
1040 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1041 367e86e8 bellard
    T0 = (eflags >> 11) & 1;
1042 367e86e8 bellard
}
1043 367e86e8 bellard
1044 367e86e8 bellard
void OPPROTO op_setb_T0_cc(void)
1045 367e86e8 bellard
{
1046 367e86e8 bellard
    T0 = cc_table[CC_OP].compute_c();
1047 367e86e8 bellard
}
1048 367e86e8 bellard
1049 367e86e8 bellard
void OPPROTO op_setz_T0_cc(void)
1050 367e86e8 bellard
{
1051 367e86e8 bellard
    int eflags;
1052 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1053 367e86e8 bellard
    T0 = (eflags >> 6) & 1;
1054 367e86e8 bellard
}
1055 367e86e8 bellard
1056 367e86e8 bellard
void OPPROTO op_setbe_T0_cc(void)
1057 367e86e8 bellard
{
1058 367e86e8 bellard
    int eflags;
1059 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1060 367e86e8 bellard
    T0 = (eflags & (CC_Z | CC_C)) != 0;
1061 367e86e8 bellard
}
1062 367e86e8 bellard
1063 367e86e8 bellard
void OPPROTO op_sets_T0_cc(void)
1064 367e86e8 bellard
{
1065 367e86e8 bellard
    int eflags;
1066 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1067 367e86e8 bellard
    T0 = (eflags >> 7) & 1;
1068 367e86e8 bellard
}
1069 367e86e8 bellard
1070 367e86e8 bellard
void OPPROTO op_setp_T0_cc(void)
1071 367e86e8 bellard
{
1072 367e86e8 bellard
    int eflags;
1073 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1074 367e86e8 bellard
    T0 = (eflags >> 2) & 1;
1075 367e86e8 bellard
}
1076 367e86e8 bellard
1077 367e86e8 bellard
void OPPROTO op_setl_T0_cc(void)
1078 367e86e8 bellard
{
1079 367e86e8 bellard
    int eflags;
1080 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1081 367e86e8 bellard
    T0 = ((eflags ^ (eflags >> 4)) >> 7) & 1;
1082 367e86e8 bellard
}
1083 367e86e8 bellard
1084 367e86e8 bellard
void OPPROTO op_setle_T0_cc(void)
1085 367e86e8 bellard
{
1086 367e86e8 bellard
    int eflags;
1087 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1088 367e86e8 bellard
    T0 = (((eflags ^ (eflags >> 4)) & 0x80) || (eflags & CC_Z)) != 0;
1089 367e86e8 bellard
}
1090 367e86e8 bellard
1091 367e86e8 bellard
void OPPROTO op_xor_T0_1(void)
1092 367e86e8 bellard
{
1093 367e86e8 bellard
    T0 ^= 1;
1094 367e86e8 bellard
}
1095 367e86e8 bellard
1096 367e86e8 bellard
void OPPROTO op_set_cc_op(void)
1097 367e86e8 bellard
{
1098 367e86e8 bellard
    CC_OP = PARAM1;
1099 367e86e8 bellard
}
1100 367e86e8 bellard
1101 90a9fdae bellard
#define FL_UPDATE_MASK16 (FL_UPDATE_MASK32 & 0xffff)
1102 a4a0ffdb bellard
1103 367e86e8 bellard
void OPPROTO op_movl_eflags_T0(void)
1104 367e86e8 bellard
{
1105 a4a0ffdb bellard
    int eflags;
1106 a4a0ffdb bellard
    eflags = T0;
1107 a4a0ffdb bellard
    CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1108 a4a0ffdb bellard
    DF = 1 - (2 * ((eflags >> 10) & 1));
1109 a4a0ffdb bellard
    /* we also update some system flags as in user mode */
1110 90a9fdae bellard
    env->eflags = (env->eflags & ~FL_UPDATE_MASK32) | 
1111 90a9fdae bellard
        (eflags & FL_UPDATE_MASK32);
1112 f631ef9b bellard
}
1113 f631ef9b bellard
1114 f631ef9b bellard
void OPPROTO op_movw_eflags_T0(void)
1115 f631ef9b bellard
{
1116 f631ef9b bellard
    int eflags;
1117 f631ef9b bellard
    eflags = T0;
1118 f631ef9b bellard
    CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1119 f631ef9b bellard
    DF = 1 - (2 * ((eflags >> 10) & 1));
1120 f631ef9b bellard
    /* we also update some system flags as in user mode */
1121 90a9fdae bellard
    env->eflags = (env->eflags & ~FL_UPDATE_MASK16) | 
1122 90a9fdae bellard
        (eflags & FL_UPDATE_MASK16);
1123 90a9fdae bellard
}
1124 90a9fdae bellard
1125 90a9fdae bellard
void OPPROTO op_movl_eflags_T0_cpl0(void)
1126 90a9fdae bellard
{
1127 90a9fdae bellard
    load_eflags(T0, FL_UPDATE_CPL0_MASK);
1128 90a9fdae bellard
}
1129 90a9fdae bellard
1130 90a9fdae bellard
void OPPROTO op_movw_eflags_T0_cpl0(void)
1131 90a9fdae bellard
{
1132 90a9fdae bellard
    load_eflags(T0, FL_UPDATE_CPL0_MASK & 0xffff);
1133 f631ef9b bellard
}
1134 f631ef9b bellard
1135 3acace13 bellard
#if 0
1136 3acace13 bellard
/* vm86plus version */
1137 f631ef9b bellard
void OPPROTO op_movw_eflags_T0_vm(void)
1138 f631ef9b bellard
{
1139 f631ef9b bellard
    int eflags;
1140 f631ef9b bellard
    eflags = T0;
1141 f631ef9b bellard
    CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1142 f631ef9b bellard
    DF = 1 - (2 * ((eflags >> 10) & 1));
1143 f631ef9b bellard
    /* we also update some system flags as in user mode */
1144 f631ef9b bellard
    env->eflags = (env->eflags & ~(FL_UPDATE_MASK16 | VIF_MASK)) |
1145 f631ef9b bellard
        (eflags & FL_UPDATE_MASK16);
1146 f631ef9b bellard
    if (eflags & IF_MASK) {
1147 f631ef9b bellard
        env->eflags |= VIF_MASK;
1148 f631ef9b bellard
        if (env->eflags & VIP_MASK) {
1149 f631ef9b bellard
            EIP = PARAM1;
1150 f631ef9b bellard
            raise_exception(EXCP0D_GPF);
1151 f631ef9b bellard
        }
1152 f631ef9b bellard
    }
1153 f631ef9b bellard
    FORCE_RET();
1154 f631ef9b bellard
}
1155 f631ef9b bellard

1156 f631ef9b bellard
void OPPROTO op_movl_eflags_T0_vm(void)
1157 f631ef9b bellard
{
1158 f631ef9b bellard
    int eflags;
1159 f631ef9b bellard
    eflags = T0;
1160 f631ef9b bellard
    CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1161 f631ef9b bellard
    DF = 1 - (2 * ((eflags >> 10) & 1));
1162 f631ef9b bellard
    /* we also update some system flags as in user mode */
1163 f631ef9b bellard
    env->eflags = (env->eflags & ~(FL_UPDATE_MASK32 | VIF_MASK)) |
1164 f631ef9b bellard
        (eflags & FL_UPDATE_MASK32);
1165 f631ef9b bellard
    if (eflags & IF_MASK) {
1166 f631ef9b bellard
        env->eflags |= VIF_MASK;
1167 f631ef9b bellard
        if (env->eflags & VIP_MASK) {
1168 f631ef9b bellard
            EIP = PARAM1;
1169 f631ef9b bellard
            raise_exception(EXCP0D_GPF);
1170 f631ef9b bellard
        }
1171 f631ef9b bellard
    }
1172 f631ef9b bellard
    FORCE_RET();
1173 367e86e8 bellard
}
1174 3acace13 bellard
#endif
1175 367e86e8 bellard
1176 367e86e8 bellard
/* XXX: compute only O flag */
1177 367e86e8 bellard
void OPPROTO op_movb_eflags_T0(void)
1178 367e86e8 bellard
{
1179 367e86e8 bellard
    int of;
1180 367e86e8 bellard
    of = cc_table[CC_OP].compute_all() & CC_O;
1181 a4a0ffdb bellard
    CC_SRC = (T0 & (CC_S | CC_Z | CC_A | CC_P | CC_C)) | of;
1182 367e86e8 bellard
}
1183 367e86e8 bellard
1184 367e86e8 bellard
void OPPROTO op_movl_T0_eflags(void)
1185 367e86e8 bellard
{
1186 a4a0ffdb bellard
    int eflags;
1187 a4a0ffdb bellard
    eflags = cc_table[CC_OP].compute_all();
1188 a4a0ffdb bellard
    eflags |= (DF & DF_MASK);
1189 a4a0ffdb bellard
    eflags |= env->eflags & ~(VM_MASK | RF_MASK);
1190 a4a0ffdb bellard
    T0 = eflags;
1191 367e86e8 bellard
}
1192 367e86e8 bellard
1193 3acace13 bellard
/* vm86plus version */
1194 3acace13 bellard
#if 0
1195 f631ef9b bellard
void OPPROTO op_movl_T0_eflags_vm(void)
1196 f631ef9b bellard
{
1197 f631ef9b bellard
    int eflags;
1198 f631ef9b bellard
    eflags = cc_table[CC_OP].compute_all();
1199 f631ef9b bellard
    eflags |= (DF & DF_MASK);
1200 f631ef9b bellard
    eflags |= env->eflags & ~(VM_MASK | RF_MASK | IF_MASK);
1201 f631ef9b bellard
    if (env->eflags & VIF_MASK)
1202 f631ef9b bellard
        eflags |= IF_MASK;
1203 f631ef9b bellard
    T0 = eflags;
1204 f631ef9b bellard
}
1205 3acace13 bellard
#endif
1206 f631ef9b bellard
1207 367e86e8 bellard
void OPPROTO op_cld(void)
1208 367e86e8 bellard
{
1209 367e86e8 bellard
    DF = 1;
1210 367e86e8 bellard
}
1211 367e86e8 bellard
1212 367e86e8 bellard
void OPPROTO op_std(void)
1213 367e86e8 bellard
{
1214 367e86e8 bellard
    DF = -1;
1215 367e86e8 bellard
}
1216 367e86e8 bellard
1217 367e86e8 bellard
void OPPROTO op_clc(void)
1218 367e86e8 bellard
{
1219 367e86e8 bellard
    int eflags;
1220 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1221 367e86e8 bellard
    eflags &= ~CC_C;
1222 367e86e8 bellard
    CC_SRC = eflags;
1223 367e86e8 bellard
}
1224 367e86e8 bellard
1225 367e86e8 bellard
void OPPROTO op_stc(void)
1226 367e86e8 bellard
{
1227 367e86e8 bellard
    int eflags;
1228 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1229 367e86e8 bellard
    eflags |= CC_C;
1230 367e86e8 bellard
    CC_SRC = eflags;
1231 367e86e8 bellard
}
1232 367e86e8 bellard
1233 367e86e8 bellard
void OPPROTO op_cmc(void)
1234 367e86e8 bellard
{
1235 367e86e8 bellard
    int eflags;
1236 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1237 367e86e8 bellard
    eflags ^= CC_C;
1238 367e86e8 bellard
    CC_SRC = eflags;
1239 367e86e8 bellard
}
1240 367e86e8 bellard
1241 27362c82 bellard
void OPPROTO op_salc(void)
1242 27362c82 bellard
{
1243 27362c82 bellard
    int cf;
1244 27362c82 bellard
    cf = cc_table[CC_OP].compute_c();
1245 27362c82 bellard
    EAX = (EAX & ~0xff) | ((-cf) & 0xff);
1246 27362c82 bellard
}
1247 27362c82 bellard
1248 367e86e8 bellard
static int compute_all_eflags(void)
1249 367e86e8 bellard
{
1250 367e86e8 bellard
    return CC_SRC;
1251 367e86e8 bellard
}
1252 367e86e8 bellard
1253 367e86e8 bellard
static int compute_c_eflags(void)
1254 367e86e8 bellard
{
1255 367e86e8 bellard
    return CC_SRC & CC_C;
1256 367e86e8 bellard
}
1257 367e86e8 bellard
1258 367e86e8 bellard
static int compute_c_mul(void)
1259 367e86e8 bellard
{
1260 367e86e8 bellard
    int cf;
1261 367e86e8 bellard
    cf = (CC_SRC != 0);
1262 367e86e8 bellard
    return cf;
1263 367e86e8 bellard
}
1264 367e86e8 bellard
1265 367e86e8 bellard
static int compute_all_mul(void)
1266 367e86e8 bellard
{
1267 367e86e8 bellard
    int cf, pf, af, zf, sf, of;
1268 367e86e8 bellard
    cf = (CC_SRC != 0);
1269 367e86e8 bellard
    pf = 0; /* undefined */
1270 367e86e8 bellard
    af = 0; /* undefined */
1271 367e86e8 bellard
    zf = 0; /* undefined */
1272 367e86e8 bellard
    sf = 0; /* undefined */
1273 367e86e8 bellard
    of = cf << 11;
1274 367e86e8 bellard
    return cf | pf | af | zf | sf | of;
1275 367e86e8 bellard
}
1276 367e86e8 bellard
    
1277 367e86e8 bellard
CCTable cc_table[CC_OP_NB] = {
1278 367e86e8 bellard
    [CC_OP_DYNAMIC] = { /* should never happen */ },
1279 367e86e8 bellard
1280 367e86e8 bellard
    [CC_OP_EFLAGS] = { compute_all_eflags, compute_c_eflags },
1281 367e86e8 bellard
1282 367e86e8 bellard
    [CC_OP_MUL] = { compute_all_mul, compute_c_mul },
1283 367e86e8 bellard
1284 367e86e8 bellard
    [CC_OP_ADDB] = { compute_all_addb, compute_c_addb },
1285 367e86e8 bellard
    [CC_OP_ADDW] = { compute_all_addw, compute_c_addw  },
1286 367e86e8 bellard
    [CC_OP_ADDL] = { compute_all_addl, compute_c_addl  },
1287 367e86e8 bellard
1288 4b74fe1f bellard
    [CC_OP_ADCB] = { compute_all_adcb, compute_c_adcb },
1289 4b74fe1f bellard
    [CC_OP_ADCW] = { compute_all_adcw, compute_c_adcw  },
1290 4b74fe1f bellard
    [CC_OP_ADCL] = { compute_all_adcl, compute_c_adcl  },
1291 4b74fe1f bellard
1292 367e86e8 bellard
    [CC_OP_SUBB] = { compute_all_subb, compute_c_subb  },
1293 367e86e8 bellard
    [CC_OP_SUBW] = { compute_all_subw, compute_c_subw  },
1294 367e86e8 bellard
    [CC_OP_SUBL] = { compute_all_subl, compute_c_subl  },
1295 367e86e8 bellard
    
1296 4b74fe1f bellard
    [CC_OP_SBBB] = { compute_all_sbbb, compute_c_sbbb  },
1297 4b74fe1f bellard
    [CC_OP_SBBW] = { compute_all_sbbw, compute_c_sbbw  },
1298 4b74fe1f bellard
    [CC_OP_SBBL] = { compute_all_sbbl, compute_c_sbbl  },
1299 4b74fe1f bellard
    
1300 367e86e8 bellard
    [CC_OP_LOGICB] = { compute_all_logicb, compute_c_logicb },
1301 367e86e8 bellard
    [CC_OP_LOGICW] = { compute_all_logicw, compute_c_logicw },
1302 367e86e8 bellard
    [CC_OP_LOGICL] = { compute_all_logicl, compute_c_logicl },
1303 367e86e8 bellard
    
1304 4b74fe1f bellard
    [CC_OP_INCB] = { compute_all_incb, compute_c_incl },
1305 4b74fe1f bellard
    [CC_OP_INCW] = { compute_all_incw, compute_c_incl },
1306 367e86e8 bellard
    [CC_OP_INCL] = { compute_all_incl, compute_c_incl },
1307 367e86e8 bellard
    
1308 4b74fe1f bellard
    [CC_OP_DECB] = { compute_all_decb, compute_c_incl },
1309 4b74fe1f bellard
    [CC_OP_DECW] = { compute_all_decw, compute_c_incl },
1310 367e86e8 bellard
    [CC_OP_DECL] = { compute_all_decl, compute_c_incl },
1311 367e86e8 bellard
    
1312 2792c4f2 bellard
    [CC_OP_SHLB] = { compute_all_shlb, compute_c_shlb },
1313 2792c4f2 bellard
    [CC_OP_SHLW] = { compute_all_shlw, compute_c_shlw },
1314 367e86e8 bellard
    [CC_OP_SHLL] = { compute_all_shll, compute_c_shll },
1315 4b74fe1f bellard
1316 2792c4f2 bellard
    [CC_OP_SARB] = { compute_all_sarb, compute_c_sarl },
1317 2792c4f2 bellard
    [CC_OP_SARW] = { compute_all_sarw, compute_c_sarl },
1318 2792c4f2 bellard
    [CC_OP_SARL] = { compute_all_sarl, compute_c_sarl },
1319 367e86e8 bellard
};
1320 927f621e bellard
1321 f631ef9b bellard
/* floating point support. Some of the code for complicated x87
1322 f631ef9b bellard
   functions comes from the LGPL'ed x86 emulator found in the Willows
1323 f631ef9b bellard
   TWIN windows emulator. */
1324 927f621e bellard
1325 51fe6890 bellard
#if defined(__powerpc__)
1326 51fe6890 bellard
extern CPU86_LDouble copysign(CPU86_LDouble, CPU86_LDouble);
1327 51fe6890 bellard
1328 51fe6890 bellard
/* correct (but slow) PowerPC rint() (glibc version is incorrect) */
1329 51fe6890 bellard
double qemu_rint(double x)
1330 51fe6890 bellard
{
1331 51fe6890 bellard
    double y = 4503599627370496.0;
1332 51fe6890 bellard
    if (fabs(x) >= y)
1333 51fe6890 bellard
        return x;
1334 51fe6890 bellard
    if (x < 0) 
1335 51fe6890 bellard
        y = -y;
1336 51fe6890 bellard
    y = (x + y) - y;
1337 51fe6890 bellard
    if (y == 0.0)
1338 51fe6890 bellard
        y = copysign(y, x);
1339 51fe6890 bellard
    return y;
1340 51fe6890 bellard
}
1341 51fe6890 bellard
1342 51fe6890 bellard
#define rint qemu_rint
1343 51fe6890 bellard
#endif
1344 51fe6890 bellard
1345 927f621e bellard
/* fp load FT0 */
1346 927f621e bellard
1347 927f621e bellard
void OPPROTO op_flds_FT0_A0(void)
1348 927f621e bellard
{
1349 d014c98c bellard
#ifdef USE_FP_CONVERT
1350 d014c98c bellard
    FP_CONVERT.i32 = ldl((void *)A0);
1351 d014c98c bellard
    FT0 = FP_CONVERT.f;
1352 d014c98c bellard
#else
1353 927f621e bellard
    FT0 = ldfl((void *)A0);
1354 d014c98c bellard
#endif
1355 927f621e bellard
}
1356 927f621e bellard
1357 927f621e bellard
void OPPROTO op_fldl_FT0_A0(void)
1358 927f621e bellard
{
1359 d014c98c bellard
#ifdef USE_FP_CONVERT
1360 d014c98c bellard
    FP_CONVERT.i64 = ldq((void *)A0);
1361 d014c98c bellard
    FT0 = FP_CONVERT.d;
1362 d014c98c bellard
#else
1363 927f621e bellard
    FT0 = ldfq((void *)A0);
1364 d014c98c bellard
#endif
1365 927f621e bellard
}
1366 927f621e bellard
1367 04369ff2 bellard
/* helpers are needed to avoid static constant reference. XXX: find a better way */
1368 04369ff2 bellard
#ifdef USE_INT_TO_FLOAT_HELPERS
1369 04369ff2 bellard
1370 04369ff2 bellard
void helper_fild_FT0_A0(void)
1371 04369ff2 bellard
{
1372 04369ff2 bellard
    FT0 = (CPU86_LDouble)ldsw((void *)A0);
1373 04369ff2 bellard
}
1374 04369ff2 bellard
1375 04369ff2 bellard
void helper_fildl_FT0_A0(void)
1376 04369ff2 bellard
{
1377 04369ff2 bellard
    FT0 = (CPU86_LDouble)((int32_t)ldl((void *)A0));
1378 04369ff2 bellard
}
1379 04369ff2 bellard
1380 04369ff2 bellard
void helper_fildll_FT0_A0(void)
1381 04369ff2 bellard
{
1382 04369ff2 bellard
    FT0 = (CPU86_LDouble)((int64_t)ldq((void *)A0));
1383 04369ff2 bellard
}
1384 04369ff2 bellard
1385 04369ff2 bellard
void OPPROTO op_fild_FT0_A0(void)
1386 04369ff2 bellard
{
1387 04369ff2 bellard
    helper_fild_FT0_A0();
1388 04369ff2 bellard
}
1389 04369ff2 bellard
1390 04369ff2 bellard
void OPPROTO op_fildl_FT0_A0(void)
1391 04369ff2 bellard
{
1392 04369ff2 bellard
    helper_fildl_FT0_A0();
1393 04369ff2 bellard
}
1394 04369ff2 bellard
1395 04369ff2 bellard
void OPPROTO op_fildll_FT0_A0(void)
1396 04369ff2 bellard
{
1397 04369ff2 bellard
    helper_fildll_FT0_A0();
1398 04369ff2 bellard
}
1399 04369ff2 bellard
1400 04369ff2 bellard
#else
1401 04369ff2 bellard
1402 927f621e bellard
void OPPROTO op_fild_FT0_A0(void)
1403 927f621e bellard
{
1404 d014c98c bellard
#ifdef USE_FP_CONVERT
1405 d014c98c bellard
    FP_CONVERT.i32 = ldsw((void *)A0);
1406 d014c98c bellard
    FT0 = (CPU86_LDouble)FP_CONVERT.i32;
1407 d014c98c bellard
#else
1408 927f621e bellard
    FT0 = (CPU86_LDouble)ldsw((void *)A0);
1409 d014c98c bellard
#endif
1410 927f621e bellard
}
1411 927f621e bellard
1412 927f621e bellard
void OPPROTO op_fildl_FT0_A0(void)
1413 927f621e bellard
{
1414 d014c98c bellard
#ifdef USE_FP_CONVERT
1415 d014c98c bellard
    FP_CONVERT.i32 = (int32_t) ldl((void *)A0);
1416 d014c98c bellard
    FT0 = (CPU86_LDouble)FP_CONVERT.i32;
1417 d014c98c bellard
#else
1418 927f621e bellard
    FT0 = (CPU86_LDouble)((int32_t)ldl((void *)A0));
1419 d014c98c bellard
#endif
1420 927f621e bellard
}
1421 927f621e bellard
1422 927f621e bellard
void OPPROTO op_fildll_FT0_A0(void)
1423 927f621e bellard
{
1424 d014c98c bellard
#ifdef USE_FP_CONVERT
1425 d014c98c bellard
    FP_CONVERT.i64 = (int64_t) ldq((void *)A0);
1426 d014c98c bellard
    FT0 = (CPU86_LDouble)FP_CONVERT.i64;
1427 d014c98c bellard
#else
1428 927f621e bellard
    FT0 = (CPU86_LDouble)((int64_t)ldq((void *)A0));
1429 d014c98c bellard
#endif
1430 927f621e bellard
}
1431 04369ff2 bellard
#endif
1432 927f621e bellard
1433 927f621e bellard
/* fp load ST0 */
1434 927f621e bellard
1435 927f621e bellard
void OPPROTO op_flds_ST0_A0(void)
1436 927f621e bellard
{
1437 c39d5b78 bellard
    int new_fpstt;
1438 c39d5b78 bellard
    new_fpstt = (env->fpstt - 1) & 7;
1439 d014c98c bellard
#ifdef USE_FP_CONVERT
1440 d014c98c bellard
    FP_CONVERT.i32 = ldl((void *)A0);
1441 c39d5b78 bellard
    env->fpregs[new_fpstt] = FP_CONVERT.f;
1442 d014c98c bellard
#else
1443 c39d5b78 bellard
    env->fpregs[new_fpstt] = ldfl((void *)A0);
1444 d014c98c bellard
#endif
1445 c39d5b78 bellard
    env->fpstt = new_fpstt;
1446 c39d5b78 bellard
    env->fptags[new_fpstt] = 0; /* validate stack entry */
1447 927f621e bellard
}
1448 927f621e bellard
1449 927f621e bellard
void OPPROTO op_fldl_ST0_A0(void)
1450 927f621e bellard
{
1451 c39d5b78 bellard
    int new_fpstt;
1452 c39d5b78 bellard
    new_fpstt = (env->fpstt - 1) & 7;
1453 d014c98c bellard
#ifdef USE_FP_CONVERT
1454 d014c98c bellard
    FP_CONVERT.i64 = ldq((void *)A0);
1455 c39d5b78 bellard
    env->fpregs[new_fpstt] = FP_CONVERT.d;
1456 d014c98c bellard
#else
1457 c39d5b78 bellard
    env->fpregs[new_fpstt] = ldfq((void *)A0);
1458 d014c98c bellard
#endif
1459 c39d5b78 bellard
    env->fpstt = new_fpstt;
1460 c39d5b78 bellard
    env->fptags[new_fpstt] = 0; /* validate stack entry */
1461 927f621e bellard
}
1462 927f621e bellard
1463 77f8dd5a bellard
#ifdef USE_X86LDOUBLE
1464 77f8dd5a bellard
void OPPROTO op_fldt_ST0_A0(void)
1465 77f8dd5a bellard
{
1466 c39d5b78 bellard
    int new_fpstt;
1467 c39d5b78 bellard
    new_fpstt = (env->fpstt - 1) & 7;
1468 c39d5b78 bellard
    env->fpregs[new_fpstt] = *(long double *)A0;
1469 c39d5b78 bellard
    env->fpstt = new_fpstt;
1470 c39d5b78 bellard
    env->fptags[new_fpstt] = 0; /* validate stack entry */
1471 77f8dd5a bellard
}
1472 77f8dd5a bellard
#else
1473 77f8dd5a bellard
void OPPROTO op_fldt_ST0_A0(void)
1474 77f8dd5a bellard
{
1475 77f8dd5a bellard
    helper_fldt_ST0_A0();
1476 77f8dd5a bellard
}
1477 77f8dd5a bellard
#endif
1478 77f8dd5a bellard
1479 04369ff2 bellard
/* helpers are needed to avoid static constant reference. XXX: find a better way */
1480 04369ff2 bellard
#ifdef USE_INT_TO_FLOAT_HELPERS
1481 04369ff2 bellard
1482 04369ff2 bellard
void helper_fild_ST0_A0(void)
1483 04369ff2 bellard
{
1484 c39d5b78 bellard
    int new_fpstt;
1485 c39d5b78 bellard
    new_fpstt = (env->fpstt - 1) & 7;
1486 c39d5b78 bellard
    env->fpregs[new_fpstt] = (CPU86_LDouble)ldsw((void *)A0);
1487 c39d5b78 bellard
    env->fpstt = new_fpstt;
1488 c39d5b78 bellard
    env->fptags[new_fpstt] = 0; /* validate stack entry */
1489 04369ff2 bellard
}
1490 04369ff2 bellard
1491 04369ff2 bellard
void helper_fildl_ST0_A0(void)
1492 04369ff2 bellard
{
1493 c39d5b78 bellard
    int new_fpstt;
1494 c39d5b78 bellard
    new_fpstt = (env->fpstt - 1) & 7;
1495 c39d5b78 bellard
    env->fpregs[new_fpstt] = (CPU86_LDouble)((int32_t)ldl((void *)A0));
1496 c39d5b78 bellard
    env->fpstt = new_fpstt;
1497 c39d5b78 bellard
    env->fptags[new_fpstt] = 0; /* validate stack entry */
1498 04369ff2 bellard
}
1499 04369ff2 bellard
1500 04369ff2 bellard
void helper_fildll_ST0_A0(void)
1501 04369ff2 bellard
{
1502 c39d5b78 bellard
    int new_fpstt;
1503 c39d5b78 bellard
    new_fpstt = (env->fpstt - 1) & 7;
1504 c39d5b78 bellard
    env->fpregs[new_fpstt] = (CPU86_LDouble)((int64_t)ldq((void *)A0));
1505 c39d5b78 bellard
    env->fpstt = new_fpstt;
1506 c39d5b78 bellard
    env->fptags[new_fpstt] = 0; /* validate stack entry */
1507 04369ff2 bellard
}
1508 04369ff2 bellard
1509 04369ff2 bellard
void OPPROTO op_fild_ST0_A0(void)
1510 04369ff2 bellard
{
1511 04369ff2 bellard
    helper_fild_ST0_A0();
1512 04369ff2 bellard
}
1513 04369ff2 bellard
1514 04369ff2 bellard
void OPPROTO op_fildl_ST0_A0(void)
1515 04369ff2 bellard
{
1516 04369ff2 bellard
    helper_fildl_ST0_A0();
1517 04369ff2 bellard
}
1518 04369ff2 bellard
1519 04369ff2 bellard
void OPPROTO op_fildll_ST0_A0(void)
1520 04369ff2 bellard
{
1521 04369ff2 bellard
    helper_fildll_ST0_A0();
1522 04369ff2 bellard
}
1523 04369ff2 bellard
1524 04369ff2 bellard
#else
1525 04369ff2 bellard
1526 927f621e bellard
void OPPROTO op_fild_ST0_A0(void)
1527 927f621e bellard
{
1528 c39d5b78 bellard
    int new_fpstt;
1529 c39d5b78 bellard
    new_fpstt = (env->fpstt - 1) & 7;
1530 d014c98c bellard
#ifdef USE_FP_CONVERT
1531 d014c98c bellard
    FP_CONVERT.i32 = ldsw((void *)A0);
1532 c39d5b78 bellard
    env->fpregs[new_fpstt] = (CPU86_LDouble)FP_CONVERT.i32;
1533 d014c98c bellard
#else
1534 c39d5b78 bellard
    env->fpregs[new_fpstt] = (CPU86_LDouble)ldsw((void *)A0);
1535 d014c98c bellard
#endif
1536 c39d5b78 bellard
    env->fpstt = new_fpstt;
1537 c39d5b78 bellard
    env->fptags[new_fpstt] = 0; /* validate stack entry */
1538 927f621e bellard
}
1539 927f621e bellard
1540 927f621e bellard
void OPPROTO op_fildl_ST0_A0(void)
1541 927f621e bellard
{
1542 c39d5b78 bellard
    int new_fpstt;
1543 c39d5b78 bellard
    new_fpstt = (env->fpstt - 1) & 7;
1544 d014c98c bellard
#ifdef USE_FP_CONVERT
1545 d014c98c bellard
    FP_CONVERT.i32 = (int32_t) ldl((void *)A0);
1546 c39d5b78 bellard
    env->fpregs[new_fpstt] = (CPU86_LDouble)FP_CONVERT.i32;
1547 d014c98c bellard
#else
1548 c39d5b78 bellard
    env->fpregs[new_fpstt] = (CPU86_LDouble)((int32_t)ldl((void *)A0));
1549 d014c98c bellard
#endif
1550 c39d5b78 bellard
    env->fpstt = new_fpstt;
1551 c39d5b78 bellard
    env->fptags[new_fpstt] = 0; /* validate stack entry */
1552 927f621e bellard
}
1553 927f621e bellard
1554 927f621e bellard
void OPPROTO op_fildll_ST0_A0(void)
1555 927f621e bellard
{
1556 c39d5b78 bellard
    int new_fpstt;
1557 c39d5b78 bellard
    new_fpstt = (env->fpstt - 1) & 7;
1558 d014c98c bellard
#ifdef USE_FP_CONVERT
1559 d014c98c bellard
    FP_CONVERT.i64 = (int64_t) ldq((void *)A0);
1560 c39d5b78 bellard
    env->fpregs[new_fpstt] = (CPU86_LDouble)FP_CONVERT.i64;
1561 d014c98c bellard
#else
1562 c39d5b78 bellard
    env->fpregs[new_fpstt] = (CPU86_LDouble)((int64_t)ldq((void *)A0));
1563 d014c98c bellard
#endif
1564 c39d5b78 bellard
    env->fpstt = new_fpstt;
1565 c39d5b78 bellard
    env->fptags[new_fpstt] = 0; /* validate stack entry */
1566 927f621e bellard
}
1567 927f621e bellard
1568 04369ff2 bellard
#endif
1569 04369ff2 bellard
1570 927f621e bellard
/* fp store */
1571 927f621e bellard
1572 927f621e bellard
void OPPROTO op_fsts_ST0_A0(void)
1573 927f621e bellard
{
1574 d014c98c bellard
#ifdef USE_FP_CONVERT
1575 87f4827e bellard
    FP_CONVERT.f = (float)ST0;
1576 d014c98c bellard
    stfl((void *)A0, FP_CONVERT.f);
1577 d014c98c bellard
#else
1578 927f621e bellard
    stfl((void *)A0, (float)ST0);
1579 d014c98c bellard
#endif
1580 927f621e bellard
}
1581 927f621e bellard
1582 927f621e bellard
void OPPROTO op_fstl_ST0_A0(void)
1583 927f621e bellard
{
1584 77f8dd5a bellard
    stfq((void *)A0, (double)ST0);
1585 927f621e bellard
}
1586 927f621e bellard
1587 77f8dd5a bellard
#ifdef USE_X86LDOUBLE
1588 77f8dd5a bellard
void OPPROTO op_fstt_ST0_A0(void)
1589 77f8dd5a bellard
{
1590 77f8dd5a bellard
    *(long double *)A0 = ST0;
1591 77f8dd5a bellard
}
1592 77f8dd5a bellard
#else
1593 77f8dd5a bellard
void OPPROTO op_fstt_ST0_A0(void)
1594 77f8dd5a bellard
{
1595 77f8dd5a bellard
    helper_fstt_ST0_A0();
1596 77f8dd5a bellard
}
1597 77f8dd5a bellard
#endif
1598 77f8dd5a bellard
1599 927f621e bellard
void OPPROTO op_fist_ST0_A0(void)
1600 927f621e bellard
{
1601 d014c98c bellard
#if defined(__sparc__) && !defined(__sparc_v9__)
1602 d014c98c bellard
    register CPU86_LDouble d asm("o0");
1603 d014c98c bellard
#else
1604 d014c98c bellard
    CPU86_LDouble d;
1605 d014c98c bellard
#endif
1606 927f621e bellard
    int val;
1607 d014c98c bellard
1608 d014c98c bellard
    d = ST0;
1609 d014c98c bellard
    val = lrint(d);
1610 1e5ffbed bellard
    if (val != (int16_t)val)
1611 1e5ffbed bellard
        val = -32768;
1612 927f621e bellard
    stw((void *)A0, val);
1613 927f621e bellard
}
1614 927f621e bellard
1615 927f621e bellard
void OPPROTO op_fistl_ST0_A0(void)
1616 927f621e bellard
{
1617 d014c98c bellard
#if defined(__sparc__) && !defined(__sparc_v9__)
1618 d014c98c bellard
    register CPU86_LDouble d asm("o0");
1619 d014c98c bellard
#else
1620 d014c98c bellard
    CPU86_LDouble d;
1621 d014c98c bellard
#endif
1622 927f621e bellard
    int val;
1623 d014c98c bellard
1624 d014c98c bellard
    d = ST0;
1625 d014c98c bellard
    val = lrint(d);
1626 927f621e bellard
    stl((void *)A0, val);
1627 927f621e bellard
}
1628 927f621e bellard
1629 927f621e bellard
void OPPROTO op_fistll_ST0_A0(void)
1630 927f621e bellard
{
1631 d014c98c bellard
#if defined(__sparc__) && !defined(__sparc_v9__)
1632 d014c98c bellard
    register CPU86_LDouble d asm("o0");
1633 d014c98c bellard
#else
1634 d014c98c bellard
    CPU86_LDouble d;
1635 d014c98c bellard
#endif
1636 927f621e bellard
    int64_t val;
1637 d014c98c bellard
1638 d014c98c bellard
    d = ST0;
1639 d014c98c bellard
    val = llrint(d);
1640 927f621e bellard
    stq((void *)A0, val);
1641 927f621e bellard
}
1642 927f621e bellard
1643 77f8dd5a bellard
void OPPROTO op_fbld_ST0_A0(void)
1644 77f8dd5a bellard
{
1645 77f8dd5a bellard
    helper_fbld_ST0_A0();
1646 77f8dd5a bellard
}
1647 77f8dd5a bellard
1648 77f8dd5a bellard
void OPPROTO op_fbst_ST0_A0(void)
1649 77f8dd5a bellard
{
1650 77f8dd5a bellard
    helper_fbst_ST0_A0();
1651 77f8dd5a bellard
}
1652 77f8dd5a bellard
1653 927f621e bellard
/* FPU move */
1654 927f621e bellard
1655 927f621e bellard
void OPPROTO op_fpush(void)
1656 927f621e bellard
{
1657 927f621e bellard
    fpush();
1658 927f621e bellard
}
1659 927f621e bellard
1660 927f621e bellard
void OPPROTO op_fpop(void)
1661 927f621e bellard
{
1662 927f621e bellard
    fpop();
1663 927f621e bellard
}
1664 927f621e bellard
1665 927f621e bellard
void OPPROTO op_fdecstp(void)
1666 927f621e bellard
{
1667 927f621e bellard
    env->fpstt = (env->fpstt - 1) & 7;
1668 927f621e bellard
    env->fpus &= (~0x4700);
1669 927f621e bellard
}
1670 927f621e bellard
1671 927f621e bellard
void OPPROTO op_fincstp(void)
1672 927f621e bellard
{
1673 927f621e bellard
    env->fpstt = (env->fpstt + 1) & 7;
1674 927f621e bellard
    env->fpus &= (~0x4700);
1675 927f621e bellard
}
1676 927f621e bellard
1677 927f621e bellard
void OPPROTO op_fmov_ST0_FT0(void)
1678 927f621e bellard
{
1679 927f621e bellard
    ST0 = FT0;
1680 927f621e bellard
}
1681 927f621e bellard
1682 927f621e bellard
void OPPROTO op_fmov_FT0_STN(void)
1683 927f621e bellard
{
1684 927f621e bellard
    FT0 = ST(PARAM1);
1685 927f621e bellard
}
1686 927f621e bellard
1687 927f621e bellard
void OPPROTO op_fmov_ST0_STN(void)
1688 927f621e bellard
{
1689 927f621e bellard
    ST0 = ST(PARAM1);
1690 927f621e bellard
}
1691 927f621e bellard
1692 927f621e bellard
void OPPROTO op_fmov_STN_ST0(void)
1693 927f621e bellard
{
1694 927f621e bellard
    ST(PARAM1) = ST0;
1695 927f621e bellard
}
1696 927f621e bellard
1697 927f621e bellard
void OPPROTO op_fxchg_ST0_STN(void)
1698 927f621e bellard
{
1699 927f621e bellard
    CPU86_LDouble tmp;
1700 927f621e bellard
    tmp = ST(PARAM1);
1701 927f621e bellard
    ST(PARAM1) = ST0;
1702 927f621e bellard
    ST0 = tmp;
1703 927f621e bellard
}
1704 927f621e bellard
1705 927f621e bellard
/* FPU operations */
1706 927f621e bellard
1707 927f621e bellard
/* XXX: handle nans */
1708 927f621e bellard
void OPPROTO op_fcom_ST0_FT0(void)
1709 927f621e bellard
{
1710 927f621e bellard
    env->fpus &= (~0x4500);        /* (C3,C2,C0) <-- 000 */
1711 927f621e bellard
    if (ST0 < FT0)
1712 927f621e bellard
        env->fpus |= 0x100;        /* (C3,C2,C0) <-- 001 */
1713 927f621e bellard
    else if (ST0 == FT0)
1714 927f621e bellard
        env->fpus |= 0x4000; /* (C3,C2,C0) <-- 100 */
1715 927f621e bellard
    FORCE_RET();
1716 927f621e bellard
}
1717 927f621e bellard
1718 77f8dd5a bellard
/* XXX: handle nans */
1719 77f8dd5a bellard
void OPPROTO op_fucom_ST0_FT0(void)
1720 77f8dd5a bellard
{
1721 77f8dd5a bellard
    env->fpus &= (~0x4500);        /* (C3,C2,C0) <-- 000 */
1722 77f8dd5a bellard
    if (ST0 < FT0)
1723 77f8dd5a bellard
        env->fpus |= 0x100;        /* (C3,C2,C0) <-- 001 */
1724 77f8dd5a bellard
    else if (ST0 == FT0)
1725 77f8dd5a bellard
        env->fpus |= 0x4000; /* (C3,C2,C0) <-- 100 */
1726 77f8dd5a bellard
    FORCE_RET();
1727 77f8dd5a bellard
}
1728 77f8dd5a bellard
1729 d0a1ffc9 bellard
/* XXX: handle nans */
1730 d0a1ffc9 bellard
void OPPROTO op_fcomi_ST0_FT0(void)
1731 d0a1ffc9 bellard
{
1732 d0a1ffc9 bellard
    int eflags;
1733 d0a1ffc9 bellard
    eflags = cc_table[CC_OP].compute_all();
1734 d0a1ffc9 bellard
    eflags &= ~(CC_Z | CC_P | CC_C);
1735 d0a1ffc9 bellard
    if (ST0 < FT0)
1736 d0a1ffc9 bellard
        eflags |= CC_C;
1737 d0a1ffc9 bellard
    else if (ST0 == FT0)
1738 d0a1ffc9 bellard
        eflags |= CC_Z;
1739 d0a1ffc9 bellard
    CC_SRC = eflags;
1740 d0a1ffc9 bellard
    FORCE_RET();
1741 d0a1ffc9 bellard
}
1742 d0a1ffc9 bellard
1743 d0a1ffc9 bellard
/* XXX: handle nans */
1744 d0a1ffc9 bellard
void OPPROTO op_fucomi_ST0_FT0(void)
1745 d0a1ffc9 bellard
{
1746 d0a1ffc9 bellard
    int eflags;
1747 d0a1ffc9 bellard
    eflags = cc_table[CC_OP].compute_all();
1748 d0a1ffc9 bellard
    eflags &= ~(CC_Z | CC_P | CC_C);
1749 d0a1ffc9 bellard
    if (ST0 < FT0)
1750 d0a1ffc9 bellard
        eflags |= CC_C;
1751 d0a1ffc9 bellard
    else if (ST0 == FT0)
1752 d0a1ffc9 bellard
        eflags |= CC_Z;
1753 d0a1ffc9 bellard
    CC_SRC = eflags;
1754 d0a1ffc9 bellard
    FORCE_RET();
1755 d0a1ffc9 bellard
}
1756 d0a1ffc9 bellard
1757 927f621e bellard
void OPPROTO op_fadd_ST0_FT0(void)
1758 927f621e bellard
{
1759 927f621e bellard
    ST0 += FT0;
1760 927f621e bellard
}
1761 927f621e bellard
1762 927f621e bellard
void OPPROTO op_fmul_ST0_FT0(void)
1763 927f621e bellard
{
1764 927f621e bellard
    ST0 *= FT0;
1765 927f621e bellard
}
1766 927f621e bellard
1767 927f621e bellard
void OPPROTO op_fsub_ST0_FT0(void)
1768 927f621e bellard
{
1769 927f621e bellard
    ST0 -= FT0;
1770 927f621e bellard
}
1771 927f621e bellard
1772 927f621e bellard
void OPPROTO op_fsubr_ST0_FT0(void)
1773 927f621e bellard
{
1774 927f621e bellard
    ST0 = FT0 - ST0;
1775 927f621e bellard
}
1776 927f621e bellard
1777 927f621e bellard
void OPPROTO op_fdiv_ST0_FT0(void)
1778 927f621e bellard
{
1779 927f621e bellard
    ST0 /= FT0;
1780 927f621e bellard
}
1781 927f621e bellard
1782 927f621e bellard
void OPPROTO op_fdivr_ST0_FT0(void)
1783 927f621e bellard
{
1784 927f621e bellard
    ST0 = FT0 / ST0;
1785 927f621e bellard
}
1786 927f621e bellard
1787 927f621e bellard
/* fp operations between STN and ST0 */
1788 927f621e bellard
1789 927f621e bellard
void OPPROTO op_fadd_STN_ST0(void)
1790 927f621e bellard
{
1791 927f621e bellard
    ST(PARAM1) += ST0;
1792 927f621e bellard
}
1793 927f621e bellard
1794 927f621e bellard
void OPPROTO op_fmul_STN_ST0(void)
1795 927f621e bellard
{
1796 927f621e bellard
    ST(PARAM1) *= ST0;
1797 927f621e bellard
}
1798 927f621e bellard
1799 927f621e bellard
void OPPROTO op_fsub_STN_ST0(void)
1800 927f621e bellard
{
1801 927f621e bellard
    ST(PARAM1) -= ST0;
1802 927f621e bellard
}
1803 927f621e bellard
1804 927f621e bellard
void OPPROTO op_fsubr_STN_ST0(void)
1805 927f621e bellard
{
1806 927f621e bellard
    CPU86_LDouble *p;
1807 927f621e bellard
    p = &ST(PARAM1);
1808 927f621e bellard
    *p = ST0 - *p;
1809 927f621e bellard
}
1810 927f621e bellard
1811 927f621e bellard
void OPPROTO op_fdiv_STN_ST0(void)
1812 927f621e bellard
{
1813 927f621e bellard
    ST(PARAM1) /= ST0;
1814 927f621e bellard
}
1815 927f621e bellard
1816 927f621e bellard
void OPPROTO op_fdivr_STN_ST0(void)
1817 927f621e bellard
{
1818 927f621e bellard
    CPU86_LDouble *p;
1819 927f621e bellard
    p = &ST(PARAM1);
1820 927f621e bellard
    *p = ST0 / *p;
1821 927f621e bellard
}
1822 927f621e bellard
1823 927f621e bellard
/* misc FPU operations */
1824 927f621e bellard
void OPPROTO op_fchs_ST0(void)
1825 927f621e bellard
{
1826 927f621e bellard
    ST0 = -ST0;
1827 927f621e bellard
}
1828 927f621e bellard
1829 927f621e bellard
void OPPROTO op_fabs_ST0(void)
1830 927f621e bellard
{
1831 927f621e bellard
    ST0 = fabs(ST0);
1832 927f621e bellard
}
1833 927f621e bellard
1834 77f8dd5a bellard
void OPPROTO op_fxam_ST0(void)
1835 77f8dd5a bellard
{
1836 77f8dd5a bellard
    helper_fxam_ST0();
1837 927f621e bellard
}
1838 927f621e bellard
1839 927f621e bellard
void OPPROTO op_fld1_ST0(void)
1840 927f621e bellard
{
1841 87f4827e bellard
    ST0 = f15rk[1];
1842 927f621e bellard
}
1843 927f621e bellard
1844 77f8dd5a bellard
void OPPROTO op_fldl2t_ST0(void)
1845 927f621e bellard
{
1846 87f4827e bellard
    ST0 = f15rk[6];
1847 927f621e bellard
}
1848 927f621e bellard
1849 77f8dd5a bellard
void OPPROTO op_fldl2e_ST0(void)
1850 927f621e bellard
{
1851 87f4827e bellard
    ST0 = f15rk[5];
1852 927f621e bellard
}
1853 927f621e bellard
1854 927f621e bellard
void OPPROTO op_fldpi_ST0(void)
1855 927f621e bellard
{
1856 87f4827e bellard
    ST0 = f15rk[2];
1857 927f621e bellard
}
1858 927f621e bellard
1859 927f621e bellard
void OPPROTO op_fldlg2_ST0(void)
1860 927f621e bellard
{
1861 87f4827e bellard
    ST0 = f15rk[3];
1862 927f621e bellard
}
1863 927f621e bellard
1864 927f621e bellard
void OPPROTO op_fldln2_ST0(void)
1865 927f621e bellard
{
1866 87f4827e bellard
    ST0 = f15rk[4];
1867 927f621e bellard
}
1868 927f621e bellard
1869 927f621e bellard
void OPPROTO op_fldz_ST0(void)
1870 927f621e bellard
{
1871 87f4827e bellard
    ST0 = f15rk[0];
1872 927f621e bellard
}
1873 927f621e bellard
1874 927f621e bellard
void OPPROTO op_fldz_FT0(void)
1875 927f621e bellard
{
1876 87f4827e bellard
    ST0 = f15rk[0];
1877 927f621e bellard
}
1878 927f621e bellard
1879 927f621e bellard
/* associated heplers to reduce generated code length and to simplify
1880 927f621e bellard
   relocation (FP constants are usually stored in .rodata section) */
1881 927f621e bellard
1882 927f621e bellard
void OPPROTO op_f2xm1(void)
1883 927f621e bellard
{
1884 927f621e bellard
    helper_f2xm1();
1885 927f621e bellard
}
1886 927f621e bellard
1887 927f621e bellard
void OPPROTO op_fyl2x(void)
1888 927f621e bellard
{
1889 927f621e bellard
    helper_fyl2x();
1890 927f621e bellard
}
1891 927f621e bellard
1892 927f621e bellard
void OPPROTO op_fptan(void)
1893 927f621e bellard
{
1894 927f621e bellard
    helper_fptan();
1895 927f621e bellard
}
1896 927f621e bellard
1897 927f621e bellard
void OPPROTO op_fpatan(void)
1898 927f621e bellard
{
1899 927f621e bellard
    helper_fpatan();
1900 927f621e bellard
}
1901 927f621e bellard
1902 927f621e bellard
void OPPROTO op_fxtract(void)
1903 927f621e bellard
{
1904 927f621e bellard
    helper_fxtract();
1905 927f621e bellard
}
1906 927f621e bellard
1907 927f621e bellard
void OPPROTO op_fprem1(void)
1908 927f621e bellard
{
1909 927f621e bellard
    helper_fprem1();
1910 927f621e bellard
}
1911 927f621e bellard
1912 927f621e bellard
1913 927f621e bellard
void OPPROTO op_fprem(void)
1914 927f621e bellard
{
1915 927f621e bellard
    helper_fprem();
1916 927f621e bellard
}
1917 927f621e bellard
1918 927f621e bellard
void OPPROTO op_fyl2xp1(void)
1919 927f621e bellard
{
1920 927f621e bellard
    helper_fyl2xp1();
1921 927f621e bellard
}
1922 927f621e bellard
1923 927f621e bellard
void OPPROTO op_fsqrt(void)
1924 927f621e bellard
{
1925 927f621e bellard
    helper_fsqrt();
1926 927f621e bellard
}
1927 927f621e bellard
1928 927f621e bellard
void OPPROTO op_fsincos(void)
1929 927f621e bellard
{
1930 927f621e bellard
    helper_fsincos();
1931 927f621e bellard
}
1932 927f621e bellard
1933 927f621e bellard
void OPPROTO op_frndint(void)
1934 927f621e bellard
{
1935 927f621e bellard
    helper_frndint();
1936 927f621e bellard
}
1937 927f621e bellard
1938 927f621e bellard
void OPPROTO op_fscale(void)
1939 927f621e bellard
{
1940 927f621e bellard
    helper_fscale();
1941 927f621e bellard
}
1942 927f621e bellard
1943 927f621e bellard
void OPPROTO op_fsin(void)
1944 927f621e bellard
{
1945 927f621e bellard
    helper_fsin();
1946 927f621e bellard
}
1947 927f621e bellard
1948 927f621e bellard
void OPPROTO op_fcos(void)
1949 927f621e bellard
{
1950 927f621e bellard
    helper_fcos();
1951 927f621e bellard
}
1952 927f621e bellard
1953 4b74fe1f bellard
void OPPROTO op_fnstsw_A0(void)
1954 4b74fe1f bellard
{
1955 4b74fe1f bellard
    int fpus;
1956 4b74fe1f bellard
    fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
1957 4b74fe1f bellard
    stw((void *)A0, fpus);
1958 4b74fe1f bellard
}
1959 4b74fe1f bellard
1960 77f8dd5a bellard
void OPPROTO op_fnstsw_EAX(void)
1961 77f8dd5a bellard
{
1962 77f8dd5a bellard
    int fpus;
1963 77f8dd5a bellard
    fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
1964 77f8dd5a bellard
    EAX = (EAX & 0xffff0000) | fpus;
1965 77f8dd5a bellard
}
1966 77f8dd5a bellard
1967 4b74fe1f bellard
void OPPROTO op_fnstcw_A0(void)
1968 4b74fe1f bellard
{
1969 4b74fe1f bellard
    stw((void *)A0, env->fpuc);
1970 4b74fe1f bellard
}
1971 4b74fe1f bellard
1972 4b74fe1f bellard
void OPPROTO op_fldcw_A0(void)
1973 4b74fe1f bellard
{
1974 4b74fe1f bellard
    int rnd_type;
1975 4b74fe1f bellard
    env->fpuc = lduw((void *)A0);
1976 4b74fe1f bellard
    /* set rounding mode */
1977 4b74fe1f bellard
    switch(env->fpuc & RC_MASK) {
1978 4b74fe1f bellard
    default:
1979 4b74fe1f bellard
    case RC_NEAR:
1980 4b74fe1f bellard
        rnd_type = FE_TONEAREST;
1981 4b74fe1f bellard
        break;
1982 4b74fe1f bellard
    case RC_DOWN:
1983 4b74fe1f bellard
        rnd_type = FE_DOWNWARD;
1984 4b74fe1f bellard
        break;
1985 4b74fe1f bellard
    case RC_UP:
1986 4b74fe1f bellard
        rnd_type = FE_UPWARD;
1987 4b74fe1f bellard
        break;
1988 4b74fe1f bellard
    case RC_CHOP:
1989 4b74fe1f bellard
        rnd_type = FE_TOWARDZERO;
1990 4b74fe1f bellard
        break;
1991 4b74fe1f bellard
    }
1992 4b74fe1f bellard
    fesetround(rnd_type);
1993 4b74fe1f bellard
}
1994 4b74fe1f bellard
1995 1a9353d2 bellard
void OPPROTO op_fclex(void)
1996 1a9353d2 bellard
{
1997 1a9353d2 bellard
    env->fpus &= 0x7f00;
1998 1a9353d2 bellard
}
1999 1a9353d2 bellard
2000 1a9353d2 bellard
void OPPROTO op_fninit(void)
2001 1a9353d2 bellard
{
2002 1a9353d2 bellard
    env->fpus = 0;
2003 1a9353d2 bellard
    env->fpstt = 0;
2004 1a9353d2 bellard
    env->fpuc = 0x37f;
2005 1a9353d2 bellard
    env->fptags[0] = 1;
2006 1a9353d2 bellard
    env->fptags[1] = 1;
2007 1a9353d2 bellard
    env->fptags[2] = 1;
2008 1a9353d2 bellard
    env->fptags[3] = 1;
2009 1a9353d2 bellard
    env->fptags[4] = 1;
2010 1a9353d2 bellard
    env->fptags[5] = 1;
2011 1a9353d2 bellard
    env->fptags[6] = 1;
2012 1a9353d2 bellard
    env->fptags[7] = 1;
2013 1a9353d2 bellard
}
2014 1b6b029e bellard
2015 d0a1ffc9 bellard
void OPPROTO op_fnstenv_A0(void)
2016 d0a1ffc9 bellard
{
2017 d0a1ffc9 bellard
    helper_fstenv((uint8_t *)A0, PARAM1);
2018 d0a1ffc9 bellard
}
2019 d0a1ffc9 bellard
2020 d0a1ffc9 bellard
void OPPROTO op_fldenv_A0(void)
2021 d0a1ffc9 bellard
{
2022 d0a1ffc9 bellard
    helper_fldenv((uint8_t *)A0, PARAM1);
2023 d0a1ffc9 bellard
}
2024 d0a1ffc9 bellard
2025 d0a1ffc9 bellard
void OPPROTO op_fnsave_A0(void)
2026 d0a1ffc9 bellard
{
2027 d0a1ffc9 bellard
    helper_fsave((uint8_t *)A0, PARAM1);
2028 d0a1ffc9 bellard
}
2029 d0a1ffc9 bellard
2030 d0a1ffc9 bellard
void OPPROTO op_frstor_A0(void)
2031 d0a1ffc9 bellard
{
2032 d0a1ffc9 bellard
    helper_frstor((uint8_t *)A0, PARAM1);
2033 d0a1ffc9 bellard
}
2034 d0a1ffc9 bellard
2035 1b6b029e bellard
/* threading support */
2036 1b6b029e bellard
void OPPROTO op_lock(void)
2037 1b6b029e bellard
{
2038 1b6b029e bellard
    cpu_lock();
2039 1b6b029e bellard
}
2040 1b6b029e bellard
2041 1b6b029e bellard
void OPPROTO op_unlock(void)
2042 1b6b029e bellard
{
2043 1b6b029e bellard
    cpu_unlock();
2044 1b6b029e bellard
}