root / target-ppc / helper.c @ fb0eaffc
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1 | 79aceca5 | bellard | /*
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2 | 79aceca5 | bellard | * PPC emulation helpers for qemu.
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3 | 79aceca5 | bellard | *
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4 | 79aceca5 | bellard | * Copyright (c) 2003 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | 79aceca5 | bellard | #include "exec.h" |
21 | 79aceca5 | bellard | |
22 | 79aceca5 | bellard | extern FILE *logfile;
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23 | 79aceca5 | bellard | |
24 | 79aceca5 | bellard | void cpu_loop_exit(void) |
25 | 79aceca5 | bellard | { |
26 | 79aceca5 | bellard | longjmp(env->jmp_env, 1);
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27 | 79aceca5 | bellard | } |
28 | 79aceca5 | bellard | |
29 | 79aceca5 | bellard | /* shortcuts to generate exceptions */
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30 | 79aceca5 | bellard | void raise_exception_err (int exception_index, int error_code) |
31 | 79aceca5 | bellard | { |
32 | 79aceca5 | bellard | env->exception_index = exception_index; |
33 | 79aceca5 | bellard | env->error_code = error_code; |
34 | 79aceca5 | bellard | |
35 | 79aceca5 | bellard | cpu_loop_exit(); |
36 | 79aceca5 | bellard | } |
37 | 79aceca5 | bellard | |
38 | 79aceca5 | bellard | void raise_exception (int exception_index) |
39 | 79aceca5 | bellard | { |
40 | 79aceca5 | bellard | env->exception_index = exception_index; |
41 | 79aceca5 | bellard | env->error_code = 0;
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42 | 79aceca5 | bellard | |
43 | 79aceca5 | bellard | cpu_loop_exit(); |
44 | 79aceca5 | bellard | } |
45 | 79aceca5 | bellard | |
46 | 79aceca5 | bellard | /* Helpers for "fat" micro operations */
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47 | 79aceca5 | bellard | uint32_t do_load_cr (void)
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48 | 79aceca5 | bellard | { |
49 | 79aceca5 | bellard | return (env->crf[0] << 28) | |
50 | 79aceca5 | bellard | (env->crf[1] << 24) | |
51 | 79aceca5 | bellard | (env->crf[2] << 20) | |
52 | 79aceca5 | bellard | (env->crf[3] << 16) | |
53 | 79aceca5 | bellard | (env->crf[4] << 12) | |
54 | 79aceca5 | bellard | (env->crf[5] << 8) | |
55 | 79aceca5 | bellard | (env->crf[6] << 4) | |
56 | 79aceca5 | bellard | (env->crf[7] << 0); |
57 | 79aceca5 | bellard | } |
58 | 79aceca5 | bellard | |
59 | 79aceca5 | bellard | void do_store_cr (uint32_t crn, uint32_t value)
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60 | 79aceca5 | bellard | { |
61 | 79aceca5 | bellard | int i, sh;
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62 | 79aceca5 | bellard | |
63 | 79aceca5 | bellard | for (i = 0, sh = 7; i < 8; i++, sh --) { |
64 | 79aceca5 | bellard | if (crn & (1 << sh)) |
65 | 79aceca5 | bellard | env->crf[i] = (value >> (sh * 4)) & 0xF; |
66 | 79aceca5 | bellard | } |
67 | 79aceca5 | bellard | } |
68 | 79aceca5 | bellard | |
69 | 79aceca5 | bellard | uint32_t do_load_xer (void)
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70 | 79aceca5 | bellard | { |
71 | 79aceca5 | bellard | return (xer_so << XER_SO) |
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72 | 79aceca5 | bellard | (xer_ov << XER_OV) | |
73 | 79aceca5 | bellard | (xer_ca << XER_CA) | |
74 | 79aceca5 | bellard | (xer_bc << XER_BC); |
75 | 79aceca5 | bellard | } |
76 | 79aceca5 | bellard | |
77 | 79aceca5 | bellard | void do_store_xer (uint32_t value)
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78 | 79aceca5 | bellard | { |
79 | 79aceca5 | bellard | xer_so = (value >> XER_SO) & 0x01;
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80 | 79aceca5 | bellard | xer_ov = (value >> XER_OV) & 0x01;
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81 | 79aceca5 | bellard | xer_ca = (value >> XER_CA) & 0x01;
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82 | 79aceca5 | bellard | xer_bc = (value >> XER_BC) & 0x1f;
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83 | 79aceca5 | bellard | } |
84 | 79aceca5 | bellard | |
85 | 79aceca5 | bellard | uint32_t do_load_msr (void)
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86 | 79aceca5 | bellard | { |
87 | 79aceca5 | bellard | return (msr_pow << MSR_POW) |
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88 | 79aceca5 | bellard | (msr_ile << MSR_ILE) | |
89 | 79aceca5 | bellard | (msr_ee << MSR_EE) | |
90 | 79aceca5 | bellard | (msr_pr << MSR_PR) | |
91 | 79aceca5 | bellard | (msr_fp << MSR_FP) | |
92 | 79aceca5 | bellard | (msr_me << MSR_ME) | |
93 | 79aceca5 | bellard | (msr_fe0 << MSR_FE0) | |
94 | 79aceca5 | bellard | (msr_se << MSR_SE) | |
95 | 79aceca5 | bellard | (msr_be << MSR_BE) | |
96 | 79aceca5 | bellard | (msr_fe1 << MSR_FE1) | |
97 | 79aceca5 | bellard | (msr_ip << MSR_IP) | |
98 | 79aceca5 | bellard | (msr_ir << MSR_IR) | |
99 | 79aceca5 | bellard | (msr_dr << MSR_DR) | |
100 | 79aceca5 | bellard | (msr_ri << MSR_RI) | |
101 | 79aceca5 | bellard | (msr_le << MSR_LE); |
102 | 79aceca5 | bellard | } |
103 | 79aceca5 | bellard | |
104 | 79aceca5 | bellard | void do_store_msr (uint32_t msr_value)
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105 | 79aceca5 | bellard | { |
106 | 79aceca5 | bellard | msr_pow = (msr_value >> MSR_POW) & 0x03;
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107 | 79aceca5 | bellard | msr_ile = (msr_value >> MSR_ILE) & 0x01;
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108 | 79aceca5 | bellard | msr_ee = (msr_value >> MSR_EE) & 0x01;
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109 | 79aceca5 | bellard | msr_pr = (msr_value >> MSR_PR) & 0x01;
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110 | 79aceca5 | bellard | msr_fp = (msr_value >> MSR_FP) & 0x01;
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111 | 79aceca5 | bellard | msr_me = (msr_value >> MSR_ME) & 0x01;
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112 | 79aceca5 | bellard | msr_fe0 = (msr_value >> MSR_FE0) & 0x01;
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113 | 79aceca5 | bellard | msr_se = (msr_value >> MSR_SE) & 0x01;
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114 | 79aceca5 | bellard | msr_be = (msr_value >> MSR_BE) & 0x01;
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115 | 79aceca5 | bellard | msr_fe1 = (msr_value >> MSR_FE1) & 0x01;
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116 | 79aceca5 | bellard | msr_ip = (msr_value >> MSR_IP) & 0x01;
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117 | 79aceca5 | bellard | msr_ir = (msr_value >> MSR_IR) & 0x01;
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118 | 79aceca5 | bellard | msr_dr = (msr_value >> MSR_DR) & 0x01;
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119 | 79aceca5 | bellard | msr_ri = (msr_value >> MSR_RI) & 0x01;
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120 | 79aceca5 | bellard | msr_le = (msr_value >> MSR_LE) & 0x01;
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121 | 79aceca5 | bellard | } |
122 | 79aceca5 | bellard | |
123 | 79aceca5 | bellard | /* The 32 MSB of the target fpr are undefined. They'll be zero... */
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124 | fb0eaffc | bellard | /* Floating point operations helpers */
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125 | fb0eaffc | bellard | void do_load_fpscr (void) |
126 | 79aceca5 | bellard | { |
127 | fb0eaffc | bellard | /* The 32 MSB of the target fpr are undefined.
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128 | fb0eaffc | bellard | * They'll be zero...
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129 | fb0eaffc | bellard | */
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130 | fb0eaffc | bellard | union {
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131 | fb0eaffc | bellard | double d;
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132 | fb0eaffc | bellard | struct {
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133 | fb0eaffc | bellard | uint32_t u[2];
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134 | fb0eaffc | bellard | } s; |
135 | fb0eaffc | bellard | } u; |
136 | fb0eaffc | bellard | int i;
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137 | fb0eaffc | bellard | |
138 | fb0eaffc | bellard | u.s.u[0] = 0; |
139 | fb0eaffc | bellard | u.s.u[1] = 0; |
140 | fb0eaffc | bellard | for (i = 0; i < 8; i++) |
141 | fb0eaffc | bellard | u.s.u[1] |= env->fpscr[i] << (4 * i); |
142 | fb0eaffc | bellard | FT0 = u.d; |
143 | 79aceca5 | bellard | } |
144 | 79aceca5 | bellard | |
145 | fb0eaffc | bellard | void do_store_fpscr (uint32_t mask)
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146 | 79aceca5 | bellard | { |
147 | fb0eaffc | bellard | /*
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148 | fb0eaffc | bellard | * We use only the 32 LSB of the incoming fpr
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149 | fb0eaffc | bellard | */
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150 | fb0eaffc | bellard | union {
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151 | fb0eaffc | bellard | double d;
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152 | fb0eaffc | bellard | struct {
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153 | fb0eaffc | bellard | uint32_t u[2];
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154 | fb0eaffc | bellard | } s; |
155 | fb0eaffc | bellard | } u; |
156 | 79aceca5 | bellard | int i;
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157 | 79aceca5 | bellard | |
158 | fb0eaffc | bellard | u.d = FT0; |
159 | fb0eaffc | bellard | if (mask & 0x80) |
160 | fb0eaffc | bellard | env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[1] >> 28) & ~0x9); |
161 | fb0eaffc | bellard | for (i = 1; i < 7; i++) { |
162 | fb0eaffc | bellard | if (mask & (1 << (7 - i))) |
163 | fb0eaffc | bellard | env->fpscr[i] = (u.s.u[1] >> (4 * (7 - i))) & 0xF; |
164 | fb0eaffc | bellard | } |
165 | fb0eaffc | bellard | /* TODO: update FEX & VX */
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166 | fb0eaffc | bellard | /* Set rounding mode */
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167 | fb0eaffc | bellard | switch (env->fpscr[0] & 0x3) { |
168 | fb0eaffc | bellard | case 0: |
169 | fb0eaffc | bellard | /* Best approximation (round to nearest) */
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170 | fb0eaffc | bellard | fesetround(FE_TONEAREST); |
171 | fb0eaffc | bellard | break;
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172 | fb0eaffc | bellard | case 1: |
173 | fb0eaffc | bellard | /* Smaller magnitude (round toward zero) */
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174 | fb0eaffc | bellard | fesetround(FE_TOWARDZERO); |
175 | fb0eaffc | bellard | break;
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176 | fb0eaffc | bellard | case 2: |
177 | fb0eaffc | bellard | /* Round toward +infinite */
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178 | fb0eaffc | bellard | fesetround(FE_UPWARD); |
179 | fb0eaffc | bellard | break;
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180 | fb0eaffc | bellard | case 3: |
181 | fb0eaffc | bellard | /* Round toward -infinite */
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182 | fb0eaffc | bellard | fesetround(FE_DOWNWARD); |
183 | fb0eaffc | bellard | break;
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184 | 79aceca5 | bellard | } |
185 | 79aceca5 | bellard | } |
186 | 79aceca5 | bellard | |
187 | 79aceca5 | bellard | int32_t do_sraw(int32_t value, uint32_t shift) |
188 | 79aceca5 | bellard | { |
189 | 79aceca5 | bellard | int32_t ret; |
190 | 79aceca5 | bellard | |
191 | 79aceca5 | bellard | xer_ca = 0;
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192 | 79aceca5 | bellard | if (shift & 0x20) { |
193 | 79aceca5 | bellard | ret = (-1) * ((uint32_t)value >> 31); |
194 | 79aceca5 | bellard | if (ret < 0) |
195 | 79aceca5 | bellard | xer_ca = 1;
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196 | 79aceca5 | bellard | } else {
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197 | 79aceca5 | bellard | ret = value >> (shift & 0x1f);
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198 | 79aceca5 | bellard | if (ret < 0 && (value & ((1 << shift) - 1)) != 0) |
199 | 79aceca5 | bellard | xer_ca = 1;
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200 | 79aceca5 | bellard | } |
201 | 79aceca5 | bellard | |
202 | 79aceca5 | bellard | return ret;
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203 | 79aceca5 | bellard | } |
204 | 79aceca5 | bellard | |
205 | 79aceca5 | bellard | void do_lmw (int reg, uint32_t src) |
206 | 79aceca5 | bellard | { |
207 | 79aceca5 | bellard | for (; reg <= 31; reg++, src += 4) |
208 | 79aceca5 | bellard | ugpr(reg) = ld32(src); |
209 | 79aceca5 | bellard | } |
210 | 79aceca5 | bellard | |
211 | 79aceca5 | bellard | void do_stmw (int reg, uint32_t dest) |
212 | 79aceca5 | bellard | { |
213 | 79aceca5 | bellard | for (; reg <= 31; reg++, dest += 4) |
214 | 79aceca5 | bellard | st32(dest, ugpr(reg)); |
215 | 79aceca5 | bellard | } |
216 | 79aceca5 | bellard | |
217 | 79aceca5 | bellard | void do_lsw (uint32_t reg, int count, uint32_t src) |
218 | 79aceca5 | bellard | { |
219 | 79aceca5 | bellard | uint32_t tmp; |
220 | 79aceca5 | bellard | int sh;
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221 | 79aceca5 | bellard | |
222 | 79aceca5 | bellard | for (; count > 3; count -= 4, src += 4) { |
223 | 79aceca5 | bellard | ugpr(reg++) = ld32(src); |
224 | fb0eaffc | bellard | if (T2 == 32) |
225 | fb0eaffc | bellard | T2 = 0;
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226 | 79aceca5 | bellard | } |
227 | 79aceca5 | bellard | if (count > 0) { |
228 | 79aceca5 | bellard | tmp = 0;
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229 | fb0eaffc | bellard | for (sh = 24; count > 0; count--, src++, sh -= 8) { |
230 | fb0eaffc | bellard | tmp |= ld8(src) << sh; |
231 | 79aceca5 | bellard | } |
232 | 79aceca5 | bellard | ugpr(reg) = tmp; |
233 | 79aceca5 | bellard | } |
234 | 79aceca5 | bellard | } |
235 | 79aceca5 | bellard | |
236 | 79aceca5 | bellard | void do_stsw (uint32_t reg, int count, uint32_t dest) |
237 | 79aceca5 | bellard | { |
238 | 79aceca5 | bellard | int sh;
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239 | 79aceca5 | bellard | |
240 | 79aceca5 | bellard | for (; count > 3; count -= 4, dest += 4) { |
241 | fb0eaffc | bellard | st32(dest, ugpr(reg++)); |
242 | 79aceca5 | bellard | if (reg == 32) |
243 | 79aceca5 | bellard | reg = 0;
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244 | 79aceca5 | bellard | } |
245 | 79aceca5 | bellard | if (count > 0) { |
246 | 79aceca5 | bellard | for (sh = 24; count > 0; count--, dest++, sh -= 8) { |
247 | 79aceca5 | bellard | st8(dest, (ugpr(reg) >> sh) & 0xFF);
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248 | 79aceca5 | bellard | } |
249 | 79aceca5 | bellard | } |
250 | fb0eaffc | bellard | } |
251 | fb0eaffc | bellard | |
252 | fb0eaffc | bellard | void do_dcbz (void) |
253 | fb0eaffc | bellard | { |
254 | fb0eaffc | bellard | int i;
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255 | fb0eaffc | bellard | |
256 | fb0eaffc | bellard | /* Assume cache line size is 32 */
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257 | fb0eaffc | bellard | for (i = 0; i < 8; i++) { |
258 | fb0eaffc | bellard | st32(T0, 0);
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259 | fb0eaffc | bellard | T0 += 4;
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260 | 79aceca5 | bellard | } |
261 | 79aceca5 | bellard | } |
262 | fb0eaffc | bellard | |
263 | fb0eaffc | bellard | /* Instruction cache invalidation helper */
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264 | fb0eaffc | bellard | void do_icbi (void) |
265 | fb0eaffc | bellard | { |
266 | fb0eaffc | bellard | tb_invalidate_page(T0); |
267 | fb0eaffc | bellard | } |