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/*
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* QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation
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* Based on the linux driver code at drivers/scsi/megaraid
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*
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* Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
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*
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* This library is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h" |
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#include "pci.h" |
| 23 |
#include "dma.h" |
| 24 |
#include "msix.h" |
| 25 |
#include "iov.h" |
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#include "scsi.h" |
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#include "scsi-defs.h" |
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#include "block_int.h" |
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#include "trace.h" |
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|
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#include "mfi.h" |
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|
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#define MEGASAS_VERSION "1.70" |
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#define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */ |
| 35 |
#define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */ |
| 36 |
#define MEGASAS_MAX_SGE 128 /* Firmware limit */ |
| 37 |
#define MEGASAS_DEFAULT_SGE 80 |
| 38 |
#define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */ |
| 39 |
#define MEGASAS_MAX_ARRAYS 128 |
| 40 |
|
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#define MEGASAS_HBA_SERIAL "QEMU123456" |
| 42 |
#define NAA_LOCALLY_ASSIGNED_ID 0x3ULL |
| 43 |
#define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400 |
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|
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#define MEGASAS_FLAG_USE_JBOD 0 |
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#define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD) |
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#define MEGASAS_FLAG_USE_MSIX 1 |
| 48 |
#define MEGASAS_MASK_USE_MSIX (1 << MEGASAS_FLAG_USE_MSIX) |
| 49 |
#define MEGASAS_FLAG_USE_QUEUE64 2 |
| 50 |
#define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64) |
| 51 |
|
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static const char *mfi_frame_desc[] = { |
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"MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI", |
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"MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"}; |
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|
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typedef struct MegasasCmd { |
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uint32_t index; |
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uint16_t flags; |
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uint16_t count; |
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uint64_t context; |
| 61 |
|
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target_phys_addr_t pa; |
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target_phys_addr_t pa_size; |
| 64 |
union mfi_frame *frame;
|
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SCSIRequest *req; |
| 66 |
QEMUSGList qsg; |
| 67 |
void *iov_buf;
|
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size_t iov_size; |
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size_t iov_offset; |
| 70 |
struct MegasasState *state;
|
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} MegasasCmd; |
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|
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typedef struct MegasasState { |
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PCIDevice dev; |
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MemoryRegion mmio_io; |
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MemoryRegion port_io; |
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MemoryRegion queue_io; |
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uint32_t frame_hi; |
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|
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int fw_state;
|
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uint32_t fw_sge; |
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uint32_t fw_cmds; |
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uint32_t flags; |
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int fw_luns;
|
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int intr_mask;
|
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int doorbell;
|
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int busy;
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|
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MegasasCmd *event_cmd; |
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int event_locale;
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int event_class;
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int event_count;
|
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int shutdown_event;
|
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int boot_event;
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|
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uint64_t sas_addr; |
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char *hba_serial;
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|
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uint64_t reply_queue_pa; |
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void *reply_queue;
|
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int reply_queue_len;
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int reply_queue_head;
|
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int reply_queue_tail;
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uint64_t consumer_pa; |
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uint64_t producer_pa; |
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|
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MegasasCmd frames[MEGASAS_MAX_FRAMES]; |
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|
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SCSIBus bus; |
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} MegasasState; |
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|
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#define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF |
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|
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static bool megasas_intr_enabled(MegasasState *s) |
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{
|
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if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
|
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MEGASAS_INTR_DISABLED_MASK) {
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return true; |
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} |
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return false; |
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} |
| 122 |
|
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static bool megasas_use_queue64(MegasasState *s) |
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{
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return s->flags & MEGASAS_MASK_USE_QUEUE64;
|
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} |
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|
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static bool megasas_use_msix(MegasasState *s) |
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{
|
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return s->flags & MEGASAS_MASK_USE_MSIX;
|
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} |
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|
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static bool megasas_is_jbod(MegasasState *s) |
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{
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return s->flags & MEGASAS_MASK_USE_JBOD;
|
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} |
| 137 |
|
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static void megasas_frame_set_cmd_status(unsigned long frame, uint8_t v) |
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{
|
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stb_phys(frame + offsetof(struct mfi_frame_header, cmd_status), v);
|
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} |
| 142 |
|
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static void megasas_frame_set_scsi_status(unsigned long frame, uint8_t v) |
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{
|
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stb_phys(frame + offsetof(struct mfi_frame_header, scsi_status), v);
|
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} |
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|
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/*
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* Context is considered opaque, but the HBA firmware is running
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* in little endian mode. So convert it to little endian, too.
|
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*/
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static uint64_t megasas_frame_get_context(unsigned long frame) |
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{
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return ldq_le_phys(frame + offsetof(struct mfi_frame_header, context)); |
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} |
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|
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static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd) |
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{
|
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return cmd->flags & MFI_FRAME_IEEE_SGL;
|
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} |
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|
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static bool megasas_frame_is_sgl64(MegasasCmd *cmd) |
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{
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return cmd->flags & MFI_FRAME_SGL64;
|
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} |
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|
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static bool megasas_frame_is_sense64(MegasasCmd *cmd) |
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{
|
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return cmd->flags & MFI_FRAME_SENSE64;
|
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} |
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|
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static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
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union mfi_sgl *sgl)
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{
|
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uint64_t addr; |
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|
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if (megasas_frame_is_ieee_sgl(cmd)) {
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addr = le64_to_cpu(sgl->sg_skinny->addr); |
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} else if (megasas_frame_is_sgl64(cmd)) { |
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addr = le64_to_cpu(sgl->sg64->addr); |
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} else {
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addr = le32_to_cpu(sgl->sg32->addr); |
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} |
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return addr;
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} |
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|
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static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
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union mfi_sgl *sgl)
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{
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uint32_t len; |
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|
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if (megasas_frame_is_ieee_sgl(cmd)) {
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len = le32_to_cpu(sgl->sg_skinny->len); |
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} else if (megasas_frame_is_sgl64(cmd)) { |
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len = le32_to_cpu(sgl->sg64->len); |
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} else {
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len = le32_to_cpu(sgl->sg32->len); |
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} |
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return len;
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} |
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|
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static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd, |
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union mfi_sgl *sgl)
|
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{
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uint8_t *next = (uint8_t *)sgl; |
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|
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if (megasas_frame_is_ieee_sgl(cmd)) {
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next += sizeof(struct mfi_sg_skinny); |
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} else if (megasas_frame_is_sgl64(cmd)) { |
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next += sizeof(struct mfi_sg64); |
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} else {
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next += sizeof(struct mfi_sg32); |
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} |
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|
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if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
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return NULL; |
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} |
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return (union mfi_sgl *)next; |
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} |
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|
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static void megasas_soft_reset(MegasasState *s); |
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|
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static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl) |
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{
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int i;
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int iov_count = 0; |
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size_t iov_size = 0;
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|
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cmd->flags = le16_to_cpu(cmd->frame->header.flags); |
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iov_count = cmd->frame->header.sge_count; |
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if (iov_count > MEGASAS_MAX_SGE) {
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trace_megasas_iovec_sgl_overflow(cmd->index, iov_count, |
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MEGASAS_MAX_SGE); |
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return iov_count;
|
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} |
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qemu_sglist_init(&cmd->qsg, iov_count, pci_dma_context(&s->dev)); |
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for (i = 0; i < iov_count; i++) { |
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dma_addr_t iov_pa, iov_size_p; |
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|
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if (!sgl) {
|
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trace_megasas_iovec_sgl_underflow(cmd->index, i); |
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goto unmap;
|
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} |
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iov_pa = megasas_sgl_get_addr(cmd, sgl); |
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iov_size_p = megasas_sgl_get_len(cmd, sgl); |
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if (!iov_pa || !iov_size_p) {
|
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trace_megasas_iovec_sgl_invalid(cmd->index, i, |
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iov_pa, iov_size_p); |
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goto unmap;
|
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} |
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qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p); |
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sgl = megasas_sgl_next(cmd, sgl); |
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iov_size += (size_t)iov_size_p; |
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} |
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if (cmd->iov_size > iov_size) {
|
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trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size); |
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} else if (cmd->iov_size < iov_size) { |
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trace_megasas_iovec_underflow(cmd->iov_size, iov_size, cmd->iov_size); |
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} |
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cmd->iov_offset = 0;
|
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return 0; |
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unmap:
|
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qemu_sglist_destroy(&cmd->qsg); |
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return iov_count - i;
|
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} |
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|
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static void megasas_unmap_sgl(MegasasCmd *cmd) |
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{
|
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qemu_sglist_destroy(&cmd->qsg); |
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cmd->iov_offset = 0;
|
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} |
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|
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/*
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* passthrough sense and io sense are at the same offset
|
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*/
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static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr, |
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uint8_t sense_len) |
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{
|
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uint32_t pa_hi = 0, pa_lo;
|
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target_phys_addr_t pa; |
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|
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if (sense_len > cmd->frame->header.sense_len) {
|
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sense_len = cmd->frame->header.sense_len; |
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} |
| 285 |
if (sense_len) {
|
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pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo); |
| 287 |
if (megasas_frame_is_sense64(cmd)) {
|
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pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi); |
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} |
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pa = ((uint64_t) pa_hi << 32) | pa_lo;
|
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cpu_physical_memory_write(pa, sense_ptr, sense_len); |
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cmd->frame->header.sense_len = sense_len; |
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} |
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return sense_len;
|
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} |
| 296 |
|
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static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense) |
| 298 |
{
|
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uint8_t sense_buf[SCSI_SENSE_BUF_SIZE]; |
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uint8_t sense_len = 18;
|
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|
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memset(sense_buf, 0, sense_len);
|
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sense_buf[0] = 0xf0; |
| 304 |
sense_buf[2] = sense.key;
|
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sense_buf[7] = 10; |
| 306 |
sense_buf[12] = sense.asc;
|
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sense_buf[13] = sense.ascq;
|
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megasas_build_sense(cmd, sense_buf, sense_len); |
| 309 |
} |
| 310 |
|
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static void megasas_copy_sense(MegasasCmd *cmd) |
| 312 |
{
|
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uint8_t sense_buf[SCSI_SENSE_BUF_SIZE]; |
| 314 |
uint8_t sense_len; |
| 315 |
|
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sense_len = scsi_req_get_sense(cmd->req, sense_buf, |
| 317 |
SCSI_SENSE_BUF_SIZE); |
| 318 |
megasas_build_sense(cmd, sense_buf, sense_len); |
| 319 |
} |
| 320 |
|
| 321 |
/*
|
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* Format an INQUIRY CDB
|
| 323 |
*/
|
| 324 |
static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len) |
| 325 |
{
|
| 326 |
memset(cdb, 0, 6); |
| 327 |
cdb[0] = INQUIRY;
|
| 328 |
if (pg > 0) { |
| 329 |
cdb[1] = 0x1; |
| 330 |
cdb[2] = pg;
|
| 331 |
} |
| 332 |
cdb[3] = (len >> 8) & 0xff; |
| 333 |
cdb[4] = (len & 0xff); |
| 334 |
return len;
|
| 335 |
} |
| 336 |
|
| 337 |
/*
|
| 338 |
* Encode lba and len into a READ_16/WRITE_16 CDB
|
| 339 |
*/
|
| 340 |
static void megasas_encode_lba(uint8_t *cdb, uint64_t lba, |
| 341 |
uint32_t len, bool is_write)
|
| 342 |
{
|
| 343 |
memset(cdb, 0x0, 16); |
| 344 |
if (is_write) {
|
| 345 |
cdb[0] = WRITE_16;
|
| 346 |
} else {
|
| 347 |
cdb[0] = READ_16;
|
| 348 |
} |
| 349 |
cdb[2] = (lba >> 56) & 0xff; |
| 350 |
cdb[3] = (lba >> 48) & 0xff; |
| 351 |
cdb[4] = (lba >> 40) & 0xff; |
| 352 |
cdb[5] = (lba >> 32) & 0xff; |
| 353 |
cdb[6] = (lba >> 24) & 0xff; |
| 354 |
cdb[7] = (lba >> 16) & 0xff; |
| 355 |
cdb[8] = (lba >> 8) & 0xff; |
| 356 |
cdb[9] = (lba) & 0xff; |
| 357 |
cdb[10] = (len >> 24) & 0xff; |
| 358 |
cdb[11] = (len >> 16) & 0xff; |
| 359 |
cdb[12] = (len >> 8) & 0xff; |
| 360 |
cdb[13] = (len) & 0xff; |
| 361 |
} |
| 362 |
|
| 363 |
/*
|
| 364 |
* Utility functions
|
| 365 |
*/
|
| 366 |
static uint64_t megasas_fw_time(void) |
| 367 |
{
|
| 368 |
struct tm curtime;
|
| 369 |
uint64_t bcd_time; |
| 370 |
|
| 371 |
qemu_get_timedate(&curtime, 0);
|
| 372 |
bcd_time = ((uint64_t)curtime.tm_sec & 0xff) << 48 | |
| 373 |
((uint64_t)curtime.tm_min & 0xff) << 40 | |
| 374 |
((uint64_t)curtime.tm_hour & 0xff) << 32 | |
| 375 |
((uint64_t)curtime.tm_mday & 0xff) << 24 | |
| 376 |
((uint64_t)curtime.tm_mon & 0xff) << 16 | |
| 377 |
((uint64_t)(curtime.tm_year + 1900) & 0xffff); |
| 378 |
|
| 379 |
return bcd_time;
|
| 380 |
} |
| 381 |
|
| 382 |
/*
|
| 383 |
* Default disk sata address
|
| 384 |
* 0x1221 is the magic number as
|
| 385 |
* present in real hardware,
|
| 386 |
* so use it here, too.
|
| 387 |
*/
|
| 388 |
static uint64_t megasas_get_sata_addr(uint16_t id)
|
| 389 |
{
|
| 390 |
uint64_t addr = (0x1221ULL << 48); |
| 391 |
return addr & (id << 24); |
| 392 |
} |
| 393 |
|
| 394 |
/*
|
| 395 |
* Frame handling
|
| 396 |
*/
|
| 397 |
static int megasas_next_index(MegasasState *s, int index, int limit) |
| 398 |
{
|
| 399 |
index++; |
| 400 |
if (index == limit) {
|
| 401 |
index = 0;
|
| 402 |
} |
| 403 |
return index;
|
| 404 |
} |
| 405 |
|
| 406 |
static MegasasCmd *megasas_lookup_frame(MegasasState *s,
|
| 407 |
target_phys_addr_t frame) |
| 408 |
{
|
| 409 |
MegasasCmd *cmd = NULL;
|
| 410 |
int num = 0, index; |
| 411 |
|
| 412 |
index = s->reply_queue_head; |
| 413 |
|
| 414 |
while (num < s->fw_cmds) {
|
| 415 |
if (s->frames[index].pa && s->frames[index].pa == frame) {
|
| 416 |
cmd = &s->frames[index]; |
| 417 |
break;
|
| 418 |
} |
| 419 |
index = megasas_next_index(s, index, s->fw_cmds); |
| 420 |
num++; |
| 421 |
} |
| 422 |
|
| 423 |
return cmd;
|
| 424 |
} |
| 425 |
|
| 426 |
static MegasasCmd *megasas_next_frame(MegasasState *s,
|
| 427 |
target_phys_addr_t frame) |
| 428 |
{
|
| 429 |
MegasasCmd *cmd = NULL;
|
| 430 |
int num = 0, index; |
| 431 |
|
| 432 |
cmd = megasas_lookup_frame(s, frame); |
| 433 |
if (cmd) {
|
| 434 |
trace_megasas_qf_found(cmd->index, cmd->pa); |
| 435 |
return cmd;
|
| 436 |
} |
| 437 |
index = s->reply_queue_head; |
| 438 |
num = 0;
|
| 439 |
while (num < s->fw_cmds) {
|
| 440 |
if (!s->frames[index].pa) {
|
| 441 |
cmd = &s->frames[index]; |
| 442 |
break;
|
| 443 |
} |
| 444 |
index = megasas_next_index(s, index, s->fw_cmds); |
| 445 |
num++; |
| 446 |
} |
| 447 |
if (!cmd) {
|
| 448 |
trace_megasas_qf_failed(frame); |
| 449 |
} |
| 450 |
trace_megasas_qf_new(index, cmd); |
| 451 |
return cmd;
|
| 452 |
} |
| 453 |
|
| 454 |
static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
|
| 455 |
target_phys_addr_t frame, uint64_t context, int count)
|
| 456 |
{
|
| 457 |
MegasasCmd *cmd = NULL;
|
| 458 |
int frame_size = MFI_FRAME_SIZE * 16; |
| 459 |
target_phys_addr_t frame_size_p = frame_size; |
| 460 |
|
| 461 |
cmd = megasas_next_frame(s, frame); |
| 462 |
/* All frames busy */
|
| 463 |
if (!cmd) {
|
| 464 |
return NULL; |
| 465 |
} |
| 466 |
if (!cmd->pa) {
|
| 467 |
cmd->pa = frame; |
| 468 |
/* Map all possible frames */
|
| 469 |
cmd->frame = cpu_physical_memory_map(frame, &frame_size_p, 0);
|
| 470 |
if (frame_size_p != frame_size) {
|
| 471 |
trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame); |
| 472 |
if (cmd->frame) {
|
| 473 |
cpu_physical_memory_unmap(cmd->frame, frame_size_p, 0, 0); |
| 474 |
cmd->frame = NULL;
|
| 475 |
cmd->pa = 0;
|
| 476 |
} |
| 477 |
s->event_count++; |
| 478 |
return NULL; |
| 479 |
} |
| 480 |
cmd->pa_size = frame_size_p; |
| 481 |
cmd->context = context; |
| 482 |
if (!megasas_use_queue64(s)) {
|
| 483 |
cmd->context &= (uint64_t)0xFFFFFFFF;
|
| 484 |
} |
| 485 |
} |
| 486 |
cmd->count = count; |
| 487 |
s->busy++; |
| 488 |
|
| 489 |
trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context, |
| 490 |
s->reply_queue_head, s->busy); |
| 491 |
|
| 492 |
return cmd;
|
| 493 |
} |
| 494 |
|
| 495 |
static void megasas_complete_frame(MegasasState *s, uint64_t context) |
| 496 |
{
|
| 497 |
int tail, queue_offset;
|
| 498 |
|
| 499 |
/* Decrement busy count */
|
| 500 |
s->busy--; |
| 501 |
|
| 502 |
if (s->reply_queue_pa) {
|
| 503 |
/*
|
| 504 |
* Put command on the reply queue.
|
| 505 |
* Context is opaque, but emulation is running in
|
| 506 |
* little endian. So convert it.
|
| 507 |
*/
|
| 508 |
tail = s->reply_queue_head; |
| 509 |
if (megasas_use_queue64(s)) {
|
| 510 |
queue_offset = tail * sizeof(uint64_t);
|
| 511 |
stq_le_phys(s->reply_queue_pa + queue_offset, context); |
| 512 |
} else {
|
| 513 |
queue_offset = tail * sizeof(uint32_t);
|
| 514 |
stl_le_phys(s->reply_queue_pa + queue_offset, context); |
| 515 |
} |
| 516 |
s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds); |
| 517 |
trace_megasas_qf_complete(context, tail, queue_offset, |
| 518 |
s->busy, s->doorbell); |
| 519 |
} |
| 520 |
|
| 521 |
if (megasas_intr_enabled(s)) {
|
| 522 |
/* Notify HBA */
|
| 523 |
s->doorbell++; |
| 524 |
if (s->doorbell == 1) { |
| 525 |
if (msix_enabled(&s->dev)) {
|
| 526 |
trace_megasas_msix_raise(0);
|
| 527 |
msix_notify(&s->dev, 0);
|
| 528 |
} else {
|
| 529 |
trace_megasas_irq_raise(); |
| 530 |
qemu_irq_raise(s->dev.irq[0]);
|
| 531 |
} |
| 532 |
} |
| 533 |
} else {
|
| 534 |
trace_megasas_qf_complete_noirq(context); |
| 535 |
} |
| 536 |
} |
| 537 |
|
| 538 |
static void megasas_reset_frames(MegasasState *s) |
| 539 |
{
|
| 540 |
int i;
|
| 541 |
MegasasCmd *cmd; |
| 542 |
|
| 543 |
for (i = 0; i < s->fw_cmds; i++) { |
| 544 |
cmd = &s->frames[i]; |
| 545 |
if (cmd->pa) {
|
| 546 |
cpu_physical_memory_unmap(cmd->frame, cmd->pa_size, 0, 0); |
| 547 |
cmd->frame = NULL;
|
| 548 |
cmd->pa = 0;
|
| 549 |
} |
| 550 |
} |
| 551 |
} |
| 552 |
|
| 553 |
static void megasas_abort_command(MegasasCmd *cmd) |
| 554 |
{
|
| 555 |
if (cmd->req) {
|
| 556 |
scsi_req_cancel(cmd->req); |
| 557 |
cmd->req = NULL;
|
| 558 |
} |
| 559 |
} |
| 560 |
|
| 561 |
static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd) |
| 562 |
{
|
| 563 |
uint32_t pa_hi, pa_lo; |
| 564 |
target_phys_addr_t iq_pa, initq_size; |
| 565 |
struct mfi_init_qinfo *initq;
|
| 566 |
uint32_t flags; |
| 567 |
int ret = MFI_STAT_OK;
|
| 568 |
|
| 569 |
pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo); |
| 570 |
pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi); |
| 571 |
iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
|
| 572 |
trace_megasas_init_firmware((uint64_t)iq_pa); |
| 573 |
initq_size = sizeof(*initq);
|
| 574 |
initq = cpu_physical_memory_map(iq_pa, &initq_size, 0);
|
| 575 |
if (!initq || initq_size != sizeof(*initq)) { |
| 576 |
trace_megasas_initq_map_failed(cmd->index); |
| 577 |
s->event_count++; |
| 578 |
ret = MFI_STAT_MEMORY_NOT_AVAILABLE; |
| 579 |
goto out;
|
| 580 |
} |
| 581 |
s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
|
| 582 |
if (s->reply_queue_len > s->fw_cmds) {
|
| 583 |
trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds); |
| 584 |
s->event_count++; |
| 585 |
ret = MFI_STAT_INVALID_PARAMETER; |
| 586 |
goto out;
|
| 587 |
} |
| 588 |
pa_lo = le32_to_cpu(initq->rq_addr_lo); |
| 589 |
pa_hi = le32_to_cpu(initq->rq_addr_hi); |
| 590 |
s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
|
| 591 |
pa_lo = le32_to_cpu(initq->ci_addr_lo); |
| 592 |
pa_hi = le32_to_cpu(initq->ci_addr_hi); |
| 593 |
s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
|
| 594 |
pa_lo = le32_to_cpu(initq->pi_addr_lo); |
| 595 |
pa_hi = le32_to_cpu(initq->pi_addr_hi); |
| 596 |
s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
|
| 597 |
s->reply_queue_head = ldl_le_phys(s->producer_pa); |
| 598 |
s->reply_queue_tail = ldl_le_phys(s->consumer_pa); |
| 599 |
flags = le32_to_cpu(initq->flags); |
| 600 |
if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
|
| 601 |
s->flags |= MEGASAS_MASK_USE_QUEUE64; |
| 602 |
} |
| 603 |
trace_megasas_init_queue((unsigned long)s->reply_queue_pa, |
| 604 |
s->reply_queue_len, s->reply_queue_head, |
| 605 |
s->reply_queue_tail, flags); |
| 606 |
megasas_reset_frames(s); |
| 607 |
s->fw_state = MFI_FWSTATE_OPERATIONAL; |
| 608 |
out:
|
| 609 |
if (initq) {
|
| 610 |
cpu_physical_memory_unmap(initq, initq_size, 0, 0); |
| 611 |
} |
| 612 |
return ret;
|
| 613 |
} |
| 614 |
|
| 615 |
static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd) |
| 616 |
{
|
| 617 |
dma_addr_t iov_pa, iov_size; |
| 618 |
|
| 619 |
cmd->flags = le16_to_cpu(cmd->frame->header.flags); |
| 620 |
if (!cmd->frame->header.sge_count) {
|
| 621 |
trace_megasas_dcmd_zero_sge(cmd->index); |
| 622 |
cmd->iov_size = 0;
|
| 623 |
return 0; |
| 624 |
} else if (cmd->frame->header.sge_count > 1) { |
| 625 |
trace_megasas_dcmd_invalid_sge(cmd->index, |
| 626 |
cmd->frame->header.sge_count); |
| 627 |
cmd->iov_size = 0;
|
| 628 |
return -1; |
| 629 |
} |
| 630 |
iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl); |
| 631 |
iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl); |
| 632 |
qemu_sglist_init(&cmd->qsg, 1, pci_dma_context(&s->dev));
|
| 633 |
qemu_sglist_add(&cmd->qsg, iov_pa, iov_size); |
| 634 |
cmd->iov_size = iov_size; |
| 635 |
return cmd->iov_size;
|
| 636 |
} |
| 637 |
|
| 638 |
static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size) |
| 639 |
{
|
| 640 |
trace_megasas_finish_dcmd(cmd->index, iov_size); |
| 641 |
|
| 642 |
if (cmd->frame->header.sge_count) {
|
| 643 |
qemu_sglist_destroy(&cmd->qsg); |
| 644 |
} |
| 645 |
if (iov_size > cmd->iov_size) {
|
| 646 |
if (megasas_frame_is_ieee_sgl(cmd)) {
|
| 647 |
cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size); |
| 648 |
} else if (megasas_frame_is_sgl64(cmd)) { |
| 649 |
cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size); |
| 650 |
} else {
|
| 651 |
cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size); |
| 652 |
} |
| 653 |
} |
| 654 |
cmd->iov_size = 0;
|
| 655 |
return;
|
| 656 |
} |
| 657 |
|
| 658 |
static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd) |
| 659 |
{
|
| 660 |
struct mfi_ctrl_info info;
|
| 661 |
size_t dcmd_size = sizeof(info);
|
| 662 |
BusChild *kid; |
| 663 |
int num_ld_disks = 0; |
| 664 |
uint16_t sdev_id; |
| 665 |
|
| 666 |
memset(&info, 0x0, cmd->iov_size);
|
| 667 |
if (cmd->iov_size < dcmd_size) {
|
| 668 |
trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, |
| 669 |
dcmd_size); |
| 670 |
return MFI_STAT_INVALID_PARAMETER;
|
| 671 |
} |
| 672 |
|
| 673 |
info.pci.vendor = cpu_to_le16(PCI_VENDOR_ID_LSI_LOGIC); |
| 674 |
info.pci.device = cpu_to_le16(PCI_DEVICE_ID_LSI_SAS1078); |
| 675 |
info.pci.subvendor = cpu_to_le16(PCI_VENDOR_ID_LSI_LOGIC); |
| 676 |
info.pci.subdevice = cpu_to_le16(0x1013);
|
| 677 |
|
| 678 |
/*
|
| 679 |
* For some reason the firmware supports
|
| 680 |
* only up to 8 device ports.
|
| 681 |
* Despite supporting a far larger number
|
| 682 |
* of devices for the physical devices.
|
| 683 |
* So just display the first 8 devices
|
| 684 |
* in the device port list, independent
|
| 685 |
* of how many logical devices are actually
|
| 686 |
* present.
|
| 687 |
*/
|
| 688 |
info.host.type = MFI_INFO_HOST_PCIE; |
| 689 |
info.device.type = MFI_INFO_DEV_SAS3G; |
| 690 |
info.device.port_count = 8;
|
| 691 |
QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
|
| 692 |
SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child); |
| 693 |
|
| 694 |
if (num_ld_disks < 8) { |
| 695 |
sdev_id = ((sdev->id & 0xFF) >> 8) | (sdev->lun & 0xFF); |
| 696 |
info.device.port_addr[num_ld_disks] = |
| 697 |
cpu_to_le64(megasas_get_sata_addr(sdev_id)); |
| 698 |
} |
| 699 |
num_ld_disks++; |
| 700 |
} |
| 701 |
|
| 702 |
memcpy(info.product_name, "MegaRAID SAS 8708EM2", 20); |
| 703 |
snprintf(info.serial_number, 32, "%s", s->hba_serial); |
| 704 |
snprintf(info.package_version, 0x60, "%s-QEMU", QEMU_VERSION); |
| 705 |
memcpy(info.image_component[0].name, "APP", 3); |
| 706 |
memcpy(info.image_component[0].version, MEGASAS_VERSION "-QEMU", 9); |
| 707 |
memcpy(info.image_component[0].build_date, __DATE__, 11); |
| 708 |
memcpy(info.image_component[0].build_time, __TIME__, 8); |
| 709 |
info.image_component_count = 1;
|
| 710 |
if (s->dev.has_rom) {
|
| 711 |
uint8_t biosver[32];
|
| 712 |
uint8_t *ptr; |
| 713 |
|
| 714 |
ptr = memory_region_get_ram_ptr(&s->dev.rom); |
| 715 |
memcpy(biosver, ptr + 0x41, 31); |
| 716 |
qemu_put_ram_ptr(ptr); |
| 717 |
memcpy(info.image_component[1].name, "BIOS", 4); |
| 718 |
memcpy(info.image_component[1].version, biosver,
|
| 719 |
strlen((const char *)biosver)); |
| 720 |
info.image_component_count++; |
| 721 |
} |
| 722 |
info.current_fw_time = cpu_to_le32(megasas_fw_time()); |
| 723 |
info.max_arms = 32;
|
| 724 |
info.max_spans = 8;
|
| 725 |
info.max_arrays = MEGASAS_MAX_ARRAYS; |
| 726 |
info.max_lds = s->fw_luns; |
| 727 |
info.max_cmds = cpu_to_le16(s->fw_cmds); |
| 728 |
info.max_sg_elements = cpu_to_le16(s->fw_sge); |
| 729 |
info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS); |
| 730 |
info.lds_present = cpu_to_le16(num_ld_disks); |
| 731 |
info.pd_present = cpu_to_le16(num_ld_disks); |
| 732 |
info.pd_disks_present = cpu_to_le16(num_ld_disks); |
| 733 |
info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM | |
| 734 |
MFI_INFO_HW_MEM | |
| 735 |
MFI_INFO_HW_FLASH); |
| 736 |
info.memory_size = cpu_to_le16(512);
|
| 737 |
info.nvram_size = cpu_to_le16(32);
|
| 738 |
info.flash_size = cpu_to_le16(16);
|
| 739 |
info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0); |
| 740 |
info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE | |
| 741 |
MFI_INFO_AOPS_SELF_DIAGNOSTIC | |
| 742 |
MFI_INFO_AOPS_MIXED_ARRAY); |
| 743 |
info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY | |
| 744 |
MFI_INFO_LDOPS_ACCESS_POLICY | |
| 745 |
MFI_INFO_LDOPS_IO_POLICY | |
| 746 |
MFI_INFO_LDOPS_WRITE_POLICY | |
| 747 |
MFI_INFO_LDOPS_READ_POLICY); |
| 748 |
info.max_strips_per_io = cpu_to_le16(s->fw_sge); |
| 749 |
info.stripe_sz_ops.min = 3;
|
| 750 |
info.stripe_sz_ops.max = ffs(MEGASAS_MAX_SECTORS + 1) - 1; |
| 751 |
info.properties.pred_fail_poll_interval = cpu_to_le16(300);
|
| 752 |
info.properties.intr_throttle_cnt = cpu_to_le16(16);
|
| 753 |
info.properties.intr_throttle_timeout = cpu_to_le16(50);
|
| 754 |
info.properties.rebuild_rate = 30;
|
| 755 |
info.properties.patrol_read_rate = 30;
|
| 756 |
info.properties.bgi_rate = 30;
|
| 757 |
info.properties.cc_rate = 30;
|
| 758 |
info.properties.recon_rate = 30;
|
| 759 |
info.properties.cache_flush_interval = 4;
|
| 760 |
info.properties.spinup_drv_cnt = 2;
|
| 761 |
info.properties.spinup_delay = 6;
|
| 762 |
info.properties.ecc_bucket_size = 15;
|
| 763 |
info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
|
| 764 |
info.properties.expose_encl_devices = 1;
|
| 765 |
info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD); |
| 766 |
info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE | |
| 767 |
MFI_INFO_PDOPS_FORCE_OFFLINE); |
| 768 |
info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS | |
| 769 |
MFI_INFO_PDMIX_SATA | |
| 770 |
MFI_INFO_PDMIX_LD); |
| 771 |
|
| 772 |
cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg); |
| 773 |
return MFI_STAT_OK;
|
| 774 |
} |
| 775 |
|
| 776 |
static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd) |
| 777 |
{
|
| 778 |
struct mfi_defaults info;
|
| 779 |
size_t dcmd_size = sizeof(struct mfi_defaults); |
| 780 |
|
| 781 |
memset(&info, 0x0, dcmd_size);
|
| 782 |
if (cmd->iov_size < dcmd_size) {
|
| 783 |
trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, |
| 784 |
dcmd_size); |
| 785 |
return MFI_STAT_INVALID_PARAMETER;
|
| 786 |
} |
| 787 |
|
| 788 |
info.sas_addr = cpu_to_le64(s->sas_addr); |
| 789 |
info.stripe_size = 3;
|
| 790 |
info.flush_time = 4;
|
| 791 |
info.background_rate = 30;
|
| 792 |
info.allow_mix_in_enclosure = 1;
|
| 793 |
info.allow_mix_in_ld = 1;
|
| 794 |
info.direct_pd_mapping = 1;
|
| 795 |
/* Enable for BIOS support */
|
| 796 |
info.bios_enumerate_lds = 1;
|
| 797 |
info.disable_ctrl_r = 1;
|
| 798 |
info.expose_enclosure_devices = 1;
|
| 799 |
info.disable_preboot_cli = 1;
|
| 800 |
info.cluster_disable = 1;
|
| 801 |
|
| 802 |
cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg); |
| 803 |
return MFI_STAT_OK;
|
| 804 |
} |
| 805 |
|
| 806 |
static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd) |
| 807 |
{
|
| 808 |
struct mfi_bios_data info;
|
| 809 |
size_t dcmd_size = sizeof(info);
|
| 810 |
|
| 811 |
memset(&info, 0x0, dcmd_size);
|
| 812 |
if (cmd->iov_size < dcmd_size) {
|
| 813 |
trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, |
| 814 |
dcmd_size); |
| 815 |
return MFI_STAT_INVALID_PARAMETER;
|
| 816 |
} |
| 817 |
info.continue_on_error = 1;
|
| 818 |
info.verbose = 1;
|
| 819 |
if (megasas_is_jbod(s)) {
|
| 820 |
info.expose_all_drives = 1;
|
| 821 |
} |
| 822 |
|
| 823 |
cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg); |
| 824 |
return MFI_STAT_OK;
|
| 825 |
} |
| 826 |
|
| 827 |
static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd) |
| 828 |
{
|
| 829 |
uint64_t fw_time; |
| 830 |
size_t dcmd_size = sizeof(fw_time);
|
| 831 |
|
| 832 |
fw_time = cpu_to_le64(megasas_fw_time()); |
| 833 |
|
| 834 |
cmd->iov_size -= dma_buf_read((uint8_t *)&fw_time, dcmd_size, &cmd->qsg); |
| 835 |
return MFI_STAT_OK;
|
| 836 |
} |
| 837 |
|
| 838 |
static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd) |
| 839 |
{
|
| 840 |
uint64_t fw_time; |
| 841 |
|
| 842 |
/* This is a dummy; setting of firmware time is not allowed */
|
| 843 |
memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
|
| 844 |
|
| 845 |
trace_megasas_dcmd_set_fw_time(cmd->index, fw_time); |
| 846 |
fw_time = cpu_to_le64(megasas_fw_time()); |
| 847 |
return MFI_STAT_OK;
|
| 848 |
} |
| 849 |
|
| 850 |
static int megasas_event_info(MegasasState *s, MegasasCmd *cmd) |
| 851 |
{
|
| 852 |
struct mfi_evt_log_state info;
|
| 853 |
size_t dcmd_size = sizeof(info);
|
| 854 |
|
| 855 |
memset(&info, 0, dcmd_size);
|
| 856 |
|
| 857 |
info.newest_seq_num = cpu_to_le32(s->event_count); |
| 858 |
info.shutdown_seq_num = cpu_to_le32(s->shutdown_event); |
| 859 |
info.boot_seq_num = cpu_to_le32(s->boot_event); |
| 860 |
|
| 861 |
cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg); |
| 862 |
return MFI_STAT_OK;
|
| 863 |
} |
| 864 |
|
| 865 |
static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd) |
| 866 |
{
|
| 867 |
union mfi_evt event;
|
| 868 |
|
| 869 |
if (cmd->iov_size < sizeof(struct mfi_evt_detail)) { |
| 870 |
trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, |
| 871 |
sizeof(struct mfi_evt_detail)); |
| 872 |
return MFI_STAT_INVALID_PARAMETER;
|
| 873 |
} |
| 874 |
s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
|
| 875 |
event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
|
| 876 |
s->event_locale = event.members.locale; |
| 877 |
s->event_class = event.members.class; |
| 878 |
s->event_cmd = cmd; |
| 879 |
/* Decrease busy count; event frame doesn't count here */
|
| 880 |
s->busy--; |
| 881 |
cmd->iov_size = sizeof(struct mfi_evt_detail); |
| 882 |
return MFI_STAT_INVALID_STATUS;
|
| 883 |
} |
| 884 |
|
| 885 |
static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd) |
| 886 |
{
|
| 887 |
struct mfi_pd_list info;
|
| 888 |
size_t dcmd_size = sizeof(info);
|
| 889 |
BusChild *kid; |
| 890 |
uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
|
| 891 |
uint16_t sdev_id; |
| 892 |
|
| 893 |
memset(&info, 0, dcmd_size);
|
| 894 |
offset = 8;
|
| 895 |
dcmd_limit = offset + sizeof(struct mfi_pd_address); |
| 896 |
if (cmd->iov_size < dcmd_limit) {
|
| 897 |
trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, |
| 898 |
dcmd_limit); |
| 899 |
return MFI_STAT_INVALID_PARAMETER;
|
| 900 |
} |
| 901 |
|
| 902 |
max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address); |
| 903 |
if (max_pd_disks > s->fw_luns) {
|
| 904 |
max_pd_disks = s->fw_luns; |
| 905 |
} |
| 906 |
|
| 907 |
QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
|
| 908 |
SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child); |
| 909 |
|
| 910 |
sdev_id = ((sdev->id & 0xFF) >> 8) | (sdev->lun & 0xFF); |
| 911 |
info.addr[num_pd_disks].device_id = cpu_to_le16(sdev_id); |
| 912 |
info.addr[num_pd_disks].encl_device_id = 0xFFFF;
|
| 913 |
info.addr[num_pd_disks].encl_index = 0;
|
| 914 |
info.addr[num_pd_disks].slot_number = (sdev->id & 0xFF);
|
| 915 |
info.addr[num_pd_disks].scsi_dev_type = sdev->type; |
| 916 |
info.addr[num_pd_disks].connect_port_bitmap = 0x1;
|
| 917 |
info.addr[num_pd_disks].sas_addr[0] =
|
| 918 |
cpu_to_le64(megasas_get_sata_addr(sdev_id)); |
| 919 |
num_pd_disks++; |
| 920 |
offset += sizeof(struct mfi_pd_address); |
| 921 |
} |
| 922 |
trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks, |
| 923 |
max_pd_disks, offset); |
| 924 |
|
| 925 |
info.size = cpu_to_le32(offset); |
| 926 |
info.count = cpu_to_le32(num_pd_disks); |
| 927 |
|
| 928 |
cmd->iov_size -= dma_buf_read((uint8_t *)&info, offset, &cmd->qsg); |
| 929 |
return MFI_STAT_OK;
|
| 930 |
} |
| 931 |
|
| 932 |
static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd) |
| 933 |
{
|
| 934 |
uint16_t flags; |
| 935 |
|
| 936 |
/* mbox0 contains flags */
|
| 937 |
flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
|
| 938 |
trace_megasas_dcmd_pd_list_query(cmd->index, flags); |
| 939 |
if (flags == MR_PD_QUERY_TYPE_ALL ||
|
| 940 |
megasas_is_jbod(s)) {
|
| 941 |
return megasas_dcmd_pd_get_list(s, cmd);
|
| 942 |
} |
| 943 |
|
| 944 |
return MFI_STAT_OK;
|
| 945 |
} |
| 946 |
|
| 947 |
static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun, |
| 948 |
MegasasCmd *cmd) |
| 949 |
{
|
| 950 |
struct mfi_pd_info *info = cmd->iov_buf;
|
| 951 |
size_t dcmd_size = sizeof(struct mfi_pd_info); |
| 952 |
BlockConf *conf = &sdev->conf; |
| 953 |
uint64_t pd_size; |
| 954 |
uint16_t sdev_id = ((sdev->id & 0xFF) >> 8) | (lun & 0xFF); |
| 955 |
uint8_t cmdbuf[6];
|
| 956 |
SCSIRequest *req; |
| 957 |
size_t len, resid; |
| 958 |
|
| 959 |
if (!cmd->iov_buf) {
|
| 960 |
cmd->iov_buf = g_malloc(dcmd_size); |
| 961 |
memset(cmd->iov_buf, 0, dcmd_size);
|
| 962 |
info = cmd->iov_buf; |
| 963 |
info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */ |
| 964 |
info->vpd_page83[0] = 0x7f; |
| 965 |
megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data)); |
| 966 |
req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd); |
| 967 |
if (!req) {
|
| 968 |
trace_megasas_dcmd_req_alloc_failed(cmd->index, |
| 969 |
"PD get info std inquiry");
|
| 970 |
g_free(cmd->iov_buf); |
| 971 |
cmd->iov_buf = NULL;
|
| 972 |
return MFI_STAT_FLASH_ALLOC_FAIL;
|
| 973 |
} |
| 974 |
trace_megasas_dcmd_internal_submit(cmd->index, |
| 975 |
"PD get info std inquiry", lun);
|
| 976 |
len = scsi_req_enqueue(req); |
| 977 |
if (len > 0) { |
| 978 |
cmd->iov_size = len; |
| 979 |
scsi_req_continue(req); |
| 980 |
} |
| 981 |
return MFI_STAT_INVALID_STATUS;
|
| 982 |
} else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) { |
| 983 |
megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83)); |
| 984 |
req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd); |
| 985 |
if (!req) {
|
| 986 |
trace_megasas_dcmd_req_alloc_failed(cmd->index, |
| 987 |
"PD get info vpd inquiry");
|
| 988 |
return MFI_STAT_FLASH_ALLOC_FAIL;
|
| 989 |
} |
| 990 |
trace_megasas_dcmd_internal_submit(cmd->index, |
| 991 |
"PD get info vpd inquiry", lun);
|
| 992 |
len = scsi_req_enqueue(req); |
| 993 |
if (len > 0) { |
| 994 |
cmd->iov_size = len; |
| 995 |
scsi_req_continue(req); |
| 996 |
} |
| 997 |
return MFI_STAT_INVALID_STATUS;
|
| 998 |
} |
| 999 |
/* Finished, set FW state */
|
| 1000 |
if ((info->inquiry_data[0] >> 5) == 0) { |
| 1001 |
if (megasas_is_jbod(cmd->state)) {
|
| 1002 |
info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM); |
| 1003 |
} else {
|
| 1004 |
info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE); |
| 1005 |
} |
| 1006 |
} else {
|
| 1007 |
info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE); |
| 1008 |
} |
| 1009 |
|
| 1010 |
info->ref.v.device_id = cpu_to_le16(sdev_id); |
| 1011 |
info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD| |
| 1012 |
MFI_PD_DDF_TYPE_INTF_SAS); |
| 1013 |
bdrv_get_geometry(conf->bs, &pd_size); |
| 1014 |
info->raw_size = cpu_to_le64(pd_size); |
| 1015 |
info->non_coerced_size = cpu_to_le64(pd_size); |
| 1016 |
info->coerced_size = cpu_to_le64(pd_size); |
| 1017 |
info->encl_device_id = 0xFFFF;
|
| 1018 |
info->slot_number = (sdev->id & 0xFF);
|
| 1019 |
info->path_info.count = 1;
|
| 1020 |
info->path_info.sas_addr[0] =
|
| 1021 |
cpu_to_le64(megasas_get_sata_addr(sdev_id)); |
| 1022 |
info->connected_port_bitmap = 0x1;
|
| 1023 |
info->device_speed = 1;
|
| 1024 |
info->link_speed = 1;
|
| 1025 |
resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg); |
| 1026 |
g_free(cmd->iov_buf); |
| 1027 |
cmd->iov_size = dcmd_size - resid; |
| 1028 |
cmd->iov_buf = NULL;
|
| 1029 |
return MFI_STAT_OK;
|
| 1030 |
} |
| 1031 |
|
| 1032 |
static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd) |
| 1033 |
{
|
| 1034 |
size_t dcmd_size = sizeof(struct mfi_pd_info); |
| 1035 |
uint16_t pd_id; |
| 1036 |
SCSIDevice *sdev = NULL;
|
| 1037 |
int retval = MFI_STAT_DEVICE_NOT_FOUND;
|
| 1038 |
|
| 1039 |
if (cmd->iov_size < dcmd_size) {
|
| 1040 |
return MFI_STAT_INVALID_PARAMETER;
|
| 1041 |
} |
| 1042 |
|
| 1043 |
/* mbox0 has the ID */
|
| 1044 |
pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
|
| 1045 |
sdev = scsi_device_find(&s->bus, 0, pd_id, 0); |
| 1046 |
trace_megasas_dcmd_pd_get_info(cmd->index, pd_id); |
| 1047 |
|
| 1048 |
if (sdev) {
|
| 1049 |
/* Submit inquiry */
|
| 1050 |
retval = megasas_pd_get_info_submit(sdev, pd_id, cmd); |
| 1051 |
} |
| 1052 |
|
| 1053 |
return retval;
|
| 1054 |
} |
| 1055 |
|
| 1056 |
static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd) |
| 1057 |
{
|
| 1058 |
struct mfi_ld_list info;
|
| 1059 |
size_t dcmd_size = sizeof(info), resid;
|
| 1060 |
uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
|
| 1061 |
uint64_t ld_size; |
| 1062 |
BusChild *kid; |
| 1063 |
|
| 1064 |
memset(&info, 0, dcmd_size);
|
| 1065 |
if (cmd->iov_size < dcmd_size) {
|
| 1066 |
trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, |
| 1067 |
dcmd_size); |
| 1068 |
return MFI_STAT_INVALID_PARAMETER;
|
| 1069 |
} |
| 1070 |
|
| 1071 |
if (megasas_is_jbod(s)) {
|
| 1072 |
max_ld_disks = 0;
|
| 1073 |
} |
| 1074 |
QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
|
| 1075 |
SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child); |
| 1076 |
BlockConf *conf = &sdev->conf; |
| 1077 |
|
| 1078 |
if (num_ld_disks >= max_ld_disks) {
|
| 1079 |
break;
|
| 1080 |
} |
| 1081 |
/* Logical device size is in blocks */
|
| 1082 |
bdrv_get_geometry(conf->bs, &ld_size); |
| 1083 |
info.ld_list[num_ld_disks].ld.v.target_id = sdev->id; |
| 1084 |
info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL; |
| 1085 |
info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size); |
| 1086 |
num_ld_disks++; |
| 1087 |
} |
| 1088 |
info.ld_count = cpu_to_le32(num_ld_disks); |
| 1089 |
trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks); |
| 1090 |
|
| 1091 |
resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg); |
| 1092 |
cmd->iov_size = dcmd_size - resid; |
| 1093 |
return MFI_STAT_OK;
|
| 1094 |
} |
| 1095 |
|
| 1096 |
static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun, |
| 1097 |
MegasasCmd *cmd) |
| 1098 |
{
|
| 1099 |
struct mfi_ld_info *info = cmd->iov_buf;
|
| 1100 |
size_t dcmd_size = sizeof(struct mfi_ld_info); |
| 1101 |
uint8_t cdb[6];
|
| 1102 |
SCSIRequest *req; |
| 1103 |
ssize_t len, resid; |
| 1104 |
BlockConf *conf = &sdev->conf; |
| 1105 |
uint16_t sdev_id = ((sdev->id & 0xFF) >> 8) | (lun & 0xFF); |
| 1106 |
uint64_t ld_size; |
| 1107 |
|
| 1108 |
if (!cmd->iov_buf) {
|
| 1109 |
cmd->iov_buf = g_malloc(dcmd_size); |
| 1110 |
memset(cmd->iov_buf, 0x0, dcmd_size);
|
| 1111 |
info = cmd->iov_buf; |
| 1112 |
megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83)); |
| 1113 |
req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd); |
| 1114 |
if (!req) {
|
| 1115 |
trace_megasas_dcmd_req_alloc_failed(cmd->index, |
| 1116 |
"LD get info vpd inquiry");
|
| 1117 |
g_free(cmd->iov_buf); |
| 1118 |
cmd->iov_buf = NULL;
|
| 1119 |
return MFI_STAT_FLASH_ALLOC_FAIL;
|
| 1120 |
} |
| 1121 |
trace_megasas_dcmd_internal_submit(cmd->index, |
| 1122 |
"LD get info vpd inquiry", lun);
|
| 1123 |
len = scsi_req_enqueue(req); |
| 1124 |
if (len > 0) { |
| 1125 |
cmd->iov_size = len; |
| 1126 |
scsi_req_continue(req); |
| 1127 |
} |
| 1128 |
return MFI_STAT_INVALID_STATUS;
|
| 1129 |
} |
| 1130 |
|
| 1131 |
info->ld_config.params.state = MFI_LD_STATE_OPTIMAL; |
| 1132 |
info->ld_config.properties.ld.v.target_id = lun; |
| 1133 |
info->ld_config.params.stripe_size = 3;
|
| 1134 |
info->ld_config.params.num_drives = 1;
|
| 1135 |
info->ld_config.params.is_consistent = 1;
|
| 1136 |
/* Logical device size is in blocks */
|
| 1137 |
bdrv_get_geometry(conf->bs, &ld_size); |
| 1138 |
info->size = cpu_to_le64(ld_size); |
| 1139 |
memset(info->ld_config.span, 0, sizeof(info->ld_config.span)); |
| 1140 |
info->ld_config.span[0].start_block = 0; |
| 1141 |
info->ld_config.span[0].num_blocks = info->size;
|
| 1142 |
info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
|
| 1143 |
|
| 1144 |
resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg); |
| 1145 |
g_free(cmd->iov_buf); |
| 1146 |
cmd->iov_size = dcmd_size - resid; |
| 1147 |
cmd->iov_buf = NULL;
|
| 1148 |
return MFI_STAT_OK;
|
| 1149 |
} |
| 1150 |
|
| 1151 |
static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd) |
| 1152 |
{
|
| 1153 |
struct mfi_ld_info info;
|
| 1154 |
size_t dcmd_size = sizeof(info);
|
| 1155 |
uint16_t ld_id; |
| 1156 |
uint32_t max_ld_disks = s->fw_luns; |
| 1157 |
SCSIDevice *sdev = NULL;
|
| 1158 |
int retval = MFI_STAT_DEVICE_NOT_FOUND;
|
| 1159 |
|
| 1160 |
if (cmd->iov_size < dcmd_size) {
|
| 1161 |
return MFI_STAT_INVALID_PARAMETER;
|
| 1162 |
} |
| 1163 |
|
| 1164 |
/* mbox0 has the ID */
|
| 1165 |
ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
|
| 1166 |
trace_megasas_dcmd_ld_get_info(cmd->index, ld_id); |
| 1167 |
|
| 1168 |
if (megasas_is_jbod(s)) {
|
| 1169 |
return MFI_STAT_DEVICE_NOT_FOUND;
|
| 1170 |
} |
| 1171 |
|
| 1172 |
if (ld_id < max_ld_disks) {
|
| 1173 |
sdev = scsi_device_find(&s->bus, 0, ld_id, 0); |
| 1174 |
} |
| 1175 |
|
| 1176 |
if (sdev) {
|
| 1177 |
retval = megasas_ld_get_info_submit(sdev, ld_id, cmd); |
| 1178 |
} |
| 1179 |
|
| 1180 |
return retval;
|
| 1181 |
} |
| 1182 |
|
| 1183 |
static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd) |
| 1184 |
{
|
| 1185 |
uint8_t data[4096];
|
| 1186 |
struct mfi_config_data *info;
|
| 1187 |
int num_pd_disks = 0, array_offset, ld_offset; |
| 1188 |
BusChild *kid; |
| 1189 |
|
| 1190 |
if (cmd->iov_size > 4096) { |
| 1191 |
return MFI_STAT_INVALID_PARAMETER;
|
| 1192 |
} |
| 1193 |
|
| 1194 |
QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
|
| 1195 |
num_pd_disks++; |
| 1196 |
} |
| 1197 |
info = (struct mfi_config_data *)&data;
|
| 1198 |
/*
|
| 1199 |
* Array mapping:
|
| 1200 |
* - One array per SCSI device
|
| 1201 |
* - One logical drive per SCSI device
|
| 1202 |
* spanning the entire device
|
| 1203 |
*/
|
| 1204 |
info->array_count = num_pd_disks; |
| 1205 |
info->array_size = sizeof(struct mfi_array) * num_pd_disks; |
| 1206 |
info->log_drv_count = num_pd_disks; |
| 1207 |
info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks; |
| 1208 |
info->spares_count = 0;
|
| 1209 |
info->spares_size = sizeof(struct mfi_spare); |
| 1210 |
info->size = sizeof(struct mfi_config_data) + info->array_size + |
| 1211 |
info->log_drv_size; |
| 1212 |
if (info->size > 4096) { |
| 1213 |
return MFI_STAT_INVALID_PARAMETER;
|
| 1214 |
} |
| 1215 |
|
| 1216 |
array_offset = sizeof(struct mfi_config_data); |
| 1217 |
ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks; |
| 1218 |
|
| 1219 |
QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
|
| 1220 |
SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child); |
| 1221 |
BlockConf *conf = &sdev->conf; |
| 1222 |
uint16_t sdev_id = ((sdev->id & 0xFF) >> 8) | (sdev->lun & 0xFF); |
| 1223 |
struct mfi_array *array;
|
| 1224 |
struct mfi_ld_config *ld;
|
| 1225 |
uint64_t pd_size; |
| 1226 |
int i;
|
| 1227 |
|
| 1228 |
array = (struct mfi_array *)(data + array_offset);
|
| 1229 |
bdrv_get_geometry(conf->bs, &pd_size); |
| 1230 |
array->size = cpu_to_le64(pd_size); |
| 1231 |
array->num_drives = 1;
|
| 1232 |
array->array_ref = cpu_to_le16(sdev_id); |
| 1233 |
array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
|
| 1234 |
array->pd[0].ref.v.seq_num = 0; |
| 1235 |
array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
|
| 1236 |
array->pd[0].encl.pd = 0xFF; |
| 1237 |
array->pd[0].encl.slot = (sdev->id & 0xFF); |
| 1238 |
for (i = 1; i < MFI_MAX_ROW_SIZE; i++) { |
| 1239 |
array->pd[i].ref.v.device_id = 0xFFFF;
|
| 1240 |
array->pd[i].ref.v.seq_num = 0;
|
| 1241 |
array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD; |
| 1242 |
array->pd[i].encl.pd = 0xFF;
|
| 1243 |
array->pd[i].encl.slot = 0xFF;
|
| 1244 |
} |
| 1245 |
array_offset += sizeof(struct mfi_array); |
| 1246 |
ld = (struct mfi_ld_config *)(data + ld_offset);
|
| 1247 |
memset(ld, 0, sizeof(struct mfi_ld_config)); |
| 1248 |
ld->properties.ld.v.target_id = (sdev->id & 0xFF);
|
| 1249 |
ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD | |
| 1250 |
MR_LD_CACHE_READ_ADAPTIVE; |
| 1251 |
ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD | |
| 1252 |
MR_LD_CACHE_READ_ADAPTIVE; |
| 1253 |
ld->params.state = MFI_LD_STATE_OPTIMAL; |
| 1254 |
ld->params.stripe_size = 3;
|
| 1255 |
ld->params.num_drives = 1;
|
| 1256 |
ld->params.span_depth = 1;
|
| 1257 |
ld->params.is_consistent = 1;
|
| 1258 |
ld->span[0].start_block = 0; |
| 1259 |
ld->span[0].num_blocks = cpu_to_le64(pd_size);
|
| 1260 |
ld->span[0].array_ref = cpu_to_le16(sdev_id);
|
| 1261 |
ld_offset += sizeof(struct mfi_ld_config); |
| 1262 |
} |
| 1263 |
|
| 1264 |
cmd->iov_size -= dma_buf_read((uint8_t *)data, info->size, &cmd->qsg); |
| 1265 |
return MFI_STAT_OK;
|
| 1266 |
} |
| 1267 |
|
| 1268 |
static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd) |
| 1269 |
{
|
| 1270 |
struct mfi_ctrl_props info;
|
| 1271 |
size_t dcmd_size = sizeof(info);
|
| 1272 |
|
| 1273 |
memset(&info, 0x0, dcmd_size);
|
| 1274 |
if (cmd->iov_size < dcmd_size) {
|
| 1275 |
trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, |
| 1276 |
dcmd_size); |
| 1277 |
return MFI_STAT_INVALID_PARAMETER;
|
| 1278 |
} |
| 1279 |
info.pred_fail_poll_interval = cpu_to_le16(300);
|
| 1280 |
info.intr_throttle_cnt = cpu_to_le16(16);
|
| 1281 |
info.intr_throttle_timeout = cpu_to_le16(50);
|
| 1282 |
info.rebuild_rate = 30;
|
| 1283 |
info.patrol_read_rate = 30;
|
| 1284 |
info.bgi_rate = 30;
|
| 1285 |
info.cc_rate = 30;
|
| 1286 |
info.recon_rate = 30;
|
| 1287 |
info.cache_flush_interval = 4;
|
| 1288 |
info.spinup_drv_cnt = 2;
|
| 1289 |
info.spinup_delay = 6;
|
| 1290 |
info.ecc_bucket_size = 15;
|
| 1291 |
info.ecc_bucket_leak_rate = cpu_to_le16(1440);
|
| 1292 |
info.expose_encl_devices = 1;
|
| 1293 |
|
| 1294 |
cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg); |
| 1295 |
return MFI_STAT_OK;
|
| 1296 |
} |
| 1297 |
|
| 1298 |
static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd) |
| 1299 |
{
|
| 1300 |
qemu_aio_flush(); |
| 1301 |
return MFI_STAT_OK;
|
| 1302 |
} |
| 1303 |
|
| 1304 |
static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd) |
| 1305 |
{
|
| 1306 |
s->fw_state = MFI_FWSTATE_READY; |
| 1307 |
return MFI_STAT_OK;
|
| 1308 |
} |
| 1309 |
|
| 1310 |
static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd) |
| 1311 |
{
|
| 1312 |
return MFI_STAT_INVALID_DCMD;
|
| 1313 |
} |
| 1314 |
|
| 1315 |
static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd) |
| 1316 |
{
|
| 1317 |
struct mfi_ctrl_props info;
|
| 1318 |
size_t dcmd_size = sizeof(info);
|
| 1319 |
|
| 1320 |
if (cmd->iov_size < dcmd_size) {
|
| 1321 |
trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, |
| 1322 |
dcmd_size); |
| 1323 |
return MFI_STAT_INVALID_PARAMETER;
|
| 1324 |
} |
| 1325 |
dma_buf_write((uint8_t *)&info, cmd->iov_size, &cmd->qsg); |
| 1326 |
trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size); |
| 1327 |
return MFI_STAT_OK;
|
| 1328 |
} |
| 1329 |
|
| 1330 |
static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd) |
| 1331 |
{
|
| 1332 |
trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size); |
| 1333 |
return MFI_STAT_OK;
|
| 1334 |
} |
| 1335 |
|
| 1336 |
static const struct dcmd_cmd_tbl_t { |
| 1337 |
int opcode;
|
| 1338 |
const char *desc; |
| 1339 |
int (*func)(MegasasState *s, MegasasCmd *cmd);
|
| 1340 |
} dcmd_cmd_tbl[] = {
|
| 1341 |
{ MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
|
| 1342 |
megasas_dcmd_dummy }, |
| 1343 |
{ MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
|
| 1344 |
megasas_ctrl_get_info }, |
| 1345 |
{ MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
|
| 1346 |
megasas_dcmd_get_properties }, |
| 1347 |
{ MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
|
| 1348 |
megasas_dcmd_set_properties }, |
| 1349 |
{ MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
|
| 1350 |
megasas_dcmd_dummy }, |
| 1351 |
{ MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
|
| 1352 |
megasas_dcmd_dummy }, |
| 1353 |
{ MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
|
| 1354 |
megasas_dcmd_dummy }, |
| 1355 |
{ MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
|
| 1356 |
megasas_dcmd_dummy }, |
| 1357 |
{ MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
|
| 1358 |
megasas_dcmd_dummy }, |
| 1359 |
{ MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
|
| 1360 |
megasas_event_info }, |
| 1361 |
{ MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
|
| 1362 |
megasas_dcmd_dummy }, |
| 1363 |
{ MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
|
| 1364 |
megasas_event_wait }, |
| 1365 |
{ MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
|
| 1366 |
megasas_ctrl_shutdown }, |
| 1367 |
{ MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
|
| 1368 |
megasas_dcmd_dummy }, |
| 1369 |
{ MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
|
| 1370 |
megasas_dcmd_get_fw_time }, |
| 1371 |
{ MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
|
| 1372 |
megasas_dcmd_set_fw_time }, |
| 1373 |
{ MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
|
| 1374 |
megasas_dcmd_get_bios_info }, |
| 1375 |
{ MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
|
| 1376 |
megasas_dcmd_dummy }, |
| 1377 |
{ MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
|
| 1378 |
megasas_mfc_get_defaults }, |
| 1379 |
{ MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
|
| 1380 |
megasas_dcmd_dummy }, |
| 1381 |
{ MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
|
| 1382 |
megasas_cache_flush }, |
| 1383 |
{ MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
|
| 1384 |
megasas_dcmd_pd_get_list }, |
| 1385 |
{ MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
|
| 1386 |
megasas_dcmd_pd_list_query }, |
| 1387 |
{ MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
|
| 1388 |
megasas_dcmd_pd_get_info }, |
| 1389 |
{ MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
|
| 1390 |
megasas_dcmd_dummy }, |
| 1391 |
{ MFI_DCMD_PD_REBUILD, "PD_REBUILD",
|
| 1392 |
megasas_dcmd_dummy }, |
| 1393 |
{ MFI_DCMD_PD_BLINK, "PD_BLINK",
|
| 1394 |
megasas_dcmd_dummy }, |
| 1395 |
{ MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
|
| 1396 |
megasas_dcmd_dummy }, |
| 1397 |
{ MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
|
| 1398 |
megasas_dcmd_ld_get_list}, |
| 1399 |
{ MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
|
| 1400 |
megasas_dcmd_ld_get_info }, |
| 1401 |
{ MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
|
| 1402 |
megasas_dcmd_dummy }, |
| 1403 |
{ MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
|
| 1404 |
megasas_dcmd_dummy }, |
| 1405 |
{ MFI_DCMD_LD_DELETE, "LD_DELETE",
|
| 1406 |
megasas_dcmd_dummy }, |
| 1407 |
{ MFI_DCMD_CFG_READ, "CFG_READ",
|
| 1408 |
megasas_dcmd_cfg_read }, |
| 1409 |
{ MFI_DCMD_CFG_ADD, "CFG_ADD",
|
| 1410 |
megasas_dcmd_dummy }, |
| 1411 |
{ MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
|
| 1412 |
megasas_dcmd_dummy }, |
| 1413 |
{ MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
|
| 1414 |
megasas_dcmd_dummy }, |
| 1415 |
{ MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
|
| 1416 |
megasas_dcmd_dummy }, |
| 1417 |
{ MFI_DCMD_BBU_STATUS, "BBU_STATUS",
|
| 1418 |
megasas_dcmd_dummy }, |
| 1419 |
{ MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
|
| 1420 |
megasas_dcmd_dummy }, |
| 1421 |
{ MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
|
| 1422 |
megasas_dcmd_dummy }, |
| 1423 |
{ MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
|
| 1424 |
megasas_dcmd_dummy }, |
| 1425 |
{ MFI_DCMD_CLUSTER, "CLUSTER",
|
| 1426 |
megasas_dcmd_dummy }, |
| 1427 |
{ MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
|
| 1428 |
megasas_dcmd_dummy }, |
| 1429 |
{ MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
|
| 1430 |
megasas_cluster_reset_ld }, |
| 1431 |
{ -1, NULL, NULL }
|
| 1432 |
}; |
| 1433 |
|
| 1434 |
static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd) |
| 1435 |
{
|
| 1436 |
int opcode, len;
|
| 1437 |
int retval = 0; |
| 1438 |
const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl; |
| 1439 |
|
| 1440 |
opcode = le32_to_cpu(cmd->frame->dcmd.opcode); |
| 1441 |
trace_megasas_handle_dcmd(cmd->index, opcode); |
| 1442 |
len = megasas_map_dcmd(s, cmd); |
| 1443 |
if (len < 0) { |
| 1444 |
return MFI_STAT_MEMORY_NOT_AVAILABLE;
|
| 1445 |
} |
| 1446 |
while (cmdptr->opcode != -1 && cmdptr->opcode != opcode) { |
| 1447 |
cmdptr++; |
| 1448 |
} |
| 1449 |
if (cmdptr->opcode == -1) { |
| 1450 |
trace_megasas_dcmd_unhandled(cmd->index, opcode, len); |
| 1451 |
retval = megasas_dcmd_dummy(s, cmd); |
| 1452 |
} else {
|
| 1453 |
trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len); |
| 1454 |
retval = cmdptr->func(s, cmd); |
| 1455 |
} |
| 1456 |
if (retval != MFI_STAT_INVALID_STATUS) {
|
| 1457 |
megasas_finish_dcmd(cmd, len); |
| 1458 |
} |
| 1459 |
return retval;
|
| 1460 |
} |
| 1461 |
|
| 1462 |
static int megasas_finish_internal_dcmd(MegasasCmd *cmd, |
| 1463 |
SCSIRequest *req) |
| 1464 |
{
|
| 1465 |
int opcode;
|
| 1466 |
int retval = MFI_STAT_OK;
|
| 1467 |
int lun = req->lun;
|
| 1468 |
|
| 1469 |
opcode = le32_to_cpu(cmd->frame->dcmd.opcode); |
| 1470 |
scsi_req_unref(req); |
| 1471 |
trace_megasas_dcmd_internal_finish(cmd->index, opcode, lun); |
| 1472 |
switch (opcode) {
|
| 1473 |
case MFI_DCMD_PD_GET_INFO:
|
| 1474 |
retval = megasas_pd_get_info_submit(req->dev, lun, cmd); |
| 1475 |
break;
|
| 1476 |
case MFI_DCMD_LD_GET_INFO:
|
| 1477 |
retval = megasas_ld_get_info_submit(req->dev, lun, cmd); |
| 1478 |
break;
|
| 1479 |
default:
|
| 1480 |
trace_megasas_dcmd_internal_invalid(cmd->index, opcode); |
| 1481 |
retval = MFI_STAT_INVALID_DCMD; |
| 1482 |
break;
|
| 1483 |
} |
| 1484 |
if (retval != MFI_STAT_INVALID_STATUS) {
|
| 1485 |
megasas_finish_dcmd(cmd, cmd->iov_size); |
| 1486 |
} |
| 1487 |
return retval;
|
| 1488 |
} |
| 1489 |
|
| 1490 |
static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write) |
| 1491 |
{
|
| 1492 |
int len;
|
| 1493 |
|
| 1494 |
len = scsi_req_enqueue(cmd->req); |
| 1495 |
if (len < 0) { |
| 1496 |
len = -len; |
| 1497 |
} |
| 1498 |
if (len > 0) { |
| 1499 |
if (len > cmd->iov_size) {
|
| 1500 |
if (is_write) {
|
| 1501 |
trace_megasas_iov_write_overflow(cmd->index, len, |
| 1502 |
cmd->iov_size); |
| 1503 |
} else {
|
| 1504 |
trace_megasas_iov_read_overflow(cmd->index, len, |
| 1505 |
cmd->iov_size); |
| 1506 |
} |
| 1507 |
} |
| 1508 |
if (len < cmd->iov_size) {
|
| 1509 |
if (is_write) {
|
| 1510 |
trace_megasas_iov_write_underflow(cmd->index, len, |
| 1511 |
cmd->iov_size); |
| 1512 |
} else {
|
| 1513 |
trace_megasas_iov_read_underflow(cmd->index, len, |
| 1514 |
cmd->iov_size); |
| 1515 |
} |
| 1516 |
cmd->iov_size = len; |
| 1517 |
} |
| 1518 |
scsi_req_continue(cmd->req); |
| 1519 |
} |
| 1520 |
return len;
|
| 1521 |
} |
| 1522 |
|
| 1523 |
static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd, |
| 1524 |
bool is_logical)
|
| 1525 |
{
|
| 1526 |
uint8_t *cdb; |
| 1527 |
int len;
|
| 1528 |
bool is_write;
|
| 1529 |
struct SCSIDevice *sdev = NULL; |
| 1530 |
|
| 1531 |
cdb = cmd->frame->pass.cdb; |
| 1532 |
|
| 1533 |
if (cmd->frame->header.target_id < s->fw_luns) {
|
| 1534 |
sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
|
| 1535 |
cmd->frame->header.lun_id); |
| 1536 |
} |
| 1537 |
cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len); |
| 1538 |
trace_megasas_handle_scsi(mfi_frame_desc[cmd->frame->header.frame_cmd], |
| 1539 |
is_logical, cmd->frame->header.target_id, |
| 1540 |
cmd->frame->header.lun_id, sdev, cmd->iov_size); |
| 1541 |
|
| 1542 |
if (!sdev || (megasas_is_jbod(s) && is_logical)) {
|
| 1543 |
trace_megasas_scsi_target_not_present( |
| 1544 |
mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical, |
| 1545 |
cmd->frame->header.target_id, cmd->frame->header.lun_id); |
| 1546 |
return MFI_STAT_DEVICE_NOT_FOUND;
|
| 1547 |
} |
| 1548 |
|
| 1549 |
if (cmd->frame->header.cdb_len > 16) { |
| 1550 |
trace_megasas_scsi_invalid_cdb_len( |
| 1551 |
mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical, |
| 1552 |
cmd->frame->header.target_id, cmd->frame->header.lun_id, |
| 1553 |
cmd->frame->header.cdb_len); |
| 1554 |
megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE)); |
| 1555 |
cmd->frame->header.scsi_status = CHECK_CONDITION; |
| 1556 |
s->event_count++; |
| 1557 |
return MFI_STAT_SCSI_DONE_WITH_ERROR;
|
| 1558 |
} |
| 1559 |
|
| 1560 |
if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
|
| 1561 |
megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE)); |
| 1562 |
cmd->frame->header.scsi_status = CHECK_CONDITION; |
| 1563 |
s->event_count++; |
| 1564 |
return MFI_STAT_SCSI_DONE_WITH_ERROR;
|
| 1565 |
} |
| 1566 |
|
| 1567 |
cmd->req = scsi_req_new(sdev, cmd->index, |
| 1568 |
cmd->frame->header.lun_id, cdb, cmd); |
| 1569 |
if (!cmd->req) {
|
| 1570 |
trace_megasas_scsi_req_alloc_failed( |
| 1571 |
mfi_frame_desc[cmd->frame->header.frame_cmd], |
| 1572 |
cmd->frame->header.target_id, cmd->frame->header.lun_id); |
| 1573 |
megasas_write_sense(cmd, SENSE_CODE(NO_SENSE)); |
| 1574 |
cmd->frame->header.scsi_status = BUSY; |
| 1575 |
s->event_count++; |
| 1576 |
return MFI_STAT_SCSI_DONE_WITH_ERROR;
|
| 1577 |
} |
| 1578 |
|
| 1579 |
is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV); |
| 1580 |
len = megasas_enqueue_req(cmd, is_write); |
| 1581 |
if (len > 0) { |
| 1582 |
if (is_write) {
|
| 1583 |
trace_megasas_scsi_write_start(cmd->index, len); |
| 1584 |
} else {
|
| 1585 |
trace_megasas_scsi_read_start(cmd->index, len); |
| 1586 |
} |
| 1587 |
} else {
|
| 1588 |
trace_megasas_scsi_nodata(cmd->index); |
| 1589 |
} |
| 1590 |
return MFI_STAT_INVALID_STATUS;
|
| 1591 |
} |
| 1592 |
|
| 1593 |
static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd) |
| 1594 |
{
|
| 1595 |
uint32_t lba_count, lba_start_hi, lba_start_lo; |
| 1596 |
uint64_t lba_start; |
| 1597 |
bool is_write = (cmd->frame->header.frame_cmd == MFI_CMD_LD_WRITE);
|
| 1598 |
uint8_t cdb[16];
|
| 1599 |
int len;
|
| 1600 |
struct SCSIDevice *sdev = NULL; |
| 1601 |
|
| 1602 |
lba_count = le32_to_cpu(cmd->frame->io.header.data_len); |
| 1603 |
lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo); |
| 1604 |
lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi); |
| 1605 |
lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
|
| 1606 |
|
| 1607 |
if (cmd->frame->header.target_id < s->fw_luns) {
|
| 1608 |
sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
|
| 1609 |
cmd->frame->header.lun_id); |
| 1610 |
} |
| 1611 |
|
| 1612 |
trace_megasas_handle_io(cmd->index, |
| 1613 |
mfi_frame_desc[cmd->frame->header.frame_cmd], |
| 1614 |
cmd->frame->header.target_id, |
| 1615 |
cmd->frame->header.lun_id, |
| 1616 |
(unsigned long)lba_start, (unsigned long)lba_count); |
| 1617 |
if (!sdev) {
|
| 1618 |
trace_megasas_io_target_not_present(cmd->index, |
| 1619 |
mfi_frame_desc[cmd->frame->header.frame_cmd], |
| 1620 |
cmd->frame->header.target_id, cmd->frame->header.lun_id); |
| 1621 |
return MFI_STAT_DEVICE_NOT_FOUND;
|
| 1622 |
} |
| 1623 |
|
| 1624 |
if (cmd->frame->header.cdb_len > 16) { |
| 1625 |
trace_megasas_scsi_invalid_cdb_len( |
| 1626 |
mfi_frame_desc[cmd->frame->header.frame_cmd], 1,
|
| 1627 |
cmd->frame->header.target_id, cmd->frame->header.lun_id, |
| 1628 |
cmd->frame->header.cdb_len); |
| 1629 |
megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE)); |
| 1630 |
cmd->frame->header.scsi_status = CHECK_CONDITION; |
| 1631 |
s->event_count++; |
| 1632 |
return MFI_STAT_SCSI_DONE_WITH_ERROR;
|
| 1633 |
} |
| 1634 |
|
| 1635 |
cmd->iov_size = lba_count * sdev->blocksize; |
| 1636 |
if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
|
| 1637 |
megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE)); |
| 1638 |
cmd->frame->header.scsi_status = CHECK_CONDITION; |
| 1639 |
s->event_count++; |
| 1640 |
return MFI_STAT_SCSI_DONE_WITH_ERROR;
|
| 1641 |
} |
| 1642 |
|
| 1643 |
megasas_encode_lba(cdb, lba_start, lba_count, is_write); |
| 1644 |
cmd->req = scsi_req_new(sdev, cmd->index, |
| 1645 |
cmd->frame->header.lun_id, cdb, cmd); |
| 1646 |
if (!cmd->req) {
|
| 1647 |
trace_megasas_scsi_req_alloc_failed( |
| 1648 |
mfi_frame_desc[cmd->frame->header.frame_cmd], |
| 1649 |
cmd->frame->header.target_id, cmd->frame->header.lun_id); |
| 1650 |
megasas_write_sense(cmd, SENSE_CODE(NO_SENSE)); |
| 1651 |
cmd->frame->header.scsi_status = BUSY; |
| 1652 |
s->event_count++; |
| 1653 |
return MFI_STAT_SCSI_DONE_WITH_ERROR;
|
| 1654 |
} |
| 1655 |
len = megasas_enqueue_req(cmd, is_write); |
| 1656 |
if (len > 0) { |
| 1657 |
if (is_write) {
|
| 1658 |
trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len); |
| 1659 |
} else {
|
| 1660 |
trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len); |
| 1661 |
} |
| 1662 |
} |
| 1663 |
return MFI_STAT_INVALID_STATUS;
|
| 1664 |
} |
| 1665 |
|
| 1666 |
static int megasas_finish_internal_command(MegasasCmd *cmd, |
| 1667 |
SCSIRequest *req, size_t resid) |
| 1668 |
{
|
| 1669 |
int retval = MFI_STAT_INVALID_CMD;
|
| 1670 |
|
| 1671 |
if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
|
| 1672 |
cmd->iov_size -= resid; |
| 1673 |
retval = megasas_finish_internal_dcmd(cmd, req); |
| 1674 |
} |
| 1675 |
return retval;
|
| 1676 |
} |
| 1677 |
|
| 1678 |
static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
|
| 1679 |
{
|
| 1680 |
MegasasCmd *cmd = req->hba_private; |
| 1681 |
|
| 1682 |
if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
|
| 1683 |
return NULL; |
| 1684 |
} else {
|
| 1685 |
return &cmd->qsg;
|
| 1686 |
} |
| 1687 |
} |
| 1688 |
|
| 1689 |
static void megasas_xfer_complete(SCSIRequest *req, uint32_t len) |
| 1690 |
{
|
| 1691 |
MegasasCmd *cmd = req->hba_private; |
| 1692 |
uint8_t *buf; |
| 1693 |
uint32_t opcode; |
| 1694 |
|
| 1695 |
trace_megasas_io_complete(cmd->index, len); |
| 1696 |
|
| 1697 |
if (cmd->frame->header.frame_cmd != MFI_CMD_DCMD) {
|
| 1698 |
scsi_req_continue(req); |
| 1699 |
return;
|
| 1700 |
} |
| 1701 |
|
| 1702 |
buf = scsi_req_get_buf(req); |
| 1703 |
opcode = le32_to_cpu(cmd->frame->dcmd.opcode); |
| 1704 |
if (opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
|
| 1705 |
struct mfi_pd_info *info = cmd->iov_buf;
|
| 1706 |
|
| 1707 |
if (info->inquiry_data[0] == 0x7f) { |
| 1708 |
memset(info->inquiry_data, 0, sizeof(info->inquiry_data)); |
| 1709 |
memcpy(info->inquiry_data, buf, len); |
| 1710 |
} else if (info->vpd_page83[0] == 0x7f) { |
| 1711 |
memset(info->vpd_page83, 0, sizeof(info->vpd_page83)); |
| 1712 |
memcpy(info->vpd_page83, buf, len); |
| 1713 |
} |
| 1714 |
scsi_req_continue(req); |
| 1715 |
} else if (opcode == MFI_DCMD_LD_GET_INFO) { |
| 1716 |
struct mfi_ld_info *info = cmd->iov_buf;
|
| 1717 |
|
| 1718 |
if (cmd->iov_buf) {
|
| 1719 |
memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
|
| 1720 |
scsi_req_continue(req); |
| 1721 |
} |
| 1722 |
} |
| 1723 |
} |
| 1724 |
|
| 1725 |
static void megasas_command_complete(SCSIRequest *req, uint32_t status, |
| 1726 |
size_t resid) |
| 1727 |
{
|
| 1728 |
MegasasCmd *cmd = req->hba_private; |
| 1729 |
uint8_t cmd_status = MFI_STAT_OK; |
| 1730 |
|
| 1731 |
trace_megasas_command_complete(cmd->index, status, resid); |
| 1732 |
|
| 1733 |
if (cmd->req != req) {
|
| 1734 |
/*
|
| 1735 |
* Internal command complete
|
| 1736 |
*/
|
| 1737 |
cmd_status = megasas_finish_internal_command(cmd, req, resid); |
| 1738 |
if (cmd_status == MFI_STAT_INVALID_STATUS) {
|
| 1739 |
return;
|
| 1740 |
} |
| 1741 |
} else {
|
| 1742 |
req->status = status; |
| 1743 |
trace_megasas_scsi_complete(cmd->index, req->status, |
| 1744 |
cmd->iov_size, req->cmd.xfer); |
| 1745 |
if (req->status != GOOD) {
|
| 1746 |
cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR; |
| 1747 |
} |
| 1748 |
if (req->status == CHECK_CONDITION) {
|
| 1749 |
megasas_copy_sense(cmd); |
| 1750 |
} |
| 1751 |
|
| 1752 |
megasas_unmap_sgl(cmd); |
| 1753 |
cmd->frame->header.scsi_status = req->status; |
| 1754 |
scsi_req_unref(cmd->req); |
| 1755 |
cmd->req = NULL;
|
| 1756 |
} |
| 1757 |
cmd->frame->header.cmd_status = cmd_status; |
| 1758 |
megasas_complete_frame(cmd->state, cmd->context); |
| 1759 |
} |
| 1760 |
|
| 1761 |
static void megasas_command_cancel(SCSIRequest *req) |
| 1762 |
{
|
| 1763 |
MegasasCmd *cmd = req->hba_private; |
| 1764 |
|
| 1765 |
if (cmd) {
|
| 1766 |
megasas_abort_command(cmd); |
| 1767 |
} else {
|
| 1768 |
scsi_req_unref(req); |
| 1769 |
} |
| 1770 |
} |
| 1771 |
|
| 1772 |
static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd) |
| 1773 |
{
|
| 1774 |
uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context); |
| 1775 |
target_phys_addr_t abort_addr, addr_hi, addr_lo; |
| 1776 |
MegasasCmd *abort_cmd; |
| 1777 |
|
| 1778 |
addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi); |
| 1779 |
addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo); |
| 1780 |
abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
|
| 1781 |
|
| 1782 |
abort_cmd = megasas_lookup_frame(s, abort_addr); |
| 1783 |
if (!abort_cmd) {
|
| 1784 |
trace_megasas_abort_no_cmd(cmd->index, abort_ctx); |
| 1785 |
s->event_count++; |
| 1786 |
return MFI_STAT_OK;
|
| 1787 |
} |
| 1788 |
if (!megasas_use_queue64(s)) {
|
| 1789 |
abort_ctx &= (uint64_t)0xFFFFFFFF;
|
| 1790 |
} |
| 1791 |
if (abort_cmd->context != abort_ctx) {
|
| 1792 |
trace_megasas_abort_invalid_context(cmd->index, abort_cmd->index, |
| 1793 |
abort_cmd->context); |
| 1794 |
s->event_count++; |
| 1795 |
return MFI_STAT_ABORT_NOT_POSSIBLE;
|
| 1796 |
} |
| 1797 |
trace_megasas_abort_frame(cmd->index, abort_cmd->index); |
| 1798 |
megasas_abort_command(abort_cmd); |
| 1799 |
if (!s->event_cmd || abort_cmd != s->event_cmd) {
|
| 1800 |
s->event_cmd = NULL;
|
| 1801 |
} |
| 1802 |
s->event_count++; |
| 1803 |
return MFI_STAT_OK;
|
| 1804 |
} |
| 1805 |
|
| 1806 |
static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr, |
| 1807 |
uint32_t frame_count) |
| 1808 |
{
|
| 1809 |
uint8_t frame_status = MFI_STAT_INVALID_CMD; |
| 1810 |
uint64_t frame_context; |
| 1811 |
MegasasCmd *cmd; |
| 1812 |
|
| 1813 |
/*
|
| 1814 |
* Always read 64bit context, top bits will be
|
| 1815 |
* masked out if required in megasas_enqueue_frame()
|
| 1816 |
*/
|
| 1817 |
frame_context = megasas_frame_get_context(frame_addr); |
| 1818 |
|
| 1819 |
cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count); |
| 1820 |
if (!cmd) {
|
| 1821 |
/* reply queue full */
|
| 1822 |
trace_megasas_frame_busy(frame_addr); |
| 1823 |
megasas_frame_set_scsi_status(frame_addr, BUSY); |
| 1824 |
megasas_frame_set_cmd_status(frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR); |
| 1825 |
megasas_complete_frame(s, frame_context); |
| 1826 |
s->event_count++; |
| 1827 |
return;
|
| 1828 |
} |
| 1829 |
switch (cmd->frame->header.frame_cmd) {
|
| 1830 |
case MFI_CMD_INIT:
|
| 1831 |
frame_status = megasas_init_firmware(s, cmd); |
| 1832 |
break;
|
| 1833 |
case MFI_CMD_DCMD:
|
| 1834 |
frame_status = megasas_handle_dcmd(s, cmd); |
| 1835 |
break;
|
| 1836 |
case MFI_CMD_ABORT:
|
| 1837 |
frame_status = megasas_handle_abort(s, cmd); |
| 1838 |
break;
|
| 1839 |
case MFI_CMD_PD_SCSI_IO:
|
| 1840 |
frame_status = megasas_handle_scsi(s, cmd, 0);
|
| 1841 |
break;
|
| 1842 |
case MFI_CMD_LD_SCSI_IO:
|
| 1843 |
frame_status = megasas_handle_scsi(s, cmd, 1);
|
| 1844 |
break;
|
| 1845 |
case MFI_CMD_LD_READ:
|
| 1846 |
case MFI_CMD_LD_WRITE:
|
| 1847 |
frame_status = megasas_handle_io(s, cmd); |
| 1848 |
break;
|
| 1849 |
default:
|
| 1850 |
trace_megasas_unhandled_frame_cmd(cmd->index, |
| 1851 |
cmd->frame->header.frame_cmd); |
| 1852 |
s->event_count++; |
| 1853 |
break;
|
| 1854 |
} |
| 1855 |
if (frame_status != MFI_STAT_INVALID_STATUS) {
|
| 1856 |
if (cmd->frame) {
|
| 1857 |
cmd->frame->header.cmd_status = frame_status; |
| 1858 |
} else {
|
| 1859 |
megasas_frame_set_cmd_status(frame_addr, frame_status); |
| 1860 |
} |
| 1861 |
megasas_complete_frame(s, cmd->context); |
| 1862 |
} |
| 1863 |
} |
| 1864 |
|
| 1865 |
static uint64_t megasas_mmio_read(void *opaque, target_phys_addr_t addr, |
| 1866 |
unsigned size)
|
| 1867 |
{
|
| 1868 |
MegasasState *s = opaque; |
| 1869 |
uint32_t retval = 0;
|
| 1870 |
|
| 1871 |
switch (addr) {
|
| 1872 |
case MFI_IDB:
|
| 1873 |
retval = 0;
|
| 1874 |
break;
|
| 1875 |
case MFI_OMSG0:
|
| 1876 |
case MFI_OSP0:
|
| 1877 |
retval = (megasas_use_msix(s) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
|
| 1878 |
(s->fw_state & MFI_FWSTATE_MASK) | |
| 1879 |
((s->fw_sge & 0xff) << 16) | |
| 1880 |
(s->fw_cmds & 0xFFFF);
|
| 1881 |
break;
|
| 1882 |
case MFI_OSTS:
|
| 1883 |
if (megasas_intr_enabled(s) && s->doorbell) {
|
| 1884 |
retval = MFI_1078_RM | 1;
|
| 1885 |
} |
| 1886 |
break;
|
| 1887 |
case MFI_OMSK:
|
| 1888 |
retval = s->intr_mask; |
| 1889 |
break;
|
| 1890 |
case MFI_ODCR0:
|
| 1891 |
retval = s->doorbell; |
| 1892 |
break;
|
| 1893 |
default:
|
| 1894 |
trace_megasas_mmio_invalid_readl(addr); |
| 1895 |
break;
|
| 1896 |
} |
| 1897 |
trace_megasas_mmio_readl(addr, retval); |
| 1898 |
return retval;
|
| 1899 |
} |
| 1900 |
|
| 1901 |
static void megasas_mmio_write(void *opaque, target_phys_addr_t addr, |
| 1902 |
uint64_t val, unsigned size)
|
| 1903 |
{
|
| 1904 |
MegasasState *s = opaque; |
| 1905 |
uint64_t frame_addr; |
| 1906 |
uint32_t frame_count; |
| 1907 |
int i;
|
| 1908 |
|
| 1909 |
trace_megasas_mmio_writel(addr, val); |
| 1910 |
switch (addr) {
|
| 1911 |
case MFI_IDB:
|
| 1912 |
if (val & MFI_FWINIT_ABORT) {
|
| 1913 |
/* Abort all pending cmds */
|
| 1914 |
for (i = 0; i < s->fw_cmds; i++) { |
| 1915 |
megasas_abort_command(&s->frames[i]); |
| 1916 |
} |
| 1917 |
} |
| 1918 |
if (val & MFI_FWINIT_READY) {
|
| 1919 |
/* move to FW READY */
|
| 1920 |
megasas_soft_reset(s); |
| 1921 |
} |
| 1922 |
if (val & MFI_FWINIT_MFIMODE) {
|
| 1923 |
/* discard MFIs */
|
| 1924 |
} |
| 1925 |
break;
|
| 1926 |
case MFI_OMSK:
|
| 1927 |
s->intr_mask = val; |
| 1928 |
if (!megasas_intr_enabled(s) && !msix_enabled(&s->dev)) {
|
| 1929 |
trace_megasas_irq_lower(); |
| 1930 |
qemu_irq_lower(s->dev.irq[0]);
|
| 1931 |
} |
| 1932 |
if (megasas_intr_enabled(s)) {
|
| 1933 |
trace_megasas_intr_enabled(); |
| 1934 |
} else {
|
| 1935 |
trace_megasas_intr_disabled(); |
| 1936 |
} |
| 1937 |
break;
|
| 1938 |
case MFI_ODCR0:
|
| 1939 |
s->doorbell = 0;
|
| 1940 |
if (s->producer_pa && megasas_intr_enabled(s)) {
|
| 1941 |
/* Update reply queue pointer */
|
| 1942 |
trace_megasas_qf_update(s->reply_queue_head, s->busy); |
| 1943 |
stl_le_phys(s->producer_pa, s->reply_queue_head); |
| 1944 |
if (!msix_enabled(&s->dev)) {
|
| 1945 |
trace_megasas_irq_lower(); |
| 1946 |
qemu_irq_lower(s->dev.irq[0]);
|
| 1947 |
} |
| 1948 |
} |
| 1949 |
break;
|
| 1950 |
case MFI_IQPH:
|
| 1951 |
/* Received high 32 bits of a 64 bit MFI frame address */
|
| 1952 |
s->frame_hi = val; |
| 1953 |
break;
|
| 1954 |
case MFI_IQPL:
|
| 1955 |
/* Received low 32 bits of a 64 bit MFI frame address */
|
| 1956 |
case MFI_IQP:
|
| 1957 |
/* Received 32 bit MFI frame address */
|
| 1958 |
frame_addr = (val & ~0x1F);
|
| 1959 |
/* Add possible 64 bit offset */
|
| 1960 |
frame_addr |= ((uint64_t)s->frame_hi << 32);
|
| 1961 |
s->frame_hi = 0;
|
| 1962 |
frame_count = (val >> 1) & 0xF; |
| 1963 |
megasas_handle_frame(s, frame_addr, frame_count); |
| 1964 |
break;
|
| 1965 |
default:
|
| 1966 |
trace_megasas_mmio_invalid_writel(addr, val); |
| 1967 |
break;
|
| 1968 |
} |
| 1969 |
} |
| 1970 |
|
| 1971 |
static const MemoryRegionOps megasas_mmio_ops = { |
| 1972 |
.read = megasas_mmio_read, |
| 1973 |
.write = megasas_mmio_write, |
| 1974 |
.endianness = DEVICE_LITTLE_ENDIAN, |
| 1975 |
.impl = {
|
| 1976 |
.min_access_size = 8,
|
| 1977 |
.max_access_size = 8,
|
| 1978 |
} |
| 1979 |
}; |
| 1980 |
|
| 1981 |
static uint64_t megasas_port_read(void *opaque, target_phys_addr_t addr, |
| 1982 |
unsigned size)
|
| 1983 |
{
|
| 1984 |
return megasas_mmio_read(opaque, addr & 0xff, size); |
| 1985 |
} |
| 1986 |
|
| 1987 |
static void megasas_port_write(void *opaque, target_phys_addr_t addr, |
| 1988 |
uint64_t val, unsigned size)
|
| 1989 |
{
|
| 1990 |
megasas_mmio_write(opaque, addr & 0xff, val, size);
|
| 1991 |
} |
| 1992 |
|
| 1993 |
static const MemoryRegionOps megasas_port_ops = { |
| 1994 |
.read = megasas_port_read, |
| 1995 |
.write = megasas_port_write, |
| 1996 |
.endianness = DEVICE_LITTLE_ENDIAN, |
| 1997 |
.impl = {
|
| 1998 |
.min_access_size = 4,
|
| 1999 |
.max_access_size = 4,
|
| 2000 |
} |
| 2001 |
}; |
| 2002 |
|
| 2003 |
static uint64_t megasas_queue_read(void *opaque, target_phys_addr_t addr, |
| 2004 |
unsigned size)
|
| 2005 |
{
|
| 2006 |
return 0; |
| 2007 |
} |
| 2008 |
|
| 2009 |
static const MemoryRegionOps megasas_queue_ops = { |
| 2010 |
.read = megasas_queue_read, |
| 2011 |
.endianness = DEVICE_LITTLE_ENDIAN, |
| 2012 |
.impl = {
|
| 2013 |
.min_access_size = 8,
|
| 2014 |
.max_access_size = 8,
|
| 2015 |
} |
| 2016 |
}; |
| 2017 |
|
| 2018 |
static void megasas_soft_reset(MegasasState *s) |
| 2019 |
{
|
| 2020 |
int i;
|
| 2021 |
MegasasCmd *cmd; |
| 2022 |
|
| 2023 |
trace_megasas_reset(); |
| 2024 |
for (i = 0; i < s->fw_cmds; i++) { |
| 2025 |
cmd = &s->frames[i]; |
| 2026 |
megasas_abort_command(cmd); |
| 2027 |
} |
| 2028 |
megasas_reset_frames(s); |
| 2029 |
s->reply_queue_len = s->fw_cmds; |
| 2030 |
s->reply_queue_pa = 0;
|
| 2031 |
s->consumer_pa = 0;
|
| 2032 |
s->producer_pa = 0;
|
| 2033 |
s->fw_state = MFI_FWSTATE_READY; |
| 2034 |
s->doorbell = 0;
|
| 2035 |
s->intr_mask = MEGASAS_INTR_DISABLED_MASK; |
| 2036 |
s->frame_hi = 0;
|
| 2037 |
s->flags &= ~MEGASAS_MASK_USE_QUEUE64; |
| 2038 |
s->event_count++; |
| 2039 |
s->boot_event = s->event_count; |
| 2040 |
} |
| 2041 |
|
| 2042 |
static void megasas_scsi_reset(DeviceState *dev) |
| 2043 |
{
|
| 2044 |
MegasasState *s = DO_UPCAST(MegasasState, dev.qdev, dev); |
| 2045 |
|
| 2046 |
megasas_soft_reset(s); |
| 2047 |
} |
| 2048 |
|
| 2049 |
static const VMStateDescription vmstate_megasas = { |
| 2050 |
.name = "megasas",
|
| 2051 |
.version_id = 0,
|
| 2052 |
.minimum_version_id = 0,
|
| 2053 |
.minimum_version_id_old = 0,
|
| 2054 |
.fields = (VMStateField[]) {
|
| 2055 |
VMSTATE_PCI_DEVICE(dev, MegasasState), |
| 2056 |
|
| 2057 |
VMSTATE_INT32(fw_state, MegasasState), |
| 2058 |
VMSTATE_INT32(intr_mask, MegasasState), |
| 2059 |
VMSTATE_INT32(doorbell, MegasasState), |
| 2060 |
VMSTATE_UINT64(reply_queue_pa, MegasasState), |
| 2061 |
VMSTATE_UINT64(consumer_pa, MegasasState), |
| 2062 |
VMSTATE_UINT64(producer_pa, MegasasState), |
| 2063 |
VMSTATE_END_OF_LIST() |
| 2064 |
} |
| 2065 |
}; |
| 2066 |
|
| 2067 |
static void megasas_scsi_uninit(PCIDevice *d) |
| 2068 |
{
|
| 2069 |
MegasasState *s = DO_UPCAST(MegasasState, dev, d); |
| 2070 |
|
| 2071 |
#ifdef USE_MSIX
|
| 2072 |
msix_uninit(&s->dev, &s->mmio_io); |
| 2073 |
#endif
|
| 2074 |
memory_region_destroy(&s->mmio_io); |
| 2075 |
memory_region_destroy(&s->port_io); |
| 2076 |
memory_region_destroy(&s->queue_io); |
| 2077 |
} |
| 2078 |
|
| 2079 |
static const struct SCSIBusInfo megasas_scsi_info = { |
| 2080 |
.tcq = true,
|
| 2081 |
.max_target = MFI_MAX_LD, |
| 2082 |
.max_lun = 255,
|
| 2083 |
|
| 2084 |
.transfer_data = megasas_xfer_complete, |
| 2085 |
.get_sg_list = megasas_get_sg_list, |
| 2086 |
.complete = megasas_command_complete, |
| 2087 |
.cancel = megasas_command_cancel, |
| 2088 |
}; |
| 2089 |
|
| 2090 |
static int megasas_scsi_init(PCIDevice *dev) |
| 2091 |
{
|
| 2092 |
MegasasState *s = DO_UPCAST(MegasasState, dev, dev); |
| 2093 |
uint8_t *pci_conf; |
| 2094 |
int i, bar_type;
|
| 2095 |
|
| 2096 |
pci_conf = s->dev.config; |
| 2097 |
|
| 2098 |
/* PCI latency timer = 0 */
|
| 2099 |
pci_conf[PCI_LATENCY_TIMER] = 0;
|
| 2100 |
/* Interrupt pin 1 */
|
| 2101 |
pci_conf[PCI_INTERRUPT_PIN] = 0x01;
|
| 2102 |
|
| 2103 |
memory_region_init_io(&s->mmio_io, &megasas_mmio_ops, s, |
| 2104 |
"megasas-mmio", 0x4000); |
| 2105 |
memory_region_init_io(&s->port_io, &megasas_port_ops, s, |
| 2106 |
"megasas-io", 256); |
| 2107 |
memory_region_init_io(&s->queue_io, &megasas_queue_ops, s, |
| 2108 |
"megasas-queue", 0x40000); |
| 2109 |
|
| 2110 |
#ifdef USE_MSIX
|
| 2111 |
/* MSI-X support is currently broken */
|
| 2112 |
if (megasas_use_msix(s) &&
|
| 2113 |
msix_init(&s->dev, 15, &s->mmio_io, 0, 0x2000)) { |
| 2114 |
s->flags &= ~MEGASAS_MASK_USE_MSIX; |
| 2115 |
} |
| 2116 |
#else
|
| 2117 |
s->flags &= ~MEGASAS_MASK_USE_MSIX; |
| 2118 |
#endif
|
| 2119 |
|
| 2120 |
bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64; |
| 2121 |
pci_register_bar(&s->dev, 0, bar_type, &s->mmio_io);
|
| 2122 |
pci_register_bar(&s->dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
|
| 2123 |
pci_register_bar(&s->dev, 3, bar_type, &s->queue_io);
|
| 2124 |
|
| 2125 |
if (megasas_use_msix(s)) {
|
| 2126 |
msix_vector_use(&s->dev, 0);
|
| 2127 |
} |
| 2128 |
|
| 2129 |
if (!s->sas_addr) {
|
| 2130 |
s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
|
| 2131 |
IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
|
| 2132 |
s->sas_addr |= (pci_bus_num(dev->bus) << 16);
|
| 2133 |
s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
|
| 2134 |
s->sas_addr |= PCI_FUNC(dev->devfn); |
| 2135 |
} |
| 2136 |
if (!s->hba_serial) {
|
| 2137 |
s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL); |
| 2138 |
} |
| 2139 |
if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) {
|
| 2140 |
s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE; |
| 2141 |
} else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) { |
| 2142 |
s->fw_sge = 128 - MFI_PASS_FRAME_SIZE;
|
| 2143 |
} else {
|
| 2144 |
s->fw_sge = 64 - MFI_PASS_FRAME_SIZE;
|
| 2145 |
} |
| 2146 |
if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
|
| 2147 |
s->fw_cmds = MEGASAS_MAX_FRAMES; |
| 2148 |
} |
| 2149 |
trace_megasas_init(s->fw_sge, s->fw_cmds, |
| 2150 |
megasas_use_msix(s) ? "MSI-X" : "INTx", |
| 2151 |
megasas_is_jbod(s) ? "jbod" : "raid"); |
| 2152 |
s->fw_luns = (MFI_MAX_LD > MAX_SCSI_DEVS) ? |
| 2153 |
MAX_SCSI_DEVS : MFI_MAX_LD; |
| 2154 |
s->producer_pa = 0;
|
| 2155 |
s->consumer_pa = 0;
|
| 2156 |
for (i = 0; i < s->fw_cmds; i++) { |
| 2157 |
s->frames[i].index = i; |
| 2158 |
s->frames[i].context = -1;
|
| 2159 |
s->frames[i].pa = 0;
|
| 2160 |
s->frames[i].state = s; |
| 2161 |
} |
| 2162 |
|
| 2163 |
scsi_bus_new(&s->bus, &dev->qdev, &megasas_scsi_info); |
| 2164 |
scsi_bus_legacy_handle_cmdline(&s->bus); |
| 2165 |
return 0; |
| 2166 |
} |
| 2167 |
|
| 2168 |
static Property megasas_properties[] = {
|
| 2169 |
DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
|
| 2170 |
MEGASAS_DEFAULT_SGE), |
| 2171 |
DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
|
| 2172 |
MEGASAS_DEFAULT_FRAMES), |
| 2173 |
DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
|
| 2174 |
DEFINE_PROP_HEX64("sas_address", MegasasState, sas_addr, 0), |
| 2175 |
#ifdef USE_MSIX
|
| 2176 |
DEFINE_PROP_BIT("use_msix", MegasasState, flags,
|
| 2177 |
MEGASAS_FLAG_USE_MSIX, false),
|
| 2178 |
#endif
|
| 2179 |
DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
|
| 2180 |
MEGASAS_FLAG_USE_JBOD, false),
|
| 2181 |
DEFINE_PROP_END_OF_LIST(), |
| 2182 |
}; |
| 2183 |
|
| 2184 |
static void megasas_class_init(ObjectClass *oc, void *data) |
| 2185 |
{
|
| 2186 |
DeviceClass *dc = DEVICE_CLASS(oc); |
| 2187 |
PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc); |
| 2188 |
|
| 2189 |
pc->init = megasas_scsi_init; |
| 2190 |
pc->exit = megasas_scsi_uninit; |
| 2191 |
pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC; |
| 2192 |
pc->device_id = PCI_DEVICE_ID_LSI_SAS1078; |
| 2193 |
pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC; |
| 2194 |
pc->subsystem_id = 0x1013;
|
| 2195 |
pc->class_id = PCI_CLASS_STORAGE_RAID; |
| 2196 |
dc->props = megasas_properties; |
| 2197 |
dc->reset = megasas_scsi_reset; |
| 2198 |
dc->vmsd = &vmstate_megasas; |
| 2199 |
dc->desc = "LSI MegaRAID SAS 1078";
|
| 2200 |
} |
| 2201 |
|
| 2202 |
static const TypeInfo megasas_info = { |
| 2203 |
.name = "megasas",
|
| 2204 |
.parent = TYPE_PCI_DEVICE, |
| 2205 |
.instance_size = sizeof(MegasasState),
|
| 2206 |
.class_init = megasas_class_init, |
| 2207 |
}; |
| 2208 |
|
| 2209 |
static void megasas_register_types(void) |
| 2210 |
{
|
| 2211 |
type_register_static(&megasas_info); |
| 2212 |
} |
| 2213 |
|
| 2214 |
type_init(megasas_register_types) |