root / target-ppc / op_template.h @ fb6cf1d0
History | View | Annotate | Download (3.6 kB)
1 | 28b6751f | bellard | /*
|
---|---|---|---|
2 | 28b6751f | bellard | * PPC emulation micro-operations for qemu.
|
3 | 28b6751f | bellard | *
|
4 | 28b6751f | bellard | * Copyright (c) 2003 Jocelyn Mayer
|
5 | 28b6751f | bellard | *
|
6 | 28b6751f | bellard | * This library is free software; you can redistribute it and/or
|
7 | 28b6751f | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | 28b6751f | bellard | * License as published by the Free Software Foundation; either
|
9 | 28b6751f | bellard | * version 2 of the License, or (at your option) any later version.
|
10 | 28b6751f | bellard | *
|
11 | 28b6751f | bellard | * This library is distributed in the hope that it will be useful,
|
12 | 28b6751f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | 28b6751f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | 28b6751f | bellard | * Lesser General Public License for more details.
|
15 | 28b6751f | bellard | *
|
16 | 28b6751f | bellard | * You should have received a copy of the GNU Lesser General Public
|
17 | 28b6751f | bellard | * License along with this library; if not, write to the Free Software
|
18 | 28b6751f | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
19 | 28b6751f | bellard | */
|
20 | 28b6751f | bellard | |
21 | 9a64fbe4 | bellard | /* General purpose registers moves */
|
22 | 28b6751f | bellard | void OPPROTO glue(op_load_gpr_T0_gpr, REG)(void) |
23 | 28b6751f | bellard | { |
24 | 28b6751f | bellard | T0 = regs->gpr[REG]; |
25 | 9a64fbe4 | bellard | RETURN(); |
26 | 28b6751f | bellard | } |
27 | 28b6751f | bellard | |
28 | 28b6751f | bellard | void OPPROTO glue(op_load_gpr_T1_gpr, REG)(void) |
29 | 28b6751f | bellard | { |
30 | 28b6751f | bellard | T1 = regs->gpr[REG]; |
31 | 9a64fbe4 | bellard | RETURN(); |
32 | 28b6751f | bellard | } |
33 | 28b6751f | bellard | |
34 | 28b6751f | bellard | void OPPROTO glue(op_load_gpr_T2_gpr, REG)(void) |
35 | 28b6751f | bellard | { |
36 | 28b6751f | bellard | T2 = regs->gpr[REG]; |
37 | 9a64fbe4 | bellard | RETURN(); |
38 | 28b6751f | bellard | } |
39 | 28b6751f | bellard | |
40 | 28b6751f | bellard | void OPPROTO glue(op_store_T0_gpr_gpr, REG)(void) |
41 | 28b6751f | bellard | { |
42 | 28b6751f | bellard | regs->gpr[REG] = T0; |
43 | 9a64fbe4 | bellard | RETURN(); |
44 | 28b6751f | bellard | } |
45 | 28b6751f | bellard | |
46 | 28b6751f | bellard | void OPPROTO glue(op_store_T1_gpr_gpr, REG)(void) |
47 | 28b6751f | bellard | { |
48 | 28b6751f | bellard | regs->gpr[REG] = T1; |
49 | 9a64fbe4 | bellard | RETURN(); |
50 | 28b6751f | bellard | } |
51 | 28b6751f | bellard | |
52 | 28b6751f | bellard | void OPPROTO glue(op_store_T2_gpr_gpr, REG)(void) |
53 | 28b6751f | bellard | { |
54 | 28b6751f | bellard | regs->gpr[REG] = T2; |
55 | 9a64fbe4 | bellard | RETURN(); |
56 | 28b6751f | bellard | } |
57 | 28b6751f | bellard | |
58 | 28b6751f | bellard | #if REG <= 7 |
59 | 9a64fbe4 | bellard | /* Condition register moves */
|
60 | 28b6751f | bellard | void OPPROTO glue(op_load_crf_T0_crf, REG)(void) |
61 | 28b6751f | bellard | { |
62 | 28b6751f | bellard | T0 = regs->crf[REG]; |
63 | 9a64fbe4 | bellard | RETURN(); |
64 | 28b6751f | bellard | } |
65 | 28b6751f | bellard | |
66 | 28b6751f | bellard | void OPPROTO glue(op_load_crf_T1_crf, REG)(void) |
67 | 28b6751f | bellard | { |
68 | 28b6751f | bellard | T1 = regs->crf[REG]; |
69 | 9a64fbe4 | bellard | RETURN(); |
70 | 28b6751f | bellard | } |
71 | 28b6751f | bellard | |
72 | 28b6751f | bellard | void OPPROTO glue(op_store_T0_crf_crf, REG)(void) |
73 | 28b6751f | bellard | { |
74 | 28b6751f | bellard | regs->crf[REG] = T0; |
75 | 9a64fbe4 | bellard | RETURN(); |
76 | 28b6751f | bellard | } |
77 | 28b6751f | bellard | |
78 | 28b6751f | bellard | void OPPROTO glue(op_store_T1_crf_crf, REG)(void) |
79 | 28b6751f | bellard | { |
80 | 28b6751f | bellard | regs->crf[REG] = T1; |
81 | 9a64fbe4 | bellard | RETURN(); |
82 | 28b6751f | bellard | } |
83 | 28b6751f | bellard | |
84 | fb0eaffc | bellard | /* Floating point condition and status register moves */
|
85 | fb0eaffc | bellard | void OPPROTO glue(op_load_fpscr_T0_fpscr, REG)(void) |
86 | fb0eaffc | bellard | { |
87 | fb0eaffc | bellard | T0 = regs->fpscr[REG]; |
88 | fb0eaffc | bellard | RETURN(); |
89 | fb0eaffc | bellard | } |
90 | fb0eaffc | bellard | |
91 | fb0eaffc | bellard | #if REG == 0 |
92 | fb0eaffc | bellard | void OPPROTO glue(op_store_T0_fpscr_fpscr, REG)(void) |
93 | fb0eaffc | bellard | { |
94 | fb0eaffc | bellard | regs->fpscr[REG] = (regs->fpscr[REG] & 0x9) | (T0 & ~0x9); |
95 | fb0eaffc | bellard | RETURN(); |
96 | fb0eaffc | bellard | } |
97 | fb0eaffc | bellard | |
98 | fb0eaffc | bellard | void OPPROTO glue(op_store_T0_fpscri_fpscr, REG)(void) |
99 | fb0eaffc | bellard | { |
100 | fb0eaffc | bellard | regs->fpscr[REG] = (regs->fpscr[REG] & ~0x9) | (PARAM(1) & 0x9); |
101 | fb0eaffc | bellard | RETURN(); |
102 | fb0eaffc | bellard | } |
103 | fb0eaffc | bellard | |
104 | fb0eaffc | bellard | void OPPROTO glue(op_clear_fpscr_fpscr, REG)(void) |
105 | fb0eaffc | bellard | { |
106 | fb0eaffc | bellard | regs->fpscr[REG] = (regs->fpscr[REG] & 0x9);
|
107 | fb0eaffc | bellard | RETURN(); |
108 | fb0eaffc | bellard | } |
109 | fb0eaffc | bellard | #else
|
110 | fb0eaffc | bellard | void OPPROTO glue(op_store_T0_fpscr_fpscr, REG)(void) |
111 | fb0eaffc | bellard | { |
112 | fb0eaffc | bellard | regs->fpscr[REG] = T0; |
113 | fb0eaffc | bellard | RETURN(); |
114 | fb0eaffc | bellard | } |
115 | fb0eaffc | bellard | |
116 | fb0eaffc | bellard | void OPPROTO glue(op_store_T0_fpscri_fpscr, REG)(void) |
117 | fb0eaffc | bellard | { |
118 | fb0eaffc | bellard | regs->fpscr[REG] = PARAM(1);
|
119 | fb0eaffc | bellard | RETURN(); |
120 | fb0eaffc | bellard | } |
121 | fb0eaffc | bellard | |
122 | fb0eaffc | bellard | void OPPROTO glue(op_clear_fpscr_fpscr, REG)(void) |
123 | fb0eaffc | bellard | { |
124 | fb0eaffc | bellard | regs->fpscr[REG] = 0x0;
|
125 | fb0eaffc | bellard | RETURN(); |
126 | fb0eaffc | bellard | } |
127 | fb0eaffc | bellard | #endif
|
128 | fb0eaffc | bellard | |
129 | 28b6751f | bellard | #endif /* REG <= 7 */ |
130 | 28b6751f | bellard | |
131 | fb0eaffc | bellard | /* floating point registers moves */
|
132 | fb0eaffc | bellard | void OPPROTO glue(op_load_fpr_FT0_fpr, REG)(void) |
133 | 28b6751f | bellard | { |
134 | 28b6751f | bellard | FT0 = env->fpr[REG]; |
135 | fb0eaffc | bellard | RETURN(); |
136 | 28b6751f | bellard | } |
137 | 28b6751f | bellard | |
138 | fb0eaffc | bellard | void OPPROTO glue(op_store_FT0_fpr_fpr, REG)(void) |
139 | 28b6751f | bellard | { |
140 | 28b6751f | bellard | env->fpr[REG] = FT0; |
141 | fb0eaffc | bellard | RETURN(); |
142 | fb0eaffc | bellard | } |
143 | fb0eaffc | bellard | |
144 | fb0eaffc | bellard | void OPPROTO glue(op_load_fpr_FT1_fpr, REG)(void) |
145 | fb0eaffc | bellard | { |
146 | fb0eaffc | bellard | FT1 = env->fpr[REG]; |
147 | fb0eaffc | bellard | RETURN(); |
148 | fb0eaffc | bellard | } |
149 | fb0eaffc | bellard | |
150 | fb0eaffc | bellard | void OPPROTO glue(op_store_FT1_fpr_fpr, REG)(void) |
151 | fb0eaffc | bellard | { |
152 | fb0eaffc | bellard | env->fpr[REG] = FT1; |
153 | fb0eaffc | bellard | RETURN(); |
154 | fb0eaffc | bellard | } |
155 | fb0eaffc | bellard | |
156 | fb0eaffc | bellard | void OPPROTO glue(op_load_fpr_FT2_fpr, REG)(void) |
157 | fb0eaffc | bellard | { |
158 | fb0eaffc | bellard | FT2 = env->fpr[REG]; |
159 | fb0eaffc | bellard | RETURN(); |
160 | fb0eaffc | bellard | } |
161 | fb0eaffc | bellard | |
162 | fb0eaffc | bellard | void OPPROTO glue(op_store_FT2_fpr_fpr, REG)(void) |
163 | fb0eaffc | bellard | { |
164 | fb0eaffc | bellard | env->fpr[REG] = FT2; |
165 | fb0eaffc | bellard | RETURN(); |
166 | 28b6751f | bellard | } |
167 | 28b6751f | bellard | |
168 | 9a64fbe4 | bellard | #if REG <= 15 |
169 | 9a64fbe4 | bellard | /* Segment register moves */
|
170 | 9a64fbe4 | bellard | void OPPROTO glue(op_load_sr, REG)(void) |
171 | 9a64fbe4 | bellard | { |
172 | 9a64fbe4 | bellard | T0 = env->sr[REG]; |
173 | 9a64fbe4 | bellard | RETURN(); |
174 | 9a64fbe4 | bellard | } |
175 | 9a64fbe4 | bellard | |
176 | 9a64fbe4 | bellard | void OPPROTO glue(op_store_sr, REG)(void) |
177 | 9a64fbe4 | bellard | { |
178 | 9a64fbe4 | bellard | #if defined (DEBUG_OP)
|
179 | 9a64fbe4 | bellard | dump_store_sr(REG); |
180 | 9a64fbe4 | bellard | #endif
|
181 | 9a64fbe4 | bellard | env->sr[REG] = T0; |
182 | 9a64fbe4 | bellard | RETURN(); |
183 | 9a64fbe4 | bellard | } |
184 | 9a64fbe4 | bellard | #endif
|
185 | 9a64fbe4 | bellard | |
186 | 28b6751f | bellard | #undef REG |