root / hw / axis_dev88.c @ fbe1b595
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1 | 10c144e2 | edgar_igl | /*
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2 | 10c144e2 | edgar_igl | * QEMU model for the AXIS devboard 88.
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3 | 10c144e2 | edgar_igl | *
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4 | 10c144e2 | edgar_igl | * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
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5 | 10c144e2 | edgar_igl | *
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6 | 10c144e2 | edgar_igl | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 10c144e2 | edgar_igl | * of this software and associated documentation files (the "Software"), to deal
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8 | 10c144e2 | edgar_igl | * in the Software without restriction, including without limitation the rights
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9 | 10c144e2 | edgar_igl | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 10c144e2 | edgar_igl | * copies of the Software, and to permit persons to whom the Software is
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11 | 10c144e2 | edgar_igl | * furnished to do so, subject to the following conditions:
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12 | 10c144e2 | edgar_igl | *
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13 | 10c144e2 | edgar_igl | * The above copyright notice and this permission notice shall be included in
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14 | 10c144e2 | edgar_igl | * all copies or substantial portions of the Software.
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15 | 10c144e2 | edgar_igl | *
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16 | 10c144e2 | edgar_igl | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 10c144e2 | edgar_igl | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 10c144e2 | edgar_igl | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 10c144e2 | edgar_igl | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 10c144e2 | edgar_igl | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 10c144e2 | edgar_igl | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 10c144e2 | edgar_igl | * THE SOFTWARE.
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23 | 10c144e2 | edgar_igl | */
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24 | 10c144e2 | edgar_igl | #include <time.h> |
25 | 10c144e2 | edgar_igl | #include <sys/time.h> |
26 | 10c144e2 | edgar_igl | #include "hw.h" |
27 | 10c144e2 | edgar_igl | #include "net.h" |
28 | 10c144e2 | edgar_igl | #include "flash.h" |
29 | 10c144e2 | edgar_igl | #include "sysemu.h" |
30 | 10c144e2 | edgar_igl | #include "devices.h" |
31 | 10c144e2 | edgar_igl | #include "boards.h" |
32 | 10c144e2 | edgar_igl | |
33 | 10c144e2 | edgar_igl | #include "etraxfs.h" |
34 | 10c144e2 | edgar_igl | |
35 | 10c144e2 | edgar_igl | #define D(x)
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36 | 10c144e2 | edgar_igl | #define DNAND(x)
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37 | 10c144e2 | edgar_igl | |
38 | 10c144e2 | edgar_igl | struct nand_state_t
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39 | 10c144e2 | edgar_igl | { |
40 | bc24a225 | Paul Brook | NANDFlashState *nand; |
41 | 10c144e2 | edgar_igl | unsigned int rdy:1; |
42 | 10c144e2 | edgar_igl | unsigned int ale:1; |
43 | 10c144e2 | edgar_igl | unsigned int cle:1; |
44 | 10c144e2 | edgar_igl | unsigned int ce:1; |
45 | 10c144e2 | edgar_igl | }; |
46 | 10c144e2 | edgar_igl | |
47 | 10c144e2 | edgar_igl | static struct nand_state_t nand_state; |
48 | 10c144e2 | edgar_igl | static uint32_t nand_readl (void *opaque, target_phys_addr_t addr) |
49 | 10c144e2 | edgar_igl | { |
50 | 10c144e2 | edgar_igl | struct nand_state_t *s = opaque;
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51 | 10c144e2 | edgar_igl | uint32_t r; |
52 | 10c144e2 | edgar_igl | int rdy;
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53 | 10c144e2 | edgar_igl | |
54 | 10c144e2 | edgar_igl | r = nand_getio(s->nand); |
55 | 10c144e2 | edgar_igl | nand_getpins(s->nand, &rdy); |
56 | 10c144e2 | edgar_igl | s->rdy = rdy; |
57 | 10c144e2 | edgar_igl | |
58 | 10c144e2 | edgar_igl | DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
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59 | 10c144e2 | edgar_igl | return r;
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60 | 10c144e2 | edgar_igl | } |
61 | 10c144e2 | edgar_igl | |
62 | 10c144e2 | edgar_igl | static void |
63 | 10c144e2 | edgar_igl | nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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64 | 10c144e2 | edgar_igl | { |
65 | 10c144e2 | edgar_igl | struct nand_state_t *s = opaque;
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66 | 10c144e2 | edgar_igl | int rdy;
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67 | 10c144e2 | edgar_igl | |
68 | 10c144e2 | edgar_igl | DNAND(printf("%s addr=%x v=%x\n", __func__, addr, value));
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69 | 10c144e2 | edgar_igl | nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0); |
70 | 10c144e2 | edgar_igl | nand_setio(s->nand, value); |
71 | 10c144e2 | edgar_igl | nand_getpins(s->nand, &rdy); |
72 | 10c144e2 | edgar_igl | s->rdy = rdy; |
73 | 10c144e2 | edgar_igl | } |
74 | 10c144e2 | edgar_igl | |
75 | 10c144e2 | edgar_igl | static CPUReadMemoryFunc *nand_read[] = {
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76 | 10c144e2 | edgar_igl | &nand_readl, |
77 | 10c144e2 | edgar_igl | &nand_readl, |
78 | 10c144e2 | edgar_igl | &nand_readl, |
79 | 10c144e2 | edgar_igl | }; |
80 | 10c144e2 | edgar_igl | |
81 | 10c144e2 | edgar_igl | static CPUWriteMemoryFunc *nand_write[] = {
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82 | 10c144e2 | edgar_igl | &nand_writel, |
83 | 10c144e2 | edgar_igl | &nand_writel, |
84 | 10c144e2 | edgar_igl | &nand_writel, |
85 | 10c144e2 | edgar_igl | }; |
86 | 10c144e2 | edgar_igl | |
87 | 4a1e6bea | edgar_igl | |
88 | 4a1e6bea | edgar_igl | struct tempsensor_t
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89 | 4a1e6bea | edgar_igl | { |
90 | 4a1e6bea | edgar_igl | unsigned int shiftreg; |
91 | 4a1e6bea | edgar_igl | unsigned int count; |
92 | 4a1e6bea | edgar_igl | enum {
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93 | 4a1e6bea | edgar_igl | ST_OUT, ST_IN, ST_Z |
94 | 4a1e6bea | edgar_igl | } state; |
95 | 4a1e6bea | edgar_igl | |
96 | 4a1e6bea | edgar_igl | uint16_t regs[3];
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97 | 4a1e6bea | edgar_igl | }; |
98 | 4a1e6bea | edgar_igl | |
99 | 4a1e6bea | edgar_igl | static void tempsensor_clkedge(struct tempsensor_t *s, |
100 | 4a1e6bea | edgar_igl | unsigned int clk, unsigned int data_in) |
101 | 4a1e6bea | edgar_igl | { |
102 | 4a1e6bea | edgar_igl | D(printf("%s clk=%d state=%d sr=%x\n", __func__,
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103 | 4a1e6bea | edgar_igl | clk, s->state, s->shiftreg)); |
104 | 4a1e6bea | edgar_igl | if (s->count == 0) { |
105 | 4a1e6bea | edgar_igl | s->count = 16;
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106 | 4a1e6bea | edgar_igl | s->state = ST_OUT; |
107 | 4a1e6bea | edgar_igl | } |
108 | 4a1e6bea | edgar_igl | switch (s->state) {
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109 | 4a1e6bea | edgar_igl | case ST_OUT:
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110 | 4a1e6bea | edgar_igl | /* Output reg is clocked at negedge. */
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111 | 4a1e6bea | edgar_igl | if (!clk) {
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112 | 4a1e6bea | edgar_igl | s->count--; |
113 | 4a1e6bea | edgar_igl | s->shiftreg <<= 1;
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114 | 4a1e6bea | edgar_igl | if (s->count == 0) { |
115 | 4a1e6bea | edgar_igl | s->shiftreg = 0;
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116 | 4a1e6bea | edgar_igl | s->state = ST_IN; |
117 | 4a1e6bea | edgar_igl | s->count = 16;
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118 | 4a1e6bea | edgar_igl | } |
119 | 4a1e6bea | edgar_igl | } |
120 | 4a1e6bea | edgar_igl | break;
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121 | 4a1e6bea | edgar_igl | case ST_Z:
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122 | 4a1e6bea | edgar_igl | if (clk) {
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123 | 4a1e6bea | edgar_igl | s->count--; |
124 | 4a1e6bea | edgar_igl | if (s->count == 0) { |
125 | 4a1e6bea | edgar_igl | s->shiftreg = 0;
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126 | 4a1e6bea | edgar_igl | s->state = ST_OUT; |
127 | 4a1e6bea | edgar_igl | s->count = 16;
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128 | 4a1e6bea | edgar_igl | } |
129 | 4a1e6bea | edgar_igl | } |
130 | 4a1e6bea | edgar_igl | break;
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131 | 4a1e6bea | edgar_igl | case ST_IN:
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132 | 4a1e6bea | edgar_igl | /* Indata is sampled at posedge. */
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133 | 4a1e6bea | edgar_igl | if (clk) {
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134 | 4a1e6bea | edgar_igl | s->count--; |
135 | 4a1e6bea | edgar_igl | s->shiftreg <<= 1;
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136 | 4a1e6bea | edgar_igl | s->shiftreg |= data_in & 1;
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137 | 4a1e6bea | edgar_igl | if (s->count == 0) { |
138 | 4a1e6bea | edgar_igl | D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
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139 | 4a1e6bea | edgar_igl | s->regs[0] = s->shiftreg;
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140 | 4a1e6bea | edgar_igl | s->state = ST_OUT; |
141 | 4a1e6bea | edgar_igl | s->count = 16;
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142 | 4a1e6bea | edgar_igl | |
143 | 4a1e6bea | edgar_igl | if ((s->regs[0] & 0xff) == 0) { |
144 | 4a1e6bea | edgar_igl | /* 25 degrees celcius. */
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145 | 4a1e6bea | edgar_igl | s->shiftreg = 0x0b9f;
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146 | 4a1e6bea | edgar_igl | } else if ((s->regs[0] & 0xff) == 0xff) { |
147 | 4a1e6bea | edgar_igl | /* Sensor ID, 0x8100 LM70. */
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148 | 4a1e6bea | edgar_igl | s->shiftreg = 0x8100;
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149 | 4a1e6bea | edgar_igl | } else
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150 | 4a1e6bea | edgar_igl | printf("Invalid tempsens state %x\n", s->regs[0]); |
151 | 4a1e6bea | edgar_igl | } |
152 | 4a1e6bea | edgar_igl | } |
153 | 4a1e6bea | edgar_igl | break;
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154 | 4a1e6bea | edgar_igl | } |
155 | 4a1e6bea | edgar_igl | } |
156 | 4a1e6bea | edgar_igl | |
157 | 4a1e6bea | edgar_igl | |
158 | 4a1e6bea | edgar_igl | #define RW_PA_DOUT 0x00 |
159 | 4a1e6bea | edgar_igl | #define R_PA_DIN 0x01 |
160 | 4a1e6bea | edgar_igl | #define RW_PA_OE 0x02 |
161 | 4a1e6bea | edgar_igl | #define RW_PD_DOUT 0x10 |
162 | 4a1e6bea | edgar_igl | #define R_PD_DIN 0x11 |
163 | 4a1e6bea | edgar_igl | #define RW_PD_OE 0x12 |
164 | 4a1e6bea | edgar_igl | |
165 | 4a1e6bea | edgar_igl | static struct gpio_state_t |
166 | 10c144e2 | edgar_igl | { |
167 | 10c144e2 | edgar_igl | struct nand_state_t *nand;
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168 | 4a1e6bea | edgar_igl | struct tempsensor_t tempsensor;
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169 | 10c144e2 | edgar_igl | uint32_t regs[0x5c / 4]; |
170 | 10c144e2 | edgar_igl | } gpio_state; |
171 | 10c144e2 | edgar_igl | |
172 | 10c144e2 | edgar_igl | static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr) |
173 | 10c144e2 | edgar_igl | { |
174 | 10c144e2 | edgar_igl | struct gpio_state_t *s = opaque;
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175 | 10c144e2 | edgar_igl | uint32_t r = 0;
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176 | 10c144e2 | edgar_igl | |
177 | 10c144e2 | edgar_igl | addr >>= 2;
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178 | 10c144e2 | edgar_igl | switch (addr)
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179 | 10c144e2 | edgar_igl | { |
180 | 10c144e2 | edgar_igl | case R_PA_DIN:
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181 | 10c144e2 | edgar_igl | r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE]; |
182 | 10c144e2 | edgar_igl | |
183 | 10c144e2 | edgar_igl | /* Encode pins from the nand. */
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184 | 10c144e2 | edgar_igl | r |= s->nand->rdy << 7;
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185 | 10c144e2 | edgar_igl | break;
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186 | 4a1e6bea | edgar_igl | case R_PD_DIN:
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187 | 4a1e6bea | edgar_igl | r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE]; |
188 | 4a1e6bea | edgar_igl | |
189 | 4a1e6bea | edgar_igl | /* Encode temp sensor pins. */
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190 | 4a1e6bea | edgar_igl | r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4; |
191 | 4a1e6bea | edgar_igl | break;
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192 | 4a1e6bea | edgar_igl | |
193 | 10c144e2 | edgar_igl | default:
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194 | 10c144e2 | edgar_igl | r = s->regs[addr]; |
195 | 10c144e2 | edgar_igl | break;
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196 | 10c144e2 | edgar_igl | } |
197 | 10c144e2 | edgar_igl | return r;
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198 | 10c144e2 | edgar_igl | D(printf("%s %x=%x\n", __func__, addr, r));
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199 | 10c144e2 | edgar_igl | } |
200 | 10c144e2 | edgar_igl | |
201 | 10c144e2 | edgar_igl | static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
202 | 10c144e2 | edgar_igl | { |
203 | 10c144e2 | edgar_igl | struct gpio_state_t *s = opaque;
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204 | 10c144e2 | edgar_igl | D(printf("%s %x=%x\n", __func__, addr, value));
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205 | 10c144e2 | edgar_igl | |
206 | 10c144e2 | edgar_igl | addr >>= 2;
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207 | 10c144e2 | edgar_igl | switch (addr)
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208 | 10c144e2 | edgar_igl | { |
209 | 10c144e2 | edgar_igl | case RW_PA_DOUT:
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210 | 10c144e2 | edgar_igl | /* Decode nand pins. */
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211 | 10c144e2 | edgar_igl | s->nand->ale = !!(value & (1 << 6)); |
212 | 10c144e2 | edgar_igl | s->nand->cle = !!(value & (1 << 5)); |
213 | 10c144e2 | edgar_igl | s->nand->ce = !!(value & (1 << 4)); |
214 | 10c144e2 | edgar_igl | |
215 | 10c144e2 | edgar_igl | s->regs[addr] = value; |
216 | 10c144e2 | edgar_igl | break;
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217 | 4a1e6bea | edgar_igl | |
218 | 4a1e6bea | edgar_igl | case RW_PD_DOUT:
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219 | 4a1e6bea | edgar_igl | /* Temp sensor clk. */
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220 | 4a1e6bea | edgar_igl | if ((s->regs[addr] ^ value) & 2) |
221 | 4a1e6bea | edgar_igl | tempsensor_clkedge(&s->tempsensor, !!(value & 2),
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222 | 4a1e6bea | edgar_igl | !!(value & 16));
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223 | 4a1e6bea | edgar_igl | s->regs[addr] = value; |
224 | 4a1e6bea | edgar_igl | break;
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225 | 4a1e6bea | edgar_igl | |
226 | 10c144e2 | edgar_igl | default:
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227 | 10c144e2 | edgar_igl | s->regs[addr] = value; |
228 | 10c144e2 | edgar_igl | break;
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229 | 10c144e2 | edgar_igl | } |
230 | 10c144e2 | edgar_igl | } |
231 | 10c144e2 | edgar_igl | |
232 | 10c144e2 | edgar_igl | static CPUReadMemoryFunc *gpio_read[] = {
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233 | 10c144e2 | edgar_igl | NULL, NULL, |
234 | 10c144e2 | edgar_igl | &gpio_readl, |
235 | 10c144e2 | edgar_igl | }; |
236 | 10c144e2 | edgar_igl | |
237 | 10c144e2 | edgar_igl | static CPUWriteMemoryFunc *gpio_write[] = {
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238 | 10c144e2 | edgar_igl | NULL, NULL, |
239 | 10c144e2 | edgar_igl | &gpio_writel, |
240 | 10c144e2 | edgar_igl | }; |
241 | 10c144e2 | edgar_igl | |
242 | 10c144e2 | edgar_igl | #define INTMEM_SIZE (128 * 1024) |
243 | 10c144e2 | edgar_igl | |
244 | 10c144e2 | edgar_igl | static uint32_t bootstrap_pc;
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245 | 10c144e2 | edgar_igl | static void main_cpu_reset(void *opaque) |
246 | 10c144e2 | edgar_igl | { |
247 | 10c144e2 | edgar_igl | CPUState *env = opaque; |
248 | 10c144e2 | edgar_igl | cpu_reset(env); |
249 | 10c144e2 | edgar_igl | |
250 | 10c144e2 | edgar_igl | env->pc = bootstrap_pc; |
251 | 10c144e2 | edgar_igl | } |
252 | 10c144e2 | edgar_igl | |
253 | 10c144e2 | edgar_igl | static
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254 | fbe1b595 | Paul Brook | void axisdev88_init (ram_addr_t ram_size,
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255 | ef998233 | edgar_igl | const char *boot_device, |
256 | 10c144e2 | edgar_igl | const char *kernel_filename, const char *kernel_cmdline, |
257 | 10c144e2 | edgar_igl | const char *initrd_filename, const char *cpu_model) |
258 | 10c144e2 | edgar_igl | { |
259 | 10c144e2 | edgar_igl | CPUState *env; |
260 | 10c144e2 | edgar_igl | struct etraxfs_pic *pic;
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261 | 10c144e2 | edgar_igl | void *etraxfs_dmac;
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262 | 10c144e2 | edgar_igl | struct etraxfs_dma_client *eth[2] = {NULL, NULL}; |
263 | 10c144e2 | edgar_igl | int kernel_size;
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264 | 10c144e2 | edgar_igl | int i;
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265 | 10c144e2 | edgar_igl | int nand_regs;
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266 | 10c144e2 | edgar_igl | int gpio_regs;
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267 | 10c144e2 | edgar_igl | ram_addr_t phys_ram; |
268 | 10c144e2 | edgar_igl | ram_addr_t phys_intmem; |
269 | 10c144e2 | edgar_igl | |
270 | 10c144e2 | edgar_igl | /* init CPUs */
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271 | 10c144e2 | edgar_igl | if (cpu_model == NULL) { |
272 | 10c144e2 | edgar_igl | cpu_model = "crisv32";
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273 | 10c144e2 | edgar_igl | } |
274 | 10c144e2 | edgar_igl | env = cpu_init(cpu_model); |
275 | 10c144e2 | edgar_igl | qemu_register_reset(main_cpu_reset, env); |
276 | 10c144e2 | edgar_igl | |
277 | 10c144e2 | edgar_igl | /* allocate RAM */
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278 | 10c144e2 | edgar_igl | phys_ram = qemu_ram_alloc(ram_size); |
279 | 10c144e2 | edgar_igl | cpu_register_physical_memory(0x40000000, ram_size, phys_ram | IO_MEM_RAM);
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280 | 10c144e2 | edgar_igl | |
281 | 10c144e2 | edgar_igl | /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
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282 | 10c144e2 | edgar_igl | internal memory. */
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283 | 10c144e2 | edgar_igl | phys_intmem = qemu_ram_alloc(INTMEM_SIZE); |
284 | 10c144e2 | edgar_igl | cpu_register_physical_memory(0x38000000, INTMEM_SIZE,
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285 | 10c144e2 | edgar_igl | phys_intmem | IO_MEM_RAM); |
286 | 10c144e2 | edgar_igl | |
287 | 10c144e2 | edgar_igl | |
288 | 10c144e2 | edgar_igl | /* Attach a NAND flash to CS1. */
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289 | 4a1e6bea | edgar_igl | nand_state.nand = nand_init(NAND_MFR_STMICRO, 0x39);
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290 | 10c144e2 | edgar_igl | nand_regs = cpu_register_io_memory(0, nand_read, nand_write, &nand_state);
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291 | 10c144e2 | edgar_igl | cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs); |
292 | 10c144e2 | edgar_igl | |
293 | 10c144e2 | edgar_igl | gpio_state.nand = &nand_state; |
294 | 10c144e2 | edgar_igl | gpio_regs = cpu_register_io_memory(0, gpio_read, gpio_write, &gpio_state);
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295 | 4a1e6bea | edgar_igl | cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs); |
296 | 10c144e2 | edgar_igl | |
297 | 10c144e2 | edgar_igl | |
298 | 10c144e2 | edgar_igl | pic = etraxfs_pic_init(env, 0x3001c000);
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299 | 10c144e2 | edgar_igl | etraxfs_dmac = etraxfs_dmac_init(env, 0x30000000, 10); |
300 | 10c144e2 | edgar_igl | for (i = 0; i < 10; i++) { |
301 | 10c144e2 | edgar_igl | /* On ETRAX, odd numbered channels are inputs. */
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302 | 10c144e2 | edgar_igl | etraxfs_dmac_connect(etraxfs_dmac, i, pic->irq + 7 + i, i & 1); |
303 | 10c144e2 | edgar_igl | } |
304 | 10c144e2 | edgar_igl | |
305 | 10c144e2 | edgar_igl | /* Add the two ethernet blocks. */
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306 | 94410b78 | edgar_igl | eth[0] = etraxfs_eth_init(&nd_table[0], env, pic->irq + 25, 0x30034000, 1); |
307 | 0ae18cee | aliguori | if (nb_nics > 1) |
308 | 94410b78 | edgar_igl | eth[1] = etraxfs_eth_init(&nd_table[1], env, |
309 | 94410b78 | edgar_igl | pic->irq + 26, 0x30036000, 2); |
310 | 10c144e2 | edgar_igl | |
311 | 10c144e2 | edgar_igl | /* The DMA Connector block is missing, hardwire things for now. */
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312 | 10c144e2 | edgar_igl | etraxfs_dmac_connect_client(etraxfs_dmac, 0, eth[0]); |
313 | 10c144e2 | edgar_igl | etraxfs_dmac_connect_client(etraxfs_dmac, 1, eth[0] + 1); |
314 | 10c144e2 | edgar_igl | if (eth[1]) { |
315 | 10c144e2 | edgar_igl | etraxfs_dmac_connect_client(etraxfs_dmac, 6, eth[1]); |
316 | 10c144e2 | edgar_igl | etraxfs_dmac_connect_client(etraxfs_dmac, 7, eth[1] + 1); |
317 | 10c144e2 | edgar_igl | } |
318 | 10c144e2 | edgar_igl | |
319 | 10c144e2 | edgar_igl | /* 2 timers. */
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320 | 10c144e2 | edgar_igl | etraxfs_timer_init(env, pic->irq + 0x1b, pic->nmi + 1, 0x3001e000); |
321 | 10c144e2 | edgar_igl | etraxfs_timer_init(env, pic->irq + 0x1b, pic->nmi + 1, 0x3005e000); |
322 | 10c144e2 | edgar_igl | |
323 | 10c144e2 | edgar_igl | for (i = 0; i < 4; i++) { |
324 | 10c144e2 | edgar_igl | if (serial_hds[i]) {
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325 | 10c144e2 | edgar_igl | etraxfs_ser_init(env, pic->irq + 0x14 + i,
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326 | 10c144e2 | edgar_igl | serial_hds[i], 0x30026000 + i * 0x2000); |
327 | 10c144e2 | edgar_igl | } |
328 | 10c144e2 | edgar_igl | } |
329 | 10c144e2 | edgar_igl | |
330 | 10c144e2 | edgar_igl | if (kernel_filename) {
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331 | 10c144e2 | edgar_igl | uint64_t entry, high; |
332 | 10c144e2 | edgar_igl | int kcmdline_len;
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333 | 10c144e2 | edgar_igl | |
334 | 10c144e2 | edgar_igl | /* Boots a kernel elf binary, os/linux-2.6/vmlinux from the axis
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335 | 10c144e2 | edgar_igl | devboard SDK. */
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336 | 10c144e2 | edgar_igl | kernel_size = load_elf(kernel_filename, -0x80000000LL,
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337 | 10c144e2 | edgar_igl | &entry, NULL, &high);
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338 | 10c144e2 | edgar_igl | bootstrap_pc = entry; |
339 | 10c144e2 | edgar_igl | if (kernel_size < 0) { |
340 | 10c144e2 | edgar_igl | /* Takes a kimage from the axis devboard SDK. */
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341 | dcac9679 | pbrook | kernel_size = load_image_targphys(kernel_filename, 0x40004000,
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342 | dcac9679 | pbrook | ram_size); |
343 | 10c144e2 | edgar_igl | bootstrap_pc = 0x40004000;
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344 | 10c144e2 | edgar_igl | env->regs[9] = 0x40004000 + kernel_size; |
345 | 10c144e2 | edgar_igl | } |
346 | 10c144e2 | edgar_igl | env->regs[8] = 0x56902387; /* RAM init magic. */ |
347 | 10c144e2 | edgar_igl | |
348 | 10c144e2 | edgar_igl | if (kernel_cmdline && (kcmdline_len = strlen(kernel_cmdline))) {
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349 | 10c144e2 | edgar_igl | if (kcmdline_len > 256) { |
350 | 10c144e2 | edgar_igl | fprintf(stderr, "Too long CRIS kernel cmdline (max 256)\n");
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351 | 10c144e2 | edgar_igl | exit(1);
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352 | 10c144e2 | edgar_igl | } |
353 | 10c144e2 | edgar_igl | pstrcpy_targphys(high, 256, kernel_cmdline);
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354 | 10c144e2 | edgar_igl | /* Let the kernel know we are modifying the cmdline. */
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355 | 10c144e2 | edgar_igl | env->regs[10] = 0x87109563; |
356 | 10c144e2 | edgar_igl | env->regs[11] = high;
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357 | 10c144e2 | edgar_igl | } |
358 | 10c144e2 | edgar_igl | } |
359 | 10c144e2 | edgar_igl | env->pc = bootstrap_pc; |
360 | 10c144e2 | edgar_igl | |
361 | 10c144e2 | edgar_igl | printf ("pc =%x\n", env->pc);
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362 | 10c144e2 | edgar_igl | printf ("ram size =%ld\n", ram_size);
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363 | 10c144e2 | edgar_igl | } |
364 | 10c144e2 | edgar_igl | |
365 | 10c144e2 | edgar_igl | QEMUMachine axisdev88_machine = { |
366 | 10c144e2 | edgar_igl | .name = "axis-dev88",
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367 | 10c144e2 | edgar_igl | .desc = "AXIS devboard 88",
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368 | 10c144e2 | edgar_igl | .init = axisdev88_init, |
369 | 10c144e2 | edgar_igl | }; |