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1 | 24859b68 | balrog | /*
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2 | 24859b68 | balrog | * Marvell MV88W8618 / Freecom MusicPal emulation.
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3 | 24859b68 | balrog | *
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4 | 24859b68 | balrog | * Copyright (c) 2008 Jan Kiszka
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5 | 24859b68 | balrog | *
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6 | 24859b68 | balrog | * This code is licenced under the GNU GPL v2.
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7 | 24859b68 | balrog | */
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8 | 24859b68 | balrog | |
9 | 24859b68 | balrog | #include "hw.h" |
10 | 24859b68 | balrog | #include "arm-misc.h" |
11 | 24859b68 | balrog | #include "devices.h" |
12 | 24859b68 | balrog | #include "net.h" |
13 | 24859b68 | balrog | #include "sysemu.h" |
14 | 24859b68 | balrog | #include "boards.h" |
15 | 24859b68 | balrog | #include "pc.h" |
16 | 24859b68 | balrog | #include "qemu-timer.h" |
17 | 24859b68 | balrog | #include "block.h" |
18 | 24859b68 | balrog | #include "flash.h" |
19 | 24859b68 | balrog | #include "console.h" |
20 | 24859b68 | balrog | #include "audio/audio.h" |
21 | 24859b68 | balrog | #include "i2c.h" |
22 | 24859b68 | balrog | |
23 | 718ec0be | malc | #define MP_MISC_BASE 0x80002000 |
24 | 718ec0be | malc | #define MP_MISC_SIZE 0x00001000 |
25 | 718ec0be | malc | |
26 | 24859b68 | balrog | #define MP_ETH_BASE 0x80008000 |
27 | 24859b68 | balrog | #define MP_ETH_SIZE 0x00001000 |
28 | 24859b68 | balrog | |
29 | 718ec0be | malc | #define MP_WLAN_BASE 0x8000C000 |
30 | 718ec0be | malc | #define MP_WLAN_SIZE 0x00000800 |
31 | 718ec0be | malc | |
32 | 24859b68 | balrog | #define MP_UART1_BASE 0x8000C840 |
33 | 24859b68 | balrog | #define MP_UART2_BASE 0x8000C940 |
34 | 24859b68 | balrog | |
35 | 718ec0be | malc | #define MP_GPIO_BASE 0x8000D000 |
36 | 718ec0be | malc | #define MP_GPIO_SIZE 0x00001000 |
37 | 718ec0be | malc | |
38 | 24859b68 | balrog | #define MP_FLASHCFG_BASE 0x90006000 |
39 | 24859b68 | balrog | #define MP_FLASHCFG_SIZE 0x00001000 |
40 | 24859b68 | balrog | |
41 | 24859b68 | balrog | #define MP_AUDIO_BASE 0x90007000 |
42 | 24859b68 | balrog | #define MP_AUDIO_SIZE 0x00001000 |
43 | 24859b68 | balrog | |
44 | 24859b68 | balrog | #define MP_PIC_BASE 0x90008000 |
45 | 24859b68 | balrog | #define MP_PIC_SIZE 0x00001000 |
46 | 24859b68 | balrog | |
47 | 24859b68 | balrog | #define MP_PIT_BASE 0x90009000 |
48 | 24859b68 | balrog | #define MP_PIT_SIZE 0x00001000 |
49 | 24859b68 | balrog | |
50 | 24859b68 | balrog | #define MP_LCD_BASE 0x9000c000 |
51 | 24859b68 | balrog | #define MP_LCD_SIZE 0x00001000 |
52 | 24859b68 | balrog | |
53 | 24859b68 | balrog | #define MP_SRAM_BASE 0xC0000000 |
54 | 24859b68 | balrog | #define MP_SRAM_SIZE 0x00020000 |
55 | 24859b68 | balrog | |
56 | 24859b68 | balrog | #define MP_RAM_DEFAULT_SIZE 32*1024*1024 |
57 | 24859b68 | balrog | #define MP_FLASH_SIZE_MAX 32*1024*1024 |
58 | 24859b68 | balrog | |
59 | 24859b68 | balrog | #define MP_TIMER1_IRQ 4 |
60 | 24859b68 | balrog | /* ... */
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61 | 24859b68 | balrog | #define MP_TIMER4_IRQ 7 |
62 | 24859b68 | balrog | #define MP_EHCI_IRQ 8 |
63 | 24859b68 | balrog | #define MP_ETH_IRQ 9 |
64 | 24859b68 | balrog | #define MP_UART1_IRQ 11 |
65 | 24859b68 | balrog | #define MP_UART2_IRQ 11 |
66 | 24859b68 | balrog | #define MP_GPIO_IRQ 12 |
67 | 24859b68 | balrog | #define MP_RTC_IRQ 28 |
68 | 24859b68 | balrog | #define MP_AUDIO_IRQ 30 |
69 | 24859b68 | balrog | |
70 | 24859b68 | balrog | static uint32_t gpio_in_state = 0xffffffff; |
71 | 7c6ce4ba | balrog | static uint32_t gpio_isr;
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72 | 24859b68 | balrog | static uint32_t gpio_out_state;
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73 | 24859b68 | balrog | static ram_addr_t sram_off;
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74 | 24859b68 | balrog | |
75 | 24859b68 | balrog | typedef enum i2c_state { |
76 | 24859b68 | balrog | STOPPED = 0,
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77 | 24859b68 | balrog | INITIALIZING, |
78 | 24859b68 | balrog | SENDING_BIT7, |
79 | 24859b68 | balrog | SENDING_BIT6, |
80 | 24859b68 | balrog | SENDING_BIT5, |
81 | 24859b68 | balrog | SENDING_BIT4, |
82 | 24859b68 | balrog | SENDING_BIT3, |
83 | 24859b68 | balrog | SENDING_BIT2, |
84 | 24859b68 | balrog | SENDING_BIT1, |
85 | 24859b68 | balrog | SENDING_BIT0, |
86 | 24859b68 | balrog | WAITING_FOR_ACK, |
87 | 24859b68 | balrog | RECEIVING_BIT7, |
88 | 24859b68 | balrog | RECEIVING_BIT6, |
89 | 24859b68 | balrog | RECEIVING_BIT5, |
90 | 24859b68 | balrog | RECEIVING_BIT4, |
91 | 24859b68 | balrog | RECEIVING_BIT3, |
92 | 24859b68 | balrog | RECEIVING_BIT2, |
93 | 24859b68 | balrog | RECEIVING_BIT1, |
94 | 24859b68 | balrog | RECEIVING_BIT0, |
95 | 24859b68 | balrog | SENDING_ACK |
96 | 24859b68 | balrog | } i2c_state; |
97 | 24859b68 | balrog | |
98 | 24859b68 | balrog | typedef struct i2c_interface { |
99 | 24859b68 | balrog | i2c_bus *bus; |
100 | 24859b68 | balrog | i2c_state state; |
101 | 24859b68 | balrog | int last_data;
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102 | 24859b68 | balrog | int last_clock;
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103 | 24859b68 | balrog | uint8_t buffer; |
104 | 24859b68 | balrog | int current_addr;
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105 | 24859b68 | balrog | } i2c_interface; |
106 | 24859b68 | balrog | |
107 | 24859b68 | balrog | static void i2c_enter_stop(i2c_interface *i2c) |
108 | 24859b68 | balrog | { |
109 | 24859b68 | balrog | if (i2c->current_addr >= 0) |
110 | 24859b68 | balrog | i2c_end_transfer(i2c->bus); |
111 | 24859b68 | balrog | i2c->current_addr = -1;
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112 | 24859b68 | balrog | i2c->state = STOPPED; |
113 | 24859b68 | balrog | } |
114 | 24859b68 | balrog | |
115 | 24859b68 | balrog | static void i2c_state_update(i2c_interface *i2c, int data, int clock) |
116 | 24859b68 | balrog | { |
117 | 24859b68 | balrog | if (!i2c)
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118 | 24859b68 | balrog | return;
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119 | 24859b68 | balrog | |
120 | 24859b68 | balrog | switch (i2c->state) {
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121 | 24859b68 | balrog | case STOPPED:
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122 | 24859b68 | balrog | if (data == 0 && i2c->last_data == 1 && clock == 1) |
123 | 24859b68 | balrog | i2c->state = INITIALIZING; |
124 | 24859b68 | balrog | break;
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125 | 24859b68 | balrog | |
126 | 24859b68 | balrog | case INITIALIZING:
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127 | 24859b68 | balrog | if (clock == 0 && i2c->last_clock == 1 && data == 0) |
128 | 24859b68 | balrog | i2c->state = SENDING_BIT7; |
129 | 24859b68 | balrog | else
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130 | 24859b68 | balrog | i2c_enter_stop(i2c); |
131 | 24859b68 | balrog | break;
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132 | 24859b68 | balrog | |
133 | 24859b68 | balrog | case SENDING_BIT7 ... SENDING_BIT0:
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134 | 24859b68 | balrog | if (clock == 0 && i2c->last_clock == 1) { |
135 | 24859b68 | balrog | i2c->buffer = (i2c->buffer << 1) | data;
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136 | 24859b68 | balrog | i2c->state++; /* will end up in WAITING_FOR_ACK */
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137 | 24859b68 | balrog | } else if (data == 1 && i2c->last_data == 0 && clock == 1) |
138 | 24859b68 | balrog | i2c_enter_stop(i2c); |
139 | 24859b68 | balrog | break;
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140 | 24859b68 | balrog | |
141 | 24859b68 | balrog | case WAITING_FOR_ACK:
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142 | 24859b68 | balrog | if (clock == 0 && i2c->last_clock == 1) { |
143 | 24859b68 | balrog | if (i2c->current_addr < 0) { |
144 | 24859b68 | balrog | i2c->current_addr = i2c->buffer; |
145 | 24859b68 | balrog | i2c_start_transfer(i2c->bus, i2c->current_addr & 0xfe,
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146 | 24859b68 | balrog | i2c->buffer & 1);
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147 | 24859b68 | balrog | } else
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148 | 24859b68 | balrog | i2c_send(i2c->bus, i2c->buffer); |
149 | 24859b68 | balrog | if (i2c->current_addr & 1) { |
150 | 24859b68 | balrog | i2c->state = RECEIVING_BIT7; |
151 | 24859b68 | balrog | i2c->buffer = i2c_recv(i2c->bus); |
152 | 24859b68 | balrog | } else
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153 | 24859b68 | balrog | i2c->state = SENDING_BIT7; |
154 | 24859b68 | balrog | } else if (data == 1 && i2c->last_data == 0 && clock == 1) |
155 | 24859b68 | balrog | i2c_enter_stop(i2c); |
156 | 24859b68 | balrog | break;
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157 | 24859b68 | balrog | |
158 | 24859b68 | balrog | case RECEIVING_BIT7 ... RECEIVING_BIT0:
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159 | 24859b68 | balrog | if (clock == 0 && i2c->last_clock == 1) { |
160 | 24859b68 | balrog | i2c->state++; /* will end up in SENDING_ACK */
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161 | 24859b68 | balrog | i2c->buffer <<= 1;
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162 | 24859b68 | balrog | } else if (data == 1 && i2c->last_data == 0 && clock == 1) |
163 | 24859b68 | balrog | i2c_enter_stop(i2c); |
164 | 24859b68 | balrog | break;
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165 | 24859b68 | balrog | |
166 | 24859b68 | balrog | case SENDING_ACK:
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167 | 24859b68 | balrog | if (clock == 0 && i2c->last_clock == 1) { |
168 | 24859b68 | balrog | i2c->state = RECEIVING_BIT7; |
169 | 24859b68 | balrog | if (data == 0) |
170 | 24859b68 | balrog | i2c->buffer = i2c_recv(i2c->bus); |
171 | 24859b68 | balrog | else
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172 | 24859b68 | balrog | i2c_nack(i2c->bus); |
173 | 24859b68 | balrog | } else if (data == 1 && i2c->last_data == 0 && clock == 1) |
174 | 24859b68 | balrog | i2c_enter_stop(i2c); |
175 | 24859b68 | balrog | break;
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176 | 24859b68 | balrog | } |
177 | 24859b68 | balrog | |
178 | 24859b68 | balrog | i2c->last_data = data; |
179 | 24859b68 | balrog | i2c->last_clock = clock; |
180 | 24859b68 | balrog | } |
181 | 24859b68 | balrog | |
182 | 24859b68 | balrog | static int i2c_get_data(i2c_interface *i2c) |
183 | 24859b68 | balrog | { |
184 | 24859b68 | balrog | if (!i2c)
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185 | 24859b68 | balrog | return 0; |
186 | 24859b68 | balrog | |
187 | 24859b68 | balrog | switch (i2c->state) {
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188 | 24859b68 | balrog | case RECEIVING_BIT7 ... RECEIVING_BIT0:
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189 | 24859b68 | balrog | return (i2c->buffer >> 7); |
190 | 24859b68 | balrog | |
191 | 24859b68 | balrog | case WAITING_FOR_ACK:
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192 | 24859b68 | balrog | default:
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193 | 24859b68 | balrog | return 0; |
194 | 24859b68 | balrog | } |
195 | 24859b68 | balrog | } |
196 | 24859b68 | balrog | |
197 | 24859b68 | balrog | static i2c_interface *mixer_i2c;
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198 | 24859b68 | balrog | |
199 | 24859b68 | balrog | #ifdef HAS_AUDIO
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200 | 24859b68 | balrog | |
201 | 24859b68 | balrog | /* Audio register offsets */
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202 | 24859b68 | balrog | #define MP_AUDIO_PLAYBACK_MODE 0x00 |
203 | 24859b68 | balrog | #define MP_AUDIO_CLOCK_DIV 0x18 |
204 | 24859b68 | balrog | #define MP_AUDIO_IRQ_STATUS 0x20 |
205 | 24859b68 | balrog | #define MP_AUDIO_IRQ_ENABLE 0x24 |
206 | 24859b68 | balrog | #define MP_AUDIO_TX_START_LO 0x28 |
207 | 24859b68 | balrog | #define MP_AUDIO_TX_THRESHOLD 0x2C |
208 | 24859b68 | balrog | #define MP_AUDIO_TX_STATUS 0x38 |
209 | 24859b68 | balrog | #define MP_AUDIO_TX_START_HI 0x40 |
210 | 24859b68 | balrog | |
211 | 24859b68 | balrog | /* Status register and IRQ enable bits */
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212 | 24859b68 | balrog | #define MP_AUDIO_TX_HALF (1 << 6) |
213 | 24859b68 | balrog | #define MP_AUDIO_TX_FULL (1 << 7) |
214 | 24859b68 | balrog | |
215 | 24859b68 | balrog | /* Playback mode bits */
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216 | 24859b68 | balrog | #define MP_AUDIO_16BIT_SAMPLE (1 << 0) |
217 | 24859b68 | balrog | #define MP_AUDIO_PLAYBACK_EN (1 << 7) |
218 | 24859b68 | balrog | #define MP_AUDIO_CLOCK_24MHZ (1 << 9) |
219 | 4001a81e | balrog | #define MP_AUDIO_MONO (1 << 14) |
220 | 24859b68 | balrog | |
221 | 24859b68 | balrog | /* Wolfson 8750 I2C address */
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222 | 24859b68 | balrog | #define MP_WM_ADDR 0x34 |
223 | 24859b68 | balrog | |
224 | b1d8e52e | blueswir1 | static const char audio_name[] = "mv88w8618"; |
225 | 24859b68 | balrog | |
226 | 24859b68 | balrog | typedef struct musicpal_audio_state { |
227 | 24859b68 | balrog | qemu_irq irq; |
228 | 24859b68 | balrog | uint32_t playback_mode; |
229 | 24859b68 | balrog | uint32_t status; |
230 | 24859b68 | balrog | uint32_t irq_enable; |
231 | 24859b68 | balrog | unsigned long phys_buf; |
232 | 930c8682 | pbrook | uint32_t target_buffer; |
233 | 24859b68 | balrog | unsigned int threshold; |
234 | 24859b68 | balrog | unsigned int play_pos; |
235 | 24859b68 | balrog | unsigned int last_free; |
236 | 24859b68 | balrog | uint32_t clock_div; |
237 | 24859b68 | balrog | i2c_slave *wm; |
238 | 24859b68 | balrog | } musicpal_audio_state; |
239 | 24859b68 | balrog | |
240 | 24859b68 | balrog | static void audio_callback(void *opaque, int free_out, int free_in) |
241 | 24859b68 | balrog | { |
242 | 24859b68 | balrog | musicpal_audio_state *s = opaque; |
243 | 4f3cb3be | balrog | int16_t *codec_buffer; |
244 | 930c8682 | pbrook | int8_t buf[4096];
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245 | a350e694 | balrog | int8_t *mem_buffer; |
246 | 24859b68 | balrog | int pos, block_size;
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247 | 24859b68 | balrog | |
248 | 24859b68 | balrog | if (!(s->playback_mode & MP_AUDIO_PLAYBACK_EN))
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249 | 24859b68 | balrog | return;
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250 | 24859b68 | balrog | |
251 | 24859b68 | balrog | if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE)
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252 | 4001a81e | balrog | free_out <<= 1;
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253 | 4001a81e | balrog | |
254 | 4001a81e | balrog | if (!(s->playback_mode & MP_AUDIO_MONO))
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255 | 24859b68 | balrog | free_out <<= 1;
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256 | 24859b68 | balrog | |
257 | 24859b68 | balrog | block_size = s->threshold/2;
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258 | 24859b68 | balrog | if (free_out - s->last_free < block_size)
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259 | 24859b68 | balrog | return;
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260 | 24859b68 | balrog | |
261 | 930c8682 | pbrook | if (block_size > 4096) |
262 | 930c8682 | pbrook | return;
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263 | 930c8682 | pbrook | |
264 | 930c8682 | pbrook | cpu_physical_memory_read(s->target_buffer + s->play_pos, (void *)buf,
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265 | 930c8682 | pbrook | block_size); |
266 | 930c8682 | pbrook | mem_buffer = buf; |
267 | 4001a81e | balrog | if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE) {
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268 | 4001a81e | balrog | if (s->playback_mode & MP_AUDIO_MONO) {
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269 | 4001a81e | balrog | codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
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270 | 4001a81e | balrog | for (pos = 0; pos < block_size; pos += 2) { |
271 | a350e694 | balrog | *codec_buffer++ = *(int16_t *)mem_buffer; |
272 | a350e694 | balrog | *codec_buffer++ = *(int16_t *)mem_buffer; |
273 | 4f3cb3be | balrog | mem_buffer += 2;
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274 | 4001a81e | balrog | } |
275 | 4001a81e | balrog | } else
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276 | 4001a81e | balrog | memcpy(wm8750_dac_buffer(s->wm, block_size >> 2),
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277 | 4001a81e | balrog | (uint32_t *)mem_buffer, block_size); |
278 | 4001a81e | balrog | } else {
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279 | 4001a81e | balrog | if (s->playback_mode & MP_AUDIO_MONO) {
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280 | 4001a81e | balrog | codec_buffer = wm8750_dac_buffer(s->wm, block_size); |
281 | 4001a81e | balrog | for (pos = 0; pos < block_size; pos++) { |
282 | a350e694 | balrog | *codec_buffer++ = cpu_to_le16(256 * *mem_buffer);
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283 | a350e694 | balrog | *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
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284 | 4001a81e | balrog | } |
285 | 4001a81e | balrog | } else {
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286 | 4001a81e | balrog | codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
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287 | 4001a81e | balrog | for (pos = 0; pos < block_size; pos += 2) { |
288 | a350e694 | balrog | *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
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289 | a350e694 | balrog | *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
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290 | 4001a81e | balrog | } |
291 | 24859b68 | balrog | } |
292 | 662caa6f | balrog | } |
293 | 662caa6f | balrog | wm8750_dac_commit(s->wm); |
294 | 24859b68 | balrog | |
295 | 24859b68 | balrog | s->last_free = free_out - block_size; |
296 | 24859b68 | balrog | |
297 | 24859b68 | balrog | if (s->play_pos == 0) { |
298 | 24859b68 | balrog | s->status |= MP_AUDIO_TX_HALF; |
299 | 24859b68 | balrog | s->play_pos = block_size; |
300 | 24859b68 | balrog | } else {
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301 | 24859b68 | balrog | s->status |= MP_AUDIO_TX_FULL; |
302 | 24859b68 | balrog | s->play_pos = 0;
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303 | 24859b68 | balrog | } |
304 | 24859b68 | balrog | |
305 | 24859b68 | balrog | if (s->status & s->irq_enable)
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306 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
307 | 24859b68 | balrog | } |
308 | 24859b68 | balrog | |
309 | af83e09e | balrog | static void musicpal_audio_clock_update(musicpal_audio_state *s) |
310 | af83e09e | balrog | { |
311 | af83e09e | balrog | int rate;
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312 | af83e09e | balrog | |
313 | af83e09e | balrog | if (s->playback_mode & MP_AUDIO_CLOCK_24MHZ)
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314 | af83e09e | balrog | rate = 24576000 / 64; /* 24.576MHz */ |
315 | af83e09e | balrog | else
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316 | af83e09e | balrog | rate = 11289600 / 64; /* 11.2896MHz */ |
317 | af83e09e | balrog | |
318 | af83e09e | balrog | rate /= ((s->clock_div >> 8) & 0xff) + 1; |
319 | af83e09e | balrog | |
320 | 91834991 | balrog | wm8750_set_bclk_in(s->wm, rate); |
321 | af83e09e | balrog | } |
322 | af83e09e | balrog | |
323 | 24859b68 | balrog | static uint32_t musicpal_audio_read(void *opaque, target_phys_addr_t offset) |
324 | 24859b68 | balrog | { |
325 | 24859b68 | balrog | musicpal_audio_state *s = opaque; |
326 | 24859b68 | balrog | |
327 | 24859b68 | balrog | switch (offset) {
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328 | 24859b68 | balrog | case MP_AUDIO_PLAYBACK_MODE:
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329 | 24859b68 | balrog | return s->playback_mode;
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330 | 24859b68 | balrog | |
331 | 24859b68 | balrog | case MP_AUDIO_CLOCK_DIV:
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332 | 24859b68 | balrog | return s->clock_div;
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333 | 24859b68 | balrog | |
334 | 24859b68 | balrog | case MP_AUDIO_IRQ_STATUS:
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335 | 24859b68 | balrog | return s->status;
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336 | 24859b68 | balrog | |
337 | 24859b68 | balrog | case MP_AUDIO_IRQ_ENABLE:
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338 | 24859b68 | balrog | return s->irq_enable;
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339 | 24859b68 | balrog | |
340 | 24859b68 | balrog | case MP_AUDIO_TX_STATUS:
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341 | 24859b68 | balrog | return s->play_pos >> 2; |
342 | 24859b68 | balrog | |
343 | 24859b68 | balrog | default:
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344 | 24859b68 | balrog | return 0; |
345 | 24859b68 | balrog | } |
346 | 24859b68 | balrog | } |
347 | 24859b68 | balrog | |
348 | 24859b68 | balrog | static void musicpal_audio_write(void *opaque, target_phys_addr_t offset, |
349 | 24859b68 | balrog | uint32_t value) |
350 | 24859b68 | balrog | { |
351 | 24859b68 | balrog | musicpal_audio_state *s = opaque; |
352 | 24859b68 | balrog | |
353 | 24859b68 | balrog | switch (offset) {
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354 | 24859b68 | balrog | case MP_AUDIO_PLAYBACK_MODE:
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355 | 24859b68 | balrog | if (value & MP_AUDIO_PLAYBACK_EN &&
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356 | 24859b68 | balrog | !(s->playback_mode & MP_AUDIO_PLAYBACK_EN)) { |
357 | 24859b68 | balrog | s->status = 0;
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358 | 24859b68 | balrog | s->last_free = 0;
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359 | 24859b68 | balrog | s->play_pos = 0;
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360 | 24859b68 | balrog | } |
361 | 24859b68 | balrog | s->playback_mode = value; |
362 | af83e09e | balrog | musicpal_audio_clock_update(s); |
363 | 24859b68 | balrog | break;
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364 | 24859b68 | balrog | |
365 | 24859b68 | balrog | case MP_AUDIO_CLOCK_DIV:
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366 | 24859b68 | balrog | s->clock_div = value; |
367 | 24859b68 | balrog | s->last_free = 0;
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368 | 24859b68 | balrog | s->play_pos = 0;
|
369 | af83e09e | balrog | musicpal_audio_clock_update(s); |
370 | 24859b68 | balrog | break;
|
371 | 24859b68 | balrog | |
372 | 24859b68 | balrog | case MP_AUDIO_IRQ_STATUS:
|
373 | 24859b68 | balrog | s->status &= ~value; |
374 | 24859b68 | balrog | break;
|
375 | 24859b68 | balrog | |
376 | 24859b68 | balrog | case MP_AUDIO_IRQ_ENABLE:
|
377 | 24859b68 | balrog | s->irq_enable = value; |
378 | 24859b68 | balrog | if (s->status & s->irq_enable)
|
379 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
380 | 24859b68 | balrog | break;
|
381 | 24859b68 | balrog | |
382 | 24859b68 | balrog | case MP_AUDIO_TX_START_LO:
|
383 | 24859b68 | balrog | s->phys_buf = (s->phys_buf & 0xFFFF0000) | (value & 0xFFFF); |
384 | 930c8682 | pbrook | s->target_buffer = s->phys_buf; |
385 | 24859b68 | balrog | s->play_pos = 0;
|
386 | 24859b68 | balrog | s->last_free = 0;
|
387 | 24859b68 | balrog | break;
|
388 | 24859b68 | balrog | |
389 | 24859b68 | balrog | case MP_AUDIO_TX_THRESHOLD:
|
390 | 24859b68 | balrog | s->threshold = (value + 1) * 4; |
391 | 24859b68 | balrog | break;
|
392 | 24859b68 | balrog | |
393 | 24859b68 | balrog | case MP_AUDIO_TX_START_HI:
|
394 | 24859b68 | balrog | s->phys_buf = (s->phys_buf & 0xFFFF) | (value << 16); |
395 | 930c8682 | pbrook | s->target_buffer = s->phys_buf; |
396 | 24859b68 | balrog | s->play_pos = 0;
|
397 | 24859b68 | balrog | s->last_free = 0;
|
398 | 24859b68 | balrog | break;
|
399 | 24859b68 | balrog | } |
400 | 24859b68 | balrog | } |
401 | 24859b68 | balrog | |
402 | 24859b68 | balrog | static void musicpal_audio_reset(void *opaque) |
403 | 24859b68 | balrog | { |
404 | 24859b68 | balrog | musicpal_audio_state *s = opaque; |
405 | 24859b68 | balrog | |
406 | 24859b68 | balrog | s->playback_mode = 0;
|
407 | 24859b68 | balrog | s->status = 0;
|
408 | 24859b68 | balrog | s->irq_enable = 0;
|
409 | 24859b68 | balrog | } |
410 | 24859b68 | balrog | |
411 | 24859b68 | balrog | static CPUReadMemoryFunc *musicpal_audio_readfn[] = {
|
412 | 24859b68 | balrog | musicpal_audio_read, |
413 | 24859b68 | balrog | musicpal_audio_read, |
414 | 24859b68 | balrog | musicpal_audio_read |
415 | 24859b68 | balrog | }; |
416 | 24859b68 | balrog | |
417 | 24859b68 | balrog | static CPUWriteMemoryFunc *musicpal_audio_writefn[] = {
|
418 | 24859b68 | balrog | musicpal_audio_write, |
419 | 24859b68 | balrog | musicpal_audio_write, |
420 | 24859b68 | balrog | musicpal_audio_write |
421 | 24859b68 | balrog | }; |
422 | 24859b68 | balrog | |
423 | 718ec0be | malc | static i2c_interface *musicpal_audio_init(qemu_irq irq)
|
424 | 24859b68 | balrog | { |
425 | 24859b68 | balrog | musicpal_audio_state *s; |
426 | 24859b68 | balrog | i2c_interface *i2c; |
427 | 24859b68 | balrog | int iomemtype;
|
428 | 24859b68 | balrog | |
429 | 24859b68 | balrog | s = qemu_mallocz(sizeof(musicpal_audio_state));
|
430 | 24859b68 | balrog | s->irq = irq; |
431 | 24859b68 | balrog | |
432 | 24859b68 | balrog | i2c = qemu_mallocz(sizeof(i2c_interface));
|
433 | 24859b68 | balrog | i2c->bus = i2c_init_bus(); |
434 | 24859b68 | balrog | i2c->current_addr = -1;
|
435 | 24859b68 | balrog | |
436 | 22d83b14 | Paul Brook | s->wm = wm8750_init(i2c->bus); |
437 | 24859b68 | balrog | if (!s->wm)
|
438 | 24859b68 | balrog | return NULL; |
439 | 24859b68 | balrog | i2c_set_slave_address(s->wm, MP_WM_ADDR); |
440 | 24859b68 | balrog | wm8750_data_req_set(s->wm, audio_callback, s); |
441 | 24859b68 | balrog | |
442 | 24859b68 | balrog | iomemtype = cpu_register_io_memory(0, musicpal_audio_readfn,
|
443 | 24859b68 | balrog | musicpal_audio_writefn, s); |
444 | 718ec0be | malc | cpu_register_physical_memory(MP_AUDIO_BASE, MP_AUDIO_SIZE, iomemtype); |
445 | 24859b68 | balrog | |
446 | 24859b68 | balrog | qemu_register_reset(musicpal_audio_reset, s); |
447 | 24859b68 | balrog | |
448 | 24859b68 | balrog | return i2c;
|
449 | 24859b68 | balrog | } |
450 | 24859b68 | balrog | #else /* !HAS_AUDIO */ |
451 | 718ec0be | malc | static i2c_interface *musicpal_audio_init(qemu_irq irq)
|
452 | 24859b68 | balrog | { |
453 | 24859b68 | balrog | return NULL; |
454 | 24859b68 | balrog | } |
455 | 24859b68 | balrog | #endif /* !HAS_AUDIO */ |
456 | 24859b68 | balrog | |
457 | 24859b68 | balrog | /* Ethernet register offsets */
|
458 | 24859b68 | balrog | #define MP_ETH_SMIR 0x010 |
459 | 24859b68 | balrog | #define MP_ETH_PCXR 0x408 |
460 | 24859b68 | balrog | #define MP_ETH_SDCMR 0x448 |
461 | 24859b68 | balrog | #define MP_ETH_ICR 0x450 |
462 | 24859b68 | balrog | #define MP_ETH_IMR 0x458 |
463 | 24859b68 | balrog | #define MP_ETH_FRDP0 0x480 |
464 | 24859b68 | balrog | #define MP_ETH_FRDP1 0x484 |
465 | 24859b68 | balrog | #define MP_ETH_FRDP2 0x488 |
466 | 24859b68 | balrog | #define MP_ETH_FRDP3 0x48C |
467 | 24859b68 | balrog | #define MP_ETH_CRDP0 0x4A0 |
468 | 24859b68 | balrog | #define MP_ETH_CRDP1 0x4A4 |
469 | 24859b68 | balrog | #define MP_ETH_CRDP2 0x4A8 |
470 | 24859b68 | balrog | #define MP_ETH_CRDP3 0x4AC |
471 | 24859b68 | balrog | #define MP_ETH_CTDP0 0x4E0 |
472 | 24859b68 | balrog | #define MP_ETH_CTDP1 0x4E4 |
473 | 24859b68 | balrog | #define MP_ETH_CTDP2 0x4E8 |
474 | 24859b68 | balrog | #define MP_ETH_CTDP3 0x4EC |
475 | 24859b68 | balrog | |
476 | 24859b68 | balrog | /* MII PHY access */
|
477 | 24859b68 | balrog | #define MP_ETH_SMIR_DATA 0x0000FFFF |
478 | 24859b68 | balrog | #define MP_ETH_SMIR_ADDR 0x03FF0000 |
479 | 24859b68 | balrog | #define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */ |
480 | 24859b68 | balrog | #define MP_ETH_SMIR_RDVALID (1 << 27) |
481 | 24859b68 | balrog | |
482 | 24859b68 | balrog | /* PHY registers */
|
483 | 24859b68 | balrog | #define MP_ETH_PHY1_BMSR 0x00210000 |
484 | 24859b68 | balrog | #define MP_ETH_PHY1_PHYSID1 0x00410000 |
485 | 24859b68 | balrog | #define MP_ETH_PHY1_PHYSID2 0x00610000 |
486 | 24859b68 | balrog | |
487 | 24859b68 | balrog | #define MP_PHY_BMSR_LINK 0x0004 |
488 | 24859b68 | balrog | #define MP_PHY_BMSR_AUTONEG 0x0008 |
489 | 24859b68 | balrog | |
490 | 24859b68 | balrog | #define MP_PHY_88E3015 0x01410E20 |
491 | 24859b68 | balrog | |
492 | 24859b68 | balrog | /* TX descriptor status */
|
493 | 24859b68 | balrog | #define MP_ETH_TX_OWN (1 << 31) |
494 | 24859b68 | balrog | |
495 | 24859b68 | balrog | /* RX descriptor status */
|
496 | 24859b68 | balrog | #define MP_ETH_RX_OWN (1 << 31) |
497 | 24859b68 | balrog | |
498 | 24859b68 | balrog | /* Interrupt cause/mask bits */
|
499 | 24859b68 | balrog | #define MP_ETH_IRQ_RX_BIT 0 |
500 | 24859b68 | balrog | #define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT) |
501 | 24859b68 | balrog | #define MP_ETH_IRQ_TXHI_BIT 2 |
502 | 24859b68 | balrog | #define MP_ETH_IRQ_TXLO_BIT 3 |
503 | 24859b68 | balrog | |
504 | 24859b68 | balrog | /* Port config bits */
|
505 | 24859b68 | balrog | #define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */ |
506 | 24859b68 | balrog | |
507 | 24859b68 | balrog | /* SDMA command bits */
|
508 | 24859b68 | balrog | #define MP_ETH_CMD_TXHI (1 << 23) |
509 | 24859b68 | balrog | #define MP_ETH_CMD_TXLO (1 << 22) |
510 | 24859b68 | balrog | |
511 | 24859b68 | balrog | typedef struct mv88w8618_tx_desc { |
512 | 24859b68 | balrog | uint32_t cmdstat; |
513 | 24859b68 | balrog | uint16_t res; |
514 | 24859b68 | balrog | uint16_t bytes; |
515 | 24859b68 | balrog | uint32_t buffer; |
516 | 24859b68 | balrog | uint32_t next; |
517 | 24859b68 | balrog | } mv88w8618_tx_desc; |
518 | 24859b68 | balrog | |
519 | 24859b68 | balrog | typedef struct mv88w8618_rx_desc { |
520 | 24859b68 | balrog | uint32_t cmdstat; |
521 | 24859b68 | balrog | uint16_t bytes; |
522 | 24859b68 | balrog | uint16_t buffer_size; |
523 | 24859b68 | balrog | uint32_t buffer; |
524 | 24859b68 | balrog | uint32_t next; |
525 | 24859b68 | balrog | } mv88w8618_rx_desc; |
526 | 24859b68 | balrog | |
527 | 24859b68 | balrog | typedef struct mv88w8618_eth_state { |
528 | 24859b68 | balrog | qemu_irq irq; |
529 | 24859b68 | balrog | uint32_t smir; |
530 | 24859b68 | balrog | uint32_t icr; |
531 | 24859b68 | balrog | uint32_t imr; |
532 | b946a153 | aliguori | int mmio_index;
|
533 | 24859b68 | balrog | int vlan_header;
|
534 | 930c8682 | pbrook | uint32_t tx_queue[2];
|
535 | 930c8682 | pbrook | uint32_t rx_queue[4];
|
536 | 930c8682 | pbrook | uint32_t frx_queue[4];
|
537 | 930c8682 | pbrook | uint32_t cur_rx[4];
|
538 | 24859b68 | balrog | VLANClientState *vc; |
539 | 24859b68 | balrog | } mv88w8618_eth_state; |
540 | 24859b68 | balrog | |
541 | 930c8682 | pbrook | static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc) |
542 | 930c8682 | pbrook | { |
543 | 930c8682 | pbrook | cpu_to_le32s(&desc->cmdstat); |
544 | 930c8682 | pbrook | cpu_to_le16s(&desc->bytes); |
545 | 930c8682 | pbrook | cpu_to_le16s(&desc->buffer_size); |
546 | 930c8682 | pbrook | cpu_to_le32s(&desc->buffer); |
547 | 930c8682 | pbrook | cpu_to_le32s(&desc->next); |
548 | 930c8682 | pbrook | cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc)); |
549 | 930c8682 | pbrook | } |
550 | 930c8682 | pbrook | |
551 | 930c8682 | pbrook | static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc) |
552 | 930c8682 | pbrook | { |
553 | 930c8682 | pbrook | cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc)); |
554 | 930c8682 | pbrook | le32_to_cpus(&desc->cmdstat); |
555 | 930c8682 | pbrook | le16_to_cpus(&desc->bytes); |
556 | 930c8682 | pbrook | le16_to_cpus(&desc->buffer_size); |
557 | 930c8682 | pbrook | le32_to_cpus(&desc->buffer); |
558 | 930c8682 | pbrook | le32_to_cpus(&desc->next); |
559 | 930c8682 | pbrook | } |
560 | 930c8682 | pbrook | |
561 | 24859b68 | balrog | static int eth_can_receive(void *opaque) |
562 | 24859b68 | balrog | { |
563 | 24859b68 | balrog | return 1; |
564 | 24859b68 | balrog | } |
565 | 24859b68 | balrog | |
566 | 24859b68 | balrog | static void eth_receive(void *opaque, const uint8_t *buf, int size) |
567 | 24859b68 | balrog | { |
568 | 24859b68 | balrog | mv88w8618_eth_state *s = opaque; |
569 | 930c8682 | pbrook | uint32_t desc_addr; |
570 | 930c8682 | pbrook | mv88w8618_rx_desc desc; |
571 | 24859b68 | balrog | int i;
|
572 | 24859b68 | balrog | |
573 | 24859b68 | balrog | for (i = 0; i < 4; i++) { |
574 | 930c8682 | pbrook | desc_addr = s->cur_rx[i]; |
575 | 930c8682 | pbrook | if (!desc_addr)
|
576 | 24859b68 | balrog | continue;
|
577 | 24859b68 | balrog | do {
|
578 | 930c8682 | pbrook | eth_rx_desc_get(desc_addr, &desc); |
579 | 930c8682 | pbrook | if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
|
580 | 930c8682 | pbrook | cpu_physical_memory_write(desc.buffer + s->vlan_header, |
581 | 930c8682 | pbrook | buf, size); |
582 | 930c8682 | pbrook | desc.bytes = size + s->vlan_header; |
583 | 930c8682 | pbrook | desc.cmdstat &= ~MP_ETH_RX_OWN; |
584 | 930c8682 | pbrook | s->cur_rx[i] = desc.next; |
585 | 24859b68 | balrog | |
586 | 24859b68 | balrog | s->icr |= MP_ETH_IRQ_RX; |
587 | 24859b68 | balrog | if (s->icr & s->imr)
|
588 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
589 | 930c8682 | pbrook | eth_rx_desc_put(desc_addr, &desc); |
590 | 24859b68 | balrog | return;
|
591 | 24859b68 | balrog | } |
592 | 930c8682 | pbrook | desc_addr = desc.next; |
593 | 930c8682 | pbrook | } while (desc_addr != s->rx_queue[i]);
|
594 | 24859b68 | balrog | } |
595 | 24859b68 | balrog | } |
596 | 24859b68 | balrog | |
597 | 930c8682 | pbrook | static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc) |
598 | 930c8682 | pbrook | { |
599 | 930c8682 | pbrook | cpu_to_le32s(&desc->cmdstat); |
600 | 930c8682 | pbrook | cpu_to_le16s(&desc->res); |
601 | 930c8682 | pbrook | cpu_to_le16s(&desc->bytes); |
602 | 930c8682 | pbrook | cpu_to_le32s(&desc->buffer); |
603 | 930c8682 | pbrook | cpu_to_le32s(&desc->next); |
604 | 930c8682 | pbrook | cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc)); |
605 | 930c8682 | pbrook | } |
606 | 930c8682 | pbrook | |
607 | 930c8682 | pbrook | static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc) |
608 | 930c8682 | pbrook | { |
609 | 930c8682 | pbrook | cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc)); |
610 | 930c8682 | pbrook | le32_to_cpus(&desc->cmdstat); |
611 | 930c8682 | pbrook | le16_to_cpus(&desc->res); |
612 | 930c8682 | pbrook | le16_to_cpus(&desc->bytes); |
613 | 930c8682 | pbrook | le32_to_cpus(&desc->buffer); |
614 | 930c8682 | pbrook | le32_to_cpus(&desc->next); |
615 | 930c8682 | pbrook | } |
616 | 930c8682 | pbrook | |
617 | 24859b68 | balrog | static void eth_send(mv88w8618_eth_state *s, int queue_index) |
618 | 24859b68 | balrog | { |
619 | 930c8682 | pbrook | uint32_t desc_addr = s->tx_queue[queue_index]; |
620 | 930c8682 | pbrook | mv88w8618_tx_desc desc; |
621 | 930c8682 | pbrook | uint8_t buf[2048];
|
622 | 930c8682 | pbrook | int len;
|
623 | 930c8682 | pbrook | |
624 | 24859b68 | balrog | |
625 | 24859b68 | balrog | do {
|
626 | 930c8682 | pbrook | eth_tx_desc_get(desc_addr, &desc); |
627 | 930c8682 | pbrook | if (desc.cmdstat & MP_ETH_TX_OWN) {
|
628 | 930c8682 | pbrook | len = desc.bytes; |
629 | 930c8682 | pbrook | if (len < 2048) { |
630 | 930c8682 | pbrook | cpu_physical_memory_read(desc.buffer, buf, len); |
631 | 930c8682 | pbrook | qemu_send_packet(s->vc, buf, len); |
632 | 930c8682 | pbrook | } |
633 | 930c8682 | pbrook | desc.cmdstat &= ~MP_ETH_TX_OWN; |
634 | 24859b68 | balrog | s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
|
635 | 930c8682 | pbrook | eth_tx_desc_put(desc_addr, &desc); |
636 | 24859b68 | balrog | } |
637 | 930c8682 | pbrook | desc_addr = desc.next; |
638 | 930c8682 | pbrook | } while (desc_addr != s->tx_queue[queue_index]);
|
639 | 24859b68 | balrog | } |
640 | 24859b68 | balrog | |
641 | 24859b68 | balrog | static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset) |
642 | 24859b68 | balrog | { |
643 | 24859b68 | balrog | mv88w8618_eth_state *s = opaque; |
644 | 24859b68 | balrog | |
645 | 24859b68 | balrog | switch (offset) {
|
646 | 24859b68 | balrog | case MP_ETH_SMIR:
|
647 | 24859b68 | balrog | if (s->smir & MP_ETH_SMIR_OPCODE) {
|
648 | 24859b68 | balrog | switch (s->smir & MP_ETH_SMIR_ADDR) {
|
649 | 24859b68 | balrog | case MP_ETH_PHY1_BMSR:
|
650 | 24859b68 | balrog | return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
|
651 | 24859b68 | balrog | MP_ETH_SMIR_RDVALID; |
652 | 24859b68 | balrog | case MP_ETH_PHY1_PHYSID1:
|
653 | 24859b68 | balrog | return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID; |
654 | 24859b68 | balrog | case MP_ETH_PHY1_PHYSID2:
|
655 | 24859b68 | balrog | return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID; |
656 | 24859b68 | balrog | default:
|
657 | 24859b68 | balrog | return MP_ETH_SMIR_RDVALID;
|
658 | 24859b68 | balrog | } |
659 | 24859b68 | balrog | } |
660 | 24859b68 | balrog | return 0; |
661 | 24859b68 | balrog | |
662 | 24859b68 | balrog | case MP_ETH_ICR:
|
663 | 24859b68 | balrog | return s->icr;
|
664 | 24859b68 | balrog | |
665 | 24859b68 | balrog | case MP_ETH_IMR:
|
666 | 24859b68 | balrog | return s->imr;
|
667 | 24859b68 | balrog | |
668 | 24859b68 | balrog | case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
|
669 | 930c8682 | pbrook | return s->frx_queue[(offset - MP_ETH_FRDP0)/4]; |
670 | 24859b68 | balrog | |
671 | 24859b68 | balrog | case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
|
672 | 930c8682 | pbrook | return s->rx_queue[(offset - MP_ETH_CRDP0)/4]; |
673 | 24859b68 | balrog | |
674 | 24859b68 | balrog | case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
|
675 | 930c8682 | pbrook | return s->tx_queue[(offset - MP_ETH_CTDP0)/4]; |
676 | 24859b68 | balrog | |
677 | 24859b68 | balrog | default:
|
678 | 24859b68 | balrog | return 0; |
679 | 24859b68 | balrog | } |
680 | 24859b68 | balrog | } |
681 | 24859b68 | balrog | |
682 | 24859b68 | balrog | static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset, |
683 | 24859b68 | balrog | uint32_t value) |
684 | 24859b68 | balrog | { |
685 | 24859b68 | balrog | mv88w8618_eth_state *s = opaque; |
686 | 24859b68 | balrog | |
687 | 24859b68 | balrog | switch (offset) {
|
688 | 24859b68 | balrog | case MP_ETH_SMIR:
|
689 | 24859b68 | balrog | s->smir = value; |
690 | 24859b68 | balrog | break;
|
691 | 24859b68 | balrog | |
692 | 24859b68 | balrog | case MP_ETH_PCXR:
|
693 | 24859b68 | balrog | s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2; |
694 | 24859b68 | balrog | break;
|
695 | 24859b68 | balrog | |
696 | 24859b68 | balrog | case MP_ETH_SDCMR:
|
697 | 24859b68 | balrog | if (value & MP_ETH_CMD_TXHI)
|
698 | 24859b68 | balrog | eth_send(s, 1);
|
699 | 24859b68 | balrog | if (value & MP_ETH_CMD_TXLO)
|
700 | 24859b68 | balrog | eth_send(s, 0);
|
701 | 24859b68 | balrog | if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr)
|
702 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
703 | 24859b68 | balrog | break;
|
704 | 24859b68 | balrog | |
705 | 24859b68 | balrog | case MP_ETH_ICR:
|
706 | 24859b68 | balrog | s->icr &= value; |
707 | 24859b68 | balrog | break;
|
708 | 24859b68 | balrog | |
709 | 24859b68 | balrog | case MP_ETH_IMR:
|
710 | 24859b68 | balrog | s->imr = value; |
711 | 24859b68 | balrog | if (s->icr & s->imr)
|
712 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
713 | 24859b68 | balrog | break;
|
714 | 24859b68 | balrog | |
715 | 24859b68 | balrog | case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
|
716 | 930c8682 | pbrook | s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
|
717 | 24859b68 | balrog | break;
|
718 | 24859b68 | balrog | |
719 | 24859b68 | balrog | case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
|
720 | 24859b68 | balrog | s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
|
721 | 930c8682 | pbrook | s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
|
722 | 24859b68 | balrog | break;
|
723 | 24859b68 | balrog | |
724 | 24859b68 | balrog | case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
|
725 | 930c8682 | pbrook | s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
|
726 | 24859b68 | balrog | break;
|
727 | 24859b68 | balrog | } |
728 | 24859b68 | balrog | } |
729 | 24859b68 | balrog | |
730 | 24859b68 | balrog | static CPUReadMemoryFunc *mv88w8618_eth_readfn[] = {
|
731 | 24859b68 | balrog | mv88w8618_eth_read, |
732 | 24859b68 | balrog | mv88w8618_eth_read, |
733 | 24859b68 | balrog | mv88w8618_eth_read |
734 | 24859b68 | balrog | }; |
735 | 24859b68 | balrog | |
736 | 24859b68 | balrog | static CPUWriteMemoryFunc *mv88w8618_eth_writefn[] = {
|
737 | 24859b68 | balrog | mv88w8618_eth_write, |
738 | 24859b68 | balrog | mv88w8618_eth_write, |
739 | 24859b68 | balrog | mv88w8618_eth_write |
740 | 24859b68 | balrog | }; |
741 | 24859b68 | balrog | |
742 | b946a153 | aliguori | static void eth_cleanup(VLANClientState *vc) |
743 | b946a153 | aliguori | { |
744 | b946a153 | aliguori | mv88w8618_eth_state *s = vc->opaque; |
745 | b946a153 | aliguori | |
746 | b946a153 | aliguori | cpu_unregister_io_memory(s->mmio_index); |
747 | b946a153 | aliguori | |
748 | b946a153 | aliguori | qemu_free(s); |
749 | b946a153 | aliguori | } |
750 | b946a153 | aliguori | |
751 | 24859b68 | balrog | static void mv88w8618_eth_init(NICInfo *nd, uint32_t base, qemu_irq irq) |
752 | 24859b68 | balrog | { |
753 | 24859b68 | balrog | mv88w8618_eth_state *s; |
754 | 24859b68 | balrog | |
755 | 0ae18cee | aliguori | qemu_check_nic_model(nd, "mv88w8618");
|
756 | 0ae18cee | aliguori | |
757 | 24859b68 | balrog | s = qemu_mallocz(sizeof(mv88w8618_eth_state));
|
758 | 24859b68 | balrog | s->irq = irq; |
759 | 7a9f6e4a | aliguori | s->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name, |
760 | b946a153 | aliguori | eth_receive, eth_can_receive, |
761 | b946a153 | aliguori | eth_cleanup, s); |
762 | b946a153 | aliguori | s->mmio_index = cpu_register_io_memory(0, mv88w8618_eth_readfn,
|
763 | b946a153 | aliguori | mv88w8618_eth_writefn, s); |
764 | b946a153 | aliguori | cpu_register_physical_memory(base, MP_ETH_SIZE, s->mmio_index); |
765 | 24859b68 | balrog | } |
766 | 24859b68 | balrog | |
767 | 24859b68 | balrog | /* LCD register offsets */
|
768 | 24859b68 | balrog | #define MP_LCD_IRQCTRL 0x180 |
769 | 24859b68 | balrog | #define MP_LCD_IRQSTAT 0x184 |
770 | 24859b68 | balrog | #define MP_LCD_SPICTRL 0x1ac |
771 | 24859b68 | balrog | #define MP_LCD_INST 0x1bc |
772 | 24859b68 | balrog | #define MP_LCD_DATA 0x1c0 |
773 | 24859b68 | balrog | |
774 | 24859b68 | balrog | /* Mode magics */
|
775 | 24859b68 | balrog | #define MP_LCD_SPI_DATA 0x00100011 |
776 | 24859b68 | balrog | #define MP_LCD_SPI_CMD 0x00104011 |
777 | 24859b68 | balrog | #define MP_LCD_SPI_INVALID 0x00000000 |
778 | 24859b68 | balrog | |
779 | 24859b68 | balrog | /* Commmands */
|
780 | 24859b68 | balrog | #define MP_LCD_INST_SETPAGE0 0xB0 |
781 | 24859b68 | balrog | /* ... */
|
782 | 24859b68 | balrog | #define MP_LCD_INST_SETPAGE7 0xB7 |
783 | 24859b68 | balrog | |
784 | 24859b68 | balrog | #define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */ |
785 | 24859b68 | balrog | |
786 | 24859b68 | balrog | typedef struct musicpal_lcd_state { |
787 | 24859b68 | balrog | uint32_t mode; |
788 | 24859b68 | balrog | uint32_t irqctrl; |
789 | 24859b68 | balrog | int page;
|
790 | 24859b68 | balrog | int page_off;
|
791 | 24859b68 | balrog | DisplayState *ds; |
792 | 24859b68 | balrog | uint8_t video_ram[128*64/8]; |
793 | 24859b68 | balrog | } musicpal_lcd_state; |
794 | 24859b68 | balrog | |
795 | 24859b68 | balrog | static uint32_t lcd_brightness;
|
796 | 24859b68 | balrog | |
797 | 24859b68 | balrog | static uint8_t scale_lcd_color(uint8_t col)
|
798 | 24859b68 | balrog | { |
799 | 24859b68 | balrog | int tmp = col;
|
800 | 24859b68 | balrog | |
801 | 24859b68 | balrog | switch (lcd_brightness) {
|
802 | 24859b68 | balrog | case 0x00000007: /* 0 */ |
803 | 24859b68 | balrog | return 0; |
804 | 24859b68 | balrog | |
805 | 24859b68 | balrog | case 0x00020000: /* 1 */ |
806 | 24859b68 | balrog | return (tmp * 1) / 7; |
807 | 24859b68 | balrog | |
808 | 24859b68 | balrog | case 0x00020001: /* 2 */ |
809 | 24859b68 | balrog | return (tmp * 2) / 7; |
810 | 24859b68 | balrog | |
811 | 24859b68 | balrog | case 0x00040000: /* 3 */ |
812 | 24859b68 | balrog | return (tmp * 3) / 7; |
813 | 24859b68 | balrog | |
814 | 24859b68 | balrog | case 0x00010006: /* 4 */ |
815 | 24859b68 | balrog | return (tmp * 4) / 7; |
816 | 24859b68 | balrog | |
817 | 24859b68 | balrog | case 0x00020005: /* 5 */ |
818 | 24859b68 | balrog | return (tmp * 5) / 7; |
819 | 24859b68 | balrog | |
820 | 24859b68 | balrog | case 0x00040003: /* 6 */ |
821 | 24859b68 | balrog | return (tmp * 6) / 7; |
822 | 24859b68 | balrog | |
823 | 24859b68 | balrog | case 0x00030004: /* 7 */ |
824 | 24859b68 | balrog | default:
|
825 | 24859b68 | balrog | return col;
|
826 | 24859b68 | balrog | } |
827 | 24859b68 | balrog | } |
828 | 24859b68 | balrog | |
829 | 0266f2c7 | balrog | #define SET_LCD_PIXEL(depth, type) \
|
830 | 0266f2c7 | balrog | static inline void glue(set_lcd_pixel, depth) \ |
831 | 0266f2c7 | balrog | (musicpal_lcd_state *s, int x, int y, type col) \ |
832 | 0266f2c7 | balrog | { \ |
833 | 0266f2c7 | balrog | int dx, dy; \
|
834 | 0e1f5a0c | aliguori | type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \ |
835 | 0266f2c7 | balrog | \ |
836 | 0266f2c7 | balrog | for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \ |
837 | 0266f2c7 | balrog | for (dx = 0; dx < 3; dx++, pixel++) \ |
838 | 0266f2c7 | balrog | *pixel = col; \ |
839 | 24859b68 | balrog | } |
840 | 0266f2c7 | balrog | SET_LCD_PIXEL(8, uint8_t)
|
841 | 0266f2c7 | balrog | SET_LCD_PIXEL(16, uint16_t)
|
842 | 0266f2c7 | balrog | SET_LCD_PIXEL(32, uint32_t)
|
843 | 0266f2c7 | balrog | |
844 | 0266f2c7 | balrog | #include "pixel_ops.h" |
845 | 24859b68 | balrog | |
846 | 24859b68 | balrog | static void lcd_refresh(void *opaque) |
847 | 24859b68 | balrog | { |
848 | 24859b68 | balrog | musicpal_lcd_state *s = opaque; |
849 | 0266f2c7 | balrog | int x, y, col;
|
850 | 24859b68 | balrog | |
851 | 0e1f5a0c | aliguori | switch (ds_get_bits_per_pixel(s->ds)) {
|
852 | 0266f2c7 | balrog | case 0: |
853 | 0266f2c7 | balrog | return;
|
854 | 0266f2c7 | balrog | #define LCD_REFRESH(depth, func) \
|
855 | 0266f2c7 | balrog | case depth: \
|
856 | 0266f2c7 | balrog | col = func(scale_lcd_color((MP_LCD_TEXTCOLOR >> 16) & 0xff), \ |
857 | 0266f2c7 | balrog | scale_lcd_color((MP_LCD_TEXTCOLOR >> 8) & 0xff), \ |
858 | 0266f2c7 | balrog | scale_lcd_color(MP_LCD_TEXTCOLOR & 0xff)); \
|
859 | 0266f2c7 | balrog | for (x = 0; x < 128; x++) \ |
860 | 0266f2c7 | balrog | for (y = 0; y < 64; y++) \ |
861 | 0266f2c7 | balrog | if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) \ |
862 | 0266f2c7 | balrog | glue(set_lcd_pixel, depth)(s, x, y, col); \ |
863 | 0266f2c7 | balrog | else \
|
864 | 0266f2c7 | balrog | glue(set_lcd_pixel, depth)(s, x, y, 0); \
|
865 | 0266f2c7 | balrog | break;
|
866 | 0266f2c7 | balrog | LCD_REFRESH(8, rgb_to_pixel8)
|
867 | 0266f2c7 | balrog | LCD_REFRESH(16, rgb_to_pixel16)
|
868 | bf9b48af | aliguori | LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
|
869 | bf9b48af | aliguori | rgb_to_pixel32bgr : rgb_to_pixel32)) |
870 | 0266f2c7 | balrog | default:
|
871 | 2ac71179 | Paul Brook | hw_error("unsupported colour depth %i\n",
|
872 | 0e1f5a0c | aliguori | ds_get_bits_per_pixel(s->ds)); |
873 | 0266f2c7 | balrog | } |
874 | 24859b68 | balrog | |
875 | 24859b68 | balrog | dpy_update(s->ds, 0, 0, 128*3, 64*3); |
876 | 24859b68 | balrog | } |
877 | 24859b68 | balrog | |
878 | 167bc3d2 | balrog | static void lcd_invalidate(void *opaque) |
879 | 167bc3d2 | balrog | { |
880 | 167bc3d2 | balrog | } |
881 | 167bc3d2 | balrog | |
882 | 24859b68 | balrog | static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset) |
883 | 24859b68 | balrog | { |
884 | 24859b68 | balrog | musicpal_lcd_state *s = opaque; |
885 | 24859b68 | balrog | |
886 | 24859b68 | balrog | switch (offset) {
|
887 | 24859b68 | balrog | case MP_LCD_IRQCTRL:
|
888 | 24859b68 | balrog | return s->irqctrl;
|
889 | 24859b68 | balrog | |
890 | 24859b68 | balrog | default:
|
891 | 24859b68 | balrog | return 0; |
892 | 24859b68 | balrog | } |
893 | 24859b68 | balrog | } |
894 | 24859b68 | balrog | |
895 | 24859b68 | balrog | static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset, |
896 | 24859b68 | balrog | uint32_t value) |
897 | 24859b68 | balrog | { |
898 | 24859b68 | balrog | musicpal_lcd_state *s = opaque; |
899 | 24859b68 | balrog | |
900 | 24859b68 | balrog | switch (offset) {
|
901 | 24859b68 | balrog | case MP_LCD_IRQCTRL:
|
902 | 24859b68 | balrog | s->irqctrl = value; |
903 | 24859b68 | balrog | break;
|
904 | 24859b68 | balrog | |
905 | 24859b68 | balrog | case MP_LCD_SPICTRL:
|
906 | 24859b68 | balrog | if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD)
|
907 | 24859b68 | balrog | s->mode = value; |
908 | 24859b68 | balrog | else
|
909 | 24859b68 | balrog | s->mode = MP_LCD_SPI_INVALID; |
910 | 24859b68 | balrog | break;
|
911 | 24859b68 | balrog | |
912 | 24859b68 | balrog | case MP_LCD_INST:
|
913 | 24859b68 | balrog | if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
|
914 | 24859b68 | balrog | s->page = value - MP_LCD_INST_SETPAGE0; |
915 | 24859b68 | balrog | s->page_off = 0;
|
916 | 24859b68 | balrog | } |
917 | 24859b68 | balrog | break;
|
918 | 24859b68 | balrog | |
919 | 24859b68 | balrog | case MP_LCD_DATA:
|
920 | 24859b68 | balrog | if (s->mode == MP_LCD_SPI_CMD) {
|
921 | 24859b68 | balrog | if (value >= MP_LCD_INST_SETPAGE0 &&
|
922 | 24859b68 | balrog | value <= MP_LCD_INST_SETPAGE7) { |
923 | 24859b68 | balrog | s->page = value - MP_LCD_INST_SETPAGE0; |
924 | 24859b68 | balrog | s->page_off = 0;
|
925 | 24859b68 | balrog | } |
926 | 24859b68 | balrog | } else if (s->mode == MP_LCD_SPI_DATA) { |
927 | 24859b68 | balrog | s->video_ram[s->page*128 + s->page_off] = value;
|
928 | 24859b68 | balrog | s->page_off = (s->page_off + 1) & 127; |
929 | 24859b68 | balrog | } |
930 | 24859b68 | balrog | break;
|
931 | 24859b68 | balrog | } |
932 | 24859b68 | balrog | } |
933 | 24859b68 | balrog | |
934 | 24859b68 | balrog | static CPUReadMemoryFunc *musicpal_lcd_readfn[] = {
|
935 | 24859b68 | balrog | musicpal_lcd_read, |
936 | 24859b68 | balrog | musicpal_lcd_read, |
937 | 24859b68 | balrog | musicpal_lcd_read |
938 | 24859b68 | balrog | }; |
939 | 24859b68 | balrog | |
940 | 24859b68 | balrog | static CPUWriteMemoryFunc *musicpal_lcd_writefn[] = {
|
941 | 24859b68 | balrog | musicpal_lcd_write, |
942 | 24859b68 | balrog | musicpal_lcd_write, |
943 | 24859b68 | balrog | musicpal_lcd_write |
944 | 24859b68 | balrog | }; |
945 | 24859b68 | balrog | |
946 | 718ec0be | malc | static void musicpal_lcd_init(void) |
947 | 24859b68 | balrog | { |
948 | 24859b68 | balrog | musicpal_lcd_state *s; |
949 | 24859b68 | balrog | int iomemtype;
|
950 | 24859b68 | balrog | |
951 | 24859b68 | balrog | s = qemu_mallocz(sizeof(musicpal_lcd_state));
|
952 | 24859b68 | balrog | iomemtype = cpu_register_io_memory(0, musicpal_lcd_readfn,
|
953 | 24859b68 | balrog | musicpal_lcd_writefn, s); |
954 | 718ec0be | malc | cpu_register_physical_memory(MP_LCD_BASE, MP_LCD_SIZE, iomemtype); |
955 | 24859b68 | balrog | |
956 | 3023f332 | aliguori | s->ds = graphic_console_init(lcd_refresh, lcd_invalidate, |
957 | 3023f332 | aliguori | NULL, NULL, s); |
958 | 3023f332 | aliguori | qemu_console_resize(s->ds, 128*3, 64*3); |
959 | 24859b68 | balrog | } |
960 | 24859b68 | balrog | |
961 | 24859b68 | balrog | /* PIC register offsets */
|
962 | 24859b68 | balrog | #define MP_PIC_STATUS 0x00 |
963 | 24859b68 | balrog | #define MP_PIC_ENABLE_SET 0x08 |
964 | 24859b68 | balrog | #define MP_PIC_ENABLE_CLR 0x0C |
965 | 24859b68 | balrog | |
966 | 24859b68 | balrog | typedef struct mv88w8618_pic_state |
967 | 24859b68 | balrog | { |
968 | 24859b68 | balrog | uint32_t level; |
969 | 24859b68 | balrog | uint32_t enabled; |
970 | 24859b68 | balrog | qemu_irq parent_irq; |
971 | 24859b68 | balrog | } mv88w8618_pic_state; |
972 | 24859b68 | balrog | |
973 | 24859b68 | balrog | static void mv88w8618_pic_update(mv88w8618_pic_state *s) |
974 | 24859b68 | balrog | { |
975 | 24859b68 | balrog | qemu_set_irq(s->parent_irq, (s->level & s->enabled)); |
976 | 24859b68 | balrog | } |
977 | 24859b68 | balrog | |
978 | 24859b68 | balrog | static void mv88w8618_pic_set_irq(void *opaque, int irq, int level) |
979 | 24859b68 | balrog | { |
980 | 24859b68 | balrog | mv88w8618_pic_state *s = opaque; |
981 | 24859b68 | balrog | |
982 | 24859b68 | balrog | if (level)
|
983 | 24859b68 | balrog | s->level |= 1 << irq;
|
984 | 24859b68 | balrog | else
|
985 | 24859b68 | balrog | s->level &= ~(1 << irq);
|
986 | 24859b68 | balrog | mv88w8618_pic_update(s); |
987 | 24859b68 | balrog | } |
988 | 24859b68 | balrog | |
989 | 24859b68 | balrog | static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset) |
990 | 24859b68 | balrog | { |
991 | 24859b68 | balrog | mv88w8618_pic_state *s = opaque; |
992 | 24859b68 | balrog | |
993 | 24859b68 | balrog | switch (offset) {
|
994 | 24859b68 | balrog | case MP_PIC_STATUS:
|
995 | 24859b68 | balrog | return s->level & s->enabled;
|
996 | 24859b68 | balrog | |
997 | 24859b68 | balrog | default:
|
998 | 24859b68 | balrog | return 0; |
999 | 24859b68 | balrog | } |
1000 | 24859b68 | balrog | } |
1001 | 24859b68 | balrog | |
1002 | 24859b68 | balrog | static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset, |
1003 | 24859b68 | balrog | uint32_t value) |
1004 | 24859b68 | balrog | { |
1005 | 24859b68 | balrog | mv88w8618_pic_state *s = opaque; |
1006 | 24859b68 | balrog | |
1007 | 24859b68 | balrog | switch (offset) {
|
1008 | 24859b68 | balrog | case MP_PIC_ENABLE_SET:
|
1009 | 24859b68 | balrog | s->enabled |= value; |
1010 | 24859b68 | balrog | break;
|
1011 | 24859b68 | balrog | |
1012 | 24859b68 | balrog | case MP_PIC_ENABLE_CLR:
|
1013 | 24859b68 | balrog | s->enabled &= ~value; |
1014 | 24859b68 | balrog | s->level &= ~value; |
1015 | 24859b68 | balrog | break;
|
1016 | 24859b68 | balrog | } |
1017 | 24859b68 | balrog | mv88w8618_pic_update(s); |
1018 | 24859b68 | balrog | } |
1019 | 24859b68 | balrog | |
1020 | 24859b68 | balrog | static void mv88w8618_pic_reset(void *opaque) |
1021 | 24859b68 | balrog | { |
1022 | 24859b68 | balrog | mv88w8618_pic_state *s = opaque; |
1023 | 24859b68 | balrog | |
1024 | 24859b68 | balrog | s->level = 0;
|
1025 | 24859b68 | balrog | s->enabled = 0;
|
1026 | 24859b68 | balrog | } |
1027 | 24859b68 | balrog | |
1028 | 24859b68 | balrog | static CPUReadMemoryFunc *mv88w8618_pic_readfn[] = {
|
1029 | 24859b68 | balrog | mv88w8618_pic_read, |
1030 | 24859b68 | balrog | mv88w8618_pic_read, |
1031 | 24859b68 | balrog | mv88w8618_pic_read |
1032 | 24859b68 | balrog | }; |
1033 | 24859b68 | balrog | |
1034 | 24859b68 | balrog | static CPUWriteMemoryFunc *mv88w8618_pic_writefn[] = {
|
1035 | 24859b68 | balrog | mv88w8618_pic_write, |
1036 | 24859b68 | balrog | mv88w8618_pic_write, |
1037 | 24859b68 | balrog | mv88w8618_pic_write |
1038 | 24859b68 | balrog | }; |
1039 | 24859b68 | balrog | |
1040 | 24859b68 | balrog | static qemu_irq *mv88w8618_pic_init(uint32_t base, qemu_irq parent_irq)
|
1041 | 24859b68 | balrog | { |
1042 | 24859b68 | balrog | mv88w8618_pic_state *s; |
1043 | 24859b68 | balrog | int iomemtype;
|
1044 | 24859b68 | balrog | qemu_irq *qi; |
1045 | 24859b68 | balrog | |
1046 | 24859b68 | balrog | s = qemu_mallocz(sizeof(mv88w8618_pic_state));
|
1047 | 24859b68 | balrog | qi = qemu_allocate_irqs(mv88w8618_pic_set_irq, s, 32);
|
1048 | 24859b68 | balrog | s->parent_irq = parent_irq; |
1049 | 24859b68 | balrog | iomemtype = cpu_register_io_memory(0, mv88w8618_pic_readfn,
|
1050 | 24859b68 | balrog | mv88w8618_pic_writefn, s); |
1051 | 24859b68 | balrog | cpu_register_physical_memory(base, MP_PIC_SIZE, iomemtype); |
1052 | 24859b68 | balrog | |
1053 | 24859b68 | balrog | qemu_register_reset(mv88w8618_pic_reset, s); |
1054 | 24859b68 | balrog | |
1055 | 24859b68 | balrog | return qi;
|
1056 | 24859b68 | balrog | } |
1057 | 24859b68 | balrog | |
1058 | 24859b68 | balrog | /* PIT register offsets */
|
1059 | 24859b68 | balrog | #define MP_PIT_TIMER1_LENGTH 0x00 |
1060 | 24859b68 | balrog | /* ... */
|
1061 | 24859b68 | balrog | #define MP_PIT_TIMER4_LENGTH 0x0C |
1062 | 24859b68 | balrog | #define MP_PIT_CONTROL 0x10 |
1063 | 24859b68 | balrog | #define MP_PIT_TIMER1_VALUE 0x14 |
1064 | 24859b68 | balrog | /* ... */
|
1065 | 24859b68 | balrog | #define MP_PIT_TIMER4_VALUE 0x20 |
1066 | 24859b68 | balrog | #define MP_BOARD_RESET 0x34 |
1067 | 24859b68 | balrog | |
1068 | 24859b68 | balrog | /* Magic board reset value (probably some watchdog behind it) */
|
1069 | 24859b68 | balrog | #define MP_BOARD_RESET_MAGIC 0x10000 |
1070 | 24859b68 | balrog | |
1071 | 24859b68 | balrog | typedef struct mv88w8618_timer_state { |
1072 | 24859b68 | balrog | ptimer_state *timer; |
1073 | 24859b68 | balrog | uint32_t limit; |
1074 | 24859b68 | balrog | int freq;
|
1075 | 24859b68 | balrog | qemu_irq irq; |
1076 | 24859b68 | balrog | } mv88w8618_timer_state; |
1077 | 24859b68 | balrog | |
1078 | 24859b68 | balrog | typedef struct mv88w8618_pit_state { |
1079 | 24859b68 | balrog | void *timer[4]; |
1080 | 24859b68 | balrog | uint32_t control; |
1081 | 24859b68 | balrog | } mv88w8618_pit_state; |
1082 | 24859b68 | balrog | |
1083 | 24859b68 | balrog | static void mv88w8618_timer_tick(void *opaque) |
1084 | 24859b68 | balrog | { |
1085 | 24859b68 | balrog | mv88w8618_timer_state *s = opaque; |
1086 | 24859b68 | balrog | |
1087 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
1088 | 24859b68 | balrog | } |
1089 | 24859b68 | balrog | |
1090 | 24859b68 | balrog | static void *mv88w8618_timer_init(uint32_t freq, qemu_irq irq) |
1091 | 24859b68 | balrog | { |
1092 | 24859b68 | balrog | mv88w8618_timer_state *s; |
1093 | 24859b68 | balrog | QEMUBH *bh; |
1094 | 24859b68 | balrog | |
1095 | 24859b68 | balrog | s = qemu_mallocz(sizeof(mv88w8618_timer_state));
|
1096 | 24859b68 | balrog | s->irq = irq; |
1097 | 24859b68 | balrog | s->freq = freq; |
1098 | 24859b68 | balrog | |
1099 | 24859b68 | balrog | bh = qemu_bh_new(mv88w8618_timer_tick, s); |
1100 | 24859b68 | balrog | s->timer = ptimer_init(bh); |
1101 | 24859b68 | balrog | |
1102 | 24859b68 | balrog | return s;
|
1103 | 24859b68 | balrog | } |
1104 | 24859b68 | balrog | |
1105 | 24859b68 | balrog | static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset) |
1106 | 24859b68 | balrog | { |
1107 | 24859b68 | balrog | mv88w8618_pit_state *s = opaque; |
1108 | 24859b68 | balrog | mv88w8618_timer_state *t; |
1109 | 24859b68 | balrog | |
1110 | 24859b68 | balrog | switch (offset) {
|
1111 | 24859b68 | balrog | case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
|
1112 | 24859b68 | balrog | t = s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
|
1113 | 24859b68 | balrog | return ptimer_get_count(t->timer);
|
1114 | 24859b68 | balrog | |
1115 | 24859b68 | balrog | default:
|
1116 | 24859b68 | balrog | return 0; |
1117 | 24859b68 | balrog | } |
1118 | 24859b68 | balrog | } |
1119 | 24859b68 | balrog | |
1120 | 24859b68 | balrog | static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset, |
1121 | 24859b68 | balrog | uint32_t value) |
1122 | 24859b68 | balrog | { |
1123 | 24859b68 | balrog | mv88w8618_pit_state *s = opaque; |
1124 | 24859b68 | balrog | mv88w8618_timer_state *t; |
1125 | 24859b68 | balrog | int i;
|
1126 | 24859b68 | balrog | |
1127 | 24859b68 | balrog | switch (offset) {
|
1128 | 24859b68 | balrog | case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
|
1129 | 24859b68 | balrog | t = s->timer[offset >> 2];
|
1130 | 24859b68 | balrog | t->limit = value; |
1131 | 24859b68 | balrog | ptimer_set_limit(t->timer, t->limit, 1);
|
1132 | 24859b68 | balrog | break;
|
1133 | 24859b68 | balrog | |
1134 | 24859b68 | balrog | case MP_PIT_CONTROL:
|
1135 | 24859b68 | balrog | for (i = 0; i < 4; i++) { |
1136 | 24859b68 | balrog | if (value & 0xf) { |
1137 | 24859b68 | balrog | t = s->timer[i]; |
1138 | 24859b68 | balrog | ptimer_set_limit(t->timer, t->limit, 0);
|
1139 | 24859b68 | balrog | ptimer_set_freq(t->timer, t->freq); |
1140 | 24859b68 | balrog | ptimer_run(t->timer, 0);
|
1141 | 24859b68 | balrog | } |
1142 | 24859b68 | balrog | value >>= 4;
|
1143 | 24859b68 | balrog | } |
1144 | 24859b68 | balrog | break;
|
1145 | 24859b68 | balrog | |
1146 | 24859b68 | balrog | case MP_BOARD_RESET:
|
1147 | 24859b68 | balrog | if (value == MP_BOARD_RESET_MAGIC)
|
1148 | 24859b68 | balrog | qemu_system_reset_request(); |
1149 | 24859b68 | balrog | break;
|
1150 | 24859b68 | balrog | } |
1151 | 24859b68 | balrog | } |
1152 | 24859b68 | balrog | |
1153 | 24859b68 | balrog | static CPUReadMemoryFunc *mv88w8618_pit_readfn[] = {
|
1154 | 24859b68 | balrog | mv88w8618_pit_read, |
1155 | 24859b68 | balrog | mv88w8618_pit_read, |
1156 | 24859b68 | balrog | mv88w8618_pit_read |
1157 | 24859b68 | balrog | }; |
1158 | 24859b68 | balrog | |
1159 | 24859b68 | balrog | static CPUWriteMemoryFunc *mv88w8618_pit_writefn[] = {
|
1160 | 24859b68 | balrog | mv88w8618_pit_write, |
1161 | 24859b68 | balrog | mv88w8618_pit_write, |
1162 | 24859b68 | balrog | mv88w8618_pit_write |
1163 | 24859b68 | balrog | }; |
1164 | 24859b68 | balrog | |
1165 | 24859b68 | balrog | static void mv88w8618_pit_init(uint32_t base, qemu_irq *pic, int irq) |
1166 | 24859b68 | balrog | { |
1167 | 24859b68 | balrog | int iomemtype;
|
1168 | 24859b68 | balrog | mv88w8618_pit_state *s; |
1169 | 24859b68 | balrog | |
1170 | 24859b68 | balrog | s = qemu_mallocz(sizeof(mv88w8618_pit_state));
|
1171 | 24859b68 | balrog | |
1172 | 24859b68 | balrog | /* Letting them all run at 1 MHz is likely just a pragmatic
|
1173 | 24859b68 | balrog | * simplification. */
|
1174 | 24859b68 | balrog | s->timer[0] = mv88w8618_timer_init(1000000, pic[irq]); |
1175 | 24859b68 | balrog | s->timer[1] = mv88w8618_timer_init(1000000, pic[irq + 1]); |
1176 | 24859b68 | balrog | s->timer[2] = mv88w8618_timer_init(1000000, pic[irq + 2]); |
1177 | 24859b68 | balrog | s->timer[3] = mv88w8618_timer_init(1000000, pic[irq + 3]); |
1178 | 24859b68 | balrog | |
1179 | 24859b68 | balrog | iomemtype = cpu_register_io_memory(0, mv88w8618_pit_readfn,
|
1180 | 24859b68 | balrog | mv88w8618_pit_writefn, s); |
1181 | 24859b68 | balrog | cpu_register_physical_memory(base, MP_PIT_SIZE, iomemtype); |
1182 | 24859b68 | balrog | } |
1183 | 24859b68 | balrog | |
1184 | 24859b68 | balrog | /* Flash config register offsets */
|
1185 | 24859b68 | balrog | #define MP_FLASHCFG_CFGR0 0x04 |
1186 | 24859b68 | balrog | |
1187 | 24859b68 | balrog | typedef struct mv88w8618_flashcfg_state { |
1188 | 24859b68 | balrog | uint32_t cfgr0; |
1189 | 24859b68 | balrog | } mv88w8618_flashcfg_state; |
1190 | 24859b68 | balrog | |
1191 | 24859b68 | balrog | static uint32_t mv88w8618_flashcfg_read(void *opaque, |
1192 | 24859b68 | balrog | target_phys_addr_t offset) |
1193 | 24859b68 | balrog | { |
1194 | 24859b68 | balrog | mv88w8618_flashcfg_state *s = opaque; |
1195 | 24859b68 | balrog | |
1196 | 24859b68 | balrog | switch (offset) {
|
1197 | 24859b68 | balrog | case MP_FLASHCFG_CFGR0:
|
1198 | 24859b68 | balrog | return s->cfgr0;
|
1199 | 24859b68 | balrog | |
1200 | 24859b68 | balrog | default:
|
1201 | 24859b68 | balrog | return 0; |
1202 | 24859b68 | balrog | } |
1203 | 24859b68 | balrog | } |
1204 | 24859b68 | balrog | |
1205 | 24859b68 | balrog | static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset, |
1206 | 24859b68 | balrog | uint32_t value) |
1207 | 24859b68 | balrog | { |
1208 | 24859b68 | balrog | mv88w8618_flashcfg_state *s = opaque; |
1209 | 24859b68 | balrog | |
1210 | 24859b68 | balrog | switch (offset) {
|
1211 | 24859b68 | balrog | case MP_FLASHCFG_CFGR0:
|
1212 | 24859b68 | balrog | s->cfgr0 = value; |
1213 | 24859b68 | balrog | break;
|
1214 | 24859b68 | balrog | } |
1215 | 24859b68 | balrog | } |
1216 | 24859b68 | balrog | |
1217 | 24859b68 | balrog | static CPUReadMemoryFunc *mv88w8618_flashcfg_readfn[] = {
|
1218 | 24859b68 | balrog | mv88w8618_flashcfg_read, |
1219 | 24859b68 | balrog | mv88w8618_flashcfg_read, |
1220 | 24859b68 | balrog | mv88w8618_flashcfg_read |
1221 | 24859b68 | balrog | }; |
1222 | 24859b68 | balrog | |
1223 | 24859b68 | balrog | static CPUWriteMemoryFunc *mv88w8618_flashcfg_writefn[] = {
|
1224 | 24859b68 | balrog | mv88w8618_flashcfg_write, |
1225 | 24859b68 | balrog | mv88w8618_flashcfg_write, |
1226 | 24859b68 | balrog | mv88w8618_flashcfg_write |
1227 | 24859b68 | balrog | }; |
1228 | 24859b68 | balrog | |
1229 | 24859b68 | balrog | static void mv88w8618_flashcfg_init(uint32_t base) |
1230 | 24859b68 | balrog | { |
1231 | 24859b68 | balrog | int iomemtype;
|
1232 | 24859b68 | balrog | mv88w8618_flashcfg_state *s; |
1233 | 24859b68 | balrog | |
1234 | 24859b68 | balrog | s = qemu_mallocz(sizeof(mv88w8618_flashcfg_state));
|
1235 | 24859b68 | balrog | |
1236 | 24859b68 | balrog | s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */ |
1237 | 24859b68 | balrog | iomemtype = cpu_register_io_memory(0, mv88w8618_flashcfg_readfn,
|
1238 | 24859b68 | balrog | mv88w8618_flashcfg_writefn, s); |
1239 | 24859b68 | balrog | cpu_register_physical_memory(base, MP_FLASHCFG_SIZE, iomemtype); |
1240 | 24859b68 | balrog | } |
1241 | 24859b68 | balrog | |
1242 | 718ec0be | malc | /* Misc register offsets */
|
1243 | 718ec0be | malc | #define MP_MISC_BOARD_REVISION 0x18 |
1244 | 718ec0be | malc | |
1245 | 718ec0be | malc | #define MP_BOARD_REVISION 0x31 |
1246 | 718ec0be | malc | |
1247 | 718ec0be | malc | static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset) |
1248 | 718ec0be | malc | { |
1249 | 718ec0be | malc | switch (offset) {
|
1250 | 718ec0be | malc | case MP_MISC_BOARD_REVISION:
|
1251 | 718ec0be | malc | return MP_BOARD_REVISION;
|
1252 | 718ec0be | malc | |
1253 | 718ec0be | malc | default:
|
1254 | 718ec0be | malc | return 0; |
1255 | 718ec0be | malc | } |
1256 | 718ec0be | malc | } |
1257 | 718ec0be | malc | |
1258 | 718ec0be | malc | static void musicpal_misc_write(void *opaque, target_phys_addr_t offset, |
1259 | 718ec0be | malc | uint32_t value) |
1260 | 718ec0be | malc | { |
1261 | 718ec0be | malc | } |
1262 | 718ec0be | malc | |
1263 | 718ec0be | malc | static CPUReadMemoryFunc *musicpal_misc_readfn[] = {
|
1264 | 718ec0be | malc | musicpal_misc_read, |
1265 | 718ec0be | malc | musicpal_misc_read, |
1266 | 718ec0be | malc | musicpal_misc_read, |
1267 | 718ec0be | malc | }; |
1268 | 718ec0be | malc | |
1269 | 718ec0be | malc | static CPUWriteMemoryFunc *musicpal_misc_writefn[] = {
|
1270 | 718ec0be | malc | musicpal_misc_write, |
1271 | 718ec0be | malc | musicpal_misc_write, |
1272 | 718ec0be | malc | musicpal_misc_write, |
1273 | 718ec0be | malc | }; |
1274 | 718ec0be | malc | |
1275 | 718ec0be | malc | static void musicpal_misc_init(void) |
1276 | 718ec0be | malc | { |
1277 | 718ec0be | malc | int iomemtype;
|
1278 | 718ec0be | malc | |
1279 | 718ec0be | malc | iomemtype = cpu_register_io_memory(0, musicpal_misc_readfn,
|
1280 | 718ec0be | malc | musicpal_misc_writefn, NULL);
|
1281 | 718ec0be | malc | cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype); |
1282 | 718ec0be | malc | } |
1283 | 718ec0be | malc | |
1284 | 718ec0be | malc | /* WLAN register offsets */
|
1285 | 718ec0be | malc | #define MP_WLAN_MAGIC1 0x11c |
1286 | 718ec0be | malc | #define MP_WLAN_MAGIC2 0x124 |
1287 | 718ec0be | malc | |
1288 | 718ec0be | malc | static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset) |
1289 | 718ec0be | malc | { |
1290 | 718ec0be | malc | switch (offset) {
|
1291 | 718ec0be | malc | /* Workaround to allow loading the binary-only wlandrv.ko crap
|
1292 | 718ec0be | malc | * from the original Freecom firmware. */
|
1293 | 718ec0be | malc | case MP_WLAN_MAGIC1:
|
1294 | 718ec0be | malc | return ~3; |
1295 | 718ec0be | malc | case MP_WLAN_MAGIC2:
|
1296 | 718ec0be | malc | return -1; |
1297 | 718ec0be | malc | |
1298 | 718ec0be | malc | default:
|
1299 | 718ec0be | malc | return 0; |
1300 | 718ec0be | malc | } |
1301 | 718ec0be | malc | } |
1302 | 718ec0be | malc | |
1303 | 718ec0be | malc | static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset, |
1304 | 718ec0be | malc | uint32_t value) |
1305 | 718ec0be | malc | { |
1306 | 718ec0be | malc | } |
1307 | 718ec0be | malc | |
1308 | 718ec0be | malc | static CPUReadMemoryFunc *mv88w8618_wlan_readfn[] = {
|
1309 | 718ec0be | malc | mv88w8618_wlan_read, |
1310 | 718ec0be | malc | mv88w8618_wlan_read, |
1311 | 718ec0be | malc | mv88w8618_wlan_read, |
1312 | 718ec0be | malc | }; |
1313 | 718ec0be | malc | |
1314 | 718ec0be | malc | static CPUWriteMemoryFunc *mv88w8618_wlan_writefn[] = {
|
1315 | 718ec0be | malc | mv88w8618_wlan_write, |
1316 | 718ec0be | malc | mv88w8618_wlan_write, |
1317 | 718ec0be | malc | mv88w8618_wlan_write, |
1318 | 718ec0be | malc | }; |
1319 | 718ec0be | malc | |
1320 | 718ec0be | malc | static void mv88w8618_wlan_init(uint32_t base) |
1321 | 718ec0be | malc | { |
1322 | 718ec0be | malc | int iomemtype;
|
1323 | 24859b68 | balrog | |
1324 | 718ec0be | malc | iomemtype = cpu_register_io_memory(0, mv88w8618_wlan_readfn,
|
1325 | 718ec0be | malc | mv88w8618_wlan_writefn, NULL);
|
1326 | 718ec0be | malc | cpu_register_physical_memory(base, MP_WLAN_SIZE, iomemtype); |
1327 | 718ec0be | malc | } |
1328 | 24859b68 | balrog | |
1329 | 718ec0be | malc | /* GPIO register offsets */
|
1330 | 718ec0be | malc | #define MP_GPIO_OE_LO 0x008 |
1331 | 718ec0be | malc | #define MP_GPIO_OUT_LO 0x00c |
1332 | 718ec0be | malc | #define MP_GPIO_IN_LO 0x010 |
1333 | 718ec0be | malc | #define MP_GPIO_ISR_LO 0x020 |
1334 | 718ec0be | malc | #define MP_GPIO_OE_HI 0x508 |
1335 | 718ec0be | malc | #define MP_GPIO_OUT_HI 0x50c |
1336 | 718ec0be | malc | #define MP_GPIO_IN_HI 0x510 |
1337 | 718ec0be | malc | #define MP_GPIO_ISR_HI 0x520 |
1338 | 24859b68 | balrog | |
1339 | 24859b68 | balrog | /* GPIO bits & masks */
|
1340 | 24859b68 | balrog | #define MP_GPIO_WHEEL_VOL (1 << 8) |
1341 | 24859b68 | balrog | #define MP_GPIO_WHEEL_VOL_INV (1 << 9) |
1342 | 24859b68 | balrog | #define MP_GPIO_WHEEL_NAV (1 << 10) |
1343 | 24859b68 | balrog | #define MP_GPIO_WHEEL_NAV_INV (1 << 11) |
1344 | 24859b68 | balrog | #define MP_GPIO_LCD_BRIGHTNESS 0x00070000 |
1345 | 24859b68 | balrog | #define MP_GPIO_BTN_FAVORITS (1 << 19) |
1346 | 24859b68 | balrog | #define MP_GPIO_BTN_MENU (1 << 20) |
1347 | 24859b68 | balrog | #define MP_GPIO_BTN_VOLUME (1 << 21) |
1348 | 24859b68 | balrog | #define MP_GPIO_BTN_NAVIGATION (1 << 22) |
1349 | 24859b68 | balrog | #define MP_GPIO_I2C_DATA_BIT 29 |
1350 | 24859b68 | balrog | #define MP_GPIO_I2C_DATA (1 << MP_GPIO_I2C_DATA_BIT) |
1351 | 24859b68 | balrog | #define MP_GPIO_I2C_CLOCK_BIT 30 |
1352 | 24859b68 | balrog | |
1353 | 24859b68 | balrog | /* LCD brightness bits in GPIO_OE_HI */
|
1354 | 24859b68 | balrog | #define MP_OE_LCD_BRIGHTNESS 0x0007 |
1355 | 24859b68 | balrog | |
1356 | 718ec0be | malc | static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset) |
1357 | 24859b68 | balrog | { |
1358 | 24859b68 | balrog | switch (offset) {
|
1359 | 24859b68 | balrog | case MP_GPIO_OE_HI: /* used for LCD brightness control */ |
1360 | 24859b68 | balrog | return lcd_brightness & MP_OE_LCD_BRIGHTNESS;
|
1361 | 24859b68 | balrog | |
1362 | 24859b68 | balrog | case MP_GPIO_OUT_LO:
|
1363 | 24859b68 | balrog | return gpio_out_state & 0xFFFF; |
1364 | 24859b68 | balrog | case MP_GPIO_OUT_HI:
|
1365 | 24859b68 | balrog | return gpio_out_state >> 16; |
1366 | 24859b68 | balrog | |
1367 | 24859b68 | balrog | case MP_GPIO_IN_LO:
|
1368 | 24859b68 | balrog | return gpio_in_state & 0xFFFF; |
1369 | 24859b68 | balrog | case MP_GPIO_IN_HI:
|
1370 | 24859b68 | balrog | /* Update received I2C data */
|
1371 | 24859b68 | balrog | gpio_in_state = (gpio_in_state & ~MP_GPIO_I2C_DATA) | |
1372 | 24859b68 | balrog | (i2c_get_data(mixer_i2c) << MP_GPIO_I2C_DATA_BIT); |
1373 | 24859b68 | balrog | return gpio_in_state >> 16; |
1374 | 24859b68 | balrog | |
1375 | 24859b68 | balrog | case MP_GPIO_ISR_LO:
|
1376 | 7c6ce4ba | balrog | return gpio_isr & 0xFFFF; |
1377 | 24859b68 | balrog | case MP_GPIO_ISR_HI:
|
1378 | 7c6ce4ba | balrog | return gpio_isr >> 16; |
1379 | 24859b68 | balrog | |
1380 | 24859b68 | balrog | default:
|
1381 | 24859b68 | balrog | return 0; |
1382 | 24859b68 | balrog | } |
1383 | 24859b68 | balrog | } |
1384 | 24859b68 | balrog | |
1385 | 718ec0be | malc | static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset, |
1386 | 718ec0be | malc | uint32_t value) |
1387 | 24859b68 | balrog | { |
1388 | 24859b68 | balrog | switch (offset) {
|
1389 | 24859b68 | balrog | case MP_GPIO_OE_HI: /* used for LCD brightness control */ |
1390 | 24859b68 | balrog | lcd_brightness = (lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) | |
1391 | 24859b68 | balrog | (value & MP_OE_LCD_BRIGHTNESS); |
1392 | 24859b68 | balrog | break;
|
1393 | 24859b68 | balrog | |
1394 | 24859b68 | balrog | case MP_GPIO_OUT_LO:
|
1395 | 24859b68 | balrog | gpio_out_state = (gpio_out_state & 0xFFFF0000) | (value & 0xFFFF); |
1396 | 24859b68 | balrog | break;
|
1397 | 24859b68 | balrog | case MP_GPIO_OUT_HI:
|
1398 | 24859b68 | balrog | gpio_out_state = (gpio_out_state & 0xFFFF) | (value << 16); |
1399 | 24859b68 | balrog | lcd_brightness = (lcd_brightness & 0xFFFF) |
|
1400 | 24859b68 | balrog | (gpio_out_state & MP_GPIO_LCD_BRIGHTNESS); |
1401 | 24859b68 | balrog | i2c_state_update(mixer_i2c, |
1402 | 24859b68 | balrog | (gpio_out_state >> MP_GPIO_I2C_DATA_BIT) & 1,
|
1403 | 24859b68 | balrog | (gpio_out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
|
1404 | 24859b68 | balrog | break;
|
1405 | 24859b68 | balrog | |
1406 | 24859b68 | balrog | } |
1407 | 24859b68 | balrog | } |
1408 | 24859b68 | balrog | |
1409 | 718ec0be | malc | static CPUReadMemoryFunc *musicpal_gpio_readfn[] = {
|
1410 | 718ec0be | malc | musicpal_gpio_read, |
1411 | 718ec0be | malc | musicpal_gpio_read, |
1412 | 718ec0be | malc | musicpal_gpio_read, |
1413 | 718ec0be | malc | }; |
1414 | 718ec0be | malc | |
1415 | 718ec0be | malc | static CPUWriteMemoryFunc *musicpal_gpio_writefn[] = {
|
1416 | 718ec0be | malc | musicpal_gpio_write, |
1417 | 718ec0be | malc | musicpal_gpio_write, |
1418 | 718ec0be | malc | musicpal_gpio_write, |
1419 | 718ec0be | malc | }; |
1420 | 718ec0be | malc | |
1421 | 718ec0be | malc | static void musicpal_gpio_init(void) |
1422 | 718ec0be | malc | { |
1423 | 718ec0be | malc | int iomemtype;
|
1424 | 718ec0be | malc | |
1425 | 718ec0be | malc | iomemtype = cpu_register_io_memory(0, musicpal_gpio_readfn,
|
1426 | 718ec0be | malc | musicpal_gpio_writefn, NULL);
|
1427 | 718ec0be | malc | cpu_register_physical_memory(MP_GPIO_BASE, MP_GPIO_SIZE, iomemtype); |
1428 | 718ec0be | malc | } |
1429 | 718ec0be | malc | |
1430 | 24859b68 | balrog | /* Keyboard codes & masks */
|
1431 | 7c6ce4ba | balrog | #define KEY_RELEASED 0x80 |
1432 | 24859b68 | balrog | #define KEY_CODE 0x7f |
1433 | 24859b68 | balrog | |
1434 | 24859b68 | balrog | #define KEYCODE_TAB 0x0f |
1435 | 24859b68 | balrog | #define KEYCODE_ENTER 0x1c |
1436 | 24859b68 | balrog | #define KEYCODE_F 0x21 |
1437 | 24859b68 | balrog | #define KEYCODE_M 0x32 |
1438 | 24859b68 | balrog | |
1439 | 24859b68 | balrog | #define KEYCODE_EXTENDED 0xe0 |
1440 | 24859b68 | balrog | #define KEYCODE_UP 0x48 |
1441 | 24859b68 | balrog | #define KEYCODE_DOWN 0x50 |
1442 | 24859b68 | balrog | #define KEYCODE_LEFT 0x4b |
1443 | 24859b68 | balrog | #define KEYCODE_RIGHT 0x4d |
1444 | 24859b68 | balrog | |
1445 | 24859b68 | balrog | static void musicpal_key_event(void *opaque, int keycode) |
1446 | 24859b68 | balrog | { |
1447 | 24859b68 | balrog | qemu_irq irq = opaque; |
1448 | 24859b68 | balrog | uint32_t event = 0;
|
1449 | 24859b68 | balrog | static int kbd_extended; |
1450 | 24859b68 | balrog | |
1451 | 24859b68 | balrog | if (keycode == KEYCODE_EXTENDED) {
|
1452 | 24859b68 | balrog | kbd_extended = 1;
|
1453 | 24859b68 | balrog | return;
|
1454 | 24859b68 | balrog | } |
1455 | 24859b68 | balrog | |
1456 | 24859b68 | balrog | if (kbd_extended)
|
1457 | 24859b68 | balrog | switch (keycode & KEY_CODE) {
|
1458 | 24859b68 | balrog | case KEYCODE_UP:
|
1459 | 24859b68 | balrog | event = MP_GPIO_WHEEL_NAV | MP_GPIO_WHEEL_NAV_INV; |
1460 | 24859b68 | balrog | break;
|
1461 | 24859b68 | balrog | |
1462 | 24859b68 | balrog | case KEYCODE_DOWN:
|
1463 | 24859b68 | balrog | event = MP_GPIO_WHEEL_NAV; |
1464 | 24859b68 | balrog | break;
|
1465 | 24859b68 | balrog | |
1466 | 24859b68 | balrog | case KEYCODE_LEFT:
|
1467 | 24859b68 | balrog | event = MP_GPIO_WHEEL_VOL | MP_GPIO_WHEEL_VOL_INV; |
1468 | 24859b68 | balrog | break;
|
1469 | 24859b68 | balrog | |
1470 | 24859b68 | balrog | case KEYCODE_RIGHT:
|
1471 | 24859b68 | balrog | event = MP_GPIO_WHEEL_VOL; |
1472 | 24859b68 | balrog | break;
|
1473 | 24859b68 | balrog | } |
1474 | 7c6ce4ba | balrog | else {
|
1475 | 24859b68 | balrog | switch (keycode & KEY_CODE) {
|
1476 | 24859b68 | balrog | case KEYCODE_F:
|
1477 | 24859b68 | balrog | event = MP_GPIO_BTN_FAVORITS; |
1478 | 24859b68 | balrog | break;
|
1479 | 24859b68 | balrog | |
1480 | 24859b68 | balrog | case KEYCODE_TAB:
|
1481 | 24859b68 | balrog | event = MP_GPIO_BTN_VOLUME; |
1482 | 24859b68 | balrog | break;
|
1483 | 24859b68 | balrog | |
1484 | 24859b68 | balrog | case KEYCODE_ENTER:
|
1485 | 24859b68 | balrog | event = MP_GPIO_BTN_NAVIGATION; |
1486 | 24859b68 | balrog | break;
|
1487 | 24859b68 | balrog | |
1488 | 24859b68 | balrog | case KEYCODE_M:
|
1489 | 24859b68 | balrog | event = MP_GPIO_BTN_MENU; |
1490 | 24859b68 | balrog | break;
|
1491 | 24859b68 | balrog | } |
1492 | 7c6ce4ba | balrog | /* Do not repeat already pressed buttons */
|
1493 | 7c6ce4ba | balrog | if (!(keycode & KEY_RELEASED) && !(gpio_in_state & event))
|
1494 | 7c6ce4ba | balrog | event = 0;
|
1495 | 7c6ce4ba | balrog | } |
1496 | 24859b68 | balrog | |
1497 | 7c6ce4ba | balrog | if (event) {
|
1498 | 7c6ce4ba | balrog | if (keycode & KEY_RELEASED) {
|
1499 | 7c6ce4ba | balrog | gpio_in_state |= event; |
1500 | 7c6ce4ba | balrog | } else {
|
1501 | 7c6ce4ba | balrog | gpio_in_state &= ~event; |
1502 | 7c6ce4ba | balrog | gpio_isr = event; |
1503 | 7c6ce4ba | balrog | qemu_irq_raise(irq); |
1504 | 7c6ce4ba | balrog | } |
1505 | 24859b68 | balrog | } |
1506 | 24859b68 | balrog | |
1507 | 24859b68 | balrog | kbd_extended = 0;
|
1508 | 24859b68 | balrog | } |
1509 | 24859b68 | balrog | |
1510 | 24859b68 | balrog | static struct arm_boot_info musicpal_binfo = { |
1511 | 24859b68 | balrog | .loader_start = 0x0,
|
1512 | 24859b68 | balrog | .board_id = 0x20e,
|
1513 | 24859b68 | balrog | }; |
1514 | 24859b68 | balrog | |
1515 | fbe1b595 | Paul Brook | static void musicpal_init(ram_addr_t ram_size, |
1516 | 3023f332 | aliguori | const char *boot_device, |
1517 | 24859b68 | balrog | const char *kernel_filename, const char *kernel_cmdline, |
1518 | 24859b68 | balrog | const char *initrd_filename, const char *cpu_model) |
1519 | 24859b68 | balrog | { |
1520 | 24859b68 | balrog | CPUState *env; |
1521 | 24859b68 | balrog | qemu_irq *pic; |
1522 | 24859b68 | balrog | int index;
|
1523 | 24859b68 | balrog | unsigned long flash_size; |
1524 | 24859b68 | balrog | |
1525 | 24859b68 | balrog | if (!cpu_model)
|
1526 | 24859b68 | balrog | cpu_model = "arm926";
|
1527 | 24859b68 | balrog | |
1528 | 24859b68 | balrog | env = cpu_init(cpu_model); |
1529 | 24859b68 | balrog | if (!env) {
|
1530 | 24859b68 | balrog | fprintf(stderr, "Unable to find CPU definition\n");
|
1531 | 24859b68 | balrog | exit(1);
|
1532 | 24859b68 | balrog | } |
1533 | 24859b68 | balrog | pic = arm_pic_init_cpu(env); |
1534 | 24859b68 | balrog | |
1535 | 24859b68 | balrog | /* For now we use a fixed - the original - RAM size */
|
1536 | 24859b68 | balrog | cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
|
1537 | 24859b68 | balrog | qemu_ram_alloc(MP_RAM_DEFAULT_SIZE)); |
1538 | 24859b68 | balrog | |
1539 | 24859b68 | balrog | sram_off = qemu_ram_alloc(MP_SRAM_SIZE); |
1540 | 24859b68 | balrog | cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off); |
1541 | 24859b68 | balrog | |
1542 | 24859b68 | balrog | pic = mv88w8618_pic_init(MP_PIC_BASE, pic[ARM_PIC_CPU_IRQ]); |
1543 | 24859b68 | balrog | mv88w8618_pit_init(MP_PIT_BASE, pic, MP_TIMER1_IRQ); |
1544 | 24859b68 | balrog | |
1545 | 24859b68 | balrog | if (serial_hds[0]) |
1546 | b6cd0ea1 | aurel32 | serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000, |
1547 | 24859b68 | balrog | serial_hds[0], 1); |
1548 | 24859b68 | balrog | if (serial_hds[1]) |
1549 | b6cd0ea1 | aurel32 | serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000, |
1550 | 24859b68 | balrog | serial_hds[1], 1); |
1551 | 24859b68 | balrog | |
1552 | 24859b68 | balrog | /* Register flash */
|
1553 | 24859b68 | balrog | index = drive_get_index(IF_PFLASH, 0, 0); |
1554 | 24859b68 | balrog | if (index != -1) { |
1555 | 24859b68 | balrog | flash_size = bdrv_getlength(drives_table[index].bdrv); |
1556 | 24859b68 | balrog | if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 && |
1557 | 24859b68 | balrog | flash_size != 32*1024*1024) { |
1558 | 24859b68 | balrog | fprintf(stderr, "Invalid flash image size\n");
|
1559 | 24859b68 | balrog | exit(1);
|
1560 | 24859b68 | balrog | } |
1561 | 24859b68 | balrog | |
1562 | 24859b68 | balrog | /*
|
1563 | 24859b68 | balrog | * The original U-Boot accesses the flash at 0xFE000000 instead of
|
1564 | 24859b68 | balrog | * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
|
1565 | 24859b68 | balrog | * image is smaller than 32 MB.
|
1566 | 24859b68 | balrog | */
|
1567 | 24859b68 | balrog | pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
|
1568 | 24859b68 | balrog | drives_table[index].bdrv, 0x10000,
|
1569 | 24859b68 | balrog | (flash_size + 0xffff) >> 16, |
1570 | 24859b68 | balrog | MP_FLASH_SIZE_MAX / flash_size, |
1571 | 24859b68 | balrog | 2, 0x00BF, 0x236D, 0x0000, 0x0000, |
1572 | 24859b68 | balrog | 0x5555, 0x2AAA); |
1573 | 24859b68 | balrog | } |
1574 | 24859b68 | balrog | mv88w8618_flashcfg_init(MP_FLASHCFG_BASE); |
1575 | 24859b68 | balrog | |
1576 | 718ec0be | malc | musicpal_lcd_init(); |
1577 | 24859b68 | balrog | |
1578 | 24859b68 | balrog | qemu_add_kbd_event_handler(musicpal_key_event, pic[MP_GPIO_IRQ]); |
1579 | 24859b68 | balrog | |
1580 | 24859b68 | balrog | mv88w8618_eth_init(&nd_table[0], MP_ETH_BASE, pic[MP_ETH_IRQ]);
|
1581 | 24859b68 | balrog | |
1582 | 718ec0be | malc | mixer_i2c = musicpal_audio_init(pic[MP_AUDIO_IRQ]); |
1583 | 718ec0be | malc | |
1584 | 718ec0be | malc | mv88w8618_wlan_init(MP_WLAN_BASE); |
1585 | 718ec0be | malc | |
1586 | 718ec0be | malc | musicpal_misc_init(); |
1587 | 718ec0be | malc | musicpal_gpio_init(); |
1588 | 24859b68 | balrog | |
1589 | 24859b68 | balrog | musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; |
1590 | 24859b68 | balrog | musicpal_binfo.kernel_filename = kernel_filename; |
1591 | 24859b68 | balrog | musicpal_binfo.kernel_cmdline = kernel_cmdline; |
1592 | 24859b68 | balrog | musicpal_binfo.initrd_filename = initrd_filename; |
1593 | b0f6edb1 | balrog | arm_load_kernel(env, &musicpal_binfo); |
1594 | 24859b68 | balrog | } |
1595 | 24859b68 | balrog | |
1596 | 24859b68 | balrog | QEMUMachine musicpal_machine = { |
1597 | 4b32e168 | aliguori | .name = "musicpal",
|
1598 | 4b32e168 | aliguori | .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
|
1599 | 4b32e168 | aliguori | .init = musicpal_init, |
1600 | 24859b68 | balrog | }; |