root / tcg / tcg-opc.h @ fbeaa26c
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| 1 | c896fe29 | bellard | /*
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| 2 | c896fe29 | bellard | * Tiny Code Generator for QEMU
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| 3 | c896fe29 | bellard | *
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| 4 | c896fe29 | bellard | * Copyright (c) 2008 Fabrice Bellard
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| 5 | c896fe29 | bellard | *
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| 6 | c896fe29 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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| 7 | c896fe29 | bellard | * of this software and associated documentation files (the "Software"), to deal
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| 8 | c896fe29 | bellard | * in the Software without restriction, including without limitation the rights
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| 9 | c896fe29 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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| 10 | c896fe29 | bellard | * copies of the Software, and to permit persons to whom the Software is
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| 11 | c896fe29 | bellard | * furnished to do so, subject to the following conditions:
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| 12 | c896fe29 | bellard | *
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| 13 | c896fe29 | bellard | * The above copyright notice and this permission notice shall be included in
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| 14 | c896fe29 | bellard | * all copies or substantial portions of the Software.
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| 15 | c896fe29 | bellard | *
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| 16 | c896fe29 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 17 | c896fe29 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 18 | c896fe29 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 19 | c896fe29 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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| 20 | c896fe29 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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| 21 | c896fe29 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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| 22 | c896fe29 | bellard | * THE SOFTWARE.
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| 23 | c896fe29 | bellard | */
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| 24 | c61aaf7a | Aurelien Jarno | |
| 25 | c61aaf7a | Aurelien Jarno | /*
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| 26 | c61aaf7a | Aurelien Jarno | * DEF(name, oargs, iargs, cargs, flags)
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| 27 | c61aaf7a | Aurelien Jarno | */
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| 28 | c896fe29 | bellard | |
| 29 | c896fe29 | bellard | /* predefined ops */
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| 30 | c61aaf7a | Aurelien Jarno | DEF(end, 0, 0, 0, 0) /* must be kept first */ |
| 31 | c61aaf7a | Aurelien Jarno | DEF(nop, 0, 0, 0, 0) |
| 32 | c61aaf7a | Aurelien Jarno | DEF(nop1, 0, 0, 1, 0) |
| 33 | c61aaf7a | Aurelien Jarno | DEF(nop2, 0, 0, 2, 0) |
| 34 | c61aaf7a | Aurelien Jarno | DEF(nop3, 0, 0, 3, 0) |
| 35 | c61aaf7a | Aurelien Jarno | DEF(nopn, 0, 0, 1, 0) /* variable number of parameters */ |
| 36 | c896fe29 | bellard | |
| 37 | c61aaf7a | Aurelien Jarno | DEF(discard, 1, 0, 0, 0) |
| 38 | 5ff9d6a4 | bellard | |
| 39 | c61aaf7a | Aurelien Jarno | DEF(set_label, 0, 0, 1, 0) |
| 40 | c61aaf7a | Aurelien Jarno | DEF(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */ |
| 41 | c61aaf7a | Aurelien Jarno | DEF(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
| 42 | c61aaf7a | Aurelien Jarno | DEF(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
| 43 | c896fe29 | bellard | |
| 44 | 25c4d9cc | Richard Henderson | #define IMPL(X) (X ? 0 : TCG_OPF_NOT_PRESENT) |
| 45 | 25c4d9cc | Richard Henderson | #if TCG_TARGET_REG_BITS == 32 |
| 46 | 25c4d9cc | Richard Henderson | # define IMPL64 TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
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| 47 | 25c4d9cc | Richard Henderson | #else
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| 48 | 25c4d9cc | Richard Henderson | # define IMPL64 TCG_OPF_64BIT
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| 49 | 25c4d9cc | Richard Henderson | #endif
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| 50 | 25c4d9cc | Richard Henderson | |
| 51 | c61aaf7a | Aurelien Jarno | DEF(mov_i32, 1, 1, 0, 0) |
| 52 | c61aaf7a | Aurelien Jarno | DEF(movi_i32, 1, 0, 1, 0) |
| 53 | c61aaf7a | Aurelien Jarno | DEF(setcond_i32, 1, 2, 1, 0) |
| 54 | c896fe29 | bellard | /* load/store */
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| 55 | c61aaf7a | Aurelien Jarno | DEF(ld8u_i32, 1, 1, 1, 0) |
| 56 | c61aaf7a | Aurelien Jarno | DEF(ld8s_i32, 1, 1, 1, 0) |
| 57 | c61aaf7a | Aurelien Jarno | DEF(ld16u_i32, 1, 1, 1, 0) |
| 58 | c61aaf7a | Aurelien Jarno | DEF(ld16s_i32, 1, 1, 1, 0) |
| 59 | c61aaf7a | Aurelien Jarno | DEF(ld_i32, 1, 1, 1, 0) |
| 60 | c61aaf7a | Aurelien Jarno | DEF(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
| 61 | c61aaf7a | Aurelien Jarno | DEF(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
| 62 | c61aaf7a | Aurelien Jarno | DEF(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
| 63 | c896fe29 | bellard | /* arith */
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| 64 | c61aaf7a | Aurelien Jarno | DEF(add_i32, 1, 2, 0, 0) |
| 65 | c61aaf7a | Aurelien Jarno | DEF(sub_i32, 1, 2, 0, 0) |
| 66 | c61aaf7a | Aurelien Jarno | DEF(mul_i32, 1, 2, 0, 0) |
| 67 | 25c4d9cc | Richard Henderson | DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) |
| 68 | 25c4d9cc | Richard Henderson | DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) |
| 69 | 25c4d9cc | Richard Henderson | DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) |
| 70 | 25c4d9cc | Richard Henderson | DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) |
| 71 | 25c4d9cc | Richard Henderson | DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32)) |
| 72 | 25c4d9cc | Richard Henderson | DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32)) |
| 73 | c61aaf7a | Aurelien Jarno | DEF(and_i32, 1, 2, 0, 0) |
| 74 | c61aaf7a | Aurelien Jarno | DEF(or_i32, 1, 2, 0, 0) |
| 75 | c61aaf7a | Aurelien Jarno | DEF(xor_i32, 1, 2, 0, 0) |
| 76 | d42f183c | aurel32 | /* shifts/rotates */
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| 77 | c61aaf7a | Aurelien Jarno | DEF(shl_i32, 1, 2, 0, 0) |
| 78 | c61aaf7a | Aurelien Jarno | DEF(shr_i32, 1, 2, 0, 0) |
| 79 | c61aaf7a | Aurelien Jarno | DEF(sar_i32, 1, 2, 0, 0) |
| 80 | 25c4d9cc | Richard Henderson | DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32)) |
| 81 | 25c4d9cc | Richard Henderson | DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32)) |
| 82 | 25c4d9cc | Richard Henderson | DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32)) |
| 83 | c896fe29 | bellard | |
| 84 | c61aaf7a | Aurelien Jarno | DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
| 85 | c896fe29 | bellard | |
| 86 | 25c4d9cc | Richard Henderson | DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_REG_BITS == 32)) |
| 87 | 25c4d9cc | Richard Henderson | DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_REG_BITS == 32)) |
| 88 | 25c4d9cc | Richard Henderson | DEF(brcond2_i32, 0, 4, 2, |
| 89 | 25c4d9cc | Richard Henderson | TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS | IMPL(TCG_TARGET_REG_BITS == 32))
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| 90 | 25c4d9cc | Richard Henderson | DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_REG_BITS == 32)) |
| 91 | 25c4d9cc | Richard Henderson | DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32)) |
| 92 | 25c4d9cc | Richard Henderson | |
| 93 | 25c4d9cc | Richard Henderson | DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32)) |
| 94 | 25c4d9cc | Richard Henderson | DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32)) |
| 95 | 25c4d9cc | Richard Henderson | DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32)) |
| 96 | 25c4d9cc | Richard Henderson | DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32)) |
| 97 | 25c4d9cc | Richard Henderson | DEF(bswap16_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32)) |
| 98 | 25c4d9cc | Richard Henderson | DEF(bswap32_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32)) |
| 99 | 25c4d9cc | Richard Henderson | DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32)) |
| 100 | 25c4d9cc | Richard Henderson | DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32)) |
| 101 | 25c4d9cc | Richard Henderson | DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32)) |
| 102 | 25c4d9cc | Richard Henderson | DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32)) |
| 103 | 25c4d9cc | Richard Henderson | DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32)) |
| 104 | 25c4d9cc | Richard Henderson | DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32)) |
| 105 | 25c4d9cc | Richard Henderson | DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32)) |
| 106 | 25c4d9cc | Richard Henderson | |
| 107 | 25c4d9cc | Richard Henderson | DEF(mov_i64, 1, 1, 0, IMPL64) |
| 108 | 25c4d9cc | Richard Henderson | DEF(movi_i64, 1, 0, 1, IMPL64) |
| 109 | 25c4d9cc | Richard Henderson | DEF(setcond_i64, 1, 2, 1, IMPL64) |
| 110 | c896fe29 | bellard | /* load/store */
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| 111 | 25c4d9cc | Richard Henderson | DEF(ld8u_i64, 1, 1, 1, IMPL64) |
| 112 | 25c4d9cc | Richard Henderson | DEF(ld8s_i64, 1, 1, 1, IMPL64) |
| 113 | 25c4d9cc | Richard Henderson | DEF(ld16u_i64, 1, 1, 1, IMPL64) |
| 114 | 25c4d9cc | Richard Henderson | DEF(ld16s_i64, 1, 1, 1, IMPL64) |
| 115 | 25c4d9cc | Richard Henderson | DEF(ld32u_i64, 1, 1, 1, IMPL64) |
| 116 | 25c4d9cc | Richard Henderson | DEF(ld32s_i64, 1, 1, 1, IMPL64) |
| 117 | 25c4d9cc | Richard Henderson | DEF(ld_i64, 1, 1, 1, IMPL64) |
| 118 | 25c4d9cc | Richard Henderson | DEF(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS | IMPL64) |
| 119 | 25c4d9cc | Richard Henderson | DEF(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS | IMPL64) |
| 120 | 25c4d9cc | Richard Henderson | DEF(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS | IMPL64) |
| 121 | 25c4d9cc | Richard Henderson | DEF(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS | IMPL64) |
| 122 | c896fe29 | bellard | /* arith */
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| 123 | 25c4d9cc | Richard Henderson | DEF(add_i64, 1, 2, 0, IMPL64) |
| 124 | 25c4d9cc | Richard Henderson | DEF(sub_i64, 1, 2, 0, IMPL64) |
| 125 | 25c4d9cc | Richard Henderson | DEF(mul_i64, 1, 2, 0, IMPL64) |
| 126 | 25c4d9cc | Richard Henderson | DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64)) |
| 127 | 25c4d9cc | Richard Henderson | DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64)) |
| 128 | 25c4d9cc | Richard Henderson | DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64)) |
| 129 | 25c4d9cc | Richard Henderson | DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64)) |
| 130 | 25c4d9cc | Richard Henderson | DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64)) |
| 131 | 25c4d9cc | Richard Henderson | DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64)) |
| 132 | 25c4d9cc | Richard Henderson | DEF(and_i64, 1, 2, 0, IMPL64) |
| 133 | 25c4d9cc | Richard Henderson | DEF(or_i64, 1, 2, 0, IMPL64) |
| 134 | 25c4d9cc | Richard Henderson | DEF(xor_i64, 1, 2, 0, IMPL64) |
| 135 | d42f183c | aurel32 | /* shifts/rotates */
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| 136 | 25c4d9cc | Richard Henderson | DEF(shl_i64, 1, 2, 0, IMPL64) |
| 137 | 25c4d9cc | Richard Henderson | DEF(shr_i64, 1, 2, 0, IMPL64) |
| 138 | 25c4d9cc | Richard Henderson | DEF(sar_i64, 1, 2, 0, IMPL64) |
| 139 | 25c4d9cc | Richard Henderson | DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64)) |
| 140 | 25c4d9cc | Richard Henderson | DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64)) |
| 141 | 25c4d9cc | Richard Henderson | DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64)) |
| 142 | c896fe29 | bellard | |
| 143 | 25c4d9cc | Richard Henderson | DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS | IMPL64) |
| 144 | 25c4d9cc | Richard Henderson | DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64)) |
| 145 | 25c4d9cc | Richard Henderson | DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64)) |
| 146 | 25c4d9cc | Richard Henderson | DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64)) |
| 147 | 25c4d9cc | Richard Henderson | DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64)) |
| 148 | 25c4d9cc | Richard Henderson | DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64)) |
| 149 | 25c4d9cc | Richard Henderson | DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64)) |
| 150 | 25c4d9cc | Richard Henderson | DEF(bswap16_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64)) |
| 151 | 25c4d9cc | Richard Henderson | DEF(bswap32_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64)) |
| 152 | 25c4d9cc | Richard Henderson | DEF(bswap64_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64)) |
| 153 | 25c4d9cc | Richard Henderson | DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64)) |
| 154 | 25c4d9cc | Richard Henderson | DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64)) |
| 155 | 25c4d9cc | Richard Henderson | DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64)) |
| 156 | 25c4d9cc | Richard Henderson | DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64)) |
| 157 | 25c4d9cc | Richard Henderson | DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64)) |
| 158 | 25c4d9cc | Richard Henderson | DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64)) |
| 159 | 25c4d9cc | Richard Henderson | DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64)) |
| 160 | c896fe29 | bellard | |
| 161 | c896fe29 | bellard | /* QEMU specific */
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| 162 | 7e4597d7 | bellard | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
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| 163 | c61aaf7a | Aurelien Jarno | DEF(debug_insn_start, 0, 0, 2, 0) |
| 164 | 7e4597d7 | bellard | #else
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| 165 | c61aaf7a | Aurelien Jarno | DEF(debug_insn_start, 0, 0, 1, 0) |
| 166 | 7e4597d7 | bellard | #endif
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| 167 | c61aaf7a | Aurelien Jarno | DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
| 168 | c61aaf7a | Aurelien Jarno | DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
| 169 | c896fe29 | bellard | /* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op
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| 170 | c896fe29 | bellard | constants must be defined */
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| 171 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 32 |
| 172 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 173 | c61aaf7a | Aurelien Jarno | DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 174 | c896fe29 | bellard | #else
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| 175 | c61aaf7a | Aurelien Jarno | DEF(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 176 | c896fe29 | bellard | #endif
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| 177 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 178 | c61aaf7a | Aurelien Jarno | DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 179 | c896fe29 | bellard | #else
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| 180 | c61aaf7a | Aurelien Jarno | DEF(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 181 | c896fe29 | bellard | #endif
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| 182 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 183 | c61aaf7a | Aurelien Jarno | DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 184 | c896fe29 | bellard | #else
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| 185 | c61aaf7a | Aurelien Jarno | DEF(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 186 | c896fe29 | bellard | #endif
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| 187 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 188 | c61aaf7a | Aurelien Jarno | DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 189 | c896fe29 | bellard | #else
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| 190 | c61aaf7a | Aurelien Jarno | DEF(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 191 | c896fe29 | bellard | #endif
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| 192 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 193 | c61aaf7a | Aurelien Jarno | DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 194 | c896fe29 | bellard | #else
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| 195 | c61aaf7a | Aurelien Jarno | DEF(qemu_ld32, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 196 | c896fe29 | bellard | #endif
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| 197 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 198 | c61aaf7a | Aurelien Jarno | DEF(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 199 | c896fe29 | bellard | #else
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| 200 | c61aaf7a | Aurelien Jarno | DEF(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 201 | c896fe29 | bellard | #endif
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| 202 | c896fe29 | bellard | |
| 203 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 204 | c61aaf7a | Aurelien Jarno | DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 205 | c896fe29 | bellard | #else
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| 206 | c61aaf7a | Aurelien Jarno | DEF(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 207 | c896fe29 | bellard | #endif
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| 208 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 209 | c61aaf7a | Aurelien Jarno | DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 210 | c896fe29 | bellard | #else
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| 211 | c61aaf7a | Aurelien Jarno | DEF(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 212 | c896fe29 | bellard | #endif
|
| 213 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 214 | c61aaf7a | Aurelien Jarno | DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 215 | c896fe29 | bellard | #else
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| 216 | c61aaf7a | Aurelien Jarno | DEF(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 217 | c896fe29 | bellard | #endif
|
| 218 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
| 219 | c61aaf7a | Aurelien Jarno | DEF(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 220 | c896fe29 | bellard | #else
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| 221 | c61aaf7a | Aurelien Jarno | DEF(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 222 | c896fe29 | bellard | #endif
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| 223 | c896fe29 | bellard | |
| 224 | c896fe29 | bellard | #else /* TCG_TARGET_REG_BITS == 32 */ |
| 225 | c896fe29 | bellard | |
| 226 | c61aaf7a | Aurelien Jarno | DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 227 | c61aaf7a | Aurelien Jarno | DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 228 | c61aaf7a | Aurelien Jarno | DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 229 | c61aaf7a | Aurelien Jarno | DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 230 | c61aaf7a | Aurelien Jarno | DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 231 | c61aaf7a | Aurelien Jarno | DEF(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 232 | c61aaf7a | Aurelien Jarno | DEF(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 233 | c61aaf7a | Aurelien Jarno | DEF(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 234 | c896fe29 | bellard | |
| 235 | c61aaf7a | Aurelien Jarno | DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 236 | c61aaf7a | Aurelien Jarno | DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 237 | c61aaf7a | Aurelien Jarno | DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 238 | c61aaf7a | Aurelien Jarno | DEF(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 239 | c896fe29 | bellard | |
| 240 | c896fe29 | bellard | #endif /* TCG_TARGET_REG_BITS != 32 */ |
| 241 | c896fe29 | bellard | |
| 242 | 25c4d9cc | Richard Henderson | #undef IMPL
|
| 243 | 25c4d9cc | Richard Henderson | #undef IMPL64
|
| 244 | c61aaf7a | Aurelien Jarno | #undef DEF |