Revision fc0b2c0f
| b/cpu-exec.c | ||
|---|---|---|
| 339 | 339 |
} |
| 340 | 340 |
} |
| 341 | 341 |
#elif defined(TARGET_PPC) |
| 342 |
#if 0 |
|
| 343 | 342 |
if ((interrupt_request & CPU_INTERRUPT_RESET)) {
|
| 344 | 343 |
cpu_reset(env); |
| 345 | 344 |
} |
| 346 |
#endif |
|
| 347 | 345 |
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
| 348 | 346 |
ppc_hw_interrupt(env); |
| 349 | 347 |
if (env->pending_interrupts == 0) |
| b/hw/ppc.c | ||
|---|---|---|
| 131 | 131 |
/* Level sensitive - active low */ |
| 132 | 132 |
if (level) {
|
| 133 | 133 |
LOG_IRQ("%s: reset the CPU\n", __func__);
|
| 134 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
|
| 135 |
/* XXX: TOFIX */ |
|
| 136 |
#if 0 |
|
| 137 |
cpu_reset(env); |
|
| 138 |
#else |
|
| 139 |
qemu_system_reset_request(); |
|
| 140 |
#endif |
|
| 134 |
cpu_interrupt(env, CPU_INTERRUPT_RESET); |
|
| 141 | 135 |
} |
| 142 | 136 |
break; |
| 143 | 137 |
case PPC6xx_INPUT_SRESET: |
| ... | ... | |
| 214 | 208 |
case PPC970_INPUT_HRESET: |
| 215 | 209 |
/* Level sensitive - active low */ |
| 216 | 210 |
if (level) {
|
| 217 |
#if 0 // XXX: TOFIX |
|
| 218 |
LOG_IRQ("%s: reset the CPU\n", __func__);
|
|
| 219 |
cpu_reset(env); |
|
| 220 |
#endif |
|
| 211 |
cpu_interrupt(env, CPU_INTERRUPT_RESET); |
|
| 221 | 212 |
} |
| 222 | 213 |
break; |
| 223 | 214 |
case PPC970_INPUT_SRESET: |
| b/hw/ppc405_uc.c | ||
|---|---|---|
| 1769 | 1769 |
target_ulong dbsr; |
| 1770 | 1770 |
|
| 1771 | 1771 |
printf("Reset PowerPC core\n");
|
| 1772 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
|
| 1773 |
/* XXX: TOFIX */ |
|
| 1774 |
#if 0 |
|
| 1775 |
cpu_reset(env); |
|
| 1776 |
#else |
|
| 1777 |
qemu_system_reset_request(); |
|
| 1778 |
#endif |
|
| 1772 |
cpu_interrupt(env, CPU_INTERRUPT_RESET); |
|
| 1779 | 1773 |
dbsr = env->spr[SPR_40x_DBSR]; |
| 1780 | 1774 |
dbsr &= ~0x00000300; |
| 1781 | 1775 |
dbsr |= 0x00000100; |
| ... | ... | |
| 1787 | 1781 |
target_ulong dbsr; |
| 1788 | 1782 |
|
| 1789 | 1783 |
printf("Reset PowerPC chip\n");
|
| 1790 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
|
| 1791 |
/* XXX: TOFIX */ |
|
| 1792 |
#if 0 |
|
| 1793 |
cpu_reset(env); |
|
| 1794 |
#else |
|
| 1795 |
qemu_system_reset_request(); |
|
| 1796 |
#endif |
|
| 1784 |
cpu_interrupt(env, CPU_INTERRUPT_RESET); |
|
| 1797 | 1785 |
/* XXX: TODO reset all internal peripherals */ |
| 1798 | 1786 |
dbsr = env->spr[SPR_40x_DBSR]; |
| 1799 | 1787 |
dbsr &= ~0x00000300; |
| b/target-ppc/cpu.h | ||
|---|---|---|
| 2051 | 2051 |
PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */ |
| 2052 | 2052 |
}; |
| 2053 | 2053 |
|
| 2054 |
/* CPU should be reset next, restart from scratch afterwards */ |
|
| 2055 |
#define CPU_INTERRUPT_RESET CPU_INTERRUPT_TGT_INT_0 |
|
| 2056 |
|
|
| 2054 | 2057 |
/*****************************************************************************/ |
| 2055 | 2058 |
|
| 2056 | 2059 |
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
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