Revision fc2b4c48 exec-i386.c
| b/exec-i386.c | ||
|---|---|---|
| 330 | 330 |
#endif |
| 331 | 331 |
|
| 332 | 332 |
/* put eflags in CPU temporary format */ |
| 333 |
T0 = env->eflags;
|
|
| 334 |
op_movl_eflags_T0();
|
|
| 333 |
CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
|
|
| 334 |
DF = 1 - (2 * ((env->eflags >> 10) & 1));
|
|
| 335 | 335 |
CC_OP = CC_OP_EFLAGS; |
| 336 |
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
|
| 336 | 337 |
env->interrupt_request = 0; |
| 337 | 338 |
|
| 338 | 339 |
/* prepare setjmp context for exception handling */ |
| ... | ... | |
| 354 | 355 |
(unsigned long)env->seg_cache[R_ES].base | |
| 355 | 356 |
(unsigned long)env->seg_cache[R_SS].base) != 0) << |
| 356 | 357 |
GEN_FLAG_ADDSEG_SHIFT; |
| 358 |
flags |= (env->eflags & VM_MASK) >> (17 - GEN_FLAG_VM_SHIFT); |
|
| 357 | 359 |
cs_base = env->seg_cache[R_CS].base; |
| 358 | 360 |
pc = cs_base + env->eip; |
| 359 | 361 |
tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, |
| ... | ... | |
| 390 | 392 |
ret = env->exception_index; |
| 391 | 393 |
|
| 392 | 394 |
/* restore flags in standard format */ |
| 393 |
op_movl_T0_eflags(); |
|
| 394 |
env->eflags = T0; |
|
| 395 |
env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
|
| 395 | 396 |
|
| 396 | 397 |
/* restore global registers */ |
| 397 | 398 |
#ifdef reg_EAX |
| ... | ... | |
| 489 | 490 |
/* for glibc 2.1 */ |
| 490 | 491 |
#define REG_EIP EIP |
| 491 | 492 |
#endif |
| 492 |
pc = uc->uc_mcontext.gregs[EIP]; |
|
| 493 |
pc = uc->uc_mcontext.gregs[REG_EIP];
|
|
| 493 | 494 |
pold_set = &uc->uc_sigmask; |
| 494 | 495 |
return handle_cpu_signal(pc, pold_set); |
| 495 | 496 |
#else |
Also available in: Unified diff