Revision fc2bf449
| b/hw/gt64xxx.c | ||
|---|---|---|
| 227 | 227 |
#define PCI_MAPPING_ENTRY(regname) \ |
| 228 | 228 |
target_phys_addr_t regname ##_start; \ |
| 229 | 229 |
target_phys_addr_t regname ##_length; \ |
| 230 |
int regname ##_handle
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|
| 230 |
MemoryRegion regname ##_mem
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|
| 231 | 231 |
|
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typedef struct GT64120State {
|
| 233 | 233 |
SysBusDevice busdev; |
| ... | ... | |
| 269 | 269 |
target_phys_addr_t start = s->regs[GT_ISD] << 21; |
| 270 | 270 |
target_phys_addr_t length = 0x1000; |
| 271 | 271 |
|
| 272 |
if (s->ISD_length) |
|
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cpu_register_physical_memory(s->ISD_start, s->ISD_length,
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IO_MEM_UNASSIGNED);
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| 272 |
if (s->ISD_length) {
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memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
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}
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|
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check_reserved_space(&start, &length); |
| 276 | 276 |
length = 0x1000; |
| 277 | 277 |
/* Map new address */ |
| ... | ... | |
| 279 | 279 |
length, start, s->ISD_handle); |
| 280 | 280 |
s->ISD_start = start; |
| 281 | 281 |
s->ISD_length = length; |
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cpu_register_physical_memory(s->ISD_start, s->ISD_length, s->ISD_handle);
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|
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memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
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|
| 283 | 283 |
} |
| 284 | 284 |
|
| 285 | 285 |
static void gt64120_pci_mapping(GT64120State *s) |
| ... | ... | |
| 290 | 290 |
/* Unmap old IO address */ |
| 291 | 291 |
if (s->PCI0IO_length) |
| 292 | 292 |
{
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cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED); |
|
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memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem); |
|
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memory_region_destroy(&s->PCI0IO_mem); |
|
| 294 | 295 |
} |
| 295 | 296 |
/* Map new IO address */ |
| 296 | 297 |
s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21; |
| ... | ... | |
| 301 | 302 |
} |
| 302 | 303 |
|
| 303 | 304 |
static void gt64120_writel (void *opaque, target_phys_addr_t addr, |
| 304 |
uint32_t val)
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uint64_t val, unsigned size)
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|
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{
|
| 306 | 307 |
GT64120State *s = opaque; |
| 307 | 308 |
uint32_t saddr; |
| ... | ... | |
| 579 | 580 |
} |
| 580 | 581 |
} |
| 581 | 582 |
|
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static uint32_t gt64120_readl (void *opaque,
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target_phys_addr_t addr) |
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static uint64_t gt64120_readl (void *opaque,
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target_phys_addr_t addr, unsigned size)
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| 584 | 585 |
{
|
| 585 | 586 |
GT64120State *s = opaque; |
| 586 | 587 |
uint32_t val; |
| ... | ... | |
| 851 | 852 |
return val; |
| 852 | 853 |
} |
| 853 | 854 |
|
| 854 |
static CPUWriteMemoryFunc * const gt64120_write[] = {
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>64120_writel, |
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>64120_writel, |
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>64120_writel, |
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}; |
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| 859 |
|
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static CPUReadMemoryFunc * const gt64120_read[] = {
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>64120_readl, |
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>64120_readl, |
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>64120_readl, |
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static const MemoryRegionOps isd_mem_ops = {
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.read = gt64120_readl, |
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.write = gt64120_writel, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
|
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}; |
| 865 | 860 |
|
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static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num) |
| ... | ... | |
| 1097 | 1092 |
get_system_memory(), |
| 1098 | 1093 |
get_system_io(), |
| 1099 | 1094 |
PCI_DEVFN(18, 0), 4); |
| 1100 |
d->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, d, |
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DEVICE_NATIVE_ENDIAN); |
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memory_region_init_io(&d->ISD_mem, &isd_mem_ops, d, "isd-mem", 0x1000); |
|
| 1102 | 1096 |
|
| 1103 | 1097 |
pci_create_simple(d->pci.bus, PCI_DEVFN(0, 0), "gt64120_pci"); |
| 1104 | 1098 |
return d->pci.bus; |
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