Revision fcb4a419 target-mips/op_helper.c
| b/target-mips/op_helper.c | ||
|---|---|---|
| 394 | 394 |
{
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| 395 | 395 |
/* Flush qemu's TLB and discard all shadowed entries. */ |
| 396 | 396 |
tlb_flush (env, flush_global); |
| 397 |
env->tlb_in_use = MIPS_TLB_NB;
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| 397 |
env->tlb_in_use = env->nb_tlb;
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} |
| 399 | 399 |
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static void mips_tlb_flush_extra (CPUState *env, int first) |
| ... | ... | |
| 430 | 430 |
/* Discard cached TLB entries. We could avoid doing this if the |
| 431 | 431 |
tlbwi is just upgrading access permissions on the current entry; |
| 432 | 432 |
that might be a further win. */ |
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mips_tlb_flush_extra (env, MIPS_TLB_NB);
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mips_tlb_flush_extra (env, env->nb_tlb);
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/* Wildly undefined effects for CP0_Index containing a too high value and |
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MIPS_TLB_NB not being a power of two. But so does real silicon. */ |
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invalidate_tlb(env, env->CP0_Index & (MIPS_TLB_NB - 1), 0); |
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fill_tlb(env->CP0_Index & (MIPS_TLB_NB - 1)); |
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invalidate_tlb(env, env->CP0_Index % env->nb_tlb, 0); |
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fill_tlb(env->CP0_Index % env->nb_tlb); |
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} |
| 440 | 438 |
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void do_tlbwr (void) |
| ... | ... | |
| 455 | 453 |
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tag = env->CP0_EntryHi & (int32_t)0xFFFFE000; |
| 457 | 455 |
ASID = env->CP0_EntryHi & 0xFF; |
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for (i = 0; i < MIPS_TLB_NB; i++) {
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for (i = 0; i < env->nb_tlb; i++) {
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tlb = &env->tlb[i]; |
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/* Check ASID, virtual page number & size */ |
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if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
|
| ... | ... | |
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break; |
| 465 | 463 |
} |
| 466 | 464 |
} |
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if (i == MIPS_TLB_NB) {
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if (i == env->nb_tlb) {
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| 468 | 466 |
/* No match. Discard any shadow entries, if any of them match. */ |
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for (i = MIPS_TLB_NB; i < env->tlb_in_use; i++) {
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for (i = env->nb_tlb; i < env->tlb_in_use; i++) {
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| 470 | 468 |
tlb = &env->tlb[i]; |
| 471 | 469 |
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/* Check ASID, virtual page number & size */ |
| ... | ... | |
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uint8_t ASID; |
| 487 | 485 |
|
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ASID = env->CP0_EntryHi & 0xFF; |
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tlb = &env->tlb[env->CP0_Index & (MIPS_TLB_NB - 1)];
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tlb = &env->tlb[env->CP0_Index % env->nb_tlb];
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| 490 | 488 |
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/* If this will change the current ASID, flush qemu's TLB. */ |
| 492 | 490 |
if (ASID != tlb->ASID) |
| 493 | 491 |
cpu_mips_tlb_flush (env, 1); |
| 494 | 492 |
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mips_tlb_flush_extra(env, MIPS_TLB_NB);
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mips_tlb_flush_extra(env, env->nb_tlb);
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| 496 | 494 |
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env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
| 498 | 496 |
env->CP0_PageMask = tlb->PageMask; |
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