Revision fcc803d1
| ID | fcc803d119a4c01a9b0ee5bda35fda1eeabffa33 |
target-xtensa: implement ATOMCTL SR
ATOMCTL SR controls s32c1i opcode behavior depending on targeted memory
type. See ISA, 4.3.12.4 for details.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Files
- added
- modified
- copied
- renamed
- deleted
- target-xtensa
- cpu.c (diff)
- cpu.h (diff)
- helper.c (diff)
- helper.h (diff)
- op_helper.c (diff)
- overlay_tool.h (diff)
- translate.c (diff)