root / target-lm32 / translate.c @ fcda9863
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/*
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* LatticeMico32 main translation routines.
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*
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* Copyright (c) 2010 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include <assert.h> |
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#include "cpu.h" |
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#include "exec-all.h" |
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#include "disas.h" |
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#include "helper.h" |
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#include "tcg-op.h" |
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#include "lm32-decode.h" |
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#include "qemu-common.h" |
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#include "hw/lm32_pic.h" |
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#define GEN_HELPER 1 |
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#include "helper.h" |
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#define DISAS_LM32 1 |
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#if DISAS_LM32
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# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
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#else
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# define LOG_DIS(...) do { } while (0) |
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#endif
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#define EXTRACT_FIELD(src, start, end) \
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(((src) >> start) & ((1 << (end - start + 1)) - 1)) |
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#define MEM_INDEX 0 |
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static TCGv_ptr cpu_env;
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static TCGv cpu_R[32]; |
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static TCGv cpu_pc;
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static TCGv cpu_ie;
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static TCGv cpu_icc;
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static TCGv cpu_dcc;
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static TCGv cpu_cc;
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static TCGv cpu_cfg;
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static TCGv cpu_eba;
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static TCGv cpu_dc;
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static TCGv cpu_deba;
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static TCGv cpu_bp[4]; |
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static TCGv cpu_wp[4]; |
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#include "gen-icount.h" |
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enum {
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OP_FMT_RI, |
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OP_FMT_RR, |
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OP_FMT_CR, |
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OP_FMT_I |
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}; |
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/* This is the state at translation time. */
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typedef struct DisasContext { |
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CPUState *env; |
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target_ulong pc; |
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/* Decoder. */
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int format;
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uint32_t ir; |
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uint8_t opcode; |
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uint8_t r0, r1, r2, csr; |
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uint16_t imm5; |
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uint16_t imm16; |
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uint32_t imm26; |
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unsigned int delayed_branch; |
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unsigned int tb_flags, synced_flags; /* tb dependent flags. */ |
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int is_jmp;
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int nr_nops;
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struct TranslationBlock *tb;
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int singlestep_enabled;
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} DisasContext; |
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static const char *regnames[] = { |
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
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"r24", "r25", "r26/gp", "r27/fp", "r28/sp", "r29/ra", |
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"r30/ea", "r31/ba", "bp0", "bp1", "bp2", "bp3", "wp0", |
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"wp1", "wp2", "wp3" |
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}; |
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static inline int zero_extend(unsigned int val, int width) |
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{ |
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return val & ((1 << width) - 1); |
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} |
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static inline int sign_extend(unsigned int val, int width) |
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{ |
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int sval;
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/* LSL. */
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val <<= 32 - width;
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sval = val; |
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/* ASR. */
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sval >>= 32 - width;
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return sval;
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} |
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static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index) |
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{ |
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TCGv_i32 tmp = tcg_const_i32(index); |
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gen_helper_raise_exception(tmp); |
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tcg_temp_free_i32(tmp); |
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} |
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static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) |
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{ |
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TranslationBlock *tb; |
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tb = dc->tb; |
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if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
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likely(!dc->singlestep_enabled)) { |
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tcg_gen_goto_tb(n); |
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tcg_gen_movi_tl(cpu_pc, dest); |
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tcg_gen_exit_tb((long)tb + n);
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} else {
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tcg_gen_movi_tl(cpu_pc, dest); |
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if (dc->singlestep_enabled) {
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t_gen_raise_exception(dc, EXCP_DEBUG); |
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} |
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tcg_gen_exit_tb(0);
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} |
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} |
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static void dec_add(DisasContext *dc) |
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{ |
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if (dc->format == OP_FMT_RI) {
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if (dc->r0 == R_R0) {
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if (dc->r1 == R_R0 && dc->imm16 == 0) { |
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LOG_DIS("nop\n");
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} else {
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LOG_DIS("mvi r%d, %d\n", dc->r1, sign_extend(dc->imm16, 16)); |
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} |
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} else {
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LOG_DIS("addi r%d, r%d, %d\n", dc->r1, dc->r0,
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sign_extend(dc->imm16, 16));
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} |
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} else {
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LOG_DIS("add r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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} |
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if (dc->format == OP_FMT_RI) {
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tcg_gen_addi_tl(cpu_R[dc->r1], cpu_R[dc->r0], |
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sign_extend(dc->imm16, 16));
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} else {
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tcg_gen_add_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); |
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} |
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} |
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static void dec_and(DisasContext *dc) |
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{ |
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if (dc->format == OP_FMT_RI) {
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LOG_DIS("andi r%d, r%d, %d\n", dc->r1, dc->r0,
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zero_extend(dc->imm16, 16));
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} else {
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LOG_DIS("and r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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} |
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if (dc->format == OP_FMT_RI) {
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tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0], |
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zero_extend(dc->imm16, 16));
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} else {
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if (dc->r0 == 0 && dc->r1 == 0 && dc->r2 == 0) { |
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tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
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gen_helper_hlt(); |
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} else {
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tcg_gen_and_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); |
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} |
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} |
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} |
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static void dec_andhi(DisasContext *dc) |
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{ |
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LOG_DIS("andhi r%d, r%d, %d\n", dc->r2, dc->r0, dc->imm16);
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tcg_gen_andi_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
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} |
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static void dec_b(DisasContext *dc) |
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{ |
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if (dc->r0 == R_RA) {
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LOG_DIS("ret\n");
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} else if (dc->r0 == R_EA) { |
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LOG_DIS("eret\n");
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} else if (dc->r0 == R_BA) { |
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LOG_DIS("bret\n");
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} else {
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LOG_DIS("b r%d\n", dc->r0);
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} |
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/* restore IE.IE in case of an eret */
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if (dc->r0 == R_EA) {
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TCGv t0 = tcg_temp_new(); |
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int l1 = gen_new_label();
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tcg_gen_andi_tl(t0, cpu_ie, IE_EIE); |
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tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE); |
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tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_EIE, l1); |
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tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE); |
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gen_set_label(l1); |
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tcg_temp_free(t0); |
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} else if (dc->r0 == R_BA) { |
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TCGv t0 = tcg_temp_new(); |
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int l1 = gen_new_label();
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tcg_gen_andi_tl(t0, cpu_ie, IE_BIE); |
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tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE); |
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tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_BIE, l1); |
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tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE); |
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gen_set_label(l1); |
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tcg_temp_free(t0); |
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} |
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tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]); |
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dc->is_jmp = DISAS_JUMP; |
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} |
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static void dec_bi(DisasContext *dc) |
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{ |
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LOG_DIS("bi %d\n", sign_extend(dc->imm26 << 2, 26)); |
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gen_goto_tb(dc, 0, dc->pc + (sign_extend(dc->imm26 << 2, 26))); |
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dc->is_jmp = DISAS_TB_JUMP; |
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} |
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static inline void gen_cond_branch(DisasContext *dc, int cond) |
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{ |
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int l1;
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l1 = gen_new_label(); |
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tcg_gen_brcond_tl(cond, cpu_R[dc->r0], cpu_R[dc->r1], l1); |
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gen_goto_tb(dc, 0, dc->pc + 4); |
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gen_set_label(l1); |
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gen_goto_tb(dc, 1, dc->pc + (sign_extend(dc->imm16 << 2, 16))); |
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dc->is_jmp = DISAS_TB_JUMP; |
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} |
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static void dec_be(DisasContext *dc) |
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{ |
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LOG_DIS("be r%d, r%d, %d\n", dc->r0, dc->r1,
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sign_extend(dc->imm16, 16) * 4); |
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gen_cond_branch(dc, TCG_COND_EQ); |
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} |
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static void dec_bg(DisasContext *dc) |
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{ |
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LOG_DIS("bg r%d, r%d, %d\n", dc->r0, dc->r1,
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sign_extend(dc->imm16, 16 * 4)); |
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gen_cond_branch(dc, TCG_COND_GT); |
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} |
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static void dec_bge(DisasContext *dc) |
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{ |
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LOG_DIS("bge r%d, r%d, %d\n", dc->r0, dc->r1,
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sign_extend(dc->imm16, 16) * 4); |
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gen_cond_branch(dc, TCG_COND_GE); |
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} |
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static void dec_bgeu(DisasContext *dc) |
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{ |
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LOG_DIS("bgeu r%d, r%d, %d\n", dc->r0, dc->r1,
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sign_extend(dc->imm16, 16) * 4); |
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gen_cond_branch(dc, TCG_COND_GEU); |
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} |
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static void dec_bgu(DisasContext *dc) |
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{ |
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LOG_DIS("bgu r%d, r%d, %d\n", dc->r0, dc->r1,
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sign_extend(dc->imm16, 16) * 4); |
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gen_cond_branch(dc, TCG_COND_GTU); |
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} |
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static void dec_bne(DisasContext *dc) |
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{ |
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LOG_DIS("bne r%d, r%d, %d\n", dc->r0, dc->r1,
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sign_extend(dc->imm16, 16) * 4); |
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gen_cond_branch(dc, TCG_COND_NE); |
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} |
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static void dec_call(DisasContext *dc) |
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{ |
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LOG_DIS("call r%d\n", dc->r0);
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tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4);
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tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]); |
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dc->is_jmp = DISAS_JUMP; |
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} |
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static void dec_calli(DisasContext *dc) |
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{ |
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LOG_DIS("calli %d\n", sign_extend(dc->imm26, 26) * 4); |
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tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4);
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gen_goto_tb(dc, 0, dc->pc + (sign_extend(dc->imm26 << 2, 26))); |
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dc->is_jmp = DISAS_TB_JUMP; |
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} |
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static inline void gen_compare(DisasContext *dc, int cond) |
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{ |
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int rX = (dc->format == OP_FMT_RR) ? dc->r2 : dc->r1;
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int rY = (dc->format == OP_FMT_RR) ? dc->r0 : dc->r0;
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int rZ = (dc->format == OP_FMT_RR) ? dc->r1 : -1; |
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if (dc->format == OP_FMT_RI) {
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tcg_gen_setcondi_tl(cond, cpu_R[rX], cpu_R[rY], |
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sign_extend(dc->imm16, 16));
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} else {
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tcg_gen_setcond_tl(cond, cpu_R[rX], cpu_R[rY], cpu_R[rZ]); |
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} |
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} |
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static void dec_cmpe(DisasContext *dc) |
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{ |
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if (dc->format == OP_FMT_RI) {
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LOG_DIS("cmpei r%d, r%d, %d\n", dc->r0, dc->r1,
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sign_extend(dc->imm16, 16));
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} else {
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LOG_DIS("cmpe r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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} |
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gen_compare(dc, TCG_COND_EQ); |
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} |
357 |
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static void dec_cmpg(DisasContext *dc) |
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{ |
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if (dc->format == OP_FMT_RI) {
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LOG_DIS("cmpgi r%d, r%d, %d\n", dc->r0, dc->r1,
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sign_extend(dc->imm16, 16));
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} else {
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LOG_DIS("cmpg r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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} |
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gen_compare(dc, TCG_COND_GT); |
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} |
369 |
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static void dec_cmpge(DisasContext *dc) |
371 |
{ |
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if (dc->format == OP_FMT_RI) {
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LOG_DIS("cmpgei r%d, r%d, %d\n", dc->r0, dc->r1,
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sign_extend(dc->imm16, 16));
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} else {
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LOG_DIS("cmpge r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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} |
378 |
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gen_compare(dc, TCG_COND_GE); |
380 |
} |
381 |
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static void dec_cmpgeu(DisasContext *dc) |
383 |
{ |
384 |
if (dc->format == OP_FMT_RI) {
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LOG_DIS("cmpgeui r%d, r%d, %d\n", dc->r0, dc->r1,
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sign_extend(dc->imm16, 16));
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} else {
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LOG_DIS("cmpgeu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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} |
390 |
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gen_compare(dc, TCG_COND_GEU); |
392 |
} |
393 |
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static void dec_cmpgu(DisasContext *dc) |
395 |
{ |
396 |
if (dc->format == OP_FMT_RI) {
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LOG_DIS("cmpgui r%d, r%d, %d\n", dc->r0, dc->r1,
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sign_extend(dc->imm16, 16));
|
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} else {
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400 |
LOG_DIS("cmpgu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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} |
402 |
|
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gen_compare(dc, TCG_COND_GTU); |
404 |
} |
405 |
|
406 |
static void dec_cmpne(DisasContext *dc) |
407 |
{ |
408 |
if (dc->format == OP_FMT_RI) {
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LOG_DIS("cmpnei r%d, r%d, %d\n", dc->r0, dc->r1,
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sign_extend(dc->imm16, 16));
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} else {
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412 |
LOG_DIS("cmpne r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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413 |
} |
414 |
|
415 |
gen_compare(dc, TCG_COND_NE); |
416 |
} |
417 |
|
418 |
static void dec_divu(DisasContext *dc) |
419 |
{ |
420 |
int l1;
|
421 |
|
422 |
LOG_DIS("divu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
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423 |
|
424 |
if (!(dc->env->features & LM32_FEATURE_DIVIDE)) {
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425 |
cpu_abort(dc->env, "hardware divider is not available\n");
|
426 |
} |
427 |
|
428 |
l1 = gen_new_label(); |
429 |
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[dc->r1], 0, l1);
|
430 |
tcg_gen_movi_tl(cpu_pc, dc->pc); |
431 |
t_gen_raise_exception(dc, EXCP_DIVIDE_BY_ZERO); |
432 |
gen_set_label(l1); |
433 |
tcg_gen_divu_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); |
434 |
} |
435 |
|
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static void dec_lb(DisasContext *dc) |
437 |
{ |
438 |
TCGv t0; |
439 |
|
440 |
LOG_DIS("lb r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
|
441 |
|
442 |
t0 = tcg_temp_new(); |
443 |
tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
|
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tcg_gen_qemu_ld8s(cpu_R[dc->r1], t0, MEM_INDEX); |
445 |
tcg_temp_free(t0); |
446 |
} |
447 |
|
448 |
static void dec_lbu(DisasContext *dc) |
449 |
{ |
450 |
TCGv t0; |
451 |
|
452 |
LOG_DIS("lbu r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
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453 |
|
454 |
t0 = tcg_temp_new(); |
455 |
tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
|
456 |
tcg_gen_qemu_ld8u(cpu_R[dc->r1], t0, MEM_INDEX); |
457 |
tcg_temp_free(t0); |
458 |
} |
459 |
|
460 |
static void dec_lh(DisasContext *dc) |
461 |
{ |
462 |
TCGv t0; |
463 |
|
464 |
LOG_DIS("lh r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
|
465 |
|
466 |
t0 = tcg_temp_new(); |
467 |
tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
|
468 |
tcg_gen_qemu_ld16s(cpu_R[dc->r1], t0, MEM_INDEX); |
469 |
tcg_temp_free(t0); |
470 |
} |
471 |
|
472 |
static void dec_lhu(DisasContext *dc) |
473 |
{ |
474 |
TCGv t0; |
475 |
|
476 |
LOG_DIS("lhu r%d, (r%d+%d)\n", dc->r1, dc->r0, dc->imm16);
|
477 |
|
478 |
t0 = tcg_temp_new(); |
479 |
tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
|
480 |
tcg_gen_qemu_ld16u(cpu_R[dc->r1], t0, MEM_INDEX); |
481 |
tcg_temp_free(t0); |
482 |
} |
483 |
|
484 |
static void dec_lw(DisasContext *dc) |
485 |
{ |
486 |
TCGv t0; |
487 |
|
488 |
LOG_DIS("lw r%d, (r%d+%d)\n", dc->r1, dc->r0, sign_extend(dc->imm16, 16)); |
489 |
|
490 |
t0 = tcg_temp_new(); |
491 |
tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
|
492 |
tcg_gen_qemu_ld32s(cpu_R[dc->r1], t0, MEM_INDEX); |
493 |
tcg_temp_free(t0); |
494 |
} |
495 |
|
496 |
static void dec_modu(DisasContext *dc) |
497 |
{ |
498 |
int l1;
|
499 |
|
500 |
LOG_DIS("modu r%d, r%d, %d\n", dc->r2, dc->r0, dc->r1);
|
501 |
|
502 |
if (!(dc->env->features & LM32_FEATURE_DIVIDE)) {
|
503 |
cpu_abort(dc->env, "hardware divider is not available\n");
|
504 |
} |
505 |
|
506 |
l1 = gen_new_label(); |
507 |
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[dc->r1], 0, l1);
|
508 |
tcg_gen_movi_tl(cpu_pc, dc->pc); |
509 |
t_gen_raise_exception(dc, EXCP_DIVIDE_BY_ZERO); |
510 |
gen_set_label(l1); |
511 |
tcg_gen_remu_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); |
512 |
} |
513 |
|
514 |
static void dec_mul(DisasContext *dc) |
515 |
{ |
516 |
if (dc->format == OP_FMT_RI) {
|
517 |
LOG_DIS("muli r%d, r%d, %d\n", dc->r0, dc->r1,
|
518 |
sign_extend(dc->imm16, 16));
|
519 |
} else {
|
520 |
LOG_DIS("mul r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
521 |
} |
522 |
|
523 |
if (!(dc->env->features & LM32_FEATURE_MULTIPLY)) {
|
524 |
cpu_abort(dc->env, "hardware multiplier is not available\n");
|
525 |
} |
526 |
|
527 |
if (dc->format == OP_FMT_RI) {
|
528 |
tcg_gen_muli_tl(cpu_R[dc->r1], cpu_R[dc->r0], |
529 |
sign_extend(dc->imm16, 16));
|
530 |
} else {
|
531 |
tcg_gen_mul_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); |
532 |
} |
533 |
} |
534 |
|
535 |
static void dec_nor(DisasContext *dc) |
536 |
{ |
537 |
if (dc->format == OP_FMT_RI) {
|
538 |
LOG_DIS("nori r%d, r%d, %d\n", dc->r0, dc->r1,
|
539 |
zero_extend(dc->imm16, 16));
|
540 |
} else {
|
541 |
LOG_DIS("nor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
542 |
} |
543 |
|
544 |
if (dc->format == OP_FMT_RI) {
|
545 |
TCGv t0 = tcg_temp_new(); |
546 |
tcg_gen_movi_tl(t0, zero_extend(dc->imm16, 16));
|
547 |
tcg_gen_nor_tl(cpu_R[dc->r1], cpu_R[dc->r0], t0); |
548 |
tcg_temp_free(t0); |
549 |
} else {
|
550 |
tcg_gen_nor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); |
551 |
} |
552 |
} |
553 |
|
554 |
static void dec_or(DisasContext *dc) |
555 |
{ |
556 |
if (dc->format == OP_FMT_RI) {
|
557 |
LOG_DIS("ori r%d, r%d, %d\n", dc->r1, dc->r0,
|
558 |
zero_extend(dc->imm16, 16));
|
559 |
} else {
|
560 |
if (dc->r1 == R_R0) {
|
561 |
LOG_DIS("mv r%d, r%d\n", dc->r2, dc->r0);
|
562 |
} else {
|
563 |
LOG_DIS("or r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
564 |
} |
565 |
} |
566 |
|
567 |
if (dc->format == OP_FMT_RI) {
|
568 |
tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0], |
569 |
zero_extend(dc->imm16, 16));
|
570 |
} else {
|
571 |
tcg_gen_or_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); |
572 |
} |
573 |
} |
574 |
|
575 |
static void dec_orhi(DisasContext *dc) |
576 |
{ |
577 |
if (dc->r0 == R_R0) {
|
578 |
LOG_DIS("mvhi r%d, %d\n", dc->r1, dc->imm16);
|
579 |
} else {
|
580 |
LOG_DIS("orhi r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm16);
|
581 |
} |
582 |
|
583 |
tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
|
584 |
} |
585 |
|
586 |
static void dec_scall(DisasContext *dc) |
587 |
{ |
588 |
TCGv t0; |
589 |
int l1;
|
590 |
|
591 |
if (dc->imm5 == 7) { |
592 |
LOG_DIS("scall\n");
|
593 |
} else if (dc->imm5 == 2) { |
594 |
LOG_DIS("break\n");
|
595 |
} else {
|
596 |
cpu_abort(dc->env, "invalid opcode\n");
|
597 |
} |
598 |
|
599 |
t0 = tcg_temp_new(); |
600 |
l1 = gen_new_label(); |
601 |
|
602 |
/* save IE.IE */
|
603 |
tcg_gen_andi_tl(t0, cpu_ie, IE_IE); |
604 |
|
605 |
/* IE.IE = 0 */
|
606 |
tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE); |
607 |
|
608 |
if (dc->imm5 == 7) { |
609 |
/* IE.EIE = IE.IE */
|
610 |
tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_EIE); |
611 |
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_IE, l1); |
612 |
tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_EIE); |
613 |
gen_set_label(l1); |
614 |
|
615 |
/* gpr[ea] = PC */
|
616 |
tcg_gen_movi_tl(cpu_R[R_EA], dc->pc); |
617 |
tcg_temp_free(t0); |
618 |
|
619 |
tcg_gen_movi_tl(cpu_pc, dc->pc); |
620 |
t_gen_raise_exception(dc, EXCP_SYSTEMCALL); |
621 |
} else {
|
622 |
/* IE.BIE = IE.IE */
|
623 |
tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_BIE); |
624 |
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_IE, l1); |
625 |
tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_BIE); |
626 |
gen_set_label(l1); |
627 |
|
628 |
/* gpr[ba] = PC */
|
629 |
tcg_gen_movi_tl(cpu_R[R_BA], dc->pc); |
630 |
tcg_temp_free(t0); |
631 |
|
632 |
tcg_gen_movi_tl(cpu_pc, dc->pc); |
633 |
t_gen_raise_exception(dc, EXCP_BREAKPOINT); |
634 |
} |
635 |
} |
636 |
|
637 |
static void dec_rcsr(DisasContext *dc) |
638 |
{ |
639 |
LOG_DIS("rcsr r%d, %d\n", dc->r2, dc->csr);
|
640 |
|
641 |
switch (dc->csr) {
|
642 |
case CSR_IE:
|
643 |
tcg_gen_mov_tl(cpu_R[dc->r2], cpu_ie); |
644 |
break;
|
645 |
case CSR_IM:
|
646 |
gen_helper_rcsr_im(cpu_R[dc->r2]); |
647 |
break;
|
648 |
case CSR_IP:
|
649 |
gen_helper_rcsr_ip(cpu_R[dc->r2]); |
650 |
break;
|
651 |
case CSR_CC:
|
652 |
tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cc); |
653 |
break;
|
654 |
case CSR_CFG:
|
655 |
tcg_gen_mov_tl(cpu_R[dc->r2], cpu_cfg); |
656 |
break;
|
657 |
case CSR_EBA:
|
658 |
tcg_gen_mov_tl(cpu_R[dc->r2], cpu_eba); |
659 |
break;
|
660 |
case CSR_DC:
|
661 |
tcg_gen_mov_tl(cpu_R[dc->r2], cpu_dc); |
662 |
break;
|
663 |
case CSR_DEBA:
|
664 |
tcg_gen_mov_tl(cpu_R[dc->r2], cpu_deba); |
665 |
break;
|
666 |
case CSR_JTX:
|
667 |
gen_helper_rcsr_jtx(cpu_R[dc->r2]); |
668 |
break;
|
669 |
case CSR_JRX:
|
670 |
gen_helper_rcsr_jrx(cpu_R[dc->r2]); |
671 |
break;
|
672 |
case CSR_ICC:
|
673 |
case CSR_DCC:
|
674 |
case CSR_BP0:
|
675 |
case CSR_BP1:
|
676 |
case CSR_BP2:
|
677 |
case CSR_BP3:
|
678 |
case CSR_WP0:
|
679 |
case CSR_WP1:
|
680 |
case CSR_WP2:
|
681 |
case CSR_WP3:
|
682 |
cpu_abort(dc->env, "invalid read access csr=%x\n", dc->csr);
|
683 |
break;
|
684 |
default:
|
685 |
cpu_abort(dc->env, "read_csr: unknown csr=%x\n", dc->csr);
|
686 |
break;
|
687 |
} |
688 |
} |
689 |
|
690 |
static void dec_sb(DisasContext *dc) |
691 |
{ |
692 |
TCGv t0; |
693 |
|
694 |
LOG_DIS("sb (r%d+%d), r%d\n", dc->r0, dc->imm16, dc->r1);
|
695 |
|
696 |
t0 = tcg_temp_new(); |
697 |
tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
|
698 |
tcg_gen_qemu_st8(cpu_R[dc->r1], t0, MEM_INDEX); |
699 |
tcg_temp_free(t0); |
700 |
} |
701 |
|
702 |
static void dec_sextb(DisasContext *dc) |
703 |
{ |
704 |
LOG_DIS("sextb r%d, r%d\n", dc->r2, dc->r0);
|
705 |
|
706 |
if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) {
|
707 |
cpu_abort(dc->env, "hardware sign extender is not available\n");
|
708 |
} |
709 |
|
710 |
tcg_gen_ext8s_tl(cpu_R[dc->r2], cpu_R[dc->r0]); |
711 |
} |
712 |
|
713 |
static void dec_sexth(DisasContext *dc) |
714 |
{ |
715 |
LOG_DIS("sexth r%d, r%d\n", dc->r2, dc->r0);
|
716 |
|
717 |
if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) {
|
718 |
cpu_abort(dc->env, "hardware sign extender is not available\n");
|
719 |
} |
720 |
|
721 |
tcg_gen_ext16s_tl(cpu_R[dc->r2], cpu_R[dc->r0]); |
722 |
} |
723 |
|
724 |
static void dec_sh(DisasContext *dc) |
725 |
{ |
726 |
TCGv t0; |
727 |
|
728 |
LOG_DIS("sh (r%d+%d), r%d\n", dc->r0, dc->imm16, dc->r1);
|
729 |
|
730 |
t0 = tcg_temp_new(); |
731 |
tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
|
732 |
tcg_gen_qemu_st16(cpu_R[dc->r1], t0, MEM_INDEX); |
733 |
tcg_temp_free(t0); |
734 |
} |
735 |
|
736 |
static void dec_sl(DisasContext *dc) |
737 |
{ |
738 |
if (dc->format == OP_FMT_RI) {
|
739 |
LOG_DIS("sli r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
|
740 |
} else {
|
741 |
LOG_DIS("sl r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
742 |
} |
743 |
|
744 |
if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
|
745 |
cpu_abort(dc->env, "hardware shifter is not available\n");
|
746 |
} |
747 |
|
748 |
if (dc->format == OP_FMT_RI) {
|
749 |
tcg_gen_shli_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5); |
750 |
} else {
|
751 |
TCGv t0 = tcg_temp_new(); |
752 |
tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
|
753 |
tcg_gen_shl_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0); |
754 |
tcg_temp_free(t0); |
755 |
} |
756 |
} |
757 |
|
758 |
static void dec_sr(DisasContext *dc) |
759 |
{ |
760 |
if (dc->format == OP_FMT_RI) {
|
761 |
LOG_DIS("sri r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
|
762 |
} else {
|
763 |
LOG_DIS("sr r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
764 |
} |
765 |
|
766 |
if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
|
767 |
if (dc->format == OP_FMT_RI) {
|
768 |
/* TODO: check r1 == 1 during runtime */
|
769 |
} else {
|
770 |
if (dc->imm5 != 1) { |
771 |
cpu_abort(dc->env, "hardware shifter is not available\n");
|
772 |
} |
773 |
} |
774 |
} |
775 |
|
776 |
if (dc->format == OP_FMT_RI) {
|
777 |
tcg_gen_sari_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5); |
778 |
} else {
|
779 |
TCGv t0 = tcg_temp_new(); |
780 |
tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
|
781 |
tcg_gen_sar_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0); |
782 |
tcg_temp_free(t0); |
783 |
} |
784 |
} |
785 |
|
786 |
static void dec_sru(DisasContext *dc) |
787 |
{ |
788 |
if (dc->format == OP_FMT_RI) {
|
789 |
LOG_DIS("srui r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
|
790 |
} else {
|
791 |
LOG_DIS("sru r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
792 |
} |
793 |
|
794 |
if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
|
795 |
if (dc->format == OP_FMT_RI) {
|
796 |
/* TODO: check r1 == 1 during runtime */
|
797 |
} else {
|
798 |
if (dc->imm5 != 1) { |
799 |
cpu_abort(dc->env, "hardware shifter is not available\n");
|
800 |
} |
801 |
} |
802 |
} |
803 |
|
804 |
if (dc->format == OP_FMT_RI) {
|
805 |
tcg_gen_shri_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5); |
806 |
} else {
|
807 |
TCGv t0 = tcg_temp_new(); |
808 |
tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
|
809 |
tcg_gen_shr_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0); |
810 |
tcg_temp_free(t0); |
811 |
} |
812 |
} |
813 |
|
814 |
static void dec_sub(DisasContext *dc) |
815 |
{ |
816 |
LOG_DIS("sub r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
817 |
|
818 |
tcg_gen_sub_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); |
819 |
} |
820 |
|
821 |
static void dec_sw(DisasContext *dc) |
822 |
{ |
823 |
TCGv t0; |
824 |
|
825 |
LOG_DIS("sw (r%d+%d), r%d\n", dc->r0, sign_extend(dc->imm16, 16), dc->r1); |
826 |
|
827 |
t0 = tcg_temp_new(); |
828 |
tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16));
|
829 |
tcg_gen_qemu_st32(cpu_R[dc->r1], t0, MEM_INDEX); |
830 |
tcg_temp_free(t0); |
831 |
} |
832 |
|
833 |
static void dec_user(DisasContext *dc) |
834 |
{ |
835 |
LOG_DIS("user");
|
836 |
|
837 |
cpu_abort(dc->env, "user insn undefined\n");
|
838 |
} |
839 |
|
840 |
static void dec_wcsr(DisasContext *dc) |
841 |
{ |
842 |
int no;
|
843 |
|
844 |
LOG_DIS("wcsr r%d, %d\n", dc->r1, dc->csr);
|
845 |
|
846 |
switch (dc->csr) {
|
847 |
case CSR_IE:
|
848 |
tcg_gen_mov_tl(cpu_ie, cpu_R[dc->r1]); |
849 |
tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
|
850 |
dc->is_jmp = DISAS_UPDATE; |
851 |
break;
|
852 |
case CSR_IM:
|
853 |
/* mark as an io operation because it could cause an interrupt */
|
854 |
if (use_icount) {
|
855 |
gen_io_start(); |
856 |
} |
857 |
gen_helper_wcsr_im(cpu_R[dc->r1]); |
858 |
tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
|
859 |
if (use_icount) {
|
860 |
gen_io_end(); |
861 |
} |
862 |
dc->is_jmp = DISAS_UPDATE; |
863 |
break;
|
864 |
case CSR_IP:
|
865 |
/* mark as an io operation because it could cause an interrupt */
|
866 |
if (use_icount) {
|
867 |
gen_io_start(); |
868 |
} |
869 |
gen_helper_wcsr_ip(cpu_R[dc->r1]); |
870 |
tcg_gen_movi_tl(cpu_pc, dc->pc + 4);
|
871 |
if (use_icount) {
|
872 |
gen_io_end(); |
873 |
} |
874 |
dc->is_jmp = DISAS_UPDATE; |
875 |
break;
|
876 |
case CSR_ICC:
|
877 |
/* TODO */
|
878 |
break;
|
879 |
case CSR_DCC:
|
880 |
/* TODO */
|
881 |
break;
|
882 |
case CSR_EBA:
|
883 |
tcg_gen_mov_tl(cpu_eba, cpu_R[dc->r1]); |
884 |
break;
|
885 |
case CSR_DEBA:
|
886 |
tcg_gen_mov_tl(cpu_deba, cpu_R[dc->r1]); |
887 |
break;
|
888 |
case CSR_JTX:
|
889 |
gen_helper_wcsr_jtx(cpu_R[dc->r1]); |
890 |
break;
|
891 |
case CSR_JRX:
|
892 |
gen_helper_wcsr_jrx(cpu_R[dc->r1]); |
893 |
break;
|
894 |
case CSR_DC:
|
895 |
tcg_gen_mov_tl(cpu_dc, cpu_R[dc->r1]); |
896 |
break;
|
897 |
case CSR_BP0:
|
898 |
case CSR_BP1:
|
899 |
case CSR_BP2:
|
900 |
case CSR_BP3:
|
901 |
no = dc->csr - CSR_BP0; |
902 |
if (dc->env->num_bps <= no) {
|
903 |
cpu_abort(dc->env, "breakpoint #%i is not available\n", no);
|
904 |
} |
905 |
tcg_gen_mov_tl(cpu_bp[no], cpu_R[dc->r1]); |
906 |
break;
|
907 |
case CSR_WP0:
|
908 |
case CSR_WP1:
|
909 |
case CSR_WP2:
|
910 |
case CSR_WP3:
|
911 |
no = dc->csr - CSR_WP0; |
912 |
if (dc->env->num_wps <= no) {
|
913 |
cpu_abort(dc->env, "watchpoint #%i is not available\n", no);
|
914 |
} |
915 |
tcg_gen_mov_tl(cpu_wp[no], cpu_R[dc->r1]); |
916 |
break;
|
917 |
case CSR_CC:
|
918 |
case CSR_CFG:
|
919 |
cpu_abort(dc->env, "invalid write access csr=%x\n", dc->csr);
|
920 |
break;
|
921 |
default:
|
922 |
cpu_abort(dc->env, "write_csr unknown csr=%x\n", dc->csr);
|
923 |
break;
|
924 |
} |
925 |
} |
926 |
|
927 |
static void dec_xnor(DisasContext *dc) |
928 |
{ |
929 |
if (dc->format == OP_FMT_RI) {
|
930 |
LOG_DIS("xnori r%d, r%d, %d\n", dc->r0, dc->r1,
|
931 |
zero_extend(dc->imm16, 16));
|
932 |
} else {
|
933 |
if (dc->r1 == R_R0) {
|
934 |
LOG_DIS("not r%d, r%d\n", dc->r2, dc->r0);
|
935 |
} else {
|
936 |
LOG_DIS("xnor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
937 |
} |
938 |
} |
939 |
|
940 |
if (dc->format == OP_FMT_RI) {
|
941 |
tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0], |
942 |
zero_extend(dc->imm16, 16));
|
943 |
tcg_gen_not_tl(cpu_R[dc->r1], cpu_R[dc->r1]); |
944 |
} else {
|
945 |
tcg_gen_eqv_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); |
946 |
} |
947 |
} |
948 |
|
949 |
static void dec_xor(DisasContext *dc) |
950 |
{ |
951 |
if (dc->format == OP_FMT_RI) {
|
952 |
LOG_DIS("xori r%d, r%d, %d\n", dc->r0, dc->r1,
|
953 |
zero_extend(dc->imm16, 16));
|
954 |
} else {
|
955 |
LOG_DIS("xor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
956 |
} |
957 |
|
958 |
if (dc->format == OP_FMT_RI) {
|
959 |
tcg_gen_xori_tl(cpu_R[dc->r1], cpu_R[dc->r0], |
960 |
zero_extend(dc->imm16, 16));
|
961 |
} else {
|
962 |
tcg_gen_xor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); |
963 |
} |
964 |
} |
965 |
|
966 |
typedef struct { |
967 |
struct {
|
968 |
uint32_t bits; |
969 |
uint32_t mask; |
970 |
}; |
971 |
void (*dec)(DisasContext *dc);
|
972 |
} DecoderInfo; |
973 |
|
974 |
static const DecoderInfo decinfo[] = { |
975 |
{DEC_ADD, dec_add}, |
976 |
{DEC_AND, dec_and}, |
977 |
{DEC_ANDHI, dec_andhi}, |
978 |
{DEC_B, dec_b}, |
979 |
{DEC_BI, dec_bi}, |
980 |
{DEC_BE, dec_be}, |
981 |
{DEC_BG, dec_bg}, |
982 |
{DEC_BGE, dec_bge}, |
983 |
{DEC_BGEU, dec_bgeu}, |
984 |
{DEC_BGU, dec_bgu}, |
985 |
{DEC_BNE, dec_bne}, |
986 |
{DEC_CALL, dec_call}, |
987 |
{DEC_CALLI, dec_calli}, |
988 |
{DEC_CMPE, dec_cmpe}, |
989 |
{DEC_CMPG, dec_cmpg}, |
990 |
{DEC_CMPGE, dec_cmpge}, |
991 |
{DEC_CMPGEU, dec_cmpgeu}, |
992 |
{DEC_CMPGU, dec_cmpgu}, |
993 |
{DEC_CMPNE, dec_cmpne}, |
994 |
{DEC_DIVU, dec_divu}, |
995 |
{DEC_LB, dec_lb}, |
996 |
{DEC_LBU, dec_lbu}, |
997 |
{DEC_LH, dec_lh}, |
998 |
{DEC_LHU, dec_lhu}, |
999 |
{DEC_LW, dec_lw}, |
1000 |
{DEC_MODU, dec_modu}, |
1001 |
{DEC_MUL, dec_mul}, |
1002 |
{DEC_NOR, dec_nor}, |
1003 |
{DEC_OR, dec_or}, |
1004 |
{DEC_ORHI, dec_orhi}, |
1005 |
{DEC_SCALL, dec_scall}, |
1006 |
{DEC_RCSR, dec_rcsr}, |
1007 |
{DEC_SB, dec_sb}, |
1008 |
{DEC_SEXTB, dec_sextb}, |
1009 |
{DEC_SEXTH, dec_sexth}, |
1010 |
{DEC_SH, dec_sh}, |
1011 |
{DEC_SL, dec_sl}, |
1012 |
{DEC_SR, dec_sr}, |
1013 |
{DEC_SRU, dec_sru}, |
1014 |
{DEC_SUB, dec_sub}, |
1015 |
{DEC_SW, dec_sw}, |
1016 |
{DEC_USER, dec_user}, |
1017 |
{DEC_WCSR, dec_wcsr}, |
1018 |
{DEC_XNOR, dec_xnor}, |
1019 |
{DEC_XOR, dec_xor}, |
1020 |
}; |
1021 |
|
1022 |
static inline void decode(DisasContext *dc) |
1023 |
{ |
1024 |
uint32_t ir; |
1025 |
int i;
|
1026 |
|
1027 |
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
|
1028 |
tcg_gen_debug_insn_start(dc->pc); |
1029 |
} |
1030 |
|
1031 |
dc->ir = ir = ldl_code(dc->pc); |
1032 |
LOG_DIS("%8.8x\t", dc->ir);
|
1033 |
|
1034 |
/* try guessing 'empty' instruction memory, although it may be a valid
|
1035 |
* instruction sequence (eg. srui r0, r0, 0) */
|
1036 |
if (dc->ir) {
|
1037 |
dc->nr_nops = 0;
|
1038 |
} else {
|
1039 |
LOG_DIS("nr_nops=%d\t", dc->nr_nops);
|
1040 |
dc->nr_nops++; |
1041 |
if (dc->nr_nops > 4) { |
1042 |
cpu_abort(dc->env, "fetching nop sequence\n");
|
1043 |
} |
1044 |
} |
1045 |
|
1046 |
dc->opcode = EXTRACT_FIELD(ir, 26, 31); |
1047 |
|
1048 |
dc->imm5 = EXTRACT_FIELD(ir, 0, 4); |
1049 |
dc->imm16 = EXTRACT_FIELD(ir, 0, 15); |
1050 |
dc->imm26 = EXTRACT_FIELD(ir, 0, 25); |
1051 |
|
1052 |
dc->csr = EXTRACT_FIELD(ir, 21, 25); |
1053 |
dc->r0 = EXTRACT_FIELD(ir, 21, 25); |
1054 |
dc->r1 = EXTRACT_FIELD(ir, 16, 20); |
1055 |
dc->r2 = EXTRACT_FIELD(ir, 11, 15); |
1056 |
|
1057 |
/* bit 31 seems to indicate insn type. */
|
1058 |
if (ir & (1 << 31)) { |
1059 |
dc->format = OP_FMT_RR; |
1060 |
} else {
|
1061 |
dc->format = OP_FMT_RI; |
1062 |
} |
1063 |
|
1064 |
/* Large switch for all insns. */
|
1065 |
for (i = 0; i < ARRAY_SIZE(decinfo); i++) { |
1066 |
if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
|
1067 |
decinfo[i].dec(dc); |
1068 |
return;
|
1069 |
} |
1070 |
} |
1071 |
|
1072 |
cpu_abort(dc->env, "unknown opcode 0x%02x\n", dc->opcode);
|
1073 |
} |
1074 |
|
1075 |
static void check_breakpoint(CPUState *env, DisasContext *dc) |
1076 |
{ |
1077 |
CPUBreakpoint *bp; |
1078 |
|
1079 |
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
1080 |
QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
1081 |
if (bp->pc == dc->pc) {
|
1082 |
tcg_gen_movi_tl(cpu_pc, dc->pc); |
1083 |
t_gen_raise_exception(dc, EXCP_DEBUG); |
1084 |
dc->is_jmp = DISAS_UPDATE; |
1085 |
} |
1086 |
} |
1087 |
} |
1088 |
} |
1089 |
|
1090 |
/* generate intermediate code for basic block 'tb'. */
|
1091 |
static void gen_intermediate_code_internal(CPUState *env, |
1092 |
TranslationBlock *tb, int search_pc)
|
1093 |
{ |
1094 |
struct DisasContext ctx, *dc = &ctx;
|
1095 |
uint16_t *gen_opc_end; |
1096 |
uint32_t pc_start; |
1097 |
int j, lj;
|
1098 |
uint32_t next_page_start; |
1099 |
int num_insns;
|
1100 |
int max_insns;
|
1101 |
|
1102 |
qemu_log_try_set_file(stderr); |
1103 |
|
1104 |
pc_start = tb->pc; |
1105 |
dc->env = env; |
1106 |
dc->tb = tb; |
1107 |
|
1108 |
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
1109 |
|
1110 |
dc->is_jmp = DISAS_NEXT; |
1111 |
dc->pc = pc_start; |
1112 |
dc->singlestep_enabled = env->singlestep_enabled; |
1113 |
dc->nr_nops = 0;
|
1114 |
|
1115 |
if (pc_start & 3) { |
1116 |
cpu_abort(env, "LM32: unaligned PC=%x\n", pc_start);
|
1117 |
} |
1118 |
|
1119 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
1120 |
qemu_log("-----------------------------------------\n");
|
1121 |
log_cpu_state(env, 0);
|
1122 |
} |
1123 |
|
1124 |
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |
1125 |
lj = -1;
|
1126 |
num_insns = 0;
|
1127 |
max_insns = tb->cflags & CF_COUNT_MASK; |
1128 |
if (max_insns == 0) { |
1129 |
max_insns = CF_COUNT_MASK; |
1130 |
} |
1131 |
|
1132 |
gen_icount_start(); |
1133 |
do {
|
1134 |
check_breakpoint(env, dc); |
1135 |
|
1136 |
if (search_pc) {
|
1137 |
j = gen_opc_ptr - gen_opc_buf; |
1138 |
if (lj < j) {
|
1139 |
lj++; |
1140 |
while (lj < j) {
|
1141 |
gen_opc_instr_start[lj++] = 0;
|
1142 |
} |
1143 |
} |
1144 |
gen_opc_pc[lj] = dc->pc; |
1145 |
gen_opc_instr_start[lj] = 1;
|
1146 |
gen_opc_icount[lj] = num_insns; |
1147 |
} |
1148 |
|
1149 |
/* Pretty disas. */
|
1150 |
LOG_DIS("%8.8x:\t", dc->pc);
|
1151 |
|
1152 |
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { |
1153 |
gen_io_start(); |
1154 |
} |
1155 |
|
1156 |
decode(dc); |
1157 |
dc->pc += 4;
|
1158 |
num_insns++; |
1159 |
|
1160 |
} while (!dc->is_jmp
|
1161 |
&& gen_opc_ptr < gen_opc_end |
1162 |
&& !env->singlestep_enabled |
1163 |
&& !singlestep |
1164 |
&& (dc->pc < next_page_start) |
1165 |
&& num_insns < max_insns); |
1166 |
|
1167 |
if (tb->cflags & CF_LAST_IO) {
|
1168 |
gen_io_end(); |
1169 |
} |
1170 |
|
1171 |
if (unlikely(env->singlestep_enabled)) {
|
1172 |
if (dc->is_jmp == DISAS_NEXT) {
|
1173 |
tcg_gen_movi_tl(cpu_pc, dc->pc); |
1174 |
} |
1175 |
t_gen_raise_exception(dc, EXCP_DEBUG); |
1176 |
} else {
|
1177 |
switch (dc->is_jmp) {
|
1178 |
case DISAS_NEXT:
|
1179 |
gen_goto_tb(dc, 1, dc->pc);
|
1180 |
break;
|
1181 |
default:
|
1182 |
case DISAS_JUMP:
|
1183 |
case DISAS_UPDATE:
|
1184 |
/* indicate that the hash table must be used
|
1185 |
to find the next TB */
|
1186 |
tcg_gen_exit_tb(0);
|
1187 |
break;
|
1188 |
case DISAS_TB_JUMP:
|
1189 |
/* nothing more to generate */
|
1190 |
break;
|
1191 |
} |
1192 |
} |
1193 |
|
1194 |
gen_icount_end(tb, num_insns); |
1195 |
*gen_opc_ptr = INDEX_op_end; |
1196 |
if (search_pc) {
|
1197 |
j = gen_opc_ptr - gen_opc_buf; |
1198 |
lj++; |
1199 |
while (lj <= j) {
|
1200 |
gen_opc_instr_start[lj++] = 0;
|
1201 |
} |
1202 |
} else {
|
1203 |
tb->size = dc->pc - pc_start; |
1204 |
tb->icount = num_insns; |
1205 |
} |
1206 |
|
1207 |
#ifdef DEBUG_DISAS
|
1208 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
1209 |
qemu_log("\n");
|
1210 |
log_target_disas(pc_start, dc->pc - pc_start, 0);
|
1211 |
qemu_log("\nisize=%d osize=%zd\n",
|
1212 |
dc->pc - pc_start, gen_opc_ptr - gen_opc_buf); |
1213 |
} |
1214 |
#endif
|
1215 |
} |
1216 |
|
1217 |
void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb) |
1218 |
{ |
1219 |
gen_intermediate_code_internal(env, tb, 0);
|
1220 |
} |
1221 |
|
1222 |
void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb) |
1223 |
{ |
1224 |
gen_intermediate_code_internal(env, tb, 1);
|
1225 |
} |
1226 |
|
1227 |
void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
|
1228 |
int flags)
|
1229 |
{ |
1230 |
int i;
|
1231 |
|
1232 |
if (!env || !f) {
|
1233 |
return;
|
1234 |
} |
1235 |
|
1236 |
cpu_fprintf(f, "IN: PC=%x %s\n",
|
1237 |
env->pc, lookup_symbol(env->pc)); |
1238 |
|
1239 |
cpu_fprintf(f, "ie=%8.8x (IE=%x EIE=%x BIE=%x) im=%8.8x ip=%8.8x\n",
|
1240 |
env->ie, |
1241 |
(env->ie & IE_IE) ? 1 : 0, |
1242 |
(env->ie & IE_EIE) ? 1 : 0, |
1243 |
(env->ie & IE_BIE) ? 1 : 0, |
1244 |
lm32_pic_get_im(env->pic_state), |
1245 |
lm32_pic_get_ip(env->pic_state)); |
1246 |
cpu_fprintf(f, "eba=%8.8x deba=%8.8x\n",
|
1247 |
env->eba, |
1248 |
env->deba); |
1249 |
|
1250 |
for (i = 0; i < 32; i++) { |
1251 |
cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
|
1252 |
if ((i + 1) % 4 == 0) { |
1253 |
cpu_fprintf(f, "\n");
|
1254 |
} |
1255 |
} |
1256 |
cpu_fprintf(f, "\n\n");
|
1257 |
} |
1258 |
|
1259 |
void gen_pc_load(CPUState *env, struct TranslationBlock *tb, |
1260 |
unsigned long searched_pc, int pc_pos, void *puc) |
1261 |
{ |
1262 |
env->pc = gen_opc_pc[pc_pos]; |
1263 |
} |
1264 |
|
1265 |
void lm32_translate_init(void) |
1266 |
{ |
1267 |
int i;
|
1268 |
|
1269 |
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
|
1270 |
|
1271 |
for (i = 0; i < ARRAY_SIZE(cpu_R); i++) { |
1272 |
cpu_R[i] = tcg_global_mem_new(TCG_AREG0, |
1273 |
offsetof(CPUState, regs[i]), |
1274 |
regnames[i]); |
1275 |
} |
1276 |
|
1277 |
for (i = 0; i < ARRAY_SIZE(cpu_bp); i++) { |
1278 |
cpu_bp[i] = tcg_global_mem_new(TCG_AREG0, |
1279 |
offsetof(CPUState, bp[i]), |
1280 |
regnames[32+i]);
|
1281 |
} |
1282 |
|
1283 |
for (i = 0; i < ARRAY_SIZE(cpu_wp); i++) { |
1284 |
cpu_wp[i] = tcg_global_mem_new(TCG_AREG0, |
1285 |
offsetof(CPUState, wp[i]), |
1286 |
regnames[36+i]);
|
1287 |
} |
1288 |
|
1289 |
cpu_pc = tcg_global_mem_new(TCG_AREG0, |
1290 |
offsetof(CPUState, pc), |
1291 |
"pc");
|
1292 |
cpu_ie = tcg_global_mem_new(TCG_AREG0, |
1293 |
offsetof(CPUState, ie), |
1294 |
"ie");
|
1295 |
cpu_icc = tcg_global_mem_new(TCG_AREG0, |
1296 |
offsetof(CPUState, icc), |
1297 |
"icc");
|
1298 |
cpu_dcc = tcg_global_mem_new(TCG_AREG0, |
1299 |
offsetof(CPUState, dcc), |
1300 |
"dcc");
|
1301 |
cpu_cc = tcg_global_mem_new(TCG_AREG0, |
1302 |
offsetof(CPUState, cc), |
1303 |
"cc");
|
1304 |
cpu_cfg = tcg_global_mem_new(TCG_AREG0, |
1305 |
offsetof(CPUState, cfg), |
1306 |
"cfg");
|
1307 |
cpu_eba = tcg_global_mem_new(TCG_AREG0, |
1308 |
offsetof(CPUState, eba), |
1309 |
"eba");
|
1310 |
cpu_dc = tcg_global_mem_new(TCG_AREG0, |
1311 |
offsetof(CPUState, dc), |
1312 |
"dc");
|
1313 |
cpu_deba = tcg_global_mem_new(TCG_AREG0, |
1314 |
offsetof(CPUState, deba), |
1315 |
"deba");
|
1316 |
} |
1317 |
|